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-rw-r--r--drivers/video/via/Makefile7
-rw-r--r--drivers/video/via/accel.c279
-rw-r--r--drivers/video/via/accel.h169
-rw-r--r--drivers/video/via/chip.h190
-rw-r--r--drivers/video/via/debug.h41
-rw-r--r--drivers/video/via/dvi.c682
-rw-r--r--drivers/video/via/dvi.h64
-rw-r--r--drivers/video/via/global.c60
-rw-r--r--drivers/video/via/global.h90
-rw-r--r--drivers/video/via/hw.c2865
-rw-r--r--drivers/video/via/hw.h933
-rw-r--r--drivers/video/via/iface.c78
-rw-r--r--drivers/video/via/iface.h38
-rw-r--r--drivers/video/via/ioctl.c112
-rw-r--r--drivers/video/via/ioctl.h210
-rw-r--r--drivers/video/via/lcd.c1821
-rw-r--r--drivers/video/via/lcd.h94
-rw-r--r--drivers/video/via/lcdtbl.h591
-rw-r--r--drivers/video/via/share.h1105
-rw-r--r--drivers/video/via/tbl1636.c71
-rw-r--r--drivers/video/via/tbl1636.h34
-rw-r--r--drivers/video/via/tblDPASetting.c109
-rw-r--r--drivers/video/via/tblDPASetting.h47
-rw-r--r--drivers/video/via/via_i2c.c177
-rw-r--r--drivers/video/via/via_i2c.h46
-rw-r--r--drivers/video/via/via_utility.c253
-rw-r--r--drivers/video/via/via_utility.h35
-rw-r--r--drivers/video/via/viafbdev.c2571
-rw-r--r--drivers/video/via/viafbdev.h112
-rw-r--r--drivers/video/via/viamode.c1086
-rw-r--r--drivers/video/via/viamode.h177
-rw-r--r--drivers/video/via/vt1636.c306
-rw-r--r--drivers/video/via/vt1636.h44
33 files changed, 14497 insertions, 0 deletions
diff --git a/drivers/video/via/Makefile b/drivers/video/via/Makefile
new file mode 100644
index 000000000000..e533b4b6aba4
--- /dev/null
+++ b/drivers/video/via/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for the VIA framebuffer driver (for Linux Kernel 2.6)
3#
4
5obj-$(CONFIG_FB_VIA) += viafb.o
6
7viafb-y :=viafbdev.o hw.o iface.o via_i2c.o dvi.o lcd.o ioctl.o accel.o via_utility.o vt1636.o global.o tblDPASetting.o viamode.o tbl1636.o
diff --git a/drivers/video/via/accel.c b/drivers/video/via/accel.c
new file mode 100644
index 000000000000..632523ff1fb7
--- /dev/null
+++ b/drivers/video/via/accel.c
@@ -0,0 +1,279 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include "global.h"
22
23void viafb_init_accel(void)
24{
25 viaparinfo->fbmem_free -= CURSOR_SIZE;
26 viaparinfo->cursor_start = viaparinfo->fbmem_free;
27 viaparinfo->fbmem_used += CURSOR_SIZE;
28
29 /* Reverse 8*1024 memory space for cursor image */
30 viaparinfo->fbmem_free -= (CURSOR_SIZE + VQ_SIZE);
31 viaparinfo->VQ_start = viaparinfo->fbmem_free;
32 viaparinfo->VQ_end = viaparinfo->VQ_start + VQ_SIZE - 1;
33 viaparinfo->fbmem_used += (CURSOR_SIZE + VQ_SIZE); }
34
35void viafb_init_2d_engine(void)
36{
37 u32 dwVQStartAddr, dwVQEndAddr;
38 u32 dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
39
40 /* init 2D engine regs to reset 2D engine */
41 writel(0x0, viaparinfo->io_virt + VIA_REG_GEMODE);
42 writel(0x0, viaparinfo->io_virt + VIA_REG_SRCPOS);
43 writel(0x0, viaparinfo->io_virt + VIA_REG_DSTPOS);
44 writel(0x0, viaparinfo->io_virt + VIA_REG_DIMENSION);
45 writel(0x0, viaparinfo->io_virt + VIA_REG_PATADDR);
46 writel(0x0, viaparinfo->io_virt + VIA_REG_FGCOLOR);
47 writel(0x0, viaparinfo->io_virt + VIA_REG_BGCOLOR);
48 writel(0x0, viaparinfo->io_virt + VIA_REG_CLIPTL);
49 writel(0x0, viaparinfo->io_virt + VIA_REG_CLIPBR);
50 writel(0x0, viaparinfo->io_virt + VIA_REG_OFFSET);
51 writel(0x0, viaparinfo->io_virt + VIA_REG_KEYCONTROL);
52 writel(0x0, viaparinfo->io_virt + VIA_REG_SRCBASE);
53 writel(0x0, viaparinfo->io_virt + VIA_REG_DSTBASE);
54 writel(0x0, viaparinfo->io_virt + VIA_REG_PITCH);
55 writel(0x0, viaparinfo->io_virt + VIA_REG_MONOPAT1);
56
57 /* Init AGP and VQ regs */
58 switch (viaparinfo->chip_info->gfx_chip_name) {
59 case UNICHROME_K8M890:
60 case UNICHROME_P4M900:
61 writel(0x00100000, viaparinfo->io_virt + VIA_REG_CR_TRANSET);
62 writel(0x680A0000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
63 writel(0x02000000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
64 break;
65
66 default:
67 writel(0x00100000, viaparinfo->io_virt + VIA_REG_TRANSET);
68 writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
69 writel(0x00333004, viaparinfo->io_virt + VIA_REG_TRANSPACE);
70 writel(0x60000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
71 writel(0x61000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
72 writel(0x62000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
73 writel(0x63000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
74 writel(0x64000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
75 writel(0x7D000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
76
77 writel(0xFE020000, viaparinfo->io_virt + VIA_REG_TRANSET);
78 writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
79 break;
80 }
81 if (viaparinfo->VQ_start != 0) {
82 /* Enable VQ */
83 dwVQStartAddr = viaparinfo->VQ_start;
84 dwVQEndAddr = viaparinfo->VQ_end;
85
86 dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
87 dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
88 dwVQStartEndH = 0x52000000 |
89 ((dwVQStartAddr & 0xFF000000) >> 24) |
90 ((dwVQEndAddr & 0xFF000000) >> 16);
91 dwVQLen = 0x53000000 | (VQ_SIZE >> 3);
92 switch (viaparinfo->chip_info->gfx_chip_name) {
93 case UNICHROME_K8M890:
94 case UNICHROME_P4M900:
95 dwVQStartL |= 0x20000000;
96 dwVQEndL |= 0x20000000;
97 dwVQStartEndH |= 0x20000000;
98 dwVQLen |= 0x20000000;
99 break;
100 default:
101 break;
102 }
103
104 switch (viaparinfo->chip_info->gfx_chip_name) {
105 case UNICHROME_K8M890:
106 case UNICHROME_P4M900:
107 writel(0x00100000,
108 viaparinfo->io_virt + VIA_REG_CR_TRANSET);
109 writel(dwVQStartEndH,
110 viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
111 writel(dwVQStartL,
112 viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
113 writel(dwVQEndL,
114 viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
115 writel(dwVQLen,
116 viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
117 writel(0x74301001,
118 viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
119 writel(0x00000000,
120 viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
121 break;
122 default:
123 writel(0x00FE0000,
124 viaparinfo->io_virt + VIA_REG_TRANSET);
125 writel(0x080003FE,
126 viaparinfo->io_virt + VIA_REG_TRANSPACE);
127 writel(0x0A00027C,
128 viaparinfo->io_virt + VIA_REG_TRANSPACE);
129 writel(0x0B000260,
130 viaparinfo->io_virt + VIA_REG_TRANSPACE);
131 writel(0x0C000274,
132 viaparinfo->io_virt + VIA_REG_TRANSPACE);
133 writel(0x0D000264,
134 viaparinfo->io_virt + VIA_REG_TRANSPACE);
135 writel(0x0E000000,
136 viaparinfo->io_virt + VIA_REG_TRANSPACE);
137 writel(0x0F000020,
138 viaparinfo->io_virt + VIA_REG_TRANSPACE);
139 writel(0x1000027E,
140 viaparinfo->io_virt + VIA_REG_TRANSPACE);
141 writel(0x110002FE,
142 viaparinfo->io_virt + VIA_REG_TRANSPACE);
143 writel(0x200F0060,
144 viaparinfo->io_virt + VIA_REG_TRANSPACE);
145
146 writel(0x00000006,
147 viaparinfo->io_virt + VIA_REG_TRANSPACE);
148 writel(0x40008C0F,
149 viaparinfo->io_virt + VIA_REG_TRANSPACE);
150 writel(0x44000000,
151 viaparinfo->io_virt + VIA_REG_TRANSPACE);
152 writel(0x45080C04,
153 viaparinfo->io_virt + VIA_REG_TRANSPACE);
154 writel(0x46800408,
155 viaparinfo->io_virt + VIA_REG_TRANSPACE);
156
157 writel(dwVQStartEndH,
158 viaparinfo->io_virt + VIA_REG_TRANSPACE);
159 writel(dwVQStartL,
160 viaparinfo->io_virt + VIA_REG_TRANSPACE);
161 writel(dwVQEndL,
162 viaparinfo->io_virt + VIA_REG_TRANSPACE);
163 writel(dwVQLen,
164 viaparinfo->io_virt + VIA_REG_TRANSPACE);
165 break;
166 }
167 } else {
168 /* Disable VQ */
169 switch (viaparinfo->chip_info->gfx_chip_name) {
170 case UNICHROME_K8M890:
171 case UNICHROME_P4M900:
172 writel(0x00100000,
173 viaparinfo->io_virt + VIA_REG_CR_TRANSET);
174 writel(0x74301000,
175 viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
176 break;
177 default:
178 writel(0x00FE0000,
179 viaparinfo->io_virt + VIA_REG_TRANSET);
180 writel(0x00000004,
181 viaparinfo->io_virt + VIA_REG_TRANSPACE);
182 writel(0x40008C0F,
183 viaparinfo->io_virt + VIA_REG_TRANSPACE);
184 writel(0x44000000,
185 viaparinfo->io_virt + VIA_REG_TRANSPACE);
186 writel(0x45080C04,
187 viaparinfo->io_virt + VIA_REG_TRANSPACE);
188 writel(0x46800408,
189 viaparinfo->io_virt + VIA_REG_TRANSPACE);
190 break;
191 }
192 }
193
194 viafb_set_2d_color_depth(viaparinfo->bpp);
195
196 writel(0x0, viaparinfo->io_virt + VIA_REG_SRCBASE);
197 writel(0x0, viaparinfo->io_virt + VIA_REG_DSTBASE);
198
199 writel(VIA_PITCH_ENABLE |
200 (((viaparinfo->hres *
201 viaparinfo->bpp >> 3) >> 3) | (((viaparinfo->hres *
202 viaparinfo->
203 bpp >> 3) >> 3) << 16)),
204 viaparinfo->io_virt + VIA_REG_PITCH);
205}
206
207void viafb_set_2d_color_depth(int bpp)
208{
209 u32 dwGEMode;
210
211 dwGEMode = readl(viaparinfo->io_virt + 0x04) & 0xFFFFFCFF;
212
213 switch (bpp) {
214 case 16:
215 dwGEMode |= VIA_GEM_16bpp;
216 break;
217 case 32:
218 dwGEMode |= VIA_GEM_32bpp;
219 break;
220 default:
221 dwGEMode |= VIA_GEM_8bpp;
222 break;
223 }
224
225 /* Set BPP and Pitch */
226 writel(dwGEMode, viaparinfo->io_virt + VIA_REG_GEMODE);
227}
228
229void viafb_hw_cursor_init(void)
230{
231 /* Set Cursor Image Base Address */
232 writel(viaparinfo->cursor_start,
233 viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
234 writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_POS);
235 writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_ORG);
236 writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_BG);
237 writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_FG);
238}
239
240void viafb_show_hw_cursor(struct fb_info *info, int Status)
241{
242 u32 temp;
243 u32 iga_path = ((struct viafb_par *)(info->par))->iga_path;
244
245 temp = readl(viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
246 switch (Status) {
247 case HW_Cursor_ON:
248 temp |= 0x1;
249 break;
250 case HW_Cursor_OFF:
251 temp &= 0xFFFFFFFE;
252 break;
253 }
254 switch (iga_path) {
255 case IGA2:
256 temp |= 0x80000000;
257 break;
258 case IGA1:
259 default:
260 temp &= 0x7FFFFFFF;
261 }
262 writel(temp, viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
263}
264
265int viafb_wait_engine_idle(void)
266{
267 int loop = 0;
268
269 while (!(readl(viaparinfo->io_virt + VIA_REG_STATUS) &
270 VIA_VR_QUEUE_BUSY) && (loop++ < MAXLOOP))
271 cpu_relax();
272
273 while ((readl(viaparinfo->io_virt + VIA_REG_STATUS) &
274 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
275 (loop++ < MAXLOOP))
276 cpu_relax();
277
278 return loop >= MAXLOOP;
279}
diff --git a/drivers/video/via/accel.h b/drivers/video/via/accel.h
new file mode 100644
index 000000000000..29bf854e8ccf
--- /dev/null
+++ b/drivers/video/via/accel.h
@@ -0,0 +1,169 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __ACCEL_H__
23#define __ACCEL_H__
24
25#define FB_ACCEL_VIA_UNICHROME 50
26
27/* MMIO Base Address Definition */
28#define MMIO_VGABASE 0x8000
29#define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
30#define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
31#define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
32#define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
33
34/* HW Cursor Status Define */
35#define HW_Cursor_ON 0
36#define HW_Cursor_OFF 1
37
38#define CURSOR_SIZE (8 * 1024)
39#define VQ_SIZE (256 * 1024)
40
41#define VIA_MMIO_BLTBASE 0x200000
42#define VIA_MMIO_BLTSIZE 0x200000
43
44/* Defines for 2D registers */
45#define VIA_REG_GECMD 0x000
46#define VIA_REG_GEMODE 0x004
47#define VIA_REG_SRCPOS 0x008
48#define VIA_REG_DSTPOS 0x00C
49/* width and height */
50#define VIA_REG_DIMENSION 0x010
51#define VIA_REG_PATADDR 0x014
52#define VIA_REG_FGCOLOR 0x018
53#define VIA_REG_BGCOLOR 0x01C
54/* top and left of clipping */
55#define VIA_REG_CLIPTL 0x020
56/* bottom and right of clipping */
57#define VIA_REG_CLIPBR 0x024
58#define VIA_REG_OFFSET 0x028
59/* color key control */
60#define VIA_REG_KEYCONTROL 0x02C
61#define VIA_REG_SRCBASE 0x030
62#define VIA_REG_DSTBASE 0x034
63/* pitch of src and dst */
64#define VIA_REG_PITCH 0x038
65#define VIA_REG_MONOPAT0 0x03C
66#define VIA_REG_MONOPAT1 0x040
67/* from 0x100 to 0x1ff */
68#define VIA_REG_COLORPAT 0x100
69
70/* VIA_REG_PITCH(0x38): Pitch Setting */
71#define VIA_PITCH_ENABLE 0x80000000
72
73/* defines for VIA HW cursor registers */
74#define VIA_REG_CURSOR_MODE 0x2D0
75#define VIA_REG_CURSOR_POS 0x2D4
76#define VIA_REG_CURSOR_ORG 0x2D8
77#define VIA_REG_CURSOR_BG 0x2DC
78#define VIA_REG_CURSOR_FG 0x2E0
79
80/* VIA_REG_GEMODE(0x04): GE mode */
81#define VIA_GEM_8bpp 0x00000000
82#define VIA_GEM_16bpp 0x00000100
83#define VIA_GEM_32bpp 0x00000300
84
85/* VIA_REG_GECMD(0x00): 2D Engine Command */
86#define VIA_GEC_NOOP 0x00000000
87#define VIA_GEC_BLT 0x00000001
88#define VIA_GEC_LINE 0x00000005
89
90/* Rotate Command */
91#define VIA_GEC_ROT 0x00000008
92
93#define VIA_GEC_SRC_XY 0x00000000
94#define VIA_GEC_SRC_LINEAR 0x00000010
95#define VIA_GEC_DST_XY 0x00000000
96#define VIA_GEC_DST_LINRAT 0x00000020
97
98#define VIA_GEC_SRC_FB 0x00000000
99#define VIA_GEC_SRC_SYS 0x00000040
100#define VIA_GEC_DST_FB 0x00000000
101#define VIA_GEC_DST_SYS 0x00000080
102
103/* source is mono */
104#define VIA_GEC_SRC_MONO 0x00000100
105/* pattern is mono */
106#define VIA_GEC_PAT_MONO 0x00000200
107/* mono src is opaque */
108#define VIA_GEC_MSRC_OPAQUE 0x00000000
109/* mono src is transparent */
110#define VIA_GEC_MSRC_TRANS 0x00000400
111/* pattern is in frame buffer */
112#define VIA_GEC_PAT_FB 0x00000000
113/* pattern is from reg setting */
114#define VIA_GEC_PAT_REG 0x00000800
115
116#define VIA_GEC_CLIP_DISABLE 0x00000000
117#define VIA_GEC_CLIP_ENABLE 0x00001000
118
119#define VIA_GEC_FIXCOLOR_PAT 0x00002000
120
121#define VIA_GEC_INCX 0x00000000
122#define VIA_GEC_DECY 0x00004000
123#define VIA_GEC_INCY 0x00000000
124#define VIA_GEC_DECX 0x00008000
125/* mono pattern is opaque */
126#define VIA_GEC_MPAT_OPAQUE 0x00000000
127/* mono pattern is transparent */
128#define VIA_GEC_MPAT_TRANS 0x00010000
129
130#define VIA_GEC_MONO_UNPACK 0x00000000
131#define VIA_GEC_MONO_PACK 0x00020000
132#define VIA_GEC_MONO_DWORD 0x00000000
133#define VIA_GEC_MONO_WORD 0x00040000
134#define VIA_GEC_MONO_BYTE 0x00080000
135
136#define VIA_GEC_LASTPIXEL_ON 0x00000000
137#define VIA_GEC_LASTPIXEL_OFF 0x00100000
138#define VIA_GEC_X_MAJOR 0x00000000
139#define VIA_GEC_Y_MAJOR 0x00200000
140#define VIA_GEC_QUICK_START 0x00800000
141
142/* defines for VIA 3D registers */
143#define VIA_REG_STATUS 0x400
144#define VIA_REG_CR_TRANSET 0x41C
145#define VIA_REG_CR_TRANSPACE 0x420
146#define VIA_REG_TRANSET 0x43C
147#define VIA_REG_TRANSPACE 0x440
148
149/* VIA_REG_STATUS(0x400): Engine Status */
150
151/* Command Regulator is busy */
152#define VIA_CMD_RGTR_BUSY 0x00000080
153/* 2D Engine is busy */
154#define VIA_2D_ENG_BUSY 0x00000002
155/* 3D Engine is busy */
156#define VIA_3D_ENG_BUSY 0x00000001
157/* Virtual Queue is busy */
158#define VIA_VR_QUEUE_BUSY 0x00020000
159
160#define MAXLOOP 0xFFFFFF
161
162void viafb_init_accel(void);
163void viafb_init_2d_engine(void);
164void set_2d_color_depth(int);
165void viafb_hw_cursor_init(void);
166void viafb_show_hw_cursor(struct fb_info *info, int Status); int
167viafb_wait_engine_idle(void); void viafb_set_2d_color_depth(int bpp);
168
169#endif /* __ACCEL_H__ */
diff --git a/drivers/video/via/chip.h b/drivers/video/via/chip.h
new file mode 100644
index 000000000000..dde95edc387a
--- /dev/null
+++ b/drivers/video/via/chip.h
@@ -0,0 +1,190 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __CHIP_H__
22#define __CHIP_H__
23
24#include "global.h"
25
26/***************************************/
27/* Definition Graphic Chip Information */
28/***************************************/
29
30#define PCI_VIA_VENDOR_ID 0x1106
31
32/* Define VIA Graphic Chip Name */
33#define UNICHROME_CLE266 1
34#define UNICHROME_CLE266_DID 0x3122
35#define CLE266_REVISION_AX 0x0A
36#define CLE266_REVISION_CX 0x0C
37
38#define UNICHROME_K400 2
39#define UNICHROME_K400_DID 0x7205
40
41#define UNICHROME_K800 3
42#define UNICHROME_K800_DID 0x3108
43
44#define UNICHROME_PM800 4
45#define UNICHROME_PM800_DID 0x3118
46
47#define UNICHROME_CN700 5
48#define UNICHROME_CN700_DID 0x3344
49
50#define UNICHROME_CX700 6
51#define UNICHROME_CX700_DID 0x3157
52#define CX700_REVISION_700 0x0
53#define CX700_REVISION_700M 0x1
54#define CX700_REVISION_700M2 0x2
55
56#define UNICHROME_CN750 7
57#define UNICHROME_CN750_DID 0x3225
58
59#define UNICHROME_K8M890 8
60#define UNICHROME_K8M890_DID 0x3230
61
62#define UNICHROME_P4M890 9
63#define UNICHROME_P4M890_DID 0x3343
64
65#define UNICHROME_P4M900 10
66#define UNICHROME_P4M900_DID 0x3371
67
68#define UNICHROME_VX800 11
69#define UNICHROME_VX800_DID 0x1122
70
71/**************************************************/
72/* Definition TMDS Trasmitter Information */
73/**************************************************/
74
75/* Definition TMDS Trasmitter Index */
76#define NON_TMDS_TRANSMITTER 0x00
77#define VT1632_TMDS 0x01
78#define INTEGRATED_TMDS 0x42
79
80/* Definition TMDS Trasmitter I2C Slave Address */
81#define VT1632_TMDS_I2C_ADDR 0x10
82
83/**************************************************/
84/* Definition LVDS Trasmitter Information */
85/**************************************************/
86
87/* Definition LVDS Trasmitter Index */
88#define NON_LVDS_TRANSMITTER 0x00
89#define VT1631_LVDS 0x01
90#define VT1636_LVDS 0x0E
91#define INTEGRATED_LVDS 0x41
92
93/* Definition Digital Transmitter Mode */
94#define TX_DATA_12_BITS 0x01
95#define TX_DATA_24_BITS 0x02
96#define TX_DATA_DDR_MODE 0x04
97#define TX_DATA_SDR_MODE 0x08
98
99/* Definition LVDS Trasmitter I2C Slave Address */
100#define VT1631_LVDS_I2C_ADDR 0x70
101#define VT3271_LVDS_I2C_ADDR 0x80
102#define VT1636_LVDS_I2C_ADDR 0x80
103
104struct tmds_chip_information {
105 int tmds_chip_name;
106 int tmds_chip_slave_addr;
107 int dvi_panel_id;
108 int data_mode;
109 int output_interface;
110 int i2c_port;
111 int device_type;
112};
113
114struct lvds_chip_information {
115 int lvds_chip_name;
116 int lvds_chip_slave_addr;
117 int data_mode;
118 int output_interface;
119 int i2c_port;
120};
121
122struct chip_information {
123 int gfx_chip_name;
124 int gfx_chip_revision;
125 int chip_on_slot;
126 struct tmds_chip_information tmds_chip_info;
127 struct lvds_chip_information lvds_chip_info;
128 struct lvds_chip_information lvds_chip_info2;
129};
130
131struct crt_setting_information {
132 int iga_path;
133 int h_active;
134 int v_active;
135 int bpp;
136 int refresh_rate;
137};
138
139struct tmds_setting_information {
140 int iga_path;
141 int h_active;
142 int v_active;
143 int bpp;
144 int refresh_rate;
145 int get_dvi_size_method;
146 int max_pixel_clock;
147 int dvi_panel_size;
148 int dvi_panel_hres;
149 int dvi_panel_vres;
150 int native_size;
151};
152
153struct lvds_setting_information {
154 int iga_path;
155 int h_active;
156 int v_active;
157 int bpp;
158 int refresh_rate;
159 int get_lcd_size_method;
160 int lcd_panel_id;
161 int lcd_panel_size;
162 int lcd_panel_hres;
163 int lcd_panel_vres;
164 int display_method;
165 int device_lcd_dualedge;
166 int LCDDithering;
167 int lcd_mode;
168 u32 vclk; /*panel mode clock value */
169};
170
171struct GFX_DPA_SETTING {
172 int ClkRangeIndex;
173 u8 DVP0; /* CR96[3:0] */
174 u8 DVP0DataDri_S1; /* SR2A[5] */
175 u8 DVP0DataDri_S; /* SR1B[1] */
176 u8 DVP0ClockDri_S1; /* SR2A[4] */
177 u8 DVP0ClockDri_S; /* SR1E[2] */
178 u8 DVP1; /* CR9B[3:0] */
179 u8 DVP1Driving; /* SR65[3:0], Data and Clock driving */
180 u8 DFPHigh; /* CR97[3:0] */
181 u8 DFPLow; /* CR99[3:0] */
182
183};
184
185struct VT1636_DPA_SETTING {
186 int PanelSizeID;
187 u8 CLK_SEL_ST1;
188 u8 CLK_SEL_ST2;
189};
190#endif /* __CHIP_H__ */
diff --git a/drivers/video/via/debug.h b/drivers/video/via/debug.h
new file mode 100644
index 000000000000..86eacc2017f3
--- /dev/null
+++ b/drivers/video/via/debug.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __DEBUG_H__
22#define __DEBUG_H__
23
24#ifndef VIAFB_DEBUG
25#define VIAFB_DEBUG 0
26#endif
27
28#if VIAFB_DEBUG
29#define DEBUG_MSG(f, a...) printk(f, ## a)
30#else
31#define DEBUG_MSG(f, a...)
32#endif
33
34#define VIAFB_WARN 0
35#if VIAFB_WARN
36#define WARN_MSG(f, a...) printk(f, ## a)
37#else
38#define WARN_MSG(f, a...)
39#endif
40
41#endif /* __DEBUG_H__ */
diff --git a/drivers/video/via/dvi.c b/drivers/video/via/dvi.c
new file mode 100644
index 000000000000..d6965447ca69
--- /dev/null
+++ b/drivers/video/via/dvi.c
@@ -0,0 +1,682 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include "global.h"
22
23static void tmds_register_write(int index, u8 data);
24static int tmds_register_read(int index);
25static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
26static int check_reduce_blanking_mode(int mode_index,
27 int refresh_rate);
28static int dvi_get_panel_size_from_DDCv1(void);
29static int dvi_get_panel_size_from_DDCv2(void);
30static unsigned char dvi_get_panel_info(void);
31static int viafb_dvi_query_EDID(void);
32
33static int check_tmds_chip(int device_id_subaddr, int device_id)
34{
35 if (tmds_register_read(device_id_subaddr) == device_id)
36 return OK;
37 else
38 return FAIL;
39}
40
41void viafb_init_dvi_size(void)
42{
43 DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
44 DEBUG_MSG(KERN_INFO
45 "viaparinfo->tmds_setting_info->get_dvi_size_method %d\n",
46 viaparinfo->tmds_setting_info->get_dvi_size_method);
47
48 switch (viaparinfo->tmds_setting_info->get_dvi_size_method) {
49 case GET_DVI_SIZE_BY_SYSTEM_BIOS:
50 break;
51 case GET_DVI_SZIE_BY_HW_STRAPPING:
52 break;
53 case GET_DVI_SIZE_BY_VGA_BIOS:
54 default:
55 dvi_get_panel_info();
56 break;
57 }
58 return;
59}
60
61int viafb_tmds_trasmitter_identify(void)
62{
63 unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
64
65 /* Turn on ouputting pad */
66 switch (viaparinfo->chip_info->gfx_chip_name) {
67 case UNICHROME_K8M890:
68 /*=* DFP Low Pad on *=*/
69 sr2a = viafb_read_reg(VIASR, SR2A);
70 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
71 break;
72
73 case UNICHROME_P4M900:
74 case UNICHROME_P4M890:
75 /* DFP Low Pad on */
76 sr2a = viafb_read_reg(VIASR, SR2A);
77 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
78 /* DVP0 Pad on */
79 sr1e = viafb_read_reg(VIASR, SR1E);
80 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
81 break;
82
83 default:
84 /* DVP0/DVP1 Pad on */
85 sr1e = viafb_read_reg(VIASR, SR1E);
86 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
87 BIT5 + BIT6 + BIT7);
88 /* SR3E[1]Multi-function selection:
89 0 = Emulate I2C and DDC bus by GPIO2/3/4. */
90 sr3e = viafb_read_reg(VIASR, SR3E);
91 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
92 break;
93 }
94
95 /* Check for VT1632: */
96 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS;
97 viaparinfo->chip_info->
98 tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
99 viaparinfo->chip_info->tmds_chip_info.i2c_port = I2CPORTINDEX;
100 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID) != FAIL) {
101 /*
102 * Currently only support 12bits,dual edge,add 24bits mode later
103 */
104 tmds_register_write(0x08, 0x3b);
105
106 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
107 DEBUG_MSG(KERN_INFO "\n %2d",
108 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
109 DEBUG_MSG(KERN_INFO "\n %2d",
110 viaparinfo->chip_info->tmds_chip_info.i2c_port);
111 return OK;
112 } else {
113 viaparinfo->chip_info->tmds_chip_info.i2c_port = GPIOPORTINDEX;
114 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)
115 != FAIL) {
116 tmds_register_write(0x08, 0x3b);
117 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
118 DEBUG_MSG(KERN_INFO "\n %2d",
119 viaparinfo->chip_info->
120 tmds_chip_info.tmds_chip_name);
121 DEBUG_MSG(KERN_INFO "\n %2d",
122 viaparinfo->chip_info->
123 tmds_chip_info.i2c_port);
124 return OK;
125 }
126 }
127
128 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS;
129
130 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) &&
131 ((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) ||
132 (viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) {
133 DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n");
134 return OK;
135 }
136
137 switch (viaparinfo->chip_info->gfx_chip_name) {
138 case UNICHROME_K8M890:
139 viafb_write_reg(SR2A, VIASR, sr2a);
140 break;
141
142 case UNICHROME_P4M900:
143 case UNICHROME_P4M890:
144 viafb_write_reg(SR2A, VIASR, sr2a);
145 viafb_write_reg(SR1E, VIASR, sr1e);
146 break;
147
148 default:
149 viafb_write_reg(SR1E, VIASR, sr1e);
150 viafb_write_reg(SR3E, VIASR, sr3e);
151 break;
152 }
153
154 viaparinfo->chip_info->
155 tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER;
156 viaparinfo->chip_info->tmds_chip_info.
157 tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
158 return FAIL;
159}
160
161static void tmds_register_write(int index, u8 data)
162{
163 viaparinfo->i2c_stuff.i2c_port =
164 viaparinfo->chip_info->tmds_chip_info.i2c_port;
165
166 viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.
167 tmds_chip_slave_addr, index,
168 data);
169}
170
171static int tmds_register_read(int index)
172{
173 u8 data;
174
175 viaparinfo->i2c_stuff.i2c_port =
176 viaparinfo->chip_info->tmds_chip_info.i2c_port;
177 viafb_i2c_readbyte((u8) viaparinfo->chip_info->
178 tmds_chip_info.tmds_chip_slave_addr,
179 (u8) index, &data);
180 return data;
181}
182
183static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
184{
185 viaparinfo->i2c_stuff.i2c_port =
186 viaparinfo->chip_info->tmds_chip_info.i2c_port;
187 viafb_i2c_readbytes((u8) viaparinfo->chip_info->tmds_chip_info.
188 tmds_chip_slave_addr, (u8) index, buff, buff_len);
189 return 0;
190}
191
192static int check_reduce_blanking_mode(int mode_index,
193 int refresh_rate)
194{
195 if (refresh_rate != 60)
196 return false;
197
198 switch (mode_index) {
199 /* Following modes have reduce blanking mode. */
200 case VIA_RES_1360X768:
201 case VIA_RES_1400X1050:
202 case VIA_RES_1440X900:
203 case VIA_RES_1600X900:
204 case VIA_RES_1680X1050:
205 case VIA_RES_1920X1080:
206 case VIA_RES_1920X1200:
207 break;
208
209 default:
210 DEBUG_MSG(KERN_INFO
211 "This dvi mode %d have no reduce blanking mode!\n",
212 mode_index);
213 return false;
214 }
215
216 return true;
217}
218
219/* DVI Set Mode */
220void viafb_dvi_set_mode(int video_index, int mode_bpp, int set_iga)
221{
222 struct VideoModeTable *videoMode = NULL;
223 struct crt_mode_table *pDviTiming;
224 unsigned long desirePixelClock, maxPixelClock;
225 int status = 0;
226 videoMode = viafb_get_modetbl_pointer(video_index);
227 pDviTiming = videoMode->crtc;
228 desirePixelClock = pDviTiming->clk / 1000000;
229 maxPixelClock = (unsigned long)viaparinfo->
230 tmds_setting_info->max_pixel_clock;
231
232 DEBUG_MSG(KERN_INFO "\nDVI_set_mode!!\n");
233
234 if ((maxPixelClock != 0) && (desirePixelClock > maxPixelClock)) {
235 /*Check if reduce-blanking mode is exist */
236 status =
237 check_reduce_blanking_mode(video_index,
238 pDviTiming->refresh_rate);
239 if (status) {
240 video_index += 100; /*Use reduce-blanking mode */
241 videoMode = viafb_get_modetbl_pointer(video_index);
242 pDviTiming = videoMode->crtc;
243 DEBUG_MSG(KERN_INFO
244 "DVI use reduce blanking mode %d!!\n",
245 video_index);
246 }
247 }
248 viafb_fill_crtc_timing(pDviTiming, video_index, mode_bpp / 8, set_iga);
249 viafb_set_output_path(DEVICE_DVI, set_iga,
250 viaparinfo->chip_info->tmds_chip_info.output_interface);
251}
252
253/* Sense DVI Connector */
254int viafb_dvi_sense(void)
255{
256 u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,
257 RegCR93 = 0, RegCR9B = 0, data;
258 int ret = false;
259
260 DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n");
261
262 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
263 /* DI1 Pad on */
264 RegSR1E = viafb_read_reg(VIASR, SR1E);
265 viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);
266
267 /* CR6B[0]VCK Input Selection: 1 = External clock. */
268 RegCR6B = viafb_read_reg(VIACR, CR6B);
269 viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);
270
271 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
272 [0] Software Control Power Sequence */
273 RegCR91 = viafb_read_reg(VIACR, CR91);
274 viafb_write_reg(CR91, VIACR, 0x1D);
275
276 /* CR93[7] DI1 Data Source Selection: 1 = DSP2.
277 CR93[5] DI1 Clock Source: 1 = internal.
278 CR93[4] DI1 Clock Polarity.
279 CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */
280 RegCR93 = viafb_read_reg(VIACR, CR93);
281 viafb_write_reg(CR93, VIACR, 0x01);
282 } else {
283 /* DVP0/DVP1 Pad on */
284 RegSR1E = viafb_read_reg(VIASR, SR1E);
285 viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);
286
287 /* SR3E[1]Multi-function selection:
288 0 = Emulate I2C and DDC bus by GPIO2/3/4. */
289 RegSR3E = viafb_read_reg(VIASR, SR3E);
290 viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));
291
292 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
293 [0] Software Control Power Sequence */
294 RegCR91 = viafb_read_reg(VIACR, CR91);
295 viafb_write_reg(CR91, VIACR, 0x1D);
296
297 /*CR9B[4] DVP1 Data Source Selection: 1 = From secondary
298 display.CR9B[2:0] DVP1 Clock Adjust */
299 RegCR9B = viafb_read_reg(VIACR, CR9B);
300 viafb_write_reg(CR9B, VIACR, 0x01);
301 }
302
303 data = (u8) tmds_register_read(0x09);
304 if (data & 0x04)
305 ret = true;
306
307 if (ret == false) {
308 if (viafb_dvi_query_EDID())
309 ret = true;
310 }
311
312 /* Restore status */
313 viafb_write_reg(SR1E, VIASR, RegSR1E);
314 viafb_write_reg(CR91, VIACR, RegCR91);
315 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
316 viafb_write_reg(CR6B, VIACR, RegCR6B);
317 viafb_write_reg(CR93, VIACR, RegCR93);
318 } else {
319 viafb_write_reg(SR3E, VIASR, RegSR3E);
320 viafb_write_reg(CR9B, VIACR, RegCR9B);
321 }
322
323 return ret;
324}
325
326/* Query Flat Panel's EDID Table Version Through DVI Connector */
327static int viafb_dvi_query_EDID(void)
328{
329 u8 data0, data1;
330 int restore;
331
332 DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");
333
334 restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
335 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
336
337 data0 = (u8) tmds_register_read(0x00);
338 data1 = (u8) tmds_register_read(0x01);
339 if ((data0 == 0) && (data1 == 0xFF)) {
340 viaparinfo->chip_info->
341 tmds_chip_info.tmds_chip_slave_addr = restore;
342 return EDID_VERSION_1; /* Found EDID1 Table */
343 }
344
345 data0 = (u8) tmds_register_read(0x00);
346 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
347 if (data0 == 0x20)
348 return EDID_VERSION_2; /* Found EDID2 Table */
349 else
350 return false;
351}
352
353/*
354 *
355 * int dvi_get_panel_size_from_DDCv1(void)
356 *
357 * - Get Panel Size Using EDID1 Table
358 *
359 * Return Type: int
360 *
361 */
362static int dvi_get_panel_size_from_DDCv1(void)
363{
364 int i, max_h = 0, max_v = 0, tmp, restore;
365 unsigned char rData;
366 unsigned char EDID_DATA[18];
367
368 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
369
370 restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
371 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
372
373 rData = tmds_register_read(0x23);
374 if (rData & 0x3C)
375 max_h = 640;
376 if (rData & 0xC0)
377 max_h = 720;
378 if (rData & 0x03)
379 max_h = 800;
380
381 rData = tmds_register_read(0x24);
382 if (rData & 0xC0)
383 max_h = 800;
384 if (rData & 0x1E)
385 max_h = 1024;
386 if (rData & 0x01)
387 max_h = 1280;
388
389 for (i = 0x25; i < 0x6D; i++) {
390 switch (i) {
391 case 0x26:
392 case 0x28:
393 case 0x2A:
394 case 0x2C:
395 case 0x2E:
396 case 0x30:
397 case 0x32:
398 case 0x34:
399 rData = tmds_register_read(i);
400 if (rData == 1)
401 break;
402 /* data = (data + 31) * 8 */
403 tmp = (rData + 31) << 3;
404 if (tmp > max_h)
405 max_h = tmp;
406 break;
407
408 case 0x36:
409 case 0x48:
410 case 0x5A:
411 case 0x6C:
412 tmds_register_read_bytes(i, EDID_DATA, 10);
413 if (!(EDID_DATA[0] || EDID_DATA[1])) {
414 /* The first two byte must be zero. */
415 if (EDID_DATA[3] == 0xFD) {
416 /* To get max pixel clock. */
417 viaparinfo->tmds_setting_info->
418 max_pixel_clock = EDID_DATA[9] * 10;
419 }
420 }
421 break;
422
423 default:
424 break;
425 }
426 }
427
428 switch (max_h) {
429 case 640:
430 viaparinfo->tmds_setting_info->dvi_panel_size =
431 VIA_RES_640X480;
432 break;
433 case 800:
434 viaparinfo->tmds_setting_info->dvi_panel_size =
435 VIA_RES_800X600;
436 break;
437 case 1024:
438 viaparinfo->tmds_setting_info->dvi_panel_size =
439 VIA_RES_1024X768;
440 break;
441 case 1280:
442 viaparinfo->tmds_setting_info->dvi_panel_size =
443 VIA_RES_1280X1024;
444 break;
445 case 1400:
446 viaparinfo->tmds_setting_info->dvi_panel_size =
447 VIA_RES_1400X1050;
448 break;
449 case 1440:
450 viaparinfo->tmds_setting_info->dvi_panel_size =
451 VIA_RES_1440X1050;
452 break;
453 case 1600:
454 viaparinfo->tmds_setting_info->dvi_panel_size =
455 VIA_RES_1600X1200;
456 break;
457 case 1920:
458 if (max_v == 1200) {
459 viaparinfo->tmds_setting_info->dvi_panel_size =
460 VIA_RES_1920X1200;
461 } else {
462 viaparinfo->tmds_setting_info->dvi_panel_size =
463 VIA_RES_1920X1080;
464 }
465
466 break;
467 default:
468 viaparinfo->tmds_setting_info->dvi_panel_size =
469 VIA_RES_1024X768;
470 DEBUG_MSG(KERN_INFO "Unknow panel size max resolution = %d !\
471 set default panel size.\n", max_h);
472 break;
473 }
474
475 DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
476 viaparinfo->tmds_setting_info->max_pixel_clock);
477 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
478 return viaparinfo->tmds_setting_info->dvi_panel_size;
479}
480
481/*
482 *
483 * int dvi_get_panel_size_from_DDCv2(void)
484 *
485 * - Get Panel Size Using EDID2 Table
486 *
487 * Return Type: int
488 *
489 */
490static int dvi_get_panel_size_from_DDCv2(void)
491{
492 int HSize = 0, restore;
493 unsigned char R_Buffer[2];
494
495 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv2 \n");
496
497 restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
498 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA2;
499
500 /* Horizontal: 0x76, 0x77 */
501 tmds_register_read_bytes(0x76, R_Buffer, 2);
502 HSize = R_Buffer[0];
503 HSize += R_Buffer[1] << 8;
504
505 switch (HSize) {
506 case 640:
507 viaparinfo->tmds_setting_info->dvi_panel_size =
508 VIA_RES_640X480;
509 break;
510 case 800:
511 viaparinfo->tmds_setting_info->dvi_panel_size =
512 VIA_RES_800X600;
513 break;
514 case 1024:
515 viaparinfo->tmds_setting_info->dvi_panel_size =
516 VIA_RES_1024X768;
517 break;
518 case 1280:
519 viaparinfo->tmds_setting_info->dvi_panel_size =
520 VIA_RES_1280X1024;
521 break;
522 case 1400:
523 viaparinfo->tmds_setting_info->dvi_panel_size =
524 VIA_RES_1400X1050;
525 break;
526 case 1440:
527 viaparinfo->tmds_setting_info->dvi_panel_size =
528 VIA_RES_1440X1050;
529 break;
530 case 1600:
531 viaparinfo->tmds_setting_info->dvi_panel_size =
532 VIA_RES_1600X1200;
533 break;
534 default:
535 viaparinfo->tmds_setting_info->dvi_panel_size =
536 VIA_RES_1024X768;
537 DEBUG_MSG(KERN_INFO "Unknow panel size max resolution = %d!\
538 set default panel size.\n", HSize);
539 break;
540 }
541
542 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
543 return viaparinfo->tmds_setting_info->dvi_panel_size;
544}
545
546/*
547 *
548 * unsigned char dvi_get_panel_info(void)
549 *
550 * - Get Panel Size
551 *
552 * Return Type: unsigned char
553 */
554static unsigned char dvi_get_panel_info(void)
555{
556 unsigned char dvipanelsize;
557 DEBUG_MSG(KERN_INFO "dvi_get_panel_info! \n");
558
559 viafb_dvi_sense();
560 switch (viafb_dvi_query_EDID()) {
561 case 1:
562 dvi_get_panel_size_from_DDCv1();
563 break;
564 case 2:
565 dvi_get_panel_size_from_DDCv2();
566 break;
567 default:
568 break;
569 }
570
571 DEBUG_MSG(KERN_INFO "dvi panel size is %2d \n",
572 viaparinfo->tmds_setting_info->dvi_panel_size);
573 dvipanelsize = (unsigned char)(viaparinfo->
574 tmds_setting_info->dvi_panel_size);
575 return dvipanelsize;
576}
577
578/* If Disable DVI, turn off pad */
579void viafb_dvi_disable(void)
580{
581 if (viaparinfo->chip_info->
582 tmds_chip_info.output_interface == INTERFACE_DVP0)
583 viafb_write_reg(SR1E, VIASR,
584 viafb_read_reg(VIASR, SR1E) & (~0xC0));
585
586 if (viaparinfo->chip_info->
587 tmds_chip_info.output_interface == INTERFACE_DVP1)
588 viafb_write_reg(SR1E, VIASR,
589 viafb_read_reg(VIASR, SR1E) & (~0x30));
590
591 if (viaparinfo->chip_info->
592 tmds_chip_info.output_interface == INTERFACE_DFP_HIGH)
593 viafb_write_reg(SR2A, VIASR,
594 viafb_read_reg(VIASR, SR2A) & (~0x0C));
595
596 if (viaparinfo->chip_info->
597 tmds_chip_info.output_interface == INTERFACE_DFP_LOW)
598 viafb_write_reg(SR2A, VIASR,
599 viafb_read_reg(VIASR, SR2A) & (~0x03));
600
601 if (viaparinfo->chip_info->
602 tmds_chip_info.output_interface == INTERFACE_TMDS)
603 /* Turn off TMDS power. */
604 viafb_write_reg(CRD2, VIACR,
605 viafb_read_reg(VIACR, CRD2) | 0x08);
606}
607
608/* If Enable DVI, turn off pad */
609void viafb_dvi_enable(void)
610{
611 u8 data;
612
613 if (viaparinfo->chip_info->
614 tmds_chip_info.output_interface == INTERFACE_DVP0) {
615 viafb_write_reg(SR1E, VIASR,
616 viafb_read_reg(VIASR, SR1E) | 0xC0);
617 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
618 tmds_register_write(0x88, 0x3b);
619 else
620 /*clear CR91[5] to direct on display period
621 in the secondary diplay path */
622 viafb_write_reg(CR91, VIACR,
623 viafb_read_reg(VIACR, CR91) & 0xDF);
624 }
625
626 if (viaparinfo->chip_info->
627 tmds_chip_info.output_interface == INTERFACE_DVP1) {
628 viafb_write_reg(SR1E, VIASR,
629 viafb_read_reg(VIASR, SR1E) | 0x30);
630
631 /*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
632 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
633 tmds_register_write(0x88, 0x3b);
634 } else {
635 /*clear CR91[5] to direct on display period
636 in the secondary diplay path */
637 viafb_write_reg(CR91, VIACR,
638 viafb_read_reg(VIACR, CR91) & 0xDF);
639 }
640
641 /*fix DVI cannot enable on EPIA-M board */
642 if (viafb_platform_epia_dvi == 1) {
643 viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
644 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
645 if (viafb_bus_width == 24) {
646 if (viafb_device_lcd_dualedge == 1)
647 data = 0x3F;
648 else
649 data = 0x37;
650 viafb_i2c_writebyte(viaparinfo->chip_info->
651 tmds_chip_info.
652 tmds_chip_slave_addr,
653 0x08, data);
654 }
655 }
656 }
657
658 if (viaparinfo->chip_info->
659 tmds_chip_info.output_interface == INTERFACE_DFP_HIGH) {
660 viafb_write_reg(SR2A, VIASR,
661 viafb_read_reg(VIASR, SR2A) | 0x0C);
662 viafb_write_reg(CR91, VIACR,
663 viafb_read_reg(VIACR, CR91) & 0xDF);
664 }
665
666 if (viaparinfo->chip_info->
667 tmds_chip_info.output_interface == INTERFACE_DFP_LOW) {
668 viafb_write_reg(SR2A, VIASR,
669 viafb_read_reg(VIASR, SR2A) | 0x03);
670 viafb_write_reg(CR91, VIACR,
671 viafb_read_reg(VIACR, CR91) & 0xDF);
672 }
673 if (viaparinfo->chip_info->
674 tmds_chip_info.output_interface == INTERFACE_TMDS) {
675 /* Turn on Display period in the panel path. */
676 viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
677
678 /* Turn on TMDS power. */
679 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
680 }
681}
682
diff --git a/drivers/video/via/dvi.h b/drivers/video/via/dvi.h
new file mode 100644
index 000000000000..e1ec37fb0dc3
--- /dev/null
+++ b/drivers/video/via/dvi.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __DVI_H__
23#define __DVI_H__
24
25/*Definition TMDS Device ID register*/
26#define VT1632_DEVICE_ID_REG 0x02
27#define VT1632_DEVICE_ID 0x92
28
29#define GET_DVI_SIZE_BY_SYSTEM_BIOS 0x01
30#define GET_DVI_SIZE_BY_VGA_BIOS 0x02
31#define GET_DVI_SZIE_BY_HW_STRAPPING 0x03
32
33/* Definition DVI Panel ID*/
34/* Resolution: 640x480, Channel: single, Dithering: Enable */
35#define DVI_PANEL_ID0_640X480 0x00
36/* Resolution: 800x600, Channel: single, Dithering: Enable */
37#define DVI_PANEL_ID1_800x600 0x01
38/* Resolution: 1024x768, Channel: single, Dithering: Enable */
39#define DVI_PANEL_ID1_1024x768 0x02
40/* Resolution: 1280x768, Channel: single, Dithering: Enable */
41#define DVI_PANEL_ID1_1280x768 0x03
42/* Resolution: 1280x1024, Channel: dual, Dithering: Enable */
43#define DVI_PANEL_ID1_1280x1024 0x04
44/* Resolution: 1400x1050, Channel: dual, Dithering: Enable */
45#define DVI_PANEL_ID1_1400x1050 0x05
46/* Resolution: 1600x1200, Channel: dual, Dithering: Enable */
47#define DVI_PANEL_ID1_1600x1200 0x06
48
49/* Define the version of EDID*/
50#define EDID_VERSION_1 1
51#define EDID_VERSION_2 2
52
53#define DEV_CONNECT_DVI 0x01
54#define DEV_CONNECT_HDMI 0x02
55
56struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index);
57int viafb_dvi_sense(void);
58void viafb_dvi_disable(void);
59void viafb_dvi_enable(void);
60int viafb_tmds_trasmitter_identify(void);
61void viafb_init_dvi_size(void);
62void viafb_dvi_set_mode(int video_index, int mode_bpp, int set_iga);
63
64#endif /* __DVI_H__ */
diff --git a/drivers/video/via/global.c b/drivers/video/via/global.c
new file mode 100644
index 000000000000..468be2425af3
--- /dev/null
+++ b/drivers/video/via/global.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include "global.h"
22int viafb_platform_epia_dvi = STATE_OFF;
23int viafb_device_lcd_dualedge = STATE_OFF;
24int viafb_bus_width = 12;
25int viafb_display_hardware_layout = HW_LAYOUT_LCD_DVI;
26int viafb_memsize;
27int viafb_DeviceStatus = CRT_Device;
28int viafb_hotplug;
29int viafb_refresh = 60;
30int viafb_refresh1 = 60;
31int viafb_lcd_dsp_method = LCD_EXPANDSION;
32int viafb_lcd_mode = LCD_OPENLDI;
33int viafb_bpp = 32;
34int viafb_bpp1 = 32;
35int viafb_accel = 1;
36int viafb_CRT_ON = 1;
37int viafb_DVI_ON;
38int viafb_LCD_ON ;
39int viafb_LCD2_ON;
40int viafb_SAMM_ON;
41int viafb_dual_fb;
42int viafb_hotplug_Xres = 640;
43int viafb_hotplug_Yres = 480;
44int viafb_hotplug_bpp = 32;
45int viafb_hotplug_refresh = 60;
46unsigned int viafb_second_offset;
47int viafb_second_size;
48int viafb_primary_dev = None_Device;
49void __iomem *viafb_FB_MM;
50unsigned int viafb_second_xres = 640;
51unsigned int viafb_second_yres = 480;
52unsigned int viafb_second_virtual_xres;
53unsigned int viafb_second_virtual_yres;
54int viafb_lcd_panel_id = LCD_PANEL_ID_MAXIMUM + 1;
55struct fb_cursor viacursor;
56struct fb_info *viafbinfo;
57struct fb_info *viafbinfo1;
58struct viafb_par *viaparinfo;
59struct viafb_par *viaparinfo1;
60
diff --git a/drivers/video/via/global.h b/drivers/video/via/global.h
new file mode 100644
index 000000000000..8e5263c5b812
--- /dev/null
+++ b/drivers/video/via/global.h
@@ -0,0 +1,90 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __GLOBAL_H__
23#define __GLOBAL_H__
24
25#include <linux/fb.h>
26#include <linux/delay.h>
27#include <linux/ioport.h>
28#include <linux/pci.h>
29#include <linux/io.h>
30#include <linux/uaccess.h>
31#include <linux/init.h>
32#include <linux/proc_fs.h>
33#include <linux/console.h>
34#include <linux/timer.h>
35
36#include "debug.h"
37
38#include "iface.h"
39#include "viafbdev.h"
40#include "chip.h"
41#include "debug.h"
42#include "accel.h"
43#include "share.h"
44#include "dvi.h"
45#include "viamode.h"
46#include "via_i2c.h"
47#include "hw.h"
48
49#include "lcd.h"
50#include "ioctl.h"
51#include "viamode.h"
52#include "via_utility.h"
53#include "vt1636.h"
54#include "tblDPASetting.h"
55#include "tbl1636.h"
56#include "viafbdev.h"
57
58/* External struct*/
59
60extern int viafb_platform_epia_dvi;
61extern int viafb_device_lcd_dualedge;
62extern int viafb_bus_width;
63extern int viafb_display_hardware_layout;
64extern struct offset offset_reg;
65extern struct viafb_par *viaparinfo;
66extern struct viafb_par *viaparinfo1;
67extern struct fb_info *viafbinfo;
68extern struct fb_info *viafbinfo1;
69extern int viafb_DeviceStatus;
70extern int viafb_refresh;
71extern int viafb_refresh1;
72extern int viafb_lcd_dsp_method;
73extern int viafb_lcd_mode;
74extern int viafb_bpp;
75extern int viafb_bpp1;
76
77extern int viafb_CRT_ON;
78extern int viafb_hotplug_Xres;
79extern int viafb_hotplug_Yres;
80extern int viafb_hotplug_bpp;
81extern int viafb_hotplug_refresh;
82extern int viafb_primary_dev;
83extern void __iomem *viafb_FB_MM;
84extern struct fb_cursor viacursor;
85
86extern unsigned int viafb_second_xres;
87extern unsigned int viafb_second_yres;
88extern int viafb_lcd_panel_id;
89
90#endif /* __GLOBAL_H__ */
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
new file mode 100644
index 000000000000..fcd53ceb88fa
--- /dev/null
+++ b/drivers/video/via/hw.c
@@ -0,0 +1,2865 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24static const struct pci_device_id_info pciidlist[] = {
25 {PCI_VIA_VENDOR_ID, UNICHROME_CLE266_DID, UNICHROME_CLE266},
26 {PCI_VIA_VENDOR_ID, UNICHROME_PM800_DID, UNICHROME_PM800},
27 {PCI_VIA_VENDOR_ID, UNICHROME_K400_DID, UNICHROME_K400},
28 {PCI_VIA_VENDOR_ID, UNICHROME_K800_DID, UNICHROME_K800},
29 {PCI_VIA_VENDOR_ID, UNICHROME_CN700_DID, UNICHROME_CN700},
30 {PCI_VIA_VENDOR_ID, UNICHROME_P4M890_DID, UNICHROME_P4M890},
31 {PCI_VIA_VENDOR_ID, UNICHROME_K8M890_DID, UNICHROME_K8M890},
32 {PCI_VIA_VENDOR_ID, UNICHROME_CX700_DID, UNICHROME_CX700},
33 {PCI_VIA_VENDOR_ID, UNICHROME_P4M900_DID, UNICHROME_P4M900},
34 {PCI_VIA_VENDOR_ID, UNICHROME_CN750_DID, UNICHROME_CN750},
35 {PCI_VIA_VENDOR_ID, UNICHROME_VX800_DID, UNICHROME_VX800},
36 {0, 0, 0}
37};
38
39struct offset offset_reg = {
40 /* IGA1 Offset Register */
41 {IGA1_OFFSET_REG_NUM, {{CR13, 0, 7}, {CR35, 5, 7} } },
42 /* IGA2 Offset Register */
43 {IGA2_OFFSET_REG_NUM, {{CR66, 0, 7}, {CR67, 0, 1} } }
44};
45
46static struct pll_map pll_value[] = {
47 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M},
48 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M},
49 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M},
50 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M},
51 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M},
52 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M},
53 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M},
54 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M},
55 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M},
56 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M},
57 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M},
58 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, CX700_45_250M},
59 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, CX700_46_000M},
60 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, CX700_46_996M},
61 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, CX700_48_000M},
62 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, CX700_48_875M},
63 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M},
64 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M},
65 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, CX700_52_977M},
66 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M},
67 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M},
68 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, CX700_61_500M},
69 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M},
70 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, CX700_65_178M},
71 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, CX700_66_750M},
72 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M},
73 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, CX700_69_924M},
74 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, CX700_70_159M},
75 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, CX700_72_000M},
76 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M},
77 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M},
78 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, CX700_83_375M},
79 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M},
80 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, CX700_84_750M},
81 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M},
82 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, CX700_88_750M},
83 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M},
84 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, CX700_97_750M},
85 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
86 CX700_101_000M},
87 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
88 CX700_106_500M},
89 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
90 CX700_108_000M},
91 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
92 CX700_113_309M},
93 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
94 CX700_118_840M},
95 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
96 CX700_119_000M},
97 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
98 CX700_121_750M},
99 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
100 CX700_125_104M},
101 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
102 CX700_133_308M},
103 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
104 CX700_135_000M},
105 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
106 CX700_136_700M},
107 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
108 CX700_138_400M},
109 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
110 CX700_146_760M},
111 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
112 CX700_153_920M},
113 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
114 CX700_156_000M},
115 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
116 CX700_157_500M},
117 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
118 CX700_162_000M},
119 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
120 CX700_187_000M},
121 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
122 CX700_193_295M},
123 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
124 CX700_202_500M},
125 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
126 CX700_204_000M},
127 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
128 CX700_218_500M},
129 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
130 CX700_234_000M},
131 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
132 CX700_267_250M},
133 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
134 CX700_297_500M},
135 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M},
136 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
137 CX700_172_798M},
138 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
139 CX700_122_614M},
140 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, CX700_74_270M},
141 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
142 CX700_148_500M}
143};
144
145static struct fifo_depth_select display_fifo_depth_reg = {
146 /* IGA1 FIFO Depth_Select */
147 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
148 /* IGA2 FIFO Depth_Select */
149 {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
150 {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
151};
152
153static struct fifo_threshold_select fifo_threshold_select_reg = {
154 /* IGA1 FIFO Threshold Select */
155 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
156 /* IGA2 FIFO Threshold Select */
157 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
158};
159
160static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
161 /* IGA1 FIFO High Threshold Select */
162 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
163 /* IGA2 FIFO High Threshold Select */
164 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
165};
166
167static struct display_queue_expire_num display_queue_expire_num_reg = {
168 /* IGA1 Display Queue Expire Num */
169 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
170 /* IGA2 Display Queue Expire Num */
171 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
172};
173
174/* Definition Fetch Count Registers*/
175static struct fetch_count fetch_count_reg = {
176 /* IGA1 Fetch Count Register */
177 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
178 /* IGA2 Fetch Count Register */
179 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
180};
181
182static struct iga1_crtc_timing iga1_crtc_reg = {
183 /* IGA1 Horizontal Total */
184 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
185 /* IGA1 Horizontal Addressable Video */
186 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
187 /* IGA1 Horizontal Blank Start */
188 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
189 /* IGA1 Horizontal Blank End */
190 {IGA1_HOR_BLANK_END_REG_NUM,
191 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
192 /* IGA1 Horizontal Sync Start */
193 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
194 /* IGA1 Horizontal Sync End */
195 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
196 /* IGA1 Vertical Total */
197 {IGA1_VER_TOTAL_REG_NUM,
198 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
199 /* IGA1 Vertical Addressable Video */
200 {IGA1_VER_ADDR_REG_NUM,
201 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
202 /* IGA1 Vertical Blank Start */
203 {IGA1_VER_BLANK_START_REG_NUM,
204 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
205 /* IGA1 Vertical Blank End */
206 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
207 /* IGA1 Vertical Sync Start */
208 {IGA1_VER_SYNC_START_REG_NUM,
209 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
210 /* IGA1 Vertical Sync End */
211 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
212};
213
214static struct iga2_crtc_timing iga2_crtc_reg = {
215 /* IGA2 Horizontal Total */
216 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
217 /* IGA2 Horizontal Addressable Video */
218 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
219 /* IGA2 Horizontal Blank Start */
220 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
221 /* IGA2 Horizontal Blank End */
222 {IGA2_HOR_BLANK_END_REG_NUM,
223 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
224 /* IGA2 Horizontal Sync Start */
225 {IGA2_HOR_SYNC_START_REG_NUM,
226 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
227 /* IGA2 Horizontal Sync End */
228 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
229 /* IGA2 Vertical Total */
230 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
231 /* IGA2 Vertical Addressable Video */
232 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
233 /* IGA2 Vertical Blank Start */
234 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
235 /* IGA2 Vertical Blank End */
236 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
237 /* IGA2 Vertical Sync Start */
238 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
239 /* IGA2 Vertical Sync End */
240 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
241};
242
243static struct rgbLUT palLUT_table[] = {
244 /* {R,G,B} */
245 /* Index 0x00~0x03 */
246 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
247 0x2A,
248 0x2A},
249 /* Index 0x04~0x07 */
250 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
251 0x2A,
252 0x2A},
253 /* Index 0x08~0x0B */
254 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
255 0x3F,
256 0x3F},
257 /* Index 0x0C~0x0F */
258 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
259 0x3F,
260 0x3F},
261 /* Index 0x10~0x13 */
262 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
263 0x0B,
264 0x0B},
265 /* Index 0x14~0x17 */
266 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
267 0x18,
268 0x18},
269 /* Index 0x18~0x1B */
270 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
271 0x28,
272 0x28},
273 /* Index 0x1C~0x1F */
274 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
275 0x3F,
276 0x3F},
277 /* Index 0x20~0x23 */
278 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
279 0x00,
280 0x3F},
281 /* Index 0x24~0x27 */
282 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
283 0x00,
284 0x10},
285 /* Index 0x28~0x2B */
286 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
287 0x2F,
288 0x00},
289 /* Index 0x2C~0x2F */
290 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
291 0x3F,
292 0x00},
293 /* Index 0x30~0x33 */
294 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
295 0x3F,
296 0x2F},
297 /* Index 0x34~0x37 */
298 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
299 0x10,
300 0x3F},
301 /* Index 0x38~0x3B */
302 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
303 0x1F,
304 0x3F},
305 /* Index 0x3C~0x3F */
306 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
307 0x1F,
308 0x27},
309 /* Index 0x40~0x43 */
310 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
311 0x3F,
312 0x1F},
313 /* Index 0x44~0x47 */
314 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
315 0x3F,
316 0x1F},
317 /* Index 0x48~0x4B */
318 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
319 0x3F,
320 0x37},
321 /* Index 0x4C~0x4F */
322 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
323 0x27,
324 0x3F},
325 /* Index 0x50~0x53 */
326 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
327 0x2D,
328 0x3F},
329 /* Index 0x54~0x57 */
330 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
331 0x2D,
332 0x31},
333 /* Index 0x58~0x5B */
334 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
335 0x3A,
336 0x2D},
337 /* Index 0x5C~0x5F */
338 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
339 0x3F,
340 0x2D},
341 /* Index 0x60~0x63 */
342 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
343 0x3F,
344 0x3A},
345 /* Index 0x64~0x67 */
346 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
347 0x31,
348 0x3F},
349 /* Index 0x68~0x6B */
350 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
351 0x00,
352 0x1C},
353 /* Index 0x6C~0x6F */
354 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
355 0x00,
356 0x07},
357 /* Index 0x70~0x73 */
358 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
359 0x15,
360 0x00},
361 /* Index 0x74~0x77 */
362 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
363 0x1C,
364 0x00},
365 /* Index 0x78~0x7B */
366 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
367 0x1C,
368 0x15},
369 /* Index 0x7C~0x7F */
370 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
371 0x07,
372 0x1C},
373 /* Index 0x80~0x83 */
374 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
375 0x0E,
376 0x1C},
377 /* Index 0x84~0x87 */
378 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
379 0x0E,
380 0x11},
381 /* Index 0x88~0x8B */
382 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
383 0x18,
384 0x0E},
385 /* Index 0x8C~0x8F */
386 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
387 0x1C,
388 0x0E},
389 /* Index 0x90~0x93 */
390 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
391 0x1C,
392 0x18},
393 /* Index 0x94~0x97 */
394 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
395 0x11,
396 0x1C},
397 /* Index 0x98~0x9B */
398 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
399 0x14,
400 0x1C},
401 /* Index 0x9C~0x9F */
402 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
403 0x14,
404 0x16},
405 /* Index 0xA0~0xA3 */
406 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
407 0x1A,
408 0x14},
409 /* Index 0xA4~0xA7 */
410 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
411 0x1C,
412 0x14},
413 /* Index 0xA8~0xAB */
414 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
415 0x1C,
416 0x1A},
417 /* Index 0xAC~0xAF */
418 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
419 0x16,
420 0x1C},
421 /* Index 0xB0~0xB3 */
422 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
423 0x00,
424 0x10},
425 /* Index 0xB4~0xB7 */
426 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
427 0x00,
428 0x04},
429 /* Index 0xB8~0xBB */
430 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
431 0x0C,
432 0x00},
433 /* Index 0xBC~0xBF */
434 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
435 0x10,
436 0x00},
437 /* Index 0xC0~0xC3 */
438 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
439 0x10,
440 0x0C},
441 /* Index 0xC4~0xC7 */
442 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
443 0x04,
444 0x10},
445 /* Index 0xC8~0xCB */
446 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
447 0x08,
448 0x10},
449 /* Index 0xCC~0xCF */
450 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
451 0x08,
452 0x0A},
453 /* Index 0xD0~0xD3 */
454 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
455 0x0E,
456 0x08},
457 /* Index 0xD4~0xD7 */
458 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
459 0x10,
460 0x08},
461 /* Index 0xD8~0xDB */
462 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
463 0x10,
464 0x0E},
465 /* Index 0xDC~0xDF */
466 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
467 0x0A,
468 0x10},
469 /* Index 0xE0~0xE3 */
470 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
471 0x0B,
472 0x10},
473 /* Index 0xE4~0xE7 */
474 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
475 0x0B,
476 0x0C},
477 /* Index 0xE8~0xEB */
478 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
479 0x0F,
480 0x0B},
481 /* Index 0xEC~0xEF */
482 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
483 0x10,
484 0x0B},
485 /* Index 0xF0~0xF3 */
486 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
487 0x10,
488 0x0F},
489 /* Index 0xF4~0xF7 */
490 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
491 0x0C,
492 0x10},
493 /* Index 0xF8~0xFB */
494 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
495 0x00,
496 0x00},
497 /* Index 0xFC~0xFF */
498 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
499 0x00,
500 0x00}
501};
502
503static void set_crt_output_path(int set_iga);
504static void dvi_patch_skew_dvp0(void);
505static void dvi_patch_skew_dvp1(void);
506static void dvi_patch_skew_dvp_low(void);
507static void set_dvi_output_path(int set_iga, int output_interface);
508static void set_lcd_output_path(int set_iga, int output_interface);
509static int search_mode_setting(int ModeInfoIndex);
510static void load_fix_bit_crtc_reg(void);
511static void init_gfx_chip_info(void);
512static void init_tmds_chip_info(void);
513static void init_lvds_chip_info(void);
514static void device_screen_off(void);
515static void device_screen_on(void);
516static void set_display_channel(void);
517static void device_off(void);
518static void device_on(void);
519static void enable_second_display_channel(void);
520static void disable_second_display_channel(void);
521static int get_fb_size_from_pci(void);
522
523void viafb_write_reg(u8 index, u16 io_port, u8 data)
524{
525 outb(index, io_port);
526 outb(data, io_port + 1);
527 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
528}
529u8 viafb_read_reg(int io_port, u8 index)
530{
531 outb(index, io_port);
532 return inb(io_port + 1);
533}
534
535void viafb_lock_crt(void)
536{
537 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
538}
539
540void viafb_unlock_crt(void)
541{
542 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
543 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
544}
545
546void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
547{
548 u8 tmp;
549
550 outb(index, io_port);
551 tmp = inb(io_port + 1);
552 outb((data & mask) | (tmp & (~mask)), io_port + 1);
553 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
554}
555
556void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
557{
558 outb(index, LUT_INDEX_WRITE);
559 outb(r, LUT_DATA);
560 outb(g, LUT_DATA);
561 outb(b, LUT_DATA);
562}
563
564/*Set IGA path for each device*/
565void viafb_set_iga_path(void)
566{
567
568 if (viafb_SAMM_ON == 1) {
569 if (viafb_CRT_ON) {
570 if (viafb_primary_dev == CRT_Device)
571 viaparinfo->crt_setting_info->iga_path = IGA1;
572 else
573 viaparinfo->crt_setting_info->iga_path = IGA2;
574 }
575
576 if (viafb_DVI_ON) {
577 if (viafb_primary_dev == DVI_Device)
578 viaparinfo->tmds_setting_info->iga_path = IGA1;
579 else
580 viaparinfo->tmds_setting_info->iga_path = IGA2;
581 }
582
583 if (viafb_LCD_ON) {
584 if (viafb_primary_dev == LCD_Device) {
585 if (viafb_dual_fb &&
586 (viaparinfo->chip_info->gfx_chip_name ==
587 UNICHROME_CLE266)) {
588 viaparinfo->
589 lvds_setting_info->iga_path = IGA2;
590 viaparinfo->
591 crt_setting_info->iga_path = IGA1;
592 viaparinfo->
593 tmds_setting_info->iga_path = IGA1;
594 } else
595 viaparinfo->
596 lvds_setting_info->iga_path = IGA1;
597 } else {
598 viaparinfo->lvds_setting_info->iga_path = IGA2;
599 }
600 }
601 if (viafb_LCD2_ON) {
602 if (LCD2_Device == viafb_primary_dev)
603 viaparinfo->lvds_setting_info2->iga_path = IGA1;
604 else
605 viaparinfo->lvds_setting_info2->iga_path = IGA2;
606 }
607 } else {
608 viafb_SAMM_ON = 0;
609
610 if (viafb_CRT_ON && viafb_LCD_ON) {
611 viaparinfo->crt_setting_info->iga_path = IGA1;
612 viaparinfo->lvds_setting_info->iga_path = IGA2;
613 } else if (viafb_CRT_ON && viafb_DVI_ON) {
614 viaparinfo->crt_setting_info->iga_path = IGA1;
615 viaparinfo->tmds_setting_info->iga_path = IGA2;
616 } else if (viafb_LCD_ON && viafb_DVI_ON) {
617 viaparinfo->tmds_setting_info->iga_path = IGA1;
618 viaparinfo->lvds_setting_info->iga_path = IGA2;
619 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
620 viaparinfo->lvds_setting_info->iga_path = IGA2;
621 viaparinfo->lvds_setting_info2->iga_path = IGA2;
622 } else if (viafb_CRT_ON) {
623 viaparinfo->crt_setting_info->iga_path = IGA1;
624 } else if (viafb_LCD_ON) {
625 viaparinfo->lvds_setting_info->iga_path = IGA2;
626 } else if (viafb_DVI_ON) {
627 viaparinfo->tmds_setting_info->iga_path = IGA1;
628 }
629 }
630}
631
632void viafb_set_start_addr(void)
633{
634 unsigned long offset = 0, tmp = 0, size = 0;
635 unsigned long length;
636
637 DEBUG_MSG(KERN_INFO "viafb_set_start_addr!\n");
638 viafb_unlock_crt();
639 /* update starting address of IGA1 */
640 viafb_write_reg(CR0C, VIACR, 0x00); /*initial starting address */
641 viafb_write_reg(CR0D, VIACR, 0x00);
642 viafb_write_reg(CR34, VIACR, 0x00);
643 viafb_write_reg_mask(CR48, VIACR, 0x00, 0x1F);
644
645 if (viafb_dual_fb) {
646 viaparinfo->iga_path = IGA1;
647 viaparinfo1->iga_path = IGA2;
648 }
649
650 if (viafb_SAMM_ON == 1) {
651 if (!viafb_dual_fb) {
652 if (viafb_second_size)
653 size = viafb_second_size * 1024 * 1024;
654 else
655 size = 8 * 1024 * 1024;
656 } else {
657
658 size = viaparinfo1->memsize;
659 }
660 offset = viafb_second_offset;
661 DEBUG_MSG(KERN_INFO
662 "viafb_second_size=%lx, second start_adddress=%lx\n",
663 size, offset);
664 }
665 if (viafb_SAMM_ON == 1) {
666 offset = offset >> 3;
667
668 tmp = viafb_read_reg(VIACR, 0x62) & 0x01;
669 tmp |= (offset & 0x7F) << 1;
670 viafb_write_reg(CR62, VIACR, tmp);
671 viafb_write_reg(CR63, VIACR, ((offset & 0x7F80) >> 7));
672 viafb_write_reg(CR64, VIACR, ((offset & 0x7F8000) >> 15));
673 viafb_write_reg(CRA3, VIACR, ((offset & 0x3800000) >> 23));
674 } else {
675 /* update starting address */
676 viafb_write_reg(CR62, VIACR, 0x00);
677 viafb_write_reg(CR63, VIACR, 0x00);
678 viafb_write_reg(CR64, VIACR, 0x00);
679 viafb_write_reg(CRA3, VIACR, 0x00);
680 }
681
682 if (viafb_SAMM_ON == 1) {
683 if (viafb_accel) {
684 if (!viafb_dual_fb)
685 length = size - viaparinfo->fbmem_used;
686 else
687 length = size - viaparinfo1->fbmem_used;
688 } else
689 length = size;
690 offset = (unsigned long)(void *)viafb_FB_MM +
691 viafb_second_offset;
692 memset((void *)offset, 0, length);
693 }
694
695 viafb_lock_crt();
696}
697
698void viafb_set_output_path(int device, int set_iga, int output_interface)
699{
700 switch (device) {
701 case DEVICE_CRT:
702 set_crt_output_path(set_iga);
703 break;
704 case DEVICE_DVI:
705 set_dvi_output_path(set_iga, output_interface);
706 break;
707 case DEVICE_LCD:
708 set_lcd_output_path(set_iga, output_interface);
709 break;
710 }
711}
712
713static void set_crt_output_path(int set_iga)
714{
715 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
716
717 switch (set_iga) {
718 case IGA1:
719 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
720 break;
721 case IGA2:
722 case IGA1_IGA2:
723 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
724 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
725 if (set_iga == IGA1_IGA2)
726 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
727 break;
728 }
729}
730
731static void dvi_patch_skew_dvp0(void)
732{
733 /* Reset data driving first: */
734 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
735 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
736
737 switch (viaparinfo->chip_info->gfx_chip_name) {
738 case UNICHROME_P4M890:
739 {
740 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
741 (viaparinfo->tmds_setting_info->v_active ==
742 1200))
743 viafb_write_reg_mask(CR96, VIACR, 0x03,
744 BIT0 + BIT1 + BIT2);
745 else
746 viafb_write_reg_mask(CR96, VIACR, 0x07,
747 BIT0 + BIT1 + BIT2);
748 break;
749 }
750
751 case UNICHROME_P4M900:
752 {
753 viafb_write_reg_mask(CR96, VIACR, 0x07,
754 BIT0 + BIT1 + BIT2 + BIT3);
755 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
756 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
757 break;
758 }
759
760 default:
761 {
762 break;
763 }
764 }
765}
766
767static void dvi_patch_skew_dvp1(void)
768{
769 switch (viaparinfo->chip_info->gfx_chip_name) {
770 case UNICHROME_CX700:
771 {
772 break;
773 }
774
775 default:
776 {
777 break;
778 }
779 }
780}
781
782static void dvi_patch_skew_dvp_low(void)
783{
784 switch (viaparinfo->chip_info->gfx_chip_name) {
785 case UNICHROME_K8M890:
786 {
787 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
788 break;
789 }
790
791 case UNICHROME_P4M900:
792 {
793 viafb_write_reg_mask(CR99, VIACR, 0x08,
794 BIT0 + BIT1 + BIT2 + BIT3);
795 break;
796 }
797
798 case UNICHROME_P4M890:
799 {
800 viafb_write_reg_mask(CR99, VIACR, 0x0F,
801 BIT0 + BIT1 + BIT2 + BIT3);
802 break;
803 }
804
805 default:
806 {
807 break;
808 }
809 }
810}
811
812static void set_dvi_output_path(int set_iga, int output_interface)
813{
814 switch (output_interface) {
815 case INTERFACE_DVP0:
816 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
817
818 if (set_iga == IGA1) {
819 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
820 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
821 BIT5 + BIT7);
822 } else {
823 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
824 viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
825 BIT5 + BIT7);
826 }
827
828 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
829
830 dvi_patch_skew_dvp0();
831 break;
832
833 case INTERFACE_DVP1:
834 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
835 if (set_iga == IGA1)
836 viafb_write_reg_mask(CR93, VIACR, 0x21,
837 BIT0 + BIT5 + BIT7);
838 else
839 viafb_write_reg_mask(CR93, VIACR, 0xA1,
840 BIT0 + BIT5 + BIT7);
841 } else {
842 if (set_iga == IGA1)
843 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
844 else
845 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
846 }
847
848 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
849 dvi_patch_skew_dvp1();
850 break;
851 case INTERFACE_DFP_HIGH:
852 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
853 if (set_iga == IGA1) {
854 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
855 viafb_write_reg_mask(CR97, VIACR, 0x03,
856 BIT0 + BIT1 + BIT4);
857 } else {
858 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
859 viafb_write_reg_mask(CR97, VIACR, 0x13,
860 BIT0 + BIT1 + BIT4);
861 }
862 }
863 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
864 break;
865
866 case INTERFACE_DFP_LOW:
867 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
868 break;
869
870 if (set_iga == IGA1) {
871 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
872 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
873 } else {
874 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
875 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
876 }
877
878 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
879 dvi_patch_skew_dvp_low();
880 break;
881
882 case INTERFACE_TMDS:
883 if (set_iga == IGA1)
884 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
885 else
886 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
887 break;
888 }
889
890 if (set_iga == IGA2) {
891 enable_second_display_channel();
892 /* Disable LCD Scaling */
893 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
894 }
895}
896
897static void set_lcd_output_path(int set_iga, int output_interface)
898{
899 DEBUG_MSG(KERN_INFO
900 "set_lcd_output_path, iga:%d,out_interface:%d\n",
901 set_iga, output_interface);
902 switch (set_iga) {
903 case IGA1:
904 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
905 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
906
907 disable_second_display_channel();
908 break;
909
910 case IGA2:
911 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
912 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
913
914 enable_second_display_channel();
915 break;
916
917 case IGA1_IGA2:
918 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
919 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
920
921 disable_second_display_channel();
922 break;
923 }
924
925 switch (output_interface) {
926 case INTERFACE_DVP0:
927 if (set_iga == IGA1) {
928 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
929 } else {
930 viafb_write_reg(CR91, VIACR, 0x00);
931 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
932 }
933 break;
934
935 case INTERFACE_DVP1:
936 if (set_iga == IGA1)
937 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
938 else {
939 viafb_write_reg(CR91, VIACR, 0x00);
940 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
941 }
942 break;
943
944 case INTERFACE_DFP_HIGH:
945 if (set_iga == IGA1)
946 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
947 else {
948 viafb_write_reg(CR91, VIACR, 0x00);
949 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
950 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
951 }
952 break;
953
954 case INTERFACE_DFP_LOW:
955 if (set_iga == IGA1)
956 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
957 else {
958 viafb_write_reg(CR91, VIACR, 0x00);
959 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
960 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
961 }
962
963 break;
964
965 case INTERFACE_DFP:
966 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
967 || (UNICHROME_P4M890 ==
968 viaparinfo->chip_info->gfx_chip_name))
969 viafb_write_reg_mask(CR97, VIACR, 0x84,
970 BIT7 + BIT2 + BIT1 + BIT0);
971 if (set_iga == IGA1) {
972 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
973 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
974 } else {
975 viafb_write_reg(CR91, VIACR, 0x00);
976 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
977 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
978 }
979 break;
980
981 case INTERFACE_LVDS0:
982 case INTERFACE_LVDS0LVDS1:
983 if (set_iga == IGA1)
984 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
985 else
986 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
987
988 break;
989
990 case INTERFACE_LVDS1:
991 if (set_iga == IGA1)
992 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
993 else
994 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
995 break;
996 }
997}
998
999/* Search Mode Index */
1000static int search_mode_setting(int ModeInfoIndex)
1001{
1002 int i = 0;
1003
1004 while ((i < NUM_TOTAL_MODETABLE) &&
1005 (ModeInfoIndex != CLE266Modes[i].ModeIndex))
1006 i++;
1007 if (i >= NUM_TOTAL_MODETABLE)
1008 i = 0;
1009 return i;
1010
1011}
1012
1013struct VideoModeTable *viafb_get_modetbl_pointer(int Index)
1014{
1015 struct VideoModeTable *TmpTbl = NULL;
1016 TmpTbl = &CLE266Modes[search_mode_setting(Index)];
1017 return TmpTbl;
1018}
1019
1020struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index)
1021{
1022 struct VideoModeTable *TmpTbl = NULL;
1023 int i = 0;
1024 while ((i < NUM_TOTAL_CEA_MODES) &&
1025 (Index != CEA_HDMI_Modes[i].ModeIndex))
1026 i++;
1027 if ((i < NUM_TOTAL_CEA_MODES))
1028 TmpTbl = &CEA_HDMI_Modes[i];
1029 else {
1030 /*Still use general timing if don't find CEA timing */
1031 i = 0;
1032 while ((i < NUM_TOTAL_MODETABLE) &&
1033 (Index != CLE266Modes[i].ModeIndex))
1034 i++;
1035 if (i >= NUM_TOTAL_MODETABLE)
1036 i = 0;
1037 TmpTbl = &CLE266Modes[i];
1038 }
1039 return TmpTbl;
1040}
1041
1042static void load_fix_bit_crtc_reg(void)
1043{
1044 /* always set to 1 */
1045 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1046 /* line compare should set all bits = 1 (extend modes) */
1047 viafb_write_reg(CR18, VIACR, 0xff);
1048 /* line compare should set all bits = 1 (extend modes) */
1049 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1050 /* line compare should set all bits = 1 (extend modes) */
1051 viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1052 /* line compare should set all bits = 1 (extend modes) */
1053 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1054 /* line compare should set all bits = 1 (extend modes) */
1055 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1056 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1057 /* extend mode always set to e3h */
1058 viafb_write_reg(CR17, VIACR, 0xe3);
1059 /* extend mode always set to 0h */
1060 viafb_write_reg(CR08, VIACR, 0x00);
1061 /* extend mode always set to 0h */
1062 viafb_write_reg(CR14, VIACR, 0x00);
1063
1064 /* If K8M800, enable Prefetch Mode. */
1065 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1066 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1067 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1068 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1069 && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1070 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1071
1072}
1073
1074void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1075 struct io_register *reg,
1076 int io_type)
1077{
1078 int reg_mask;
1079 int bit_num = 0;
1080 int data;
1081 int i, j;
1082 int shift_next_reg;
1083 int start_index, end_index, cr_index;
1084 u16 get_bit;
1085
1086 for (i = 0; i < viafb_load_reg_num; i++) {
1087 reg_mask = 0;
1088 data = 0;
1089 start_index = reg[i].start_bit;
1090 end_index = reg[i].end_bit;
1091 cr_index = reg[i].io_addr;
1092
1093 shift_next_reg = bit_num;
1094 for (j = start_index; j <= end_index; j++) {
1095 /*if (bit_num==8) timing_value = timing_value >>8; */
1096 reg_mask = reg_mask | (BIT0 << j);
1097 get_bit = (timing_value & (BIT0 << bit_num));
1098 data =
1099 data | ((get_bit >> shift_next_reg) << start_index);
1100 bit_num++;
1101 }
1102 if (io_type == VIACR)
1103 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1104 else
1105 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1106 }
1107
1108}
1109
1110/* Write Registers */
1111void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1112{
1113 int i;
1114 unsigned char RegTemp;
1115
1116 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1117
1118 for (i = 0; i < ItemNum; i++) {
1119 outb(RegTable[i].index, RegTable[i].port);
1120 RegTemp = inb(RegTable[i].port + 1);
1121 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1122 outb(RegTemp, RegTable[i].port + 1);
1123 }
1124}
1125
1126void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga)
1127{
1128 int reg_value;
1129 int viafb_load_reg_num;
1130 struct io_register *reg;
1131
1132 switch (set_iga) {
1133 case IGA1_IGA2:
1134 case IGA1:
1135 reg_value = IGA1_OFFSET_FORMULA(h_addr, bpp_byte);
1136 viafb_load_reg_num = offset_reg.iga1_offset_reg.reg_num;
1137 reg = offset_reg.iga1_offset_reg.reg;
1138 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1139 if (set_iga == IGA1)
1140 break;
1141 case IGA2:
1142 reg_value = IGA2_OFFSET_FORMULA(h_addr, bpp_byte);
1143 viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
1144 reg = offset_reg.iga2_offset_reg.reg;
1145 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1146 break;
1147 }
1148}
1149
1150void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1151{
1152 int reg_value;
1153 int viafb_load_reg_num;
1154 struct io_register *reg = NULL;
1155
1156 switch (set_iga) {
1157 case IGA1_IGA2:
1158 case IGA1:
1159 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1160 viafb_load_reg_num = fetch_count_reg.
1161 iga1_fetch_count_reg.reg_num;
1162 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1163 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1164 if (set_iga == IGA1)
1165 break;
1166 case IGA2:
1167 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1168 viafb_load_reg_num = fetch_count_reg.
1169 iga2_fetch_count_reg.reg_num;
1170 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1171 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1172 break;
1173 }
1174
1175}
1176
1177void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1178{
1179 int reg_value;
1180 int viafb_load_reg_num;
1181 struct io_register *reg = NULL;
1182 int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1183 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1184 int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1185 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1186
1187 if (set_iga == IGA1) {
1188 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1189 iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1190 iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1191 iga1_fifo_high_threshold =
1192 K800_IGA1_FIFO_HIGH_THRESHOLD;
1193 /* If resolution > 1280x1024, expire length = 64, else
1194 expire length = 128 */
1195 if ((hor_active > 1280) && (ver_active > 1024))
1196 iga1_display_queue_expire_num = 16;
1197 else
1198 iga1_display_queue_expire_num =
1199 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1200
1201 }
1202
1203 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1204 iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1205 iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1206 iga1_fifo_high_threshold =
1207 P880_IGA1_FIFO_HIGH_THRESHOLD;
1208 iga1_display_queue_expire_num =
1209 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1210
1211 /* If resolution > 1280x1024, expire length = 64, else
1212 expire length = 128 */
1213 if ((hor_active > 1280) && (ver_active > 1024))
1214 iga1_display_queue_expire_num = 16;
1215 else
1216 iga1_display_queue_expire_num =
1217 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1218 }
1219
1220 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1221 iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1222 iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1223 iga1_fifo_high_threshold =
1224 CN700_IGA1_FIFO_HIGH_THRESHOLD;
1225
1226 /* If resolution > 1280x1024, expire length = 64,
1227 else expire length = 128 */
1228 if ((hor_active > 1280) && (ver_active > 1024))
1229 iga1_display_queue_expire_num = 16;
1230 else
1231 iga1_display_queue_expire_num =
1232 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1233 }
1234
1235 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1236 iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1237 iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1238 iga1_fifo_high_threshold =
1239 CX700_IGA1_FIFO_HIGH_THRESHOLD;
1240 iga1_display_queue_expire_num =
1241 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1242 }
1243
1244 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1245 iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1246 iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1247 iga1_fifo_high_threshold =
1248 K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1249 iga1_display_queue_expire_num =
1250 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1251 }
1252
1253 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1254 iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1255 iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1256 iga1_fifo_high_threshold =
1257 P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1258 iga1_display_queue_expire_num =
1259 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1260 }
1261
1262 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1263 iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1264 iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1265 iga1_fifo_high_threshold =
1266 P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1267 iga1_display_queue_expire_num =
1268 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1269 }
1270
1271 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1272 iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1273 iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1274 iga1_fifo_high_threshold =
1275 VX800_IGA1_FIFO_HIGH_THRESHOLD;
1276 iga1_display_queue_expire_num =
1277 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1278 }
1279
1280 /* Set Display FIFO Depath Select */
1281 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1282 viafb_load_reg_num =
1283 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1284 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1285 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1286
1287 /* Set Display FIFO Threshold Select */
1288 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1289 viafb_load_reg_num =
1290 fifo_threshold_select_reg.
1291 iga1_fifo_threshold_select_reg.reg_num;
1292 reg =
1293 fifo_threshold_select_reg.
1294 iga1_fifo_threshold_select_reg.reg;
1295 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1296
1297 /* Set FIFO High Threshold Select */
1298 reg_value =
1299 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1300 viafb_load_reg_num =
1301 fifo_high_threshold_select_reg.
1302 iga1_fifo_high_threshold_select_reg.reg_num;
1303 reg =
1304 fifo_high_threshold_select_reg.
1305 iga1_fifo_high_threshold_select_reg.reg;
1306 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1307
1308 /* Set Display Queue Expire Num */
1309 reg_value =
1310 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1311 (iga1_display_queue_expire_num);
1312 viafb_load_reg_num =
1313 display_queue_expire_num_reg.
1314 iga1_display_queue_expire_num_reg.reg_num;
1315 reg =
1316 display_queue_expire_num_reg.
1317 iga1_display_queue_expire_num_reg.reg;
1318 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1319
1320 } else {
1321 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1322 iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1323 iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1324 iga2_fifo_high_threshold =
1325 K800_IGA2_FIFO_HIGH_THRESHOLD;
1326
1327 /* If resolution > 1280x1024, expire length = 64,
1328 else expire length = 128 */
1329 if ((hor_active > 1280) && (ver_active > 1024))
1330 iga2_display_queue_expire_num = 16;
1331 else
1332 iga2_display_queue_expire_num =
1333 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1334 }
1335
1336 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1337 iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1338 iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1339 iga2_fifo_high_threshold =
1340 P880_IGA2_FIFO_HIGH_THRESHOLD;
1341
1342 /* If resolution > 1280x1024, expire length = 64,
1343 else expire length = 128 */
1344 if ((hor_active > 1280) && (ver_active > 1024))
1345 iga2_display_queue_expire_num = 16;
1346 else
1347 iga2_display_queue_expire_num =
1348 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1349 }
1350
1351 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1352 iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1353 iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1354 iga2_fifo_high_threshold =
1355 CN700_IGA2_FIFO_HIGH_THRESHOLD;
1356
1357 /* If resolution > 1280x1024, expire length = 64,
1358 else expire length = 128 */
1359 if ((hor_active > 1280) && (ver_active > 1024))
1360 iga2_display_queue_expire_num = 16;
1361 else
1362 iga2_display_queue_expire_num =
1363 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1364 }
1365
1366 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1367 iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1368 iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1369 iga2_fifo_high_threshold =
1370 CX700_IGA2_FIFO_HIGH_THRESHOLD;
1371 iga2_display_queue_expire_num =
1372 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1373 }
1374
1375 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1376 iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1377 iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1378 iga2_fifo_high_threshold =
1379 K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1380 iga2_display_queue_expire_num =
1381 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1382 }
1383
1384 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1385 iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1386 iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1387 iga2_fifo_high_threshold =
1388 P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1389 iga2_display_queue_expire_num =
1390 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1391 }
1392
1393 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1394 iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1395 iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1396 iga2_fifo_high_threshold =
1397 P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1398 iga2_display_queue_expire_num =
1399 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1400 }
1401
1402 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1403 iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1404 iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1405 iga2_fifo_high_threshold =
1406 VX800_IGA2_FIFO_HIGH_THRESHOLD;
1407 iga2_display_queue_expire_num =
1408 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1409 }
1410
1411 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1412 /* Set Display FIFO Depath Select */
1413 reg_value =
1414 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1415 - 1;
1416 /* Patch LCD in IGA2 case */
1417 viafb_load_reg_num =
1418 display_fifo_depth_reg.
1419 iga2_fifo_depth_select_reg.reg_num;
1420 reg =
1421 display_fifo_depth_reg.
1422 iga2_fifo_depth_select_reg.reg;
1423 viafb_load_reg(reg_value,
1424 viafb_load_reg_num, reg, VIACR);
1425 } else {
1426
1427 /* Set Display FIFO Depath Select */
1428 reg_value =
1429 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1430 viafb_load_reg_num =
1431 display_fifo_depth_reg.
1432 iga2_fifo_depth_select_reg.reg_num;
1433 reg =
1434 display_fifo_depth_reg.
1435 iga2_fifo_depth_select_reg.reg;
1436 viafb_load_reg(reg_value,
1437 viafb_load_reg_num, reg, VIACR);
1438 }
1439
1440 /* Set Display FIFO Threshold Select */
1441 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1442 viafb_load_reg_num =
1443 fifo_threshold_select_reg.
1444 iga2_fifo_threshold_select_reg.reg_num;
1445 reg =
1446 fifo_threshold_select_reg.
1447 iga2_fifo_threshold_select_reg.reg;
1448 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1449
1450 /* Set FIFO High Threshold Select */
1451 reg_value =
1452 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1453 viafb_load_reg_num =
1454 fifo_high_threshold_select_reg.
1455 iga2_fifo_high_threshold_select_reg.reg_num;
1456 reg =
1457 fifo_high_threshold_select_reg.
1458 iga2_fifo_high_threshold_select_reg.reg;
1459 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1460
1461 /* Set Display Queue Expire Num */
1462 reg_value =
1463 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1464 (iga2_display_queue_expire_num);
1465 viafb_load_reg_num =
1466 display_queue_expire_num_reg.
1467 iga2_display_queue_expire_num_reg.reg_num;
1468 reg =
1469 display_queue_expire_num_reg.
1470 iga2_display_queue_expire_num_reg.reg;
1471 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1472
1473 }
1474
1475}
1476
1477u32 viafb_get_clk_value(int clk)
1478{
1479 int i;
1480
1481 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1482 if (clk == pll_value[i].clk) {
1483 switch (viaparinfo->chip_info->gfx_chip_name) {
1484 case UNICHROME_CLE266:
1485 case UNICHROME_K400:
1486 return pll_value[i].cle266_pll;
1487
1488 case UNICHROME_K800:
1489 case UNICHROME_PM800:
1490 case UNICHROME_CN700:
1491 return pll_value[i].k800_pll;
1492
1493 case UNICHROME_CX700:
1494 case UNICHROME_K8M890:
1495 case UNICHROME_P4M890:
1496 case UNICHROME_P4M900:
1497 case UNICHROME_VX800:
1498 return pll_value[i].cx700_pll;
1499 }
1500 }
1501 }
1502
1503 DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1504 return 0;
1505}
1506
1507/* Set VCLK*/
1508void viafb_set_vclock(u32 CLK, int set_iga)
1509{
1510 unsigned char RegTemp;
1511
1512 /* H.W. Reset : ON */
1513 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1514
1515 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1516 /* Change D,N FOR VCLK */
1517 switch (viaparinfo->chip_info->gfx_chip_name) {
1518 case UNICHROME_CLE266:
1519 case UNICHROME_K400:
1520 viafb_write_reg(SR46, VIASR, CLK / 0x100);
1521 viafb_write_reg(SR47, VIASR, CLK % 0x100);
1522 break;
1523
1524 case UNICHROME_K800:
1525 case UNICHROME_PM800:
1526 case UNICHROME_CN700:
1527 case UNICHROME_CX700:
1528 case UNICHROME_K8M890:
1529 case UNICHROME_P4M890:
1530 case UNICHROME_P4M900:
1531 case UNICHROME_VX800:
1532 viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1533 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1534 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1535 DEBUG_MSG(KERN_INFO "\nSR45=%x",
1536 (CLK & 0xFFFF) / 0x100);
1537 viafb_write_reg(SR46, VIASR, CLK % 0x100);
1538 DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1539 break;
1540 }
1541 }
1542
1543 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1544 /* Change D,N FOR LCK */
1545 switch (viaparinfo->chip_info->gfx_chip_name) {
1546 case UNICHROME_CLE266:
1547 case UNICHROME_K400:
1548 viafb_write_reg(SR44, VIASR, CLK / 0x100);
1549 viafb_write_reg(SR45, VIASR, CLK % 0x100);
1550 break;
1551
1552 case UNICHROME_K800:
1553 case UNICHROME_PM800:
1554 case UNICHROME_CN700:
1555 case UNICHROME_CX700:
1556 case UNICHROME_K8M890:
1557 case UNICHROME_P4M890:
1558 case UNICHROME_P4M900:
1559 case UNICHROME_VX800:
1560 viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1561 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1562 viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1563 break;
1564 }
1565 }
1566
1567 /* H.W. Reset : OFF */
1568 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1569
1570 /* Reset PLL */
1571 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1572 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1573 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1574 }
1575
1576 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1577 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1578 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1579 }
1580
1581 /* Fire! */
1582 RegTemp = inb(VIARMisc);
1583 outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1584}
1585
1586void viafb_load_crtc_timing(struct display_timing device_timing,
1587 int set_iga)
1588{
1589 int i;
1590 int viafb_load_reg_num = 0;
1591 int reg_value = 0;
1592 struct io_register *reg = NULL;
1593
1594 viafb_unlock_crt();
1595
1596 for (i = 0; i < 12; i++) {
1597 if (set_iga == IGA1) {
1598 switch (i) {
1599 case H_TOTAL_INDEX:
1600 reg_value =
1601 IGA1_HOR_TOTAL_FORMULA(device_timing.
1602 hor_total);
1603 viafb_load_reg_num =
1604 iga1_crtc_reg.hor_total.reg_num;
1605 reg = iga1_crtc_reg.hor_total.reg;
1606 break;
1607 case H_ADDR_INDEX:
1608 reg_value =
1609 IGA1_HOR_ADDR_FORMULA(device_timing.
1610 hor_addr);
1611 viafb_load_reg_num =
1612 iga1_crtc_reg.hor_addr.reg_num;
1613 reg = iga1_crtc_reg.hor_addr.reg;
1614 break;
1615 case H_BLANK_START_INDEX:
1616 reg_value =
1617 IGA1_HOR_BLANK_START_FORMULA
1618 (device_timing.hor_blank_start);
1619 viafb_load_reg_num =
1620 iga1_crtc_reg.hor_blank_start.reg_num;
1621 reg = iga1_crtc_reg.hor_blank_start.reg;
1622 break;
1623 case H_BLANK_END_INDEX:
1624 reg_value =
1625 IGA1_HOR_BLANK_END_FORMULA
1626 (device_timing.hor_blank_start,
1627 device_timing.hor_blank_end);
1628 viafb_load_reg_num =
1629 iga1_crtc_reg.hor_blank_end.reg_num;
1630 reg = iga1_crtc_reg.hor_blank_end.reg;
1631 break;
1632 case H_SYNC_START_INDEX:
1633 reg_value =
1634 IGA1_HOR_SYNC_START_FORMULA
1635 (device_timing.hor_sync_start);
1636 viafb_load_reg_num =
1637 iga1_crtc_reg.hor_sync_start.reg_num;
1638 reg = iga1_crtc_reg.hor_sync_start.reg;
1639 break;
1640 case H_SYNC_END_INDEX:
1641 reg_value =
1642 IGA1_HOR_SYNC_END_FORMULA
1643 (device_timing.hor_sync_start,
1644 device_timing.hor_sync_end);
1645 viafb_load_reg_num =
1646 iga1_crtc_reg.hor_sync_end.reg_num;
1647 reg = iga1_crtc_reg.hor_sync_end.reg;
1648 break;
1649 case V_TOTAL_INDEX:
1650 reg_value =
1651 IGA1_VER_TOTAL_FORMULA(device_timing.
1652 ver_total);
1653 viafb_load_reg_num =
1654 iga1_crtc_reg.ver_total.reg_num;
1655 reg = iga1_crtc_reg.ver_total.reg;
1656 break;
1657 case V_ADDR_INDEX:
1658 reg_value =
1659 IGA1_VER_ADDR_FORMULA(device_timing.
1660 ver_addr);
1661 viafb_load_reg_num =
1662 iga1_crtc_reg.ver_addr.reg_num;
1663 reg = iga1_crtc_reg.ver_addr.reg;
1664 break;
1665 case V_BLANK_START_INDEX:
1666 reg_value =
1667 IGA1_VER_BLANK_START_FORMULA
1668 (device_timing.ver_blank_start);
1669 viafb_load_reg_num =
1670 iga1_crtc_reg.ver_blank_start.reg_num;
1671 reg = iga1_crtc_reg.ver_blank_start.reg;
1672 break;
1673 case V_BLANK_END_INDEX:
1674 reg_value =
1675 IGA1_VER_BLANK_END_FORMULA
1676 (device_timing.ver_blank_start,
1677 device_timing.ver_blank_end);
1678 viafb_load_reg_num =
1679 iga1_crtc_reg.ver_blank_end.reg_num;
1680 reg = iga1_crtc_reg.ver_blank_end.reg;
1681 break;
1682 case V_SYNC_START_INDEX:
1683 reg_value =
1684 IGA1_VER_SYNC_START_FORMULA
1685 (device_timing.ver_sync_start);
1686 viafb_load_reg_num =
1687 iga1_crtc_reg.ver_sync_start.reg_num;
1688 reg = iga1_crtc_reg.ver_sync_start.reg;
1689 break;
1690 case V_SYNC_END_INDEX:
1691 reg_value =
1692 IGA1_VER_SYNC_END_FORMULA
1693 (device_timing.ver_sync_start,
1694 device_timing.ver_sync_end);
1695 viafb_load_reg_num =
1696 iga1_crtc_reg.ver_sync_end.reg_num;
1697 reg = iga1_crtc_reg.ver_sync_end.reg;
1698 break;
1699
1700 }
1701 }
1702
1703 if (set_iga == IGA2) {
1704 switch (i) {
1705 case H_TOTAL_INDEX:
1706 reg_value =
1707 IGA2_HOR_TOTAL_FORMULA(device_timing.
1708 hor_total);
1709 viafb_load_reg_num =
1710 iga2_crtc_reg.hor_total.reg_num;
1711 reg = iga2_crtc_reg.hor_total.reg;
1712 break;
1713 case H_ADDR_INDEX:
1714 reg_value =
1715 IGA2_HOR_ADDR_FORMULA(device_timing.
1716 hor_addr);
1717 viafb_load_reg_num =
1718 iga2_crtc_reg.hor_addr.reg_num;
1719 reg = iga2_crtc_reg.hor_addr.reg;
1720 break;
1721 case H_BLANK_START_INDEX:
1722 reg_value =
1723 IGA2_HOR_BLANK_START_FORMULA
1724 (device_timing.hor_blank_start);
1725 viafb_load_reg_num =
1726 iga2_crtc_reg.hor_blank_start.reg_num;
1727 reg = iga2_crtc_reg.hor_blank_start.reg;
1728 break;
1729 case H_BLANK_END_INDEX:
1730 reg_value =
1731 IGA2_HOR_BLANK_END_FORMULA
1732 (device_timing.hor_blank_start,
1733 device_timing.hor_blank_end);
1734 viafb_load_reg_num =
1735 iga2_crtc_reg.hor_blank_end.reg_num;
1736 reg = iga2_crtc_reg.hor_blank_end.reg;
1737 break;
1738 case H_SYNC_START_INDEX:
1739 reg_value =
1740 IGA2_HOR_SYNC_START_FORMULA
1741 (device_timing.hor_sync_start);
1742 if (UNICHROME_CN700 <=
1743 viaparinfo->chip_info->gfx_chip_name)
1744 viafb_load_reg_num =
1745 iga2_crtc_reg.hor_sync_start.
1746 reg_num;
1747 else
1748 viafb_load_reg_num = 3;
1749 reg = iga2_crtc_reg.hor_sync_start.reg;
1750 break;
1751 case H_SYNC_END_INDEX:
1752 reg_value =
1753 IGA2_HOR_SYNC_END_FORMULA
1754 (device_timing.hor_sync_start,
1755 device_timing.hor_sync_end);
1756 viafb_load_reg_num =
1757 iga2_crtc_reg.hor_sync_end.reg_num;
1758 reg = iga2_crtc_reg.hor_sync_end.reg;
1759 break;
1760 case V_TOTAL_INDEX:
1761 reg_value =
1762 IGA2_VER_TOTAL_FORMULA(device_timing.
1763 ver_total);
1764 viafb_load_reg_num =
1765 iga2_crtc_reg.ver_total.reg_num;
1766 reg = iga2_crtc_reg.ver_total.reg;
1767 break;
1768 case V_ADDR_INDEX:
1769 reg_value =
1770 IGA2_VER_ADDR_FORMULA(device_timing.
1771 ver_addr);
1772 viafb_load_reg_num =
1773 iga2_crtc_reg.ver_addr.reg_num;
1774 reg = iga2_crtc_reg.ver_addr.reg;
1775 break;
1776 case V_BLANK_START_INDEX:
1777 reg_value =
1778 IGA2_VER_BLANK_START_FORMULA
1779 (device_timing.ver_blank_start);
1780 viafb_load_reg_num =
1781 iga2_crtc_reg.ver_blank_start.reg_num;
1782 reg = iga2_crtc_reg.ver_blank_start.reg;
1783 break;
1784 case V_BLANK_END_INDEX:
1785 reg_value =
1786 IGA2_VER_BLANK_END_FORMULA
1787 (device_timing.ver_blank_start,
1788 device_timing.ver_blank_end);
1789 viafb_load_reg_num =
1790 iga2_crtc_reg.ver_blank_end.reg_num;
1791 reg = iga2_crtc_reg.ver_blank_end.reg;
1792 break;
1793 case V_SYNC_START_INDEX:
1794 reg_value =
1795 IGA2_VER_SYNC_START_FORMULA
1796 (device_timing.ver_sync_start);
1797 viafb_load_reg_num =
1798 iga2_crtc_reg.ver_sync_start.reg_num;
1799 reg = iga2_crtc_reg.ver_sync_start.reg;
1800 break;
1801 case V_SYNC_END_INDEX:
1802 reg_value =
1803 IGA2_VER_SYNC_END_FORMULA
1804 (device_timing.ver_sync_start,
1805 device_timing.ver_sync_end);
1806 viafb_load_reg_num =
1807 iga2_crtc_reg.ver_sync_end.reg_num;
1808 reg = iga2_crtc_reg.ver_sync_end.reg;
1809 break;
1810
1811 }
1812 }
1813 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1814 }
1815
1816 viafb_lock_crt();
1817}
1818
1819void viafb_set_color_depth(int bpp_byte, int set_iga)
1820{
1821 if (set_iga == IGA1) {
1822 switch (bpp_byte) {
1823 case MODE_8BPP:
1824 viafb_write_reg_mask(SR15, VIASR, 0x22, 0x7E);
1825 break;
1826 case MODE_16BPP:
1827 viafb_write_reg_mask(SR15, VIASR, 0xB6, 0xFE);
1828 break;
1829 case MODE_32BPP:
1830 viafb_write_reg_mask(SR15, VIASR, 0xAE, 0xFE);
1831 break;
1832 }
1833 } else {
1834 switch (bpp_byte) {
1835 case MODE_8BPP:
1836 viafb_write_reg_mask(CR67, VIACR, 0x00, BIT6 + BIT7);
1837 break;
1838 case MODE_16BPP:
1839 viafb_write_reg_mask(CR67, VIACR, 0x40, BIT6 + BIT7);
1840 break;
1841 case MODE_32BPP:
1842 viafb_write_reg_mask(CR67, VIACR, 0xC0, BIT6 + BIT7);
1843 break;
1844 }
1845 }
1846}
1847
1848void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1849 int mode_index, int bpp_byte, int set_iga)
1850{
1851 struct VideoModeTable *video_mode;
1852 struct display_timing crt_reg;
1853 int i;
1854 int index = 0;
1855 int h_addr, v_addr;
1856 u32 pll_D_N;
1857
1858 video_mode = &CLE266Modes[search_mode_setting(mode_index)];
1859
1860 for (i = 0; i < video_mode->mode_array; i++) {
1861 index = i;
1862
1863 if (crt_table[i].refresh_rate == viaparinfo->
1864 crt_setting_info->refresh_rate)
1865 break;
1866 }
1867
1868 crt_reg = crt_table[index].crtc;
1869
1870 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1871 /* So we would delete border. */
1872 if ((viafb_LCD_ON | viafb_DVI_ON) && (mode_index == VIA_RES_640X480)
1873 && (viaparinfo->crt_setting_info->refresh_rate == 60)) {
1874 /* The border is 8 pixels. */
1875 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1876
1877 /* Blanking time should add left and right borders. */
1878 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1879 }
1880
1881 h_addr = crt_reg.hor_addr;
1882 v_addr = crt_reg.ver_addr;
1883
1884 /* update polarity for CRT timing */
1885 if (crt_table[index].h_sync_polarity == NEGATIVE) {
1886 if (crt_table[index].v_sync_polarity == NEGATIVE)
1887 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1888 (BIT6 + BIT7), VIAWMisc);
1889 else
1890 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1891 VIAWMisc);
1892 } else {
1893 if (crt_table[index].v_sync_polarity == NEGATIVE)
1894 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1895 VIAWMisc);
1896 else
1897 outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1898 }
1899
1900 if (set_iga == IGA1) {
1901 viafb_unlock_crt();
1902 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
1903 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1904 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1905 }
1906
1907 switch (set_iga) {
1908 case IGA1:
1909 viafb_load_crtc_timing(crt_reg, IGA1);
1910 break;
1911 case IGA2:
1912 viafb_load_crtc_timing(crt_reg, IGA2);
1913 break;
1914 }
1915
1916 load_fix_bit_crtc_reg();
1917 viafb_lock_crt();
1918 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1919 viafb_load_offset_reg(h_addr, bpp_byte, set_iga);
1920 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1921
1922 /* load FIFO */
1923 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1924 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1925 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1926
1927 /* load SR Register About Memory and Color part */
1928 viafb_set_color_depth(bpp_byte, set_iga);
1929
1930 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1931 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1932 viafb_set_vclock(pll_D_N, set_iga);
1933
1934}
1935
1936void viafb_init_chip_info(void)
1937{
1938 init_gfx_chip_info();
1939 init_tmds_chip_info();
1940 init_lvds_chip_info();
1941
1942 viaparinfo->crt_setting_info->iga_path = IGA1;
1943 viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1944
1945 /*Set IGA path for each device */
1946 viafb_set_iga_path();
1947
1948 viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1949 viaparinfo->lvds_setting_info->get_lcd_size_method =
1950 GET_LCD_SIZE_BY_USER_SETTING;
1951 viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1952 viaparinfo->lvds_setting_info2->display_method =
1953 viaparinfo->lvds_setting_info->display_method;
1954 viaparinfo->lvds_setting_info2->lcd_mode =
1955 viaparinfo->lvds_setting_info->lcd_mode;
1956}
1957
1958void viafb_update_device_setting(int hres, int vres,
1959 int bpp, int vmode_refresh, int flag)
1960{
1961 if (flag == 0) {
1962 viaparinfo->crt_setting_info->h_active = hres;
1963 viaparinfo->crt_setting_info->v_active = vres;
1964 viaparinfo->crt_setting_info->bpp = bpp;
1965 viaparinfo->crt_setting_info->refresh_rate =
1966 vmode_refresh;
1967
1968 viaparinfo->tmds_setting_info->h_active = hres;
1969 viaparinfo->tmds_setting_info->v_active = vres;
1970 viaparinfo->tmds_setting_info->bpp = bpp;
1971 viaparinfo->tmds_setting_info->refresh_rate =
1972 vmode_refresh;
1973
1974 viaparinfo->lvds_setting_info->h_active = hres;
1975 viaparinfo->lvds_setting_info->v_active = vres;
1976 viaparinfo->lvds_setting_info->bpp = bpp;
1977 viaparinfo->lvds_setting_info->refresh_rate =
1978 vmode_refresh;
1979 viaparinfo->lvds_setting_info2->h_active = hres;
1980 viaparinfo->lvds_setting_info2->v_active = vres;
1981 viaparinfo->lvds_setting_info2->bpp = bpp;
1982 viaparinfo->lvds_setting_info2->refresh_rate =
1983 vmode_refresh;
1984 } else {
1985
1986 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1987 viaparinfo->tmds_setting_info->h_active = hres;
1988 viaparinfo->tmds_setting_info->v_active = vres;
1989 viaparinfo->tmds_setting_info->bpp = bpp;
1990 viaparinfo->tmds_setting_info->refresh_rate =
1991 vmode_refresh;
1992 }
1993
1994 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1995 viaparinfo->lvds_setting_info->h_active = hres;
1996 viaparinfo->lvds_setting_info->v_active = vres;
1997 viaparinfo->lvds_setting_info->bpp = bpp;
1998 viaparinfo->lvds_setting_info->refresh_rate =
1999 vmode_refresh;
2000 }
2001 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2002 viaparinfo->lvds_setting_info2->h_active = hres;
2003 viaparinfo->lvds_setting_info2->v_active = vres;
2004 viaparinfo->lvds_setting_info2->bpp = bpp;
2005 viaparinfo->lvds_setting_info2->refresh_rate =
2006 vmode_refresh;
2007 }
2008 }
2009}
2010
2011static void init_gfx_chip_info(void)
2012{
2013 struct pci_dev *pdev = NULL;
2014 u32 i;
2015 u8 tmp;
2016
2017 /* Indentify GFX Chip Name */
2018 for (i = 0; pciidlist[i].vendor != 0; i++) {
2019 pdev = pci_get_device(pciidlist[i].vendor,
2020 pciidlist[i].device, 0);
2021 if (pdev)
2022 break;
2023 }
2024
2025 if (!pciidlist[i].vendor)
2026 return ;
2027
2028 viaparinfo->chip_info->gfx_chip_name = pciidlist[i].chip_index;
2029
2030 /* Check revision of CLE266 Chip */
2031 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2032 /* CR4F only define in CLE266.CX chip */
2033 tmp = viafb_read_reg(VIACR, CR4F);
2034 viafb_write_reg(CR4F, VIACR, 0x55);
2035 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2036 viaparinfo->chip_info->gfx_chip_revision =
2037 CLE266_REVISION_AX;
2038 else
2039 viaparinfo->chip_info->gfx_chip_revision =
2040 CLE266_REVISION_CX;
2041 /* restore orignal CR4F value */
2042 viafb_write_reg(CR4F, VIACR, tmp);
2043 }
2044
2045 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2046 tmp = viafb_read_reg(VIASR, SR43);
2047 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2048 if (tmp & 0x02) {
2049 viaparinfo->chip_info->gfx_chip_revision =
2050 CX700_REVISION_700M2;
2051 } else if (tmp & 0x40) {
2052 viaparinfo->chip_info->gfx_chip_revision =
2053 CX700_REVISION_700M;
2054 } else {
2055 viaparinfo->chip_info->gfx_chip_revision =
2056 CX700_REVISION_700;
2057 }
2058 }
2059
2060 pci_dev_put(pdev);
2061}
2062
2063static void init_tmds_chip_info(void)
2064{
2065 viafb_tmds_trasmitter_identify();
2066
2067 if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2068 output_interface) {
2069 switch (viaparinfo->chip_info->gfx_chip_name) {
2070 case UNICHROME_CX700:
2071 {
2072 /* we should check support by hardware layout.*/
2073 if ((viafb_display_hardware_layout ==
2074 HW_LAYOUT_DVI_ONLY)
2075 || (viafb_display_hardware_layout ==
2076 HW_LAYOUT_LCD_DVI)) {
2077 viaparinfo->chip_info->tmds_chip_info.
2078 output_interface = INTERFACE_TMDS;
2079 } else {
2080 viaparinfo->chip_info->tmds_chip_info.
2081 output_interface =
2082 INTERFACE_NONE;
2083 }
2084 break;
2085 }
2086 case UNICHROME_K8M890:
2087 case UNICHROME_P4M900:
2088 case UNICHROME_P4M890:
2089 /* TMDS on PCIE, we set DFPLOW as default. */
2090 viaparinfo->chip_info->tmds_chip_info.output_interface =
2091 INTERFACE_DFP_LOW;
2092 break;
2093 default:
2094 {
2095 /* set DVP1 default for DVI */
2096 viaparinfo->chip_info->tmds_chip_info
2097 .output_interface = INTERFACE_DVP1;
2098 }
2099 }
2100 }
2101
2102 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2103 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2104 viaparinfo->tmds_setting_info->get_dvi_size_method =
2105 GET_DVI_SIZE_BY_VGA_BIOS;
2106 viafb_init_dvi_size();
2107}
2108
2109static void init_lvds_chip_info(void)
2110{
2111 if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2112 viaparinfo->lvds_setting_info->get_lcd_size_method =
2113 GET_LCD_SIZE_BY_VGA_BIOS;
2114 else
2115 viaparinfo->lvds_setting_info->get_lcd_size_method =
2116 GET_LCD_SIZE_BY_USER_SETTING;
2117
2118 viafb_lvds_trasmitter_identify();
2119 viafb_init_lcd_size();
2120 viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2121 viaparinfo->lvds_setting_info);
2122 if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2123 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2124 lvds_chip_info2, viaparinfo->lvds_setting_info2);
2125 }
2126 /*If CX700,two singel LCD, we need to reassign
2127 LCD interface to different LVDS port */
2128 if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2129 && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2130 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2131 lvds_chip_name) && (INTEGRATED_LVDS ==
2132 viaparinfo->chip_info->
2133 lvds_chip_info2.lvds_chip_name)) {
2134 viaparinfo->chip_info->lvds_chip_info.output_interface =
2135 INTERFACE_LVDS0;
2136 viaparinfo->chip_info->lvds_chip_info2.
2137 output_interface =
2138 INTERFACE_LVDS1;
2139 }
2140 }
2141
2142 DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2143 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2144 DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2145 viaparinfo->chip_info->lvds_chip_info.output_interface);
2146 DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2147 viaparinfo->chip_info->lvds_chip_info.output_interface);
2148}
2149
2150void viafb_init_dac(int set_iga)
2151{
2152 int i;
2153 u8 tmp;
2154
2155 if (set_iga == IGA1) {
2156 /* access Primary Display's LUT */
2157 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2158 /* turn off LCK */
2159 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2160 for (i = 0; i < 256; i++) {
2161 write_dac_reg(i, palLUT_table[i].red,
2162 palLUT_table[i].green,
2163 palLUT_table[i].blue);
2164 }
2165 /* turn on LCK */
2166 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2167 } else {
2168 tmp = viafb_read_reg(VIACR, CR6A);
2169 /* access Secondary Display's LUT */
2170 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2171 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2172 for (i = 0; i < 256; i++) {
2173 write_dac_reg(i, palLUT_table[i].red,
2174 palLUT_table[i].green,
2175 palLUT_table[i].blue);
2176 }
2177 /* set IGA1 DAC for default */
2178 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2179 viafb_write_reg(CR6A, VIACR, tmp);
2180 }
2181}
2182
2183static void device_screen_off(void)
2184{
2185 /* turn off CRT screen (IGA1) */
2186 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2187}
2188
2189static void device_screen_on(void)
2190{
2191 /* turn on CRT screen (IGA1) */
2192 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2193}
2194
2195static void set_display_channel(void)
2196{
2197 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2198 is keeped on lvds_setting_info2 */
2199 if (viafb_LCD2_ON &&
2200 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2201 /* For dual channel LCD: */
2202 /* Set to Dual LVDS channel. */
2203 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2204 } else if (viafb_LCD_ON && viafb_DVI_ON) {
2205 /* For LCD+DFP: */
2206 /* Set to LVDS1 + TMDS channel. */
2207 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2208 } else if (viafb_DVI_ON) {
2209 /* Set to single TMDS channel. */
2210 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2211 } else if (viafb_LCD_ON) {
2212 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2213 /* For dual channel LCD: */
2214 /* Set to Dual LVDS channel. */
2215 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2216 } else {
2217 /* Set to LVDS0 + LVDS1 channel. */
2218 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2219 }
2220 }
2221}
2222
2223int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2224 int vmode_index1, int hor_res1, int ver_res1, int video_bpp1)
2225{
2226 int i, j;
2227 int port;
2228 u8 value, index, mask;
2229 struct VideoModeTable *vmode_tbl;
2230 struct crt_mode_table *crt_timing;
2231 struct VideoModeTable *vmode_tbl1 = NULL;
2232 struct crt_mode_table *crt_timing1 = NULL;
2233
2234 DEBUG_MSG(KERN_INFO "Set Mode!!\n");
2235 DEBUG_MSG(KERN_INFO
2236 "vmode_index=%d hor_res=%d ver_res=%d video_bpp=%d\n",
2237 vmode_index, hor_res, ver_res, video_bpp);
2238
2239 device_screen_off();
2240 vmode_tbl = &CLE266Modes[search_mode_setting(vmode_index)];
2241 crt_timing = vmode_tbl->crtc;
2242
2243 if (viafb_SAMM_ON == 1) {
2244 vmode_tbl1 = &CLE266Modes[search_mode_setting(vmode_index1)];
2245 crt_timing1 = vmode_tbl1->crtc;
2246 }
2247
2248 inb(VIAStatus);
2249 outb(0x00, VIAAR);
2250
2251 /* Write Common Setting for Video Mode */
2252 switch (viaparinfo->chip_info->gfx_chip_name) {
2253 case UNICHROME_CLE266:
2254 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2255 break;
2256
2257 case UNICHROME_K400:
2258 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2259 break;
2260
2261 case UNICHROME_K800:
2262 case UNICHROME_PM800:
2263 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2264 break;
2265
2266 case UNICHROME_CN700:
2267 case UNICHROME_K8M890:
2268 case UNICHROME_P4M890:
2269 case UNICHROME_P4M900:
2270 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2271 break;
2272
2273 case UNICHROME_CX700:
2274 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2275
2276 case UNICHROME_VX800:
2277 viafb_write_regx(VX800_ModeXregs, NUM_TOTAL_VX800_ModeXregs);
2278
2279 break;
2280 }
2281
2282 device_off();
2283
2284 /* Fill VPIT Parameters */
2285 /* Write Misc Register */
2286 outb(VPIT.Misc, VIAWMisc);
2287
2288 /* Write Sequencer */
2289 for (i = 1; i <= StdSR; i++) {
2290 outb(i, VIASR);
2291 outb(VPIT.SR[i - 1], VIASR + 1);
2292 }
2293
2294 viafb_set_start_addr();
2295 viafb_set_iga_path();
2296
2297 /* Write CRTC */
2298 viafb_fill_crtc_timing(crt_timing, vmode_index, video_bpp / 8, IGA1);
2299
2300 /* Write Graphic Controller */
2301 for (i = 0; i < StdGR; i++) {
2302 outb(i, VIAGR);
2303 outb(VPIT.GR[i], VIAGR + 1);
2304 }
2305
2306 /* Write Attribute Controller */
2307 for (i = 0; i < StdAR; i++) {
2308 inb(VIAStatus);
2309 outb(i, VIAAR);
2310 outb(VPIT.AR[i], VIAAR);
2311 }
2312
2313 inb(VIAStatus);
2314 outb(0x20, VIAAR);
2315
2316 /* Update Patch Register */
2317
2318 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2319 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)) {
2320 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2321 if (res_patch_table[i].mode_index == vmode_index) {
2322 for (j = 0;
2323 j < res_patch_table[i].table_length; j++) {
2324 index =
2325 res_patch_table[i].
2326 io_reg_table[j].index;
2327 port =
2328 res_patch_table[i].
2329 io_reg_table[j].port;
2330 value =
2331 res_patch_table[i].
2332 io_reg_table[j].value;
2333 mask =
2334 res_patch_table[i].
2335 io_reg_table[j].mask;
2336 viafb_write_reg_mask(index, port, value,
2337 mask);
2338 }
2339 }
2340 }
2341 }
2342
2343 if (viafb_SAMM_ON == 1) {
2344 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2345 || (viaparinfo->chip_info->gfx_chip_name ==
2346 UNICHROME_K400)) {
2347 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2348 if (res_patch_table[i].mode_index ==
2349 vmode_index1) {
2350 for (j = 0;
2351 j <
2352 res_patch_table[i].
2353 table_length; j++) {
2354 index =
2355 res_patch_table[i].
2356 io_reg_table[j].index;
2357 port =
2358 res_patch_table[i].
2359 io_reg_table[j].port;
2360 value =
2361 res_patch_table[i].
2362 io_reg_table[j].value;
2363 mask =
2364 res_patch_table[i].
2365 io_reg_table[j].mask;
2366 viafb_write_reg_mask(index,
2367 port, value, mask);
2368 }
2369 }
2370 }
2371 }
2372 }
2373
2374 /* Update Refresh Rate Setting */
2375
2376 /* Clear On Screen */
2377
2378 /* CRT set mode */
2379 if (viafb_CRT_ON) {
2380 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2381 IGA2)) {
2382 viafb_fill_crtc_timing(crt_timing1, vmode_index1,
2383 video_bpp1 / 8,
2384 viaparinfo->crt_setting_info->iga_path);
2385 } else {
2386 viafb_fill_crtc_timing(crt_timing, vmode_index,
2387 video_bpp / 8,
2388 viaparinfo->crt_setting_info->iga_path);
2389 }
2390
2391 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2392
2393 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2394 to 8 alignment (1368),there is several pixels (2 pixels)
2395 on right side of screen. */
2396 if (hor_res % 8) {
2397 viafb_unlock_crt();
2398 viafb_write_reg(CR02, VIACR,
2399 viafb_read_reg(VIACR, CR02) - 1);
2400 viafb_lock_crt();
2401 }
2402 }
2403
2404 if (viafb_DVI_ON) {
2405 if (viafb_SAMM_ON &&
2406 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2407 viafb_dvi_set_mode(viafb_get_mode_index
2408 (viaparinfo->tmds_setting_info->h_active,
2409 viaparinfo->tmds_setting_info->
2410 v_active, 1),
2411 video_bpp1, viaparinfo->
2412 tmds_setting_info->iga_path);
2413 } else {
2414 viafb_dvi_set_mode(viafb_get_mode_index
2415 (viaparinfo->tmds_setting_info->h_active,
2416 viaparinfo->
2417 tmds_setting_info->v_active, 0),
2418 video_bpp, viaparinfo->
2419 tmds_setting_info->iga_path);
2420 }
2421 }
2422
2423 if (viafb_LCD_ON) {
2424 if (viafb_SAMM_ON &&
2425 (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2426 viaparinfo->lvds_setting_info->bpp = video_bpp1;
2427 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2428 lvds_setting_info,
2429 &viaparinfo->chip_info->lvds_chip_info);
2430 } else {
2431 /* IGA1 doesn't have LCD scaling, so set it center. */
2432 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2433 viaparinfo->lvds_setting_info->display_method =
2434 LCD_CENTERING;
2435 }
2436 viaparinfo->lvds_setting_info->bpp = video_bpp;
2437 viafb_lcd_set_mode(crt_timing, viaparinfo->
2438 lvds_setting_info,
2439 &viaparinfo->chip_info->lvds_chip_info);
2440 }
2441 }
2442 if (viafb_LCD2_ON) {
2443 if (viafb_SAMM_ON &&
2444 (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2445 viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2446 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2447 lvds_setting_info2,
2448 &viaparinfo->chip_info->lvds_chip_info2);
2449 } else {
2450 /* IGA1 doesn't have LCD scaling, so set it center. */
2451 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2452 viaparinfo->lvds_setting_info2->display_method =
2453 LCD_CENTERING;
2454 }
2455 viaparinfo->lvds_setting_info2->bpp = video_bpp;
2456 viafb_lcd_set_mode(crt_timing, viaparinfo->
2457 lvds_setting_info2,
2458 &viaparinfo->chip_info->lvds_chip_info2);
2459 }
2460 }
2461
2462 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2463 && (viafb_LCD_ON || viafb_DVI_ON))
2464 set_display_channel();
2465
2466 /* If set mode normally, save resolution information for hot-plug . */
2467 if (!viafb_hotplug) {
2468 viafb_hotplug_Xres = hor_res;
2469 viafb_hotplug_Yres = ver_res;
2470 viafb_hotplug_bpp = video_bpp;
2471 viafb_hotplug_refresh = viafb_refresh;
2472
2473 if (viafb_DVI_ON)
2474 viafb_DeviceStatus = DVI_Device;
2475 else
2476 viafb_DeviceStatus = CRT_Device;
2477 }
2478 device_on();
2479
2480 if (viafb_SAMM_ON == 1)
2481 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2482
2483 device_screen_on();
2484 return 1;
2485}
2486
2487int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2488{
2489 int i;
2490
2491 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2492 if ((hres == res_map_refresh_tbl[i].hres)
2493 && (vres == res_map_refresh_tbl[i].vres)
2494 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2495 return res_map_refresh_tbl[i].pixclock;
2496 }
2497 return RES_640X480_60HZ_PIXCLOCK;
2498
2499}
2500
2501int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2502{
2503#define REFRESH_TOLERANCE 3
2504 int i, nearest = -1, diff = REFRESH_TOLERANCE;
2505 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2506 if ((hres == res_map_refresh_tbl[i].hres)
2507 && (vres == res_map_refresh_tbl[i].vres)
2508 && (diff > (abs(long_refresh -
2509 res_map_refresh_tbl[i].vmode_refresh)))) {
2510 diff = abs(long_refresh - res_map_refresh_tbl[i].
2511 vmode_refresh);
2512 nearest = i;
2513 }
2514 }
2515#undef REFRESH_TOLERANCE
2516 if (nearest > 0)
2517 return res_map_refresh_tbl[nearest].vmode_refresh;
2518 return 60;
2519}
2520
2521static void device_off(void)
2522{
2523 viafb_crt_disable();
2524 viafb_dvi_disable();
2525 viafb_lcd_disable();
2526}
2527
2528static void device_on(void)
2529{
2530 if (viafb_CRT_ON == 1)
2531 viafb_crt_enable();
2532 if (viafb_DVI_ON == 1)
2533 viafb_dvi_enable();
2534 if (viafb_LCD_ON == 1)
2535 viafb_lcd_enable();
2536}
2537
2538void viafb_crt_disable(void)
2539{
2540 viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2541}
2542
2543void viafb_crt_enable(void)
2544{
2545 viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2546}
2547
2548void viafb_get_mmio_info(unsigned long *mmio_base,
2549 unsigned long *mmio_len)
2550{
2551 struct pci_dev *pdev = NULL;
2552 u32 vendor, device;
2553 u32 i;
2554
2555 for (i = 0; pciidlist[i].vendor != 0; i++)
2556 if (viaparinfo->chip_info->gfx_chip_name ==
2557 pciidlist[i].chip_index)
2558 break;
2559
2560 if (!pciidlist[i].vendor)
2561 return ;
2562
2563 vendor = pciidlist[i].vendor;
2564 device = pciidlist[i].device;
2565
2566 pdev = pci_get_device(vendor, device, NULL);
2567
2568 if (!pdev) {
2569 *mmio_base = 0;
2570 *mmio_len = 0;
2571 return ;
2572 }
2573
2574 *mmio_base = pci_resource_start(pdev, 1);
2575 *mmio_len = pci_resource_len(pdev, 1);
2576
2577 pci_dev_put(pdev);
2578}
2579
2580static void enable_second_display_channel(void)
2581{
2582 /* to enable second display channel. */
2583 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2584 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2585 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2586}
2587
2588static void disable_second_display_channel(void)
2589{
2590 /* to disable second display channel. */
2591 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2592 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2593 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2594}
2595
2596void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len)
2597{
2598 struct pci_dev *pdev = NULL;
2599 u32 vendor, device;
2600 u32 i;
2601
2602 for (i = 0; pciidlist[i].vendor != 0; i++)
2603 if (viaparinfo->chip_info->gfx_chip_name ==
2604 pciidlist[i].chip_index)
2605 break;
2606
2607 if (!pciidlist[i].vendor)
2608 return ;
2609
2610 vendor = pciidlist[i].vendor;
2611 device = pciidlist[i].device;
2612
2613 pdev = pci_get_device(vendor, device, NULL);
2614
2615 if (!pdev) {
2616 *fb_base = viafb_read_reg(VIASR, SR30) << 24;
2617 *fb_len = viafb_get_memsize();
2618 DEBUG_MSG(KERN_INFO "Get FB info from SR30!\n");
2619 DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
2620 DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
2621 return ;
2622 }
2623
2624 *fb_base = (unsigned int)pci_resource_start(pdev, 0);
2625 *fb_len = get_fb_size_from_pci();
2626 DEBUG_MSG(KERN_INFO "Get FB info from PCI system!\n");
2627 DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
2628 DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
2629
2630 pci_dev_put(pdev);
2631}
2632
2633static int get_fb_size_from_pci(void)
2634{
2635 unsigned long configid, deviceid, FBSize = 0;
2636 int VideoMemSize;
2637 int DeviceFound = false;
2638
2639 for (configid = 0x80000000; configid < 0x80010800; configid += 0x100) {
2640 outl(configid, (unsigned long)0xCF8);
2641 deviceid = (inl((unsigned long)0xCFC) >> 16) & 0xffff;
2642
2643 switch (deviceid) {
2644 case CLE266:
2645 case KM400:
2646 outl(configid + 0xE0, (unsigned long)0xCF8);
2647 FBSize = inl((unsigned long)0xCFC);
2648 DeviceFound = true; /* Found device id */
2649 break;
2650
2651 case CN400_FUNCTION3:
2652 case CN700_FUNCTION3:
2653 case CX700_FUNCTION3:
2654 case KM800_FUNCTION3:
2655 case KM890_FUNCTION3:
2656 case P4M890_FUNCTION3:
2657 case P4M900_FUNCTION3:
2658 case VX800_FUNCTION3:
2659 /*case CN750_FUNCTION3: */
2660 outl(configid + 0xA0, (unsigned long)0xCF8);
2661 FBSize = inl((unsigned long)0xCFC);
2662 DeviceFound = true; /* Found device id */
2663 break;
2664
2665 default:
2666 break;
2667 }
2668
2669 if (DeviceFound)
2670 break;
2671 }
2672
2673 DEBUG_MSG(KERN_INFO "Device ID = %lx\n", deviceid);
2674
2675 FBSize = FBSize & 0x00007000;
2676 DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2677
2678 if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2679 switch (FBSize) {
2680 case 0x00004000:
2681 VideoMemSize = (16 << 20); /*16M */
2682 break;
2683
2684 case 0x00005000:
2685 VideoMemSize = (32 << 20); /*32M */
2686 break;
2687
2688 case 0x00006000:
2689 VideoMemSize = (64 << 20); /*64M */
2690 break;
2691
2692 default:
2693 VideoMemSize = (32 << 20); /*32M */
2694 break;
2695 }
2696 } else {
2697 switch (FBSize) {
2698 case 0x00001000:
2699 VideoMemSize = (8 << 20); /*8M */
2700 break;
2701
2702 case 0x00002000:
2703 VideoMemSize = (16 << 20); /*16M */
2704 break;
2705
2706 case 0x00003000:
2707 VideoMemSize = (32 << 20); /*32M */
2708 break;
2709
2710 case 0x00004000:
2711 VideoMemSize = (64 << 20); /*64M */
2712 break;
2713
2714 case 0x00005000:
2715 VideoMemSize = (128 << 20); /*128M */
2716 break;
2717
2718 case 0x00006000:
2719 VideoMemSize = (256 << 20); /*256M */
2720 break;
2721
2722 default:
2723 VideoMemSize = (32 << 20); /*32M */
2724 break;
2725 }
2726 }
2727
2728 return VideoMemSize;
2729}
2730
2731void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2732 *p_gfx_dpa_setting)
2733{
2734 switch (output_interface) {
2735 case INTERFACE_DVP0:
2736 {
2737 /* DVP0 Clock Polarity and Adjust: */
2738 viafb_write_reg_mask(CR96, VIACR,
2739 p_gfx_dpa_setting->DVP0, 0x0F);
2740
2741 /* DVP0 Clock and Data Pads Driving: */
2742 viafb_write_reg_mask(SR1E, VIASR,
2743 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2744 viafb_write_reg_mask(SR2A, VIASR,
2745 p_gfx_dpa_setting->DVP0ClockDri_S1,
2746 BIT4);
2747 viafb_write_reg_mask(SR1B, VIASR,
2748 p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2749 viafb_write_reg_mask(SR2A, VIASR,
2750 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2751 break;
2752 }
2753
2754 case INTERFACE_DVP1:
2755 {
2756 /* DVP1 Clock Polarity and Adjust: */
2757 viafb_write_reg_mask(CR9B, VIACR,
2758 p_gfx_dpa_setting->DVP1, 0x0F);
2759
2760 /* DVP1 Clock and Data Pads Driving: */
2761 viafb_write_reg_mask(SR65, VIASR,
2762 p_gfx_dpa_setting->DVP1Driving, 0x0F);
2763 break;
2764 }
2765
2766 case INTERFACE_DFP_HIGH:
2767 {
2768 viafb_write_reg_mask(CR97, VIACR,
2769 p_gfx_dpa_setting->DFPHigh, 0x0F);
2770 break;
2771 }
2772
2773 case INTERFACE_DFP_LOW:
2774 {
2775 viafb_write_reg_mask(CR99, VIACR,
2776 p_gfx_dpa_setting->DFPLow, 0x0F);
2777 break;
2778 }
2779
2780 case INTERFACE_DFP:
2781 {
2782 viafb_write_reg_mask(CR97, VIACR,
2783 p_gfx_dpa_setting->DFPHigh, 0x0F);
2784 viafb_write_reg_mask(CR99, VIACR,
2785 p_gfx_dpa_setting->DFPLow, 0x0F);
2786 break;
2787 }
2788 }
2789}
2790
2791void viafb_memory_pitch_patch(struct fb_info *info)
2792{
2793 if (info->var.xres != info->var.xres_virtual) {
2794 viafb_load_offset_reg(info->var.xres_virtual,
2795 info->var.bits_per_pixel >> 3, IGA1);
2796
2797 if (viafb_SAMM_ON) {
2798 viafb_load_offset_reg(viafb_second_virtual_xres,
2799 viafb_bpp1 >> 3,
2800 IGA2);
2801 } else {
2802 viafb_load_offset_reg(info->var.xres_virtual,
2803 info->var.bits_per_pixel >> 3, IGA2);
2804 }
2805
2806 }
2807}
2808
2809/*According var's xres, yres fill var's other timing information*/
2810void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2811 int mode_index)
2812{
2813 struct VideoModeTable *vmode_tbl = NULL;
2814 struct crt_mode_table *crt_timing = NULL;
2815 struct display_timing crt_reg;
2816 int i = 0, index = 0;
2817 vmode_tbl = &CLE266Modes[search_mode_setting(mode_index)];
2818 crt_timing = vmode_tbl->crtc;
2819 for (i = 0; i < vmode_tbl->mode_array; i++) {
2820 index = i;
2821 if (crt_timing[i].refresh_rate == refresh)
2822 break;
2823 }
2824
2825 crt_reg = crt_timing[index].crtc;
2826 switch (var->bits_per_pixel) {
2827 case 8:
2828 var->red.offset = 0;
2829 var->green.offset = 0;
2830 var->blue.offset = 0;
2831 var->red.length = 6;
2832 var->green.length = 6;
2833 var->blue.length = 6;
2834 break;
2835 case 16:
2836 var->red.offset = 11;
2837 var->green.offset = 5;
2838 var->blue.offset = 0;
2839 var->red.length = 5;
2840 var->green.length = 6;
2841 var->blue.length = 5;
2842 break;
2843 case 32:
2844 var->red.offset = 16;
2845 var->green.offset = 8;
2846 var->blue.offset = 0;
2847 var->red.length = 8;
2848 var->green.length = 8;
2849 var->blue.length = 8;
2850 break;
2851 default:
2852 /* never happed, put here to keep consistent */
2853 break;
2854 }
2855
2856 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2857 var->left_margin =
2858 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2859 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2860 var->hsync_len = crt_reg.hor_sync_end;
2861 var->upper_margin =
2862 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2863 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2864 var->vsync_len = crt_reg.ver_sync_end;
2865}
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
new file mode 100644
index 000000000000..6ff38fa8569a
--- /dev/null
+++ b/drivers/video/via/hw.h
@@ -0,0 +1,933 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __HW_H__
23#define __HW_H__
24
25#include "global.h"
26
27/***************************************************
28* Definition IGA1 Design Method of CRTC Registers *
29****************************************************/
30#define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5)
31#define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1)
32#define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1)
33#define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1)
34#define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8)
35#define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8)
36
37#define IGA1_VER_TOTAL_FORMULA(x) ((x)-2)
38#define IGA1_VER_ADDR_FORMULA(x) ((x)-1)
39#define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1)
40#define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
41#define IGA1_VER_SYNC_START_FORMULA(x) ((x)-1)
42#define IGA1_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
43
44/***************************************************
45** Definition IGA2 Design Method of CRTC Registers *
46****************************************************/
47#define IGA2_HOR_TOTAL_FORMULA(x) ((x)-1)
48#define IGA2_HOR_ADDR_FORMULA(x) ((x)-1)
49#define IGA2_HOR_BLANK_START_FORMULA(x) ((x)-1)
50#define IGA2_HOR_BLANK_END_FORMULA(x, y) ((x+y)-1)
51#define IGA2_HOR_SYNC_START_FORMULA(x) ((x)-1)
52#define IGA2_HOR_SYNC_END_FORMULA(x, y) ((x+y)-1)
53
54#define IGA2_VER_TOTAL_FORMULA(x) ((x)-1)
55#define IGA2_VER_ADDR_FORMULA(x) ((x)-1)
56#define IGA2_VER_BLANK_START_FORMULA(x) ((x)-1)
57#define IGA2_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
58#define IGA2_VER_SYNC_START_FORMULA(x) ((x)-1)
59#define IGA2_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
60
61/**********************************************************/
62/* Definition IGA2 Design Method of CRTC Shadow Registers */
63/**********************************************************/
64#define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5)
65#define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1)
66#define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2)
67#define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1)
68#define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1)
69#define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1)
70#define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x)
71#define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y)
72
73/* Define Register Number for IGA1 CRTC Timing */
74
75/* location: {CR00,0,7},{CR36,3,3} */
76#define IGA1_HOR_TOTAL_REG_NUM 2
77/* location: {CR01,0,7} */
78#define IGA1_HOR_ADDR_REG_NUM 1
79/* location: {CR02,0,7} */
80#define IGA1_HOR_BLANK_START_REG_NUM 1
81/* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
82#define IGA1_HOR_BLANK_END_REG_NUM 3
83/* location: {CR04,0,7},{CR33,4,4} */
84#define IGA1_HOR_SYNC_START_REG_NUM 2
85/* location: {CR05,0,4} */
86#define IGA1_HOR_SYNC_END_REG_NUM 1
87/* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
88#define IGA1_VER_TOTAL_REG_NUM 4
89/* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
90#define IGA1_VER_ADDR_REG_NUM 4
91/* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
92#define IGA1_VER_BLANK_START_REG_NUM 4
93/* location: {CR16,0,7} */
94#define IGA1_VER_BLANK_END_REG_NUM 1
95/* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
96#define IGA1_VER_SYNC_START_REG_NUM 4
97/* location: {CR11,0,3} */
98#define IGA1_VER_SYNC_END_REG_NUM 1
99
100/* Define Register Number for IGA2 Shadow CRTC Timing */
101
102/* location: {CR6D,0,7},{CR71,3,3} */
103#define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2
104/* location: {CR6E,0,7} */
105#define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1
106/* location: {CR6F,0,7},{CR71,0,2} */
107#define IGA2_SHADOW_VER_TOTAL_REG_NUM 2
108/* location: {CR70,0,7},{CR71,4,6} */
109#define IGA2_SHADOW_VER_ADDR_REG_NUM 2
110/* location: {CR72,0,7},{CR74,4,6} */
111#define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
112/* location: {CR73,0,7},{CR74,0,2} */
113#define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2
114/* location: {CR75,0,7},{CR76,4,6} */
115#define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2
116/* location: {CR76,0,3} */
117#define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1
118
119/* Define Register Number for IGA2 CRTC Timing */
120
121/* location: {CR50,0,7},{CR55,0,3} */
122#define IGA2_HOR_TOTAL_REG_NUM 2
123/* location: {CR51,0,7},{CR55,4,6} */
124#define IGA2_HOR_ADDR_REG_NUM 2
125/* location: {CR52,0,7},{CR54,0,2} */
126#define IGA2_HOR_BLANK_START_REG_NUM 2
127/* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
128is reserved, so it may have problem to set 1600x1200 on IGA2. */
129/* Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
130#define IGA2_HOR_BLANK_END_REG_NUM 3
131/* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
132/* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
133#define IGA2_HOR_SYNC_START_REG_NUM 4
134
135/* location: {CR57,0,7},{CR5C,6,6} */
136#define IGA2_HOR_SYNC_END_REG_NUM 2
137/* location: {CR58,0,7},{CR5D,0,2} */
138#define IGA2_VER_TOTAL_REG_NUM 2
139/* location: {CR59,0,7},{CR5D,3,5} */
140#define IGA2_VER_ADDR_REG_NUM 2
141/* location: {CR5A,0,7},{CR5C,0,2} */
142#define IGA2_VER_BLANK_START_REG_NUM 2
143/* location: {CR5E,0,7},{CR5C,3,5} */
144#define IGA2_VER_BLANK_END_REG_NUM 2
145/* location: {CR5E,0,7},{CR5F,5,7} */
146#define IGA2_VER_SYNC_START_REG_NUM 2
147/* location: {CR5F,0,4} */
148#define IGA2_VER_SYNC_END_REG_NUM 1
149
150/* Define Offset and Fetch Count Register*/
151
152/* location: {CR13,0,7},{CR35,5,7} */
153#define IGA1_OFFSET_REG_NUM 2
154/* 8 bytes alignment. */
155#define IGA1_OFFSER_ALIGN_BYTE 8
156/* x: H resolution, y: color depth */
157#define IGA1_OFFSET_FORMULA(x, y) ((x*y)/IGA1_OFFSER_ALIGN_BYTE)
158/* location: {SR1C,0,7},{SR1D,0,1} */
159#define IGA1_FETCH_COUNT_REG_NUM 2
160/* 16 bytes alignment. */
161#define IGA1_FETCH_COUNT_ALIGN_BYTE 16
162/* x: H resolution, y: color depth */
163#define IGA1_FETCH_COUNT_PATCH_VALUE 4
164#define IGA1_FETCH_COUNT_FORMULA(x, y) \
165 (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
166
167/* location: {CR66,0,7},{CR67,0,1} */
168#define IGA2_OFFSET_REG_NUM 2
169#define IGA2_OFFSET_ALIGN_BYTE 8
170/* x: H resolution, y: color depth */
171#define IGA2_OFFSET_FORMULA(x, y) ((x*y)/IGA2_OFFSET_ALIGN_BYTE)
172/* location: {CR65,0,7},{CR67,2,3} */
173#define IGA2_FETCH_COUNT_REG_NUM 2
174#define IGA2_FETCH_COUNT_ALIGN_BYTE 16
175#define IGA2_FETCH_COUNT_PATCH_VALUE 0
176#define IGA2_FETCH_COUNT_FORMULA(x, y) \
177 (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
178
179/* Staring Address*/
180
181/* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
182#define IGA1_STARTING_ADDR_REG_NUM 4
183/* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
184#define IGA2_STARTING_ADDR_REG_NUM 3
185
186/* Define Display OFFSET*/
187/* These value are by HW suggested value*/
188/* location: {SR17,0,7} */
189#define K800_IGA1_FIFO_MAX_DEPTH 384
190/* location: {SR16,0,5},{SR16,7,7} */
191#define K800_IGA1_FIFO_THRESHOLD 328
192/* location: {SR18,0,5},{SR18,7,7} */
193#define K800_IGA1_FIFO_HIGH_THRESHOLD 296
194/* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
195 /* because HW only 5 bits */
196#define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
197
198/* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
199#define K800_IGA2_FIFO_MAX_DEPTH 384
200/* location: {CR68,0,3},{CR95,4,6} */
201#define K800_IGA2_FIFO_THRESHOLD 328
202/* location: {CR92,0,3},{CR95,0,2} */
203#define K800_IGA2_FIFO_HIGH_THRESHOLD 296
204/* location: {CR94,0,6} */
205#define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
206
207/* location: {SR17,0,7} */
208#define P880_IGA1_FIFO_MAX_DEPTH 192
209/* location: {SR16,0,5},{SR16,7,7} */
210#define P880_IGA1_FIFO_THRESHOLD 128
211/* location: {SR18,0,5},{SR18,7,7} */
212#define P880_IGA1_FIFO_HIGH_THRESHOLD 64
213/* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
214 /* because HW only 5 bits */
215#define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
216
217/* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
218#define P880_IGA2_FIFO_MAX_DEPTH 96
219/* location: {CR68,0,3},{CR95,4,6} */
220#define P880_IGA2_FIFO_THRESHOLD 64
221/* location: {CR92,0,3},{CR95,0,2} */
222#define P880_IGA2_FIFO_HIGH_THRESHOLD 32
223/* location: {CR94,0,6} */
224#define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
225
226/* VT3314 chipset*/
227
228/* location: {SR17,0,7} */
229#define CN700_IGA1_FIFO_MAX_DEPTH 96
230/* location: {SR16,0,5},{SR16,7,7} */
231#define CN700_IGA1_FIFO_THRESHOLD 80
232/* location: {SR18,0,5},{SR18,7,7} */
233#define CN700_IGA1_FIFO_HIGH_THRESHOLD 64
234/* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
235 because HW only 5 bits */
236#define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
237/* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
238#define CN700_IGA2_FIFO_MAX_DEPTH 96
239/* location: {CR68,0,3},{CR95,4,6} */
240#define CN700_IGA2_FIFO_THRESHOLD 80
241/* location: {CR92,0,3},{CR95,0,2} */
242#define CN700_IGA2_FIFO_HIGH_THRESHOLD 32
243/* location: {CR94,0,6} */
244#define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
245
246/* For VT3324, these values are suggested by HW */
247/* location: {SR17,0,7} */
248#define CX700_IGA1_FIFO_MAX_DEPTH 192
249/* location: {SR16,0,5},{SR16,7,7} */
250#define CX700_IGA1_FIFO_THRESHOLD 128
251/* location: {SR18,0,5},{SR18,7,7} */
252#define CX700_IGA1_FIFO_HIGH_THRESHOLD 128
253/* location: {SR22,0,4} */
254#define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
255
256/* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
257#define CX700_IGA2_FIFO_MAX_DEPTH 96
258/* location: {CR68,0,3},{CR95,4,6} */
259#define CX700_IGA2_FIFO_THRESHOLD 64
260/* location: {CR92,0,3},{CR95,0,2} */
261#define CX700_IGA2_FIFO_HIGH_THRESHOLD 32
262/* location: {CR94,0,6} */
263#define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
264
265/* VT3336 chipset*/
266/* location: {SR17,0,7} */
267#define K8M890_IGA1_FIFO_MAX_DEPTH 360
268/* location: {SR16,0,5},{SR16,7,7} */
269#define K8M890_IGA1_FIFO_THRESHOLD 328
270/* location: {SR18,0,5},{SR18,7,7} */
271#define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296
272/* location: {SR22,0,4}. */
273#define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
274
275/* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
276#define K8M890_IGA2_FIFO_MAX_DEPTH 360
277/* location: {CR68,0,3},{CR95,4,6} */
278#define K8M890_IGA2_FIFO_THRESHOLD 328
279/* location: {CR92,0,3},{CR95,0,2} */
280#define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296
281/* location: {CR94,0,6} */
282#define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124
283
284/* VT3327 chipset*/
285/* location: {SR17,0,7} */
286#define P4M890_IGA1_FIFO_MAX_DEPTH 96
287/* location: {SR16,0,5},{SR16,7,7} */
288#define P4M890_IGA1_FIFO_THRESHOLD 76
289/* location: {SR18,0,5},{SR18,7,7} */
290#define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64
291/* location: {SR22,0,4}. (32/4) =8 */
292#define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
293/* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
294#define P4M890_IGA2_FIFO_MAX_DEPTH 96
295/* location: {CR68,0,3},{CR95,4,6} */
296#define P4M890_IGA2_FIFO_THRESHOLD 76
297/* location: {CR92,0,3},{CR95,0,2} */
298#define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64
299/* location: {CR94,0,6} */
300#define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
301
302/* VT3364 chipset*/
303/* location: {SR17,0,7} */
304#define P4M900_IGA1_FIFO_MAX_DEPTH 96
305/* location: {SR16,0,5},{SR16,7,7} */
306#define P4M900_IGA1_FIFO_THRESHOLD 76
307/* location: {SR18,0,5},{SR18,7,7} */
308#define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76
309/* location: {SR22,0,4}. */
310#define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
311/* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
312#define P4M900_IGA2_FIFO_MAX_DEPTH 96
313/* location: {CR68,0,3},{CR95,4,6} */
314#define P4M900_IGA2_FIFO_THRESHOLD 76
315/* location: {CR92,0,3},{CR95,0,2} */
316#define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76
317/* location: {CR94,0,6} */
318#define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
319
320/* For VT3353, these values are suggested by HW */
321/* location: {SR17,0,7} */
322#define VX800_IGA1_FIFO_MAX_DEPTH 192
323/* location: {SR16,0,5},{SR16,7,7} */
324#define VX800_IGA1_FIFO_THRESHOLD 152
325/* location: {SR18,0,5},{SR18,7,7} */
326#define VX800_IGA1_FIFO_HIGH_THRESHOLD 152
327/* location: {SR22,0,4} */
328#define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64
329/* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
330#define VX800_IGA2_FIFO_MAX_DEPTH 96
331/* location: {CR68,0,3},{CR95,4,6} */
332#define VX800_IGA2_FIFO_THRESHOLD 64
333/* location: {CR92,0,3},{CR95,0,2} */
334#define VX800_IGA2_FIFO_HIGH_THRESHOLD 32
335/* location: {CR94,0,6} */
336#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
337
338#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
339#define IGA1_FIFO_THRESHOLD_REG_NUM 2
340#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
341#define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
342
343#define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3
344#define IGA2_FIFO_THRESHOLD_REG_NUM 2
345#define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2
346#define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
347
348#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1)
349#define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4)
350#define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
351#define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
352#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1)
353#define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4)
354#define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
355#define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
356
357/************************************************************************/
358/* LCD Timing */
359/************************************************************************/
360
361/* 500 ms = 500000 us */
362#define LCD_POWER_SEQ_TD0 500000
363/* 50 ms = 50000 us */
364#define LCD_POWER_SEQ_TD1 50000
365/* 0 us */
366#define LCD_POWER_SEQ_TD2 0
367/* 210 ms = 210000 us */
368#define LCD_POWER_SEQ_TD3 210000
369/* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
370#define CLE266_POWER_SEQ_UNIT 71
371/* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
372#define K800_POWER_SEQ_UNIT 142
373/* 2^13 * (1/14.31818M) = 572.1 us */
374#define P880_POWER_SEQ_UNIT 572
375
376#define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT)
377#define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT)
378#define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT)
379
380/* location: {CR8B,0,7},{CR8F,0,3} */
381#define LCD_POWER_SEQ_TD0_REG_NUM 2
382/* location: {CR8C,0,7},{CR8F,4,7} */
383#define LCD_POWER_SEQ_TD1_REG_NUM 2
384/* location: {CR8D,0,7},{CR90,0,3} */
385#define LCD_POWER_SEQ_TD2_REG_NUM 2
386/* location: {CR8E,0,7},{CR90,4,7} */
387#define LCD_POWER_SEQ_TD3_REG_NUM 2
388
389/* LCD Scaling factor*/
390/* x: indicate setting horizontal size*/
391/* y: indicate panel horizontal size*/
392
393/* Horizontal scaling factor 10 bits (2^10) */
394#define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
395/* Vertical scaling factor 10 bits (2^10) */
396#define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
397/* Horizontal scaling factor 10 bits (2^12) */
398#define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1))
399/* Vertical scaling factor 10 bits (2^11) */
400#define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1))
401
402/* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
403#define LCD_HOR_SCALING_FACTOR_REG_NUM 3
404/* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
405#define LCD_VER_SCALING_FACTOR_REG_NUM 3
406/* location: {CR77,0,7},{CR79,4,5} */
407#define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2
408/* location: {CR78,0,7},{CR79,6,7} */
409#define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2
410
411/************************************************
412 ***** Define IGA1 Display Timing *****
413 ************************************************/
414struct io_register {
415 u8 io_addr;
416 u8 start_bit;
417 u8 end_bit;
418};
419
420/* IGA1 Horizontal Total */
421struct iga1_hor_total {
422 int reg_num;
423 struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
424};
425
426/* IGA1 Horizontal Addressable Video */
427struct iga1_hor_addr {
428 int reg_num;
429 struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
430};
431
432/* IGA1 Horizontal Blank Start */
433struct iga1_hor_blank_start {
434 int reg_num;
435 struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
436};
437
438/* IGA1 Horizontal Blank End */
439struct iga1_hor_blank_end {
440 int reg_num;
441 struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
442};
443
444/* IGA1 Horizontal Sync Start */
445struct iga1_hor_sync_start {
446 int reg_num;
447 struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
448};
449
450/* IGA1 Horizontal Sync End */
451struct iga1_hor_sync_end {
452 int reg_num;
453 struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
454};
455
456/* IGA1 Vertical Total */
457struct iga1_ver_total {
458 int reg_num;
459 struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
460};
461
462/* IGA1 Vertical Addressable Video */
463struct iga1_ver_addr {
464 int reg_num;
465 struct io_register reg[IGA1_VER_ADDR_REG_NUM];
466};
467
468/* IGA1 Vertical Blank Start */
469struct iga1_ver_blank_start {
470 int reg_num;
471 struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
472};
473
474/* IGA1 Vertical Blank End */
475struct iga1_ver_blank_end {
476 int reg_num;
477 struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
478};
479
480/* IGA1 Vertical Sync Start */
481struct iga1_ver_sync_start {
482 int reg_num;
483 struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
484};
485
486/* IGA1 Vertical Sync End */
487struct iga1_ver_sync_end {
488 int reg_num;
489 struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
490};
491
492/*****************************************************
493** Define IGA2 Shadow Display Timing ****
494*****************************************************/
495
496/* IGA2 Shadow Horizontal Total */
497struct iga2_shadow_hor_total {
498 int reg_num;
499 struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
500};
501
502/* IGA2 Shadow Horizontal Blank End */
503struct iga2_shadow_hor_blank_end {
504 int reg_num;
505 struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
506};
507
508/* IGA2 Shadow Vertical Total */
509struct iga2_shadow_ver_total {
510 int reg_num;
511 struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
512};
513
514/* IGA2 Shadow Vertical Addressable Video */
515struct iga2_shadow_ver_addr {
516 int reg_num;
517 struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
518};
519
520/* IGA2 Shadow Vertical Blank Start */
521struct iga2_shadow_ver_blank_start {
522 int reg_num;
523 struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
524};
525
526/* IGA2 Shadow Vertical Blank End */
527struct iga2_shadow_ver_blank_end {
528 int reg_num;
529 struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
530};
531
532/* IGA2 Shadow Vertical Sync Start */
533struct iga2_shadow_ver_sync_start {
534 int reg_num;
535 struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
536};
537
538/* IGA2 Shadow Vertical Sync End */
539struct iga2_shadow_ver_sync_end {
540 int reg_num;
541 struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
542};
543
544/*****************************************************
545** Define IGA2 Display Timing ****
546******************************************************/
547
548/* IGA2 Horizontal Total */
549struct iga2_hor_total {
550 int reg_num;
551 struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
552};
553
554/* IGA2 Horizontal Addressable Video */
555struct iga2_hor_addr {
556 int reg_num;
557 struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
558};
559
560/* IGA2 Horizontal Blank Start */
561struct iga2_hor_blank_start {
562 int reg_num;
563 struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
564};
565
566/* IGA2 Horizontal Blank End */
567struct iga2_hor_blank_end {
568 int reg_num;
569 struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
570};
571
572/* IGA2 Horizontal Sync Start */
573struct iga2_hor_sync_start {
574 int reg_num;
575 struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
576};
577
578/* IGA2 Horizontal Sync End */
579struct iga2_hor_sync_end {
580 int reg_num;
581 struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
582};
583
584/* IGA2 Vertical Total */
585struct iga2_ver_total {
586 int reg_num;
587 struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
588};
589
590/* IGA2 Vertical Addressable Video */
591struct iga2_ver_addr {
592 int reg_num;
593 struct io_register reg[IGA2_VER_ADDR_REG_NUM];
594};
595
596/* IGA2 Vertical Blank Start */
597struct iga2_ver_blank_start {
598 int reg_num;
599 struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
600};
601
602/* IGA2 Vertical Blank End */
603struct iga2_ver_blank_end {
604 int reg_num;
605 struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
606};
607
608/* IGA2 Vertical Sync Start */
609struct iga2_ver_sync_start {
610 int reg_num;
611 struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
612};
613
614/* IGA2 Vertical Sync End */
615struct iga2_ver_sync_end {
616 int reg_num;
617 struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
618};
619
620/* IGA1 Offset Register */
621struct iga1_offset {
622 int reg_num;
623 struct io_register reg[IGA1_OFFSET_REG_NUM];
624};
625
626/* IGA2 Offset Register */
627struct iga2_offset {
628 int reg_num;
629 struct io_register reg[IGA2_OFFSET_REG_NUM];
630};
631
632struct offset {
633 struct iga1_offset iga1_offset_reg;
634 struct iga2_offset iga2_offset_reg;
635};
636
637/* IGA1 Fetch Count Register */
638struct iga1_fetch_count {
639 int reg_num;
640 struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
641};
642
643/* IGA2 Fetch Count Register */
644struct iga2_fetch_count {
645 int reg_num;
646 struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
647};
648
649struct fetch_count {
650 struct iga1_fetch_count iga1_fetch_count_reg;
651 struct iga2_fetch_count iga2_fetch_count_reg;
652};
653
654/* Starting Address Register */
655struct iga1_starting_addr {
656 int reg_num;
657 struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
658};
659
660struct iga2_starting_addr {
661 int reg_num;
662 struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
663};
664
665struct starting_addr {
666 struct iga1_starting_addr iga1_starting_addr_reg;
667 struct iga2_starting_addr iga2_starting_addr_reg;
668};
669
670/* LCD Power Sequence Timer */
671struct lcd_pwd_seq_td0 {
672 int reg_num;
673 struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
674};
675
676struct lcd_pwd_seq_td1 {
677 int reg_num;
678 struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
679};
680
681struct lcd_pwd_seq_td2 {
682 int reg_num;
683 struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
684};
685
686struct lcd_pwd_seq_td3 {
687 int reg_num;
688 struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
689};
690
691struct _lcd_pwd_seq_timer {
692 struct lcd_pwd_seq_td0 td0;
693 struct lcd_pwd_seq_td1 td1;
694 struct lcd_pwd_seq_td2 td2;
695 struct lcd_pwd_seq_td3 td3;
696};
697
698/* LCD Scaling Factor */
699struct _lcd_hor_scaling_factor {
700 int reg_num;
701 struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
702};
703
704struct _lcd_ver_scaling_factor {
705 int reg_num;
706 struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
707};
708
709struct _lcd_scaling_factor {
710 struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
711 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
712};
713
714struct pll_map {
715 u32 clk;
716 u32 cle266_pll;
717 u32 k800_pll;
718 u32 cx700_pll;
719};
720
721struct rgbLUT {
722 u8 red;
723 u8 green;
724 u8 blue;
725};
726
727struct lcd_pwd_seq_timer {
728 u16 td0;
729 u16 td1;
730 u16 td2;
731 u16 td3;
732};
733
734/* Display FIFO Relation Registers*/
735struct iga1_fifo_depth_select {
736 int reg_num;
737 struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
738};
739
740struct iga1_fifo_threshold_select {
741 int reg_num;
742 struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
743};
744
745struct iga1_fifo_high_threshold_select {
746 int reg_num;
747 struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
748};
749
750struct iga1_display_queue_expire_num {
751 int reg_num;
752 struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
753};
754
755struct iga2_fifo_depth_select {
756 int reg_num;
757 struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
758};
759
760struct iga2_fifo_threshold_select {
761 int reg_num;
762 struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
763};
764
765struct iga2_fifo_high_threshold_select {
766 int reg_num;
767 struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
768};
769
770struct iga2_display_queue_expire_num {
771 int reg_num;
772 struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
773};
774
775struct fifo_depth_select {
776 struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
777 struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
778};
779
780struct fifo_threshold_select {
781 struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
782 struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
783};
784
785struct fifo_high_threshold_select {
786 struct iga1_fifo_high_threshold_select
787 iga1_fifo_high_threshold_select_reg;
788 struct iga2_fifo_high_threshold_select
789 iga2_fifo_high_threshold_select_reg;
790};
791
792struct display_queue_expire_num {
793 struct iga1_display_queue_expire_num
794 iga1_display_queue_expire_num_reg;
795 struct iga2_display_queue_expire_num
796 iga2_display_queue_expire_num_reg;
797};
798
799struct iga1_crtc_timing {
800 struct iga1_hor_total hor_total;
801 struct iga1_hor_addr hor_addr;
802 struct iga1_hor_blank_start hor_blank_start;
803 struct iga1_hor_blank_end hor_blank_end;
804 struct iga1_hor_sync_start hor_sync_start;
805 struct iga1_hor_sync_end hor_sync_end;
806 struct iga1_ver_total ver_total;
807 struct iga1_ver_addr ver_addr;
808 struct iga1_ver_blank_start ver_blank_start;
809 struct iga1_ver_blank_end ver_blank_end;
810 struct iga1_ver_sync_start ver_sync_start;
811 struct iga1_ver_sync_end ver_sync_end;
812};
813
814struct iga2_shadow_crtc_timing {
815 struct iga2_shadow_hor_total hor_total_shadow;
816 struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
817 struct iga2_shadow_ver_total ver_total_shadow;
818 struct iga2_shadow_ver_addr ver_addr_shadow;
819 struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
820 struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
821 struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
822 struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
823};
824
825struct iga2_crtc_timing {
826 struct iga2_hor_total hor_total;
827 struct iga2_hor_addr hor_addr;
828 struct iga2_hor_blank_start hor_blank_start;
829 struct iga2_hor_blank_end hor_blank_end;
830 struct iga2_hor_sync_start hor_sync_start;
831 struct iga2_hor_sync_end hor_sync_end;
832 struct iga2_ver_total ver_total;
833 struct iga2_ver_addr ver_addr;
834 struct iga2_ver_blank_start ver_blank_start;
835 struct iga2_ver_blank_end ver_blank_end;
836 struct iga2_ver_sync_start ver_sync_start;
837 struct iga2_ver_sync_end ver_sync_end;
838};
839
840/* device ID */
841#define CLE266 0x3123
842#define KM400 0x3205
843#define CN400_FUNCTION2 0x2259
844#define CN400_FUNCTION3 0x3259
845/* support VT3314 chipset */
846#define CN700_FUNCTION2 0x2314
847#define CN700_FUNCTION3 0x3208
848/* VT3324 chipset */
849#define CX700_FUNCTION2 0x2324
850#define CX700_FUNCTION3 0x3324
851/* VT3204 chipset*/
852#define KM800_FUNCTION3 0x3204
853/* VT3336 chipset*/
854#define KM890_FUNCTION3 0x3336
855/* VT3327 chipset*/
856#define P4M890_FUNCTION3 0x3327
857/* VT3293 chipset*/
858#define CN750_FUNCTION3 0x3208
859/* VT3364 chipset*/
860#define P4M900_FUNCTION3 0x3364
861/* VT3353 chipset*/
862#define VX800_FUNCTION3 0x3353
863
864#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
865
866struct IODATA {
867 u8 Index;
868 u8 Mask;
869 u8 Data;
870};
871
872struct pci_device_id_info {
873 u32 vendor;
874 u32 device;
875 u32 chip_index;
876};
877
878extern unsigned int viafb_second_virtual_xres;
879extern unsigned int viafb_second_offset;
880extern int viafb_second_size;
881extern int viafb_SAMM_ON;
882extern int viafb_dual_fb;
883extern int viafb_LCD2_ON;
884extern int viafb_LCD_ON;
885extern int viafb_DVI_ON;
886extern int viafb_accel;
887extern int viafb_hotplug;
888
889void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask);
890void viafb_set_output_path(int device, int set_iga,
891 int output_interface);
892void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
893 int mode_index, int bpp_byte, int set_iga);
894
895void viafb_set_vclock(u32 CLK, int set_iga);
896void viafb_load_reg(int timing_value, int viafb_load_reg_num,
897 struct io_register *reg,
898 int io_type);
899void viafb_crt_disable(void);
900void viafb_crt_enable(void);
901void init_ad9389(void);
902/* Access I/O Function */
903void viafb_write_reg(u8 index, u16 io_port, u8 data);
904u8 viafb_read_reg(int io_port, u8 index);
905void viafb_lock_crt(void);
906void viafb_unlock_crt(void);
907void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga);
908void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
909void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
910struct VideoModeTable *viafb_get_modetbl_pointer(int Index);
911u32 viafb_get_clk_value(int clk);
912void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
913void viafb_set_color_depth(int bpp_byte, int set_iga);
914void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
915 *p_gfx_dpa_setting);
916
917int viafb_setmode(int vmode_index, int hor_res, int ver_res,
918 int video_bpp, int vmode_index1, int hor_res1,
919 int ver_res1, int video_bpp1);
920void viafb_init_chip_info(void);
921void viafb_init_dac(int set_iga);
922int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
923int viafb_get_refresh(int hres, int vres, u32 float_refresh);
924void viafb_update_device_setting(int hres, int vres, int bpp,
925 int vmode_refresh, int flag);
926void viafb_get_mmio_info(unsigned long *mmio_base,
927 unsigned long *mmio_len);
928
929void viafb_set_iga_path(void);
930void viafb_set_start_addr(void);
931void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
932
933#endif /* __HW_H__ */
diff --git a/drivers/video/via/iface.c b/drivers/video/via/iface.c
new file mode 100644
index 000000000000..1570636c8d51
--- /dev/null
+++ b/drivers/video/via/iface.c
@@ -0,0 +1,78 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24/* Get frame buffer size from VGA BIOS */
25
26unsigned int viafb_get_memsize(void)
27{
28 unsigned int m;
29
30 /* If memory size provided by user */
31 if (viafb_memsize)
32 m = viafb_memsize * Mb;
33 else {
34 m = (unsigned int)viafb_read_reg(VIASR, SR39);
35 m = m * (4 * Mb);
36
37 if ((m < (16 * Mb)) || (m > (64 * Mb)))
38 m = 16 * Mb;
39 }
40 DEBUG_MSG(KERN_INFO "framebuffer size = %d Mb\n", m / Mb);
41 return m;
42}
43
44/* Get Video Buffer Starting Physical Address(back door)*/
45
46unsigned long viafb_get_videobuf_addr(void)
47{
48 struct pci_dev *pdev = NULL;
49 unsigned char sys_mem;
50 unsigned char video_mem;
51 unsigned long sys_mem_size;
52 unsigned long video_mem_size;
53 /*system memory = 256 MB, video memory 64 MB */
54 unsigned long vmem_starting_adr = 0x0C000000;
55
56 pdev =
57 (struct pci_dev *)pci_get_device(VIA_K800_BRIDGE_VID,
58 VIA_K800_BRIDGE_DID, NULL);
59 if (pdev != NULL) {
60 pci_read_config_byte(pdev, VIA_K800_SYSTEM_MEMORY_REG,
61 &sys_mem);
62 pci_read_config_byte(pdev, VIA_K800_VIDEO_MEMORY_REG,
63 &video_mem);
64 video_mem = (video_mem & 0x70) >> 4;
65 sys_mem_size = ((unsigned long)sys_mem) << 24;
66 if (video_mem != 0)
67 video_mem_size = (1 << (video_mem)) * 1024 * 1024;
68 else
69 video_mem_size = 0;
70
71 vmem_starting_adr = sys_mem_size - video_mem_size;
72 pci_dev_put(pdev);
73 }
74
75 DEBUG_MSG(KERN_INFO "Video Memory Starting Address = %lx \n",
76 vmem_starting_adr);
77 return vmem_starting_adr;
78}
diff --git a/drivers/video/via/iface.h b/drivers/video/via/iface.h
new file mode 100644
index 000000000000..790ec3e3aea2
--- /dev/null
+++ b/drivers/video/via/iface.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __IFACE_H__
23#define __IFACE_H__
24
25#define Kb (1024)
26#define Mb (Kb*Kb)
27
28#define VIA_K800_BRIDGE_VID 0x1106
29#define VIA_K800_BRIDGE_DID 0x3204
30
31#define VIA_K800_SYSTEM_MEMORY_REG 0x47
32#define VIA_K800_VIDEO_MEMORY_REG 0xA1
33
34extern int viafb_memsize;
35unsigned int viafb_get_memsize(void);
36unsigned long viafb_get_videobuf_addr(void);
37
38#endif /* __IFACE_H__ */
diff --git a/drivers/video/via/ioctl.c b/drivers/video/via/ioctl.c
new file mode 100644
index 000000000000..da03c074e32a
--- /dev/null
+++ b/drivers/video/via/ioctl.c
@@ -0,0 +1,112 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24int viafb_ioctl_get_viafb_info(u_long arg)
25{
26 struct viafb_ioctl_info viainfo;
27
28 viainfo.viafb_id = VIAID;
29 viainfo.vendor_id = PCI_VIA_VENDOR_ID;
30
31 switch (viaparinfo->chip_info->gfx_chip_name) {
32 case UNICHROME_CLE266:
33 viainfo.device_id = UNICHROME_CLE266_DID;
34 break;
35
36 case UNICHROME_K400:
37 viainfo.device_id = UNICHROME_K400_DID;
38 break;
39
40 case UNICHROME_K800:
41 viainfo.device_id = UNICHROME_K800_DID;
42 break;
43
44 case UNICHROME_PM800:
45 viainfo.device_id = UNICHROME_PM800_DID;
46 break;
47
48 case UNICHROME_CN700:
49 viainfo.device_id = UNICHROME_CN700_DID;
50 break;
51
52 case UNICHROME_CX700:
53 viainfo.device_id = UNICHROME_CX700_DID;
54 break;
55
56 case UNICHROME_K8M890:
57 viainfo.device_id = UNICHROME_K8M890_DID;
58 break;
59
60 case UNICHROME_P4M890:
61 viainfo.device_id = UNICHROME_P4M890_DID;
62 break;
63
64 case UNICHROME_P4M900:
65 viainfo.device_id = UNICHROME_P4M900_DID;
66 break;
67 }
68
69 viainfo.version = VERSION_MAJOR;
70 viainfo.revision = VERSION_MINOR;
71
72 if (copy_to_user((void __user *)arg, &viainfo, sizeof(viainfo)))
73 return -EFAULT;
74
75 return 0;
76}
77
78/* Hot-Plug Priority: DVI > CRT*/
79int viafb_ioctl_hotplug(int hres, int vres, int bpp)
80{
81 int DVIsense, status = 0;
82 DEBUG_MSG(KERN_INFO "viafb_ioctl_hotplug!!\n");
83
84 if (viaparinfo->chip_info->tmds_chip_info.tmds_chip_name !=
85 NON_TMDS_TRANSMITTER) {
86 DVIsense = viafb_dvi_sense();
87
88 if (DVIsense) {
89 DEBUG_MSG(KERN_INFO "DVI Attached...\n");
90 if (viafb_DeviceStatus != DVI_Device) {
91 viafb_DVI_ON = 1;
92 viafb_CRT_ON = 0;
93 viafb_LCD_ON = 0;
94 viafb_DeviceStatus = DVI_Device;
95 return viafb_DeviceStatus;
96 }
97 status = 1;
98 } else
99 DEBUG_MSG(KERN_INFO "DVI De-attached...\n");
100 }
101
102 if ((viafb_DeviceStatus != CRT_Device) && (status == 0)) {
103 viafb_CRT_ON = 1;
104 viafb_DVI_ON = 0;
105 viafb_LCD_ON = 0;
106
107 viafb_DeviceStatus = CRT_Device;
108 return viafb_DeviceStatus;
109 }
110
111 return 0;
112}
diff --git a/drivers/video/via/ioctl.h b/drivers/video/via/ioctl.h
new file mode 100644
index 000000000000..842fe30b9868
--- /dev/null
+++ b/drivers/video/via/ioctl.h
@@ -0,0 +1,210 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __IOCTL_H__
23#define __IOCTL_H__
24
25#ifndef __user
26#define __user
27#endif
28
29/* VIAFB IOCTL definition */
30#define VIAFB_GET_INFO_SIZE 0x56494101 /* 'VIA\01' */
31#define VIAFB_GET_INFO 0x56494102 /* 'VIA\02' */
32#define VIAFB_HOTPLUG 0x56494103 /* 'VIA\03' */
33#define VIAFB_SET_HOTPLUG_FLAG 0x56494104 /* 'VIA\04' */
34#define VIAFB_GET_RESOLUTION 0x56494105 /* 'VIA\05' */
35#define VIAFB_GET_SAMM_INFO 0x56494107 /* 'VIA\07' */
36#define VIAFB_TURN_ON_OUTPUT_DEVICE 0x56494108 /* 'VIA\08' */
37#define VIAFB_TURN_OFF_OUTPUT_DEVICE 0x56494109 /* 'VIA\09' */
38#define VIAFB_SET_DEVICE 0x5649410A
39#define VIAFB_GET_DEVICE 0x5649410B
40#define VIAFB_GET_DRIVER_VERSION 0x56494112 /* 'VIA\12' */
41#define VIAFB_GET_CHIP_INFO 0x56494113 /* 'VIA\13' */
42#define VIAFB_SET_DEVICE_INFO 0x56494114
43#define VIAFB_GET_DEVICE_INFO 0x56494115
44
45#define VIAFB_GET_DEVICE_SUPPORT 0x56494118
46#define VIAFB_GET_DEVICE_CONNECT 0x56494119
47#define VIAFB_GET_PANEL_SUPPORT_EXPAND 0x5649411A
48#define VIAFB_GET_DRIVER_NAME 0x56494122
49#define VIAFB_GET_DEVICE_SUPPORT_STATE 0x56494123
50#define VIAFB_GET_GAMMA_LUT 0x56494124
51#define VIAFB_SET_GAMMA_LUT 0x56494125
52#define VIAFB_GET_GAMMA_SUPPORT_STATE 0x56494126
53#define VIAFB_SET_VIDEO_DEVICE 0x56494127
54#define VIAFB_GET_VIDEO_DEVICE 0x56494128
55#define VIAFB_SET_SECOND_MODE 0x56494129
56#define VIAFB_SYNC_SURFACE 0x56494130
57#define VIAFB_GET_DRIVER_CAPS 0x56494131
58#define VIAFB_GET_IGA_SCALING_INFO 0x56494132
59#define VIAFB_GET_PANEL_MAX_SIZE 0x56494133
60#define VIAFB_GET_PANEL_MAX_POSITION 0x56494134
61#define VIAFB_SET_PANEL_SIZE 0x56494135
62#define VIAFB_SET_PANEL_POSITION 0x56494136
63#define VIAFB_GET_PANEL_POSITION 0x56494137
64#define VIAFB_GET_PANEL_SIZE 0x56494138
65
66#define None_Device 0x00
67#define CRT_Device 0x01
68#define LCD_Device 0x02
69#define DVI_Device 0x08
70#define CRT2_Device 0x10
71#define LCD2_Device 0x40
72
73#define OP_LCD_CENTERING 0x01
74#define OP_LCD_PANEL_ID 0x02
75#define OP_LCD_MODE 0x03
76
77/*SAMM operation flag*/
78#define OP_SAMM 0x80
79
80#define LCD_PANEL_ID_MAXIMUM 22
81
82#define STATE_ON 0x1
83#define STATE_OFF 0x0
84#define STATE_DEFAULT 0xFFFF
85
86#define MAX_ACTIVE_DEV_NUM 2
87
88struct device_t {
89 unsigned short crt:1;
90 unsigned short dvi:1;
91 unsigned short lcd:1;
92 unsigned short samm:1;
93 unsigned short lcd_dsp_cent:1;
94 unsigned char lcd_mode:1;
95 unsigned short epia_dvi:1;
96 unsigned short lcd_dual_edge:1;
97 unsigned short lcd2:1;
98
99 unsigned short primary_dev;
100 unsigned char lcd_panel_id;
101 unsigned short xres, yres;
102 unsigned short xres1, yres1;
103 unsigned short refresh;
104 unsigned short bpp;
105 unsigned short refresh1;
106 unsigned short bpp1;
107 unsigned short sequence;
108 unsigned short bus_width;
109};
110
111struct viafb_ioctl_info {
112 u32 viafb_id; /* for identifying viafb */
113#define VIAID 0x56494146 /* Identify myself with 'VIAF' */
114 u16 vendor_id;
115 u16 device_id;
116 u8 version;
117 u8 revision;
118 u8 reserved[246]; /* for future use */
119};
120
121struct viafb_ioctl_mode {
122 u32 xres;
123 u32 yres;
124 u32 refresh;
125 u32 bpp;
126 u32 xres_sec;
127 u32 yres_sec;
128 u32 virtual_xres_sec;
129 u32 virtual_yres_sec;
130 u32 refresh_sec;
131 u32 bpp_sec;
132};
133struct viafb_ioctl_samm {
134 u32 samm_status;
135 u32 size_prim;
136 u32 size_sec;
137 u32 mem_base;
138 u32 offset_sec;
139};
140
141struct viafb_driver_version {
142 int iMajorNum;
143 int iKernelNum;
144 int iOSNum;
145 int iMinorNum;
146};
147
148struct viafb_ioctl_lcd_attribute {
149 unsigned int panel_id;
150 unsigned int display_center;
151 unsigned int lcd_mode;
152};
153
154struct viafb_ioctl_setting {
155 /* Enable or disable active devices */
156 unsigned short device_flag;
157 /* Indicate which device should be turn on or turn off. */
158 unsigned short device_status;
159 unsigned int reserved;
160 /* Indicate which LCD's attribute can be changed. */
161 unsigned short lcd_operation_flag;
162 /* 1: SAMM ON 0: SAMM OFF */
163 unsigned short samm_status;
164 /* horizontal resolution of first device */
165 unsigned short first_dev_hor_res;
166 /* vertical resolution of first device */
167 unsigned short first_dev_ver_res;
168 /* horizontal resolution of second device */
169 unsigned short second_dev_hor_res;
170 /* vertical resolution of second device */
171 unsigned short second_dev_ver_res;
172 /* refresh rate of first device */
173 unsigned short first_dev_refresh;
174 /* bpp of first device */
175 unsigned short first_dev_bpp;
176 /* refresh rate of second device */
177 unsigned short second_dev_refresh;
178 /* bpp of second device */
179 unsigned short second_dev_bpp;
180 /* Indicate which device are primary display device. */
181 unsigned int primary_device;
182 /* Indicate which device will show video. only valid in duoview mode */
183 unsigned int video_device_status;
184 unsigned int struct_reserved[34];
185 struct viafb_ioctl_lcd_attribute lcd_attributes;
186};
187
188struct _UTFunctionCaps {
189 unsigned int dw3DScalingState;
190 unsigned int reserved[31];
191};
192
193struct _POSITIONVALUE {
194 unsigned int dwX;
195 unsigned int dwY;
196};
197
198struct _panel_size_pos_info {
199 unsigned int device_type;
200 int x;
201 int y;
202};
203
204extern int viafb_LCD_ON;
205extern int viafb_DVI_ON;
206
207int viafb_ioctl_get_viafb_info(u_long arg);
208int viafb_ioctl_hotplug(int hres, int vres, int bpp);
209
210#endif /* __IOCTL_H__ */
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
new file mode 100644
index 000000000000..6c7290a6a447
--- /dev/null
+++ b/drivers/video/via/lcd.c
@@ -0,0 +1,1821 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23#include "lcdtbl.h"
24
25static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = {
26 /* IGA2 Shadow Horizontal Total */
27 {IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D, 0, 7}, {CR71, 3, 3} } },
28 /* IGA2 Shadow Horizontal Blank End */
29 {IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E, 0, 7} } },
30 /* IGA2 Shadow Vertical Total */
31 {IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F, 0, 7}, {CR71, 0, 2} } },
32 /* IGA2 Shadow Vertical Addressable Video */
33 {IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70, 0, 7}, {CR71, 4, 6} } },
34 /* IGA2 Shadow Vertical Blank Start */
35 {IGA2_SHADOW_VER_BLANK_START_REG_NUM,
36 {{CR72, 0, 7}, {CR74, 4, 6} } },
37 /* IGA2 Shadow Vertical Blank End */
38 {IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73, 0, 7}, {CR74, 0, 2} } },
39 /* IGA2 Shadow Vertical Sync Start */
40 {IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75, 0, 7}, {CR76, 4, 6} } },
41 /* IGA2 Shadow Vertical Sync End */
42 {IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76, 0, 3} } }
43};
44
45static struct _lcd_scaling_factor lcd_scaling_factor = {
46 /* LCD Horizontal Scaling Factor Register */
47 {LCD_HOR_SCALING_FACTOR_REG_NUM,
48 {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
49 /* LCD Vertical Scaling Factor Register */
50 {LCD_VER_SCALING_FACTOR_REG_NUM,
51 {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
52};
53static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
54 /* LCD Horizontal Scaling Factor Register */
55 {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
56 /* LCD Vertical Scaling Factor Register */
57 {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
58};
59
60static int check_lvds_chip(int device_id_subaddr, int device_id);
61static bool lvds_identify_integratedlvds(void);
62static int fp_id_to_vindex(int panel_id);
63static int lvds_register_read(int index);
64static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
65 int panel_vres);
66static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
67 int panel_id);
68static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
69 int panel_id);
70static void load_lcd_patch_regs(int set_hres, int set_vres,
71 int panel_id, int set_iga);
72static void via_pitch_alignment_patch_lcd(
73 struct lvds_setting_information *plvds_setting_info,
74 struct lvds_chip_information
75 *plvds_chip_info);
76static void lcd_patch_skew_dvp0(struct lvds_setting_information
77 *plvds_setting_info,
78 struct lvds_chip_information *plvds_chip_info);
79static void lcd_patch_skew_dvp1(struct lvds_setting_information
80 *plvds_setting_info,
81 struct lvds_chip_information *plvds_chip_info);
82static void lcd_patch_skew(struct lvds_setting_information
83 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
84
85static void integrated_lvds_disable(struct lvds_setting_information
86 *plvds_setting_info,
87 struct lvds_chip_information *plvds_chip_info);
88static void integrated_lvds_enable(struct lvds_setting_information
89 *plvds_setting_info,
90 struct lvds_chip_information *plvds_chip_info);
91static void lcd_powersequence_off(void);
92static void lcd_powersequence_on(void);
93static void fill_lcd_format(void);
94static void check_diport_of_integrated_lvds(
95 struct lvds_chip_information *plvds_chip_info,
96 struct lvds_setting_information
97 *plvds_setting_info);
98static struct display_timing lcd_centering_timging(struct display_timing
99 mode_crt_reg,
100 struct display_timing panel_crt_reg);
101static void load_crtc_shadow_timing(struct display_timing mode_timing,
102 struct display_timing panel_timing);
103static void viafb_load_scaling_factor_for_p4m900(int set_hres,
104 int set_vres, int panel_hres, int panel_vres);
105
106static int check_lvds_chip(int device_id_subaddr, int device_id)
107{
108 if (lvds_register_read(device_id_subaddr) == device_id)
109 return OK;
110 else
111 return FAIL;
112}
113
114void viafb_init_lcd_size(void)
115{
116 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
117 DEBUG_MSG(KERN_INFO
118 "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
119 viaparinfo->lvds_setting_info->get_lcd_size_method);
120
121 switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
122 case GET_LCD_SIZE_BY_SYSTEM_BIOS:
123 break;
124 case GET_LCD_SZIE_BY_HW_STRAPPING:
125 break;
126 case GET_LCD_SIZE_BY_VGA_BIOS:
127 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
128 viaparinfo->lvds_setting_info->lcd_panel_size =
129 fp_id_to_vindex(viafb_lcd_panel_id);
130 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
131 viaparinfo->lvds_setting_info->lcd_panel_id);
132 DEBUG_MSG(KERN_INFO "LCD Panel Size = %d\n",
133 viaparinfo->lvds_setting_info->lcd_panel_size);
134 break;
135 case GET_LCD_SIZE_BY_USER_SETTING:
136 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
137 viaparinfo->lvds_setting_info->lcd_panel_size =
138 fp_id_to_vindex(viafb_lcd_panel_id);
139 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
140 viaparinfo->lvds_setting_info->lcd_panel_id);
141 DEBUG_MSG(KERN_INFO "LCD Panel Size = %d\n",
142 viaparinfo->lvds_setting_info->lcd_panel_size);
143 break;
144 default:
145 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
146 viaparinfo->lvds_setting_info->lcd_panel_id =
147 LCD_PANEL_ID1_800X600;
148 viaparinfo->lvds_setting_info->lcd_panel_size =
149 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
150 }
151 viaparinfo->lvds_setting_info2->lcd_panel_id =
152 viaparinfo->lvds_setting_info->lcd_panel_id;
153 viaparinfo->lvds_setting_info2->lcd_panel_size =
154 viaparinfo->lvds_setting_info->lcd_panel_size;
155 viaparinfo->lvds_setting_info2->lcd_panel_hres =
156 viaparinfo->lvds_setting_info->lcd_panel_hres;
157 viaparinfo->lvds_setting_info2->lcd_panel_vres =
158 viaparinfo->lvds_setting_info->lcd_panel_vres;
159 viaparinfo->lvds_setting_info2->device_lcd_dualedge =
160 viaparinfo->lvds_setting_info->device_lcd_dualedge;
161 viaparinfo->lvds_setting_info2->LCDDithering =
162 viaparinfo->lvds_setting_info->LCDDithering;
163}
164
165static bool lvds_identify_integratedlvds(void)
166{
167 if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
168 /* Two dual channel LCD (Internal LVDS + External LVDS): */
169 /* If we have an external LVDS, such as VT1636, we should
170 have its chip ID already. */
171 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
172 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
173 INTEGRATED_LVDS;
174 DEBUG_MSG(KERN_INFO "Support two dual channel LVDS!\
175 (Internal LVDS + External LVDS)\n");
176 } else {
177 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
178 INTEGRATED_LVDS;
179 DEBUG_MSG(KERN_INFO "Not found external LVDS,\
180 so can't support two dual channel LVDS!\n");
181 }
182 } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
183 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
184 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
185 INTEGRATED_LVDS;
186 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
187 INTEGRATED_LVDS;
188 DEBUG_MSG(KERN_INFO "Support two single channel LVDS!\
189 (Internal LVDS + Internal LVDS)\n");
190 } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
191 /* If we have found external LVDS, just use it,
192 otherwise, we will use internal LVDS as default. */
193 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
194 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
195 INTEGRATED_LVDS;
196 DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
197 }
198 } else {
199 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
200 NON_LVDS_TRANSMITTER;
201 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
202 return false;
203 }
204
205 return true;
206}
207
208int viafb_lvds_trasmitter_identify(void)
209{
210 viaparinfo->i2c_stuff.i2c_port = I2CPORTINDEX;
211 if (viafb_lvds_identify_vt1636()) {
212 viaparinfo->chip_info->lvds_chip_info.i2c_port = I2CPORTINDEX;
213 DEBUG_MSG(KERN_INFO
214 "Found VIA VT1636 LVDS on port i2c 0x31 \n");
215 } else {
216 viaparinfo->i2c_stuff.i2c_port = GPIOPORTINDEX;
217 if (viafb_lvds_identify_vt1636()) {
218 viaparinfo->chip_info->lvds_chip_info.i2c_port =
219 GPIOPORTINDEX;
220 DEBUG_MSG(KERN_INFO
221 "Found VIA VT1636 LVDS on port gpio 0x2c \n");
222 }
223 }
224
225 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
226 lvds_identify_integratedlvds();
227
228 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
229 return true;
230 /* Check for VT1631: */
231 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
232 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
233 VT1631_LVDS_I2C_ADDR;
234
235 if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
236 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
237 DEBUG_MSG(KERN_INFO "\n %2d",
238 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
239 DEBUG_MSG(KERN_INFO "\n %2d",
240 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
241 return OK;
242 }
243
244 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
245 NON_LVDS_TRANSMITTER;
246 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
247 VT1631_LVDS_I2C_ADDR;
248 return FAIL;
249}
250
251static int fp_id_to_vindex(int panel_id)
252{
253 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
254
255 if (panel_id > LCD_PANEL_ID_MAXIMUM)
256 viafb_lcd_panel_id = panel_id =
257 viafb_read_reg(VIACR, CR3F) & 0x0F;
258
259 switch (panel_id) {
260 case 0x0:
261 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
262 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
263 viaparinfo->lvds_setting_info->lcd_panel_id =
264 LCD_PANEL_ID0_640X480;
265 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
266 viaparinfo->lvds_setting_info->LCDDithering = 1;
267 return VIA_RES_640X480;
268 break;
269 case 0x1:
270 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
271 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
272 viaparinfo->lvds_setting_info->lcd_panel_id =
273 LCD_PANEL_ID1_800X600;
274 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
275 viaparinfo->lvds_setting_info->LCDDithering = 1;
276 return VIA_RES_800X600;
277 break;
278 case 0x2:
279 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
280 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
281 viaparinfo->lvds_setting_info->lcd_panel_id =
282 LCD_PANEL_ID2_1024X768;
283 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
284 viaparinfo->lvds_setting_info->LCDDithering = 1;
285 return VIA_RES_1024X768;
286 break;
287 case 0x3:
288 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
289 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
290 viaparinfo->lvds_setting_info->lcd_panel_id =
291 LCD_PANEL_ID3_1280X768;
292 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
293 viaparinfo->lvds_setting_info->LCDDithering = 1;
294 return VIA_RES_1280X768;
295 break;
296 case 0x4:
297 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
298 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
299 viaparinfo->lvds_setting_info->lcd_panel_id =
300 LCD_PANEL_ID4_1280X1024;
301 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
302 viaparinfo->lvds_setting_info->LCDDithering = 1;
303 return VIA_RES_1280X1024;
304 break;
305 case 0x5:
306 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
307 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
308 viaparinfo->lvds_setting_info->lcd_panel_id =
309 LCD_PANEL_ID5_1400X1050;
310 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
311 viaparinfo->lvds_setting_info->LCDDithering = 1;
312 return VIA_RES_1400X1050;
313 break;
314 case 0x6:
315 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
316 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
317 viaparinfo->lvds_setting_info->lcd_panel_id =
318 LCD_PANEL_ID6_1600X1200;
319 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
320 viaparinfo->lvds_setting_info->LCDDithering = 1;
321 return VIA_RES_1600X1200;
322 break;
323 case 0x8:
324 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
325 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
326 viaparinfo->lvds_setting_info->lcd_panel_id =
327 LCD_PANEL_IDA_800X480;
328 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
329 viaparinfo->lvds_setting_info->LCDDithering = 1;
330 return VIA_RES_800X480;
331 break;
332 case 0x9:
333 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
334 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
335 viaparinfo->lvds_setting_info->lcd_panel_id =
336 LCD_PANEL_ID2_1024X768;
337 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
338 viaparinfo->lvds_setting_info->LCDDithering = 1;
339 return VIA_RES_1024X768;
340 break;
341 case 0xA:
342 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
343 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
344 viaparinfo->lvds_setting_info->lcd_panel_id =
345 LCD_PANEL_ID2_1024X768;
346 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
347 viaparinfo->lvds_setting_info->LCDDithering = 0;
348 return VIA_RES_1024X768;
349 break;
350 case 0xB:
351 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
352 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
353 viaparinfo->lvds_setting_info->lcd_panel_id =
354 LCD_PANEL_ID2_1024X768;
355 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
356 viaparinfo->lvds_setting_info->LCDDithering = 0;
357 return VIA_RES_1024X768;
358 break;
359 case 0xC:
360 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
361 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
362 viaparinfo->lvds_setting_info->lcd_panel_id =
363 LCD_PANEL_ID3_1280X768;
364 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
365 viaparinfo->lvds_setting_info->LCDDithering = 0;
366 return VIA_RES_1280X768;
367 break;
368 case 0xD:
369 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
370 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
371 viaparinfo->lvds_setting_info->lcd_panel_id =
372 LCD_PANEL_ID4_1280X1024;
373 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
374 viaparinfo->lvds_setting_info->LCDDithering = 0;
375 return VIA_RES_1280X1024;
376 break;
377 case 0xE:
378 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
379 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
380 viaparinfo->lvds_setting_info->lcd_panel_id =
381 LCD_PANEL_ID5_1400X1050;
382 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
383 viaparinfo->lvds_setting_info->LCDDithering = 0;
384 return VIA_RES_1400X1050;
385 break;
386 case 0xF:
387 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
388 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
389 viaparinfo->lvds_setting_info->lcd_panel_id =
390 LCD_PANEL_ID6_1600X1200;
391 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
392 viaparinfo->lvds_setting_info->LCDDithering = 0;
393 return VIA_RES_1600X1200;
394 break;
395 case 0x10:
396 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
397 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
398 viaparinfo->lvds_setting_info->lcd_panel_id =
399 LCD_PANEL_ID7_1366X768;
400 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
401 viaparinfo->lvds_setting_info->LCDDithering = 0;
402 return VIA_RES_1368X768;
403 break;
404 case 0x11:
405 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
406 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
407 viaparinfo->lvds_setting_info->lcd_panel_id =
408 LCD_PANEL_ID8_1024X600;
409 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
410 viaparinfo->lvds_setting_info->LCDDithering = 1;
411 return VIA_RES_1024X600;
412 break;
413 case 0x12:
414 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
415 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
416 viaparinfo->lvds_setting_info->lcd_panel_id =
417 LCD_PANEL_ID3_1280X768;
418 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
419 viaparinfo->lvds_setting_info->LCDDithering = 1;
420 return VIA_RES_1280X768;
421 break;
422 case 0x13:
423 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
424 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
425 viaparinfo->lvds_setting_info->lcd_panel_id =
426 LCD_PANEL_ID9_1280X800;
427 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
428 viaparinfo->lvds_setting_info->LCDDithering = 1;
429 return VIA_RES_1280X800;
430 break;
431 case 0x14:
432 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
433 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
434 viaparinfo->lvds_setting_info->lcd_panel_id =
435 LCD_PANEL_IDB_1360X768;
436 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
437 viaparinfo->lvds_setting_info->LCDDithering = 0;
438 return VIA_RES_1360X768;
439 break;
440 case 0x15:
441 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
442 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
443 viaparinfo->lvds_setting_info->lcd_panel_id =
444 LCD_PANEL_ID3_1280X768;
445 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
446 viaparinfo->lvds_setting_info->LCDDithering = 0;
447 return VIA_RES_1280X768;
448 break;
449 case 0x16:
450 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
451 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
452 viaparinfo->lvds_setting_info->lcd_panel_id =
453 LCD_PANEL_IDC_480X640;
454 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
455 viaparinfo->lvds_setting_info->LCDDithering = 1;
456 return VIA_RES_480X640;
457 break;
458 default:
459 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
460 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
461 viaparinfo->lvds_setting_info->lcd_panel_id =
462 LCD_PANEL_ID1_800X600;
463 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
464 viaparinfo->lvds_setting_info->LCDDithering = 1;
465 return VIA_RES_800X600;
466 }
467}
468
469static int lvds_register_read(int index)
470{
471 u8 data;
472
473 viaparinfo->i2c_stuff.i2c_port = GPIOPORTINDEX;
474 viafb_i2c_readbyte((u8) viaparinfo->chip_info->
475 lvds_chip_info.lvds_chip_slave_addr,
476 (u8) index, &data);
477 return data;
478}
479
480static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
481 int panel_vres)
482{
483 int reg_value = 0;
484 int viafb_load_reg_num;
485 struct io_register *reg = NULL;
486
487 DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
488
489 /* LCD Scaling Enable */
490 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
491 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
492 viafb_load_scaling_factor_for_p4m900(set_hres, set_vres,
493 panel_hres, panel_vres);
494 return;
495 }
496
497 /* Check if expansion for horizontal */
498 if (set_hres != panel_hres) {
499 /* Load Horizontal Scaling Factor */
500 switch (viaparinfo->chip_info->gfx_chip_name) {
501 case UNICHROME_CLE266:
502 case UNICHROME_K400:
503 reg_value =
504 CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
505 viafb_load_reg_num =
506 lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
507 reg_num;
508 reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
509 viafb_load_reg(reg_value,
510 viafb_load_reg_num, reg, VIACR);
511 break;
512 case UNICHROME_K800:
513 case UNICHROME_PM800:
514 case UNICHROME_CN700:
515 case UNICHROME_CX700:
516 case UNICHROME_K8M890:
517 case UNICHROME_P4M890:
518 reg_value =
519 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
520 /* Horizontal scaling enabled */
521 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
522 viafb_load_reg_num =
523 lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
524 reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
525 viafb_load_reg(reg_value,
526 viafb_load_reg_num, reg, VIACR);
527 break;
528 }
529
530 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
531 } else {
532 /* Horizontal scaling disabled */
533 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
534 }
535
536 /* Check if expansion for vertical */
537 if (set_vres != panel_vres) {
538 /* Load Vertical Scaling Factor */
539 switch (viaparinfo->chip_info->gfx_chip_name) {
540 case UNICHROME_CLE266:
541 case UNICHROME_K400:
542 reg_value =
543 CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
544 viafb_load_reg_num =
545 lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
546 reg_num;
547 reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
548 viafb_load_reg(reg_value,
549 viafb_load_reg_num, reg, VIACR);
550 break;
551 case UNICHROME_K800:
552 case UNICHROME_PM800:
553 case UNICHROME_CN700:
554 case UNICHROME_CX700:
555 case UNICHROME_K8M890:
556 case UNICHROME_P4M890:
557 reg_value =
558 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
559 /* Vertical scaling enabled */
560 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
561 viafb_load_reg_num =
562 lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
563 reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
564 viafb_load_reg(reg_value,
565 viafb_load_reg_num, reg, VIACR);
566 break;
567 }
568
569 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
570 } else {
571 /* Vertical scaling disabled */
572 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
573 }
574}
575
576static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
577 int panel_id)
578{
579 int vmode_index;
580 int reg_num = 0;
581 struct io_reg *lcd_patch_reg = NULL;
582
583 if (viaparinfo->lvds_setting_info->iga_path == IGA2)
584 vmode_index = viafb_get_mode_index(set_hres, set_vres, 1);
585 else
586 vmode_index = viafb_get_mode_index(set_hres, set_vres, 0);
587 switch (panel_id) {
588 /* LCD 800x600 */
589 case LCD_PANEL_ID1_800X600:
590 switch (vmode_index) {
591 case VIA_RES_640X400:
592 case VIA_RES_640X480:
593 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_8X6;
594 lcd_patch_reg = K400_LCD_RES_6X4_8X6;
595 break;
596 case VIA_RES_720X480:
597 case VIA_RES_720X576:
598 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_8X6;
599 lcd_patch_reg = K400_LCD_RES_7X4_8X6;
600 break;
601 }
602 break;
603
604 /* LCD 1024x768 */
605 case LCD_PANEL_ID2_1024X768:
606 switch (vmode_index) {
607 case VIA_RES_640X400:
608 case VIA_RES_640X480:
609 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_10X7;
610 lcd_patch_reg = K400_LCD_RES_6X4_10X7;
611 break;
612 case VIA_RES_720X480:
613 case VIA_RES_720X576:
614 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_10X7;
615 lcd_patch_reg = K400_LCD_RES_7X4_10X7;
616 break;
617 case VIA_RES_800X600:
618 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_10X7;
619 lcd_patch_reg = K400_LCD_RES_8X6_10X7;
620 break;
621 }
622 break;
623
624 /* LCD 1280x1024 */
625 case LCD_PANEL_ID4_1280X1024:
626 switch (vmode_index) {
627 case VIA_RES_640X400:
628 case VIA_RES_640X480:
629 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_12X10;
630 lcd_patch_reg = K400_LCD_RES_6X4_12X10;
631 break;
632 case VIA_RES_720X480:
633 case VIA_RES_720X576:
634 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_12X10;
635 lcd_patch_reg = K400_LCD_RES_7X4_12X10;
636 break;
637 case VIA_RES_800X600:
638 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_12X10;
639 lcd_patch_reg = K400_LCD_RES_8X6_12X10;
640 break;
641 case VIA_RES_1024X768:
642 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_12X10;
643 lcd_patch_reg = K400_LCD_RES_10X7_12X10;
644 break;
645
646 }
647 break;
648
649 /* LCD 1400x1050 */
650 case LCD_PANEL_ID5_1400X1050:
651 switch (vmode_index) {
652 case VIA_RES_640X480:
653 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_14X10;
654 lcd_patch_reg = K400_LCD_RES_6X4_14X10;
655 break;
656 case VIA_RES_800X600:
657 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_14X10;
658 lcd_patch_reg = K400_LCD_RES_8X6_14X10;
659 break;
660 case VIA_RES_1024X768:
661 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_14X10;
662 lcd_patch_reg = K400_LCD_RES_10X7_14X10;
663 break;
664 case VIA_RES_1280X768:
665 case VIA_RES_1280X800:
666 case VIA_RES_1280X960:
667 case VIA_RES_1280X1024:
668 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_14X10;
669 lcd_patch_reg = K400_LCD_RES_12X10_14X10;
670 break;
671 }
672 break;
673
674 /* LCD 1600x1200 */
675 case LCD_PANEL_ID6_1600X1200:
676 switch (vmode_index) {
677 case VIA_RES_640X400:
678 case VIA_RES_640X480:
679 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_16X12;
680 lcd_patch_reg = K400_LCD_RES_6X4_16X12;
681 break;
682 case VIA_RES_720X480:
683 case VIA_RES_720X576:
684 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_16X12;
685 lcd_patch_reg = K400_LCD_RES_7X4_16X12;
686 break;
687 case VIA_RES_800X600:
688 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_16X12;
689 lcd_patch_reg = K400_LCD_RES_8X6_16X12;
690 break;
691 case VIA_RES_1024X768:
692 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_16X12;
693 lcd_patch_reg = K400_LCD_RES_10X7_16X12;
694 break;
695 case VIA_RES_1280X768:
696 case VIA_RES_1280X800:
697 case VIA_RES_1280X960:
698 case VIA_RES_1280X1024:
699 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_16X12;
700 lcd_patch_reg = K400_LCD_RES_12X10_16X12;
701 break;
702 }
703 break;
704
705 /* LCD 1366x768 */
706 case LCD_PANEL_ID7_1366X768:
707 switch (vmode_index) {
708 case VIA_RES_640X480:
709 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_1366X7;
710 lcd_patch_reg = K400_LCD_RES_6X4_1366X7;
711 break;
712 case VIA_RES_720X480:
713 case VIA_RES_720X576:
714 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_1366X7;
715 lcd_patch_reg = K400_LCD_RES_7X4_1366X7;
716 break;
717 case VIA_RES_800X600:
718 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_1366X7;
719 lcd_patch_reg = K400_LCD_RES_8X6_1366X7;
720 break;
721 case VIA_RES_1024X768:
722 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_1366X7;
723 lcd_patch_reg = K400_LCD_RES_10X7_1366X7;
724 break;
725 case VIA_RES_1280X768:
726 case VIA_RES_1280X800:
727 case VIA_RES_1280X960:
728 case VIA_RES_1280X1024:
729 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_1366X7;
730 lcd_patch_reg = K400_LCD_RES_12X10_1366X7;
731 break;
732 }
733 break;
734
735 /* LCD 1360x768 */
736 case LCD_PANEL_IDB_1360X768:
737 break;
738 }
739 if (reg_num != 0) {
740 /* H.W. Reset : ON */
741 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
742
743 viafb_write_regx(lcd_patch_reg, reg_num);
744
745 /* H.W. Reset : OFF */
746 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
747
748 /* Reset PLL */
749 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
750 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
751
752 /* Fire! */
753 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
754 }
755}
756
757static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
758 int panel_id)
759{
760 int vmode_index;
761 int reg_num = 0;
762 struct io_reg *lcd_patch_reg = NULL;
763
764 if (viaparinfo->lvds_setting_info->iga_path == IGA2)
765 vmode_index = viafb_get_mode_index(set_hres, set_vres, 1);
766 else
767 vmode_index = viafb_get_mode_index(set_hres, set_vres, 0);
768
769 switch (panel_id) {
770 case LCD_PANEL_ID5_1400X1050:
771 switch (vmode_index) {
772 case VIA_RES_640X480:
773 reg_num = NUM_TOTAL_P880_LCD_RES_6X4_14X10;
774 lcd_patch_reg = P880_LCD_RES_6X4_14X10;
775 break;
776 case VIA_RES_800X600:
777 reg_num = NUM_TOTAL_P880_LCD_RES_8X6_14X10;
778 lcd_patch_reg = P880_LCD_RES_8X6_14X10;
779 break;
780 }
781 break;
782 case LCD_PANEL_ID6_1600X1200:
783 switch (vmode_index) {
784 case VIA_RES_640X400:
785 case VIA_RES_640X480:
786 reg_num = NUM_TOTAL_P880_LCD_RES_6X4_16X12;
787 lcd_patch_reg = P880_LCD_RES_6X4_16X12;
788 break;
789 case VIA_RES_720X480:
790 case VIA_RES_720X576:
791 reg_num = NUM_TOTAL_P880_LCD_RES_7X4_16X12;
792 lcd_patch_reg = P880_LCD_RES_7X4_16X12;
793 break;
794 case VIA_RES_800X600:
795 reg_num = NUM_TOTAL_P880_LCD_RES_8X6_16X12;
796 lcd_patch_reg = P880_LCD_RES_8X6_16X12;
797 break;
798 case VIA_RES_1024X768:
799 reg_num = NUM_TOTAL_P880_LCD_RES_10X7_16X12;
800 lcd_patch_reg = P880_LCD_RES_10X7_16X12;
801 break;
802 case VIA_RES_1280X768:
803 case VIA_RES_1280X960:
804 case VIA_RES_1280X1024:
805 reg_num = NUM_TOTAL_P880_LCD_RES_12X10_16X12;
806 lcd_patch_reg = P880_LCD_RES_12X10_16X12;
807 break;
808 }
809 break;
810
811 }
812 if (reg_num != 0) {
813 /* H.W. Reset : ON */
814 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
815
816 viafb_write_regx(lcd_patch_reg, reg_num);
817
818 /* H.W. Reset : OFF */
819 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
820
821 /* Reset PLL */
822 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
823 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
824
825 /* Fire! */
826 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
827 }
828}
829
830static void load_lcd_patch_regs(int set_hres, int set_vres,
831 int panel_id, int set_iga)
832{
833 int vmode_index;
834
835 if (viaparinfo->lvds_setting_info->iga_path == IGA2)
836 vmode_index = viafb_get_mode_index(set_hres, set_vres, 1);
837 else
838 vmode_index = viafb_get_mode_index(set_hres, set_vres, 0);
839
840 viafb_unlock_crt();
841
842 /* Patch for simultaneous & Expansion */
843 if ((set_iga == IGA1_IGA2) &&
844 (viaparinfo->lvds_setting_info->display_method ==
845 LCD_EXPANDSION)) {
846 switch (viaparinfo->chip_info->gfx_chip_name) {
847 case UNICHROME_CLE266:
848 case UNICHROME_K400:
849 load_lcd_k400_patch_tbl(set_hres, set_vres, panel_id);
850 break;
851 case UNICHROME_K800:
852 break;
853 case UNICHROME_PM800:
854 case UNICHROME_CN700:
855 case UNICHROME_CX700:
856 load_lcd_p880_patch_tbl(set_hres, set_vres, panel_id);
857 }
858 }
859
860 viafb_lock_crt();
861}
862
863static void via_pitch_alignment_patch_lcd(
864 struct lvds_setting_information *plvds_setting_info,
865 struct lvds_chip_information
866 *plvds_chip_info)
867{
868 unsigned char cr13, cr35, cr65, cr66, cr67;
869 unsigned long dwScreenPitch = 0;
870 unsigned long dwPitch;
871
872 dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
873 if (dwPitch & 0x1F) {
874 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
875 if (plvds_setting_info->iga_path == IGA2) {
876 if (plvds_setting_info->bpp > 8) {
877 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
878 viafb_write_reg(CR66, VIACR, cr66);
879 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
880 cr67 |=
881 (unsigned
882 char)((dwScreenPitch & 0x300) >> 8);
883 viafb_write_reg(CR67, VIACR, cr67);
884 }
885
886 /* Fetch Count */
887 cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
888 cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
889 viafb_write_reg(CR67, VIACR, cr67);
890 cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
891 cr65 += 2;
892 viafb_write_reg(CR65, VIACR, cr65);
893 } else {
894 if (plvds_setting_info->bpp > 8) {
895 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
896 viafb_write_reg(CR13, VIACR, cr13);
897 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
898 cr35 |=
899 (unsigned
900 char)((dwScreenPitch & 0x700) >> 3);
901 viafb_write_reg(CR35, VIACR, cr35);
902 }
903 }
904 }
905}
906static void lcd_patch_skew_dvp0(struct lvds_setting_information
907 *plvds_setting_info,
908 struct lvds_chip_information *plvds_chip_info)
909{
910 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
911 switch (viaparinfo->chip_info->gfx_chip_name) {
912 case UNICHROME_P4M900:
913 viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
914 plvds_chip_info);
915 break;
916 case UNICHROME_P4M890:
917 viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
918 plvds_chip_info);
919 break;
920 }
921 }
922}
923static void lcd_patch_skew_dvp1(struct lvds_setting_information
924 *plvds_setting_info,
925 struct lvds_chip_information *plvds_chip_info)
926{
927 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
928 switch (viaparinfo->chip_info->gfx_chip_name) {
929 case UNICHROME_CX700:
930 viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
931 plvds_chip_info);
932 break;
933 }
934 }
935}
936static void lcd_patch_skew(struct lvds_setting_information
937 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
938{
939 DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
940 switch (plvds_chip_info->output_interface) {
941 case INTERFACE_DVP0:
942 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
943 break;
944 case INTERFACE_DVP1:
945 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
946 break;
947 case INTERFACE_DFP_LOW:
948 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
949 viafb_write_reg_mask(CR99, VIACR, 0x08,
950 BIT0 + BIT1 + BIT2 + BIT3);
951 }
952 break;
953 }
954}
955
956/* LCD Set Mode */
957void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
958 struct lvds_setting_information *plvds_setting_info,
959 struct lvds_chip_information *plvds_chip_info)
960{
961 int video_index = plvds_setting_info->lcd_panel_size;
962 int set_iga = plvds_setting_info->iga_path;
963 int mode_bpp = plvds_setting_info->bpp;
964 int viafb_load_reg_num = 0;
965 int reg_value = 0;
966 int set_hres, set_vres;
967 int panel_hres, panel_vres;
968 u32 pll_D_N;
969 int offset;
970 struct io_register *reg = NULL;
971 struct display_timing mode_crt_reg, panel_crt_reg;
972 struct crt_mode_table *panel_crt_table = NULL;
973 struct VideoModeTable *vmode_tbl = NULL;
974
975 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
976 /* Get mode table */
977 mode_crt_reg = mode_crt_table->crtc;
978 /* Get panel table Pointer */
979 vmode_tbl = viafb_get_modetbl_pointer(video_index);
980 panel_crt_table = vmode_tbl->crtc;
981 panel_crt_reg = panel_crt_table->crtc;
982 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
983 set_hres = plvds_setting_info->h_active;
984 set_vres = plvds_setting_info->v_active;
985 panel_hres = plvds_setting_info->lcd_panel_hres;
986 panel_vres = plvds_setting_info->lcd_panel_vres;
987 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
988 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
989 plvds_setting_info->vclk = panel_crt_table->clk;
990 if (set_iga == IGA1) {
991 /* IGA1 doesn't have LCD scaling, so set it as centering. */
992 viafb_load_crtc_timing(lcd_centering_timging
993 (mode_crt_reg, panel_crt_reg), IGA1);
994 } else {
995 /* Expansion */
996 if ((plvds_setting_info->display_method ==
997 LCD_EXPANDSION) & ((set_hres != panel_hres)
998 || (set_vres != panel_vres))) {
999 /* expansion timing IGA2 loaded panel set timing*/
1000 viafb_load_crtc_timing(panel_crt_reg, IGA2);
1001 DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
1002 load_lcd_scaling(set_hres, set_vres, panel_hres,
1003 panel_vres);
1004 DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
1005 } else { /* Centering */
1006 /* centering timing IGA2 always loaded panel
1007 and mode releative timing */
1008 viafb_load_crtc_timing(lcd_centering_timging
1009 (mode_crt_reg, panel_crt_reg), IGA2);
1010 viafb_write_reg_mask(CR79, VIACR, 0x00,
1011 BIT0 + BIT1 + BIT2);
1012 /* LCD scaling disabled */
1013 }
1014 }
1015
1016 if (set_iga == IGA1_IGA2) {
1017 load_crtc_shadow_timing(mode_crt_reg, panel_crt_reg);
1018 /* Fill shadow registers */
1019
1020 switch (plvds_setting_info->lcd_panel_id) {
1021 case LCD_PANEL_ID0_640X480:
1022 offset = 80;
1023 break;
1024 case LCD_PANEL_ID1_800X600:
1025 case LCD_PANEL_IDA_800X480:
1026 offset = 110;
1027 break;
1028 case LCD_PANEL_ID2_1024X768:
1029 offset = 150;
1030 break;
1031 case LCD_PANEL_ID3_1280X768:
1032 case LCD_PANEL_ID4_1280X1024:
1033 case LCD_PANEL_ID5_1400X1050:
1034 case LCD_PANEL_ID9_1280X800:
1035 offset = 190;
1036 break;
1037 case LCD_PANEL_ID6_1600X1200:
1038 offset = 250;
1039 break;
1040 case LCD_PANEL_ID7_1366X768:
1041 case LCD_PANEL_IDB_1360X768:
1042 offset = 212;
1043 break;
1044 default:
1045 offset = 140;
1046 break;
1047 }
1048
1049 /* Offset for simultaneous */
1050 reg_value = offset;
1051 viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
1052 reg = offset_reg.iga2_offset_reg.reg;
1053 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1054 DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n");
1055 viafb_load_fetch_count_reg(set_hres, 4, IGA2);
1056 /* Fetch count for simultaneous */
1057 } else { /* SAMM */
1058 /* Offset for IGA2 only */
1059 viafb_load_offset_reg(set_hres, mode_bpp / 8, set_iga);
1060 /* Fetch count for IGA2 only */
1061 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
1062
1063 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1064 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1065 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
1066
1067 viafb_set_color_depth(mode_bpp / 8, set_iga);
1068 }
1069
1070 fill_lcd_format();
1071
1072 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
1073 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
1074 viafb_set_vclock(pll_D_N, set_iga);
1075
1076 viafb_set_output_path(DEVICE_LCD, set_iga,
1077 plvds_chip_info->output_interface);
1078 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
1079
1080 /* If K8M800, enable LCD Prefetch Mode. */
1081 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1082 || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
1083 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
1084
1085 load_lcd_patch_regs(set_hres, set_vres,
1086 plvds_setting_info->lcd_panel_id, set_iga);
1087
1088 DEBUG_MSG(KERN_INFO "load_lcd_patch_regs!!\n");
1089
1090 /* Patch for non 32bit alignment mode */
1091 via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
1092}
1093
1094static void integrated_lvds_disable(struct lvds_setting_information
1095 *plvds_setting_info,
1096 struct lvds_chip_information *plvds_chip_info)
1097{
1098 bool turn_off_first_powersequence = false;
1099 bool turn_off_second_powersequence = false;
1100 if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
1101 turn_off_first_powersequence = true;
1102 if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
1103 turn_off_first_powersequence = true;
1104 if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
1105 turn_off_second_powersequence = true;
1106 if (turn_off_second_powersequence) {
1107 /* Use second power sequence control: */
1108
1109 /* Turn off power sequence. */
1110 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
1111
1112 /* Turn off back light. */
1113 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
1114 }
1115 if (turn_off_first_powersequence) {
1116 /* Use first power sequence control: */
1117
1118 /* Turn off power sequence. */
1119 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
1120
1121 /* Turn off back light. */
1122 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
1123 }
1124
1125 /* Turn DFP High/Low Pad off. */
1126 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
1127
1128 /* Power off LVDS channel. */
1129 switch (plvds_chip_info->output_interface) {
1130 case INTERFACE_LVDS0:
1131 {
1132 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
1133 break;
1134 }
1135
1136 case INTERFACE_LVDS1:
1137 {
1138 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
1139 break;
1140 }
1141
1142 case INTERFACE_LVDS0LVDS1:
1143 {
1144 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
1145 break;
1146 }
1147 }
1148}
1149
1150static void integrated_lvds_enable(struct lvds_setting_information
1151 *plvds_setting_info,
1152 struct lvds_chip_information *plvds_chip_info)
1153{
1154 bool turn_on_first_powersequence = false;
1155 bool turn_on_second_powersequence = false;
1156
1157 DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
1158 plvds_chip_info->output_interface);
1159 if (plvds_setting_info->lcd_mode == LCD_SPWG)
1160 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
1161 else
1162 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
1163 if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
1164 turn_on_first_powersequence = true;
1165 if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
1166 turn_on_first_powersequence = true;
1167 if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
1168 turn_on_second_powersequence = true;
1169
1170 if (turn_on_second_powersequence) {
1171 /* Use second power sequence control: */
1172
1173 /* Use hardware control power sequence. */
1174 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
1175
1176 /* Turn on back light. */
1177 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
1178
1179 /* Turn on hardware power sequence. */
1180 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
1181 }
1182 if (turn_on_first_powersequence) {
1183 /* Use first power sequence control: */
1184
1185 /* Use hardware control power sequence. */
1186 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
1187
1188 /* Turn on back light. */
1189 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
1190
1191 /* Turn on hardware power sequence. */
1192 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1193 }
1194
1195 /* Turn DFP High/Low pad on. */
1196 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
1197
1198 /* Power on LVDS channel. */
1199 switch (plvds_chip_info->output_interface) {
1200 case INTERFACE_LVDS0:
1201 {
1202 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
1203 break;
1204 }
1205
1206 case INTERFACE_LVDS1:
1207 {
1208 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
1209 break;
1210 }
1211
1212 case INTERFACE_LVDS0LVDS1:
1213 {
1214 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
1215 break;
1216 }
1217 }
1218}
1219
1220void viafb_lcd_disable(void)
1221{
1222
1223 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1224 lcd_powersequence_off();
1225 /* DI1 pad off */
1226 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
1227 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1228 if (viafb_LCD2_ON
1229 && (INTEGRATED_LVDS ==
1230 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
1231 integrated_lvds_disable(viaparinfo->lvds_setting_info,
1232 &viaparinfo->chip_info->lvds_chip_info2);
1233 if (INTEGRATED_LVDS ==
1234 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
1235 integrated_lvds_disable(viaparinfo->lvds_setting_info,
1236 &viaparinfo->chip_info->lvds_chip_info);
1237 if (VT1636_LVDS == viaparinfo->chip_info->
1238 lvds_chip_info.lvds_chip_name)
1239 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
1240 &viaparinfo->chip_info->lvds_chip_info);
1241 } else if (VT1636_LVDS ==
1242 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1243 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
1244 &viaparinfo->chip_info->lvds_chip_info);
1245 } else {
1246 /* DFP-HL pad off */
1247 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
1248 /* Backlight off */
1249 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
1250 /* 24 bit DI data paht off */
1251 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
1252 /* Simultaneout disabled */
1253 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
1254 }
1255
1256 /* Disable expansion bit */
1257 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
1258 /* CRT path set to IGA1 */
1259 viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
1260 /* Simultaneout disabled */
1261 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
1262 /* IGA2 path disabled */
1263 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
1264
1265}
1266
1267void viafb_lcd_enable(void)
1268{
1269 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1270 /* DI1 pad on */
1271 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
1272 lcd_powersequence_on();
1273 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1274 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
1275 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
1276 integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
1277 &viaparinfo->chip_info->lvds_chip_info2);
1278 if (INTEGRATED_LVDS ==
1279 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
1280 integrated_lvds_enable(viaparinfo->lvds_setting_info,
1281 &viaparinfo->chip_info->lvds_chip_info);
1282 if (VT1636_LVDS == viaparinfo->chip_info->
1283 lvds_chip_info.lvds_chip_name)
1284 viafb_enable_lvds_vt1636(viaparinfo->
1285 lvds_setting_info, &viaparinfo->chip_info->
1286 lvds_chip_info);
1287 } else if (VT1636_LVDS ==
1288 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1289 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
1290 &viaparinfo->chip_info->lvds_chip_info);
1291 } else {
1292 /* DFP-HL pad on */
1293 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
1294 /* Backlight on */
1295 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
1296 /* 24 bit DI data paht on */
1297 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
1298
1299 /* Set data source selection bit by iga path */
1300 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
1301 /* DFP-H set to IGA1 */
1302 viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
1303 /* DFP-L set to IGA1 */
1304 viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
1305 } else {
1306 /* DFP-H set to IGA2 */
1307 viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
1308 /* DFP-L set to IGA2 */
1309 viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
1310 }
1311 /* LCD enabled */
1312 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
1313 }
1314
1315 if ((viaparinfo->lvds_setting_info->iga_path == IGA1)
1316 || (viaparinfo->lvds_setting_info->iga_path == IGA1_IGA2)) {
1317 /* CRT path set to IGA2 */
1318 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
1319 /* IGA2 path disabled */
1320 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
1321 /* IGA2 path enabled */
1322 } else { /* IGA2 */
1323 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
1324 }
1325
1326}
1327
1328static void lcd_powersequence_off(void)
1329{
1330 int i, mask, data;
1331
1332 /* Software control power sequence */
1333 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
1334
1335 for (i = 0; i < 3; i++) {
1336 mask = PowerSequenceOff[0][i];
1337 data = PowerSequenceOff[1][i] & mask;
1338 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
1339 udelay(PowerSequenceOff[2][i]);
1340 }
1341
1342 /* Disable LCD */
1343 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
1344}
1345
1346static void lcd_powersequence_on(void)
1347{
1348 int i, mask, data;
1349
1350 /* Software control power sequence */
1351 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
1352
1353 /* Enable LCD */
1354 viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
1355
1356 for (i = 0; i < 3; i++) {
1357 mask = PowerSequenceOn[0][i];
1358 data = PowerSequenceOn[1][i] & mask;
1359 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
1360 udelay(PowerSequenceOn[2][i]);
1361 }
1362
1363 udelay(1);
1364}
1365
1366static void fill_lcd_format(void)
1367{
1368 u8 bdithering = 0, bdual = 0;
1369
1370 if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
1371 bdual = BIT4;
1372 if (viaparinfo->lvds_setting_info->LCDDithering)
1373 bdithering = BIT0;
1374 /* Dual & Dithering */
1375 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
1376}
1377
1378static void check_diport_of_integrated_lvds(
1379 struct lvds_chip_information *plvds_chip_info,
1380 struct lvds_setting_information
1381 *plvds_setting_info)
1382{
1383 /* Determine LCD DI Port by hardware layout. */
1384 switch (viafb_display_hardware_layout) {
1385 case HW_LAYOUT_LCD_ONLY:
1386 {
1387 if (plvds_setting_info->device_lcd_dualedge) {
1388 plvds_chip_info->output_interface =
1389 INTERFACE_LVDS0LVDS1;
1390 } else {
1391 plvds_chip_info->output_interface =
1392 INTERFACE_LVDS0;
1393 }
1394
1395 break;
1396 }
1397
1398 case HW_LAYOUT_DVI_ONLY:
1399 {
1400 plvds_chip_info->output_interface = INTERFACE_NONE;
1401 break;
1402 }
1403
1404 case HW_LAYOUT_LCD1_LCD2:
1405 case HW_LAYOUT_LCD_EXTERNAL_LCD2:
1406 {
1407 plvds_chip_info->output_interface =
1408 INTERFACE_LVDS0LVDS1;
1409 break;
1410 }
1411
1412 case HW_LAYOUT_LCD_DVI:
1413 {
1414 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1415 break;
1416 }
1417
1418 default:
1419 {
1420 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1421 break;
1422 }
1423 }
1424
1425 DEBUG_MSG(KERN_INFO
1426 "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
1427 viafb_display_hardware_layout,
1428 plvds_chip_info->output_interface);
1429}
1430
1431void viafb_init_lvds_output_interface(struct lvds_chip_information
1432 *plvds_chip_info,
1433 struct lvds_setting_information
1434 *plvds_setting_info)
1435{
1436 if (INTERFACE_NONE != plvds_chip_info->output_interface) {
1437 /*Do nothing, lcd port is specified by module parameter */
1438 return;
1439 }
1440
1441 switch (plvds_chip_info->lvds_chip_name) {
1442
1443 case VT1636_LVDS:
1444 switch (viaparinfo->chip_info->gfx_chip_name) {
1445 case UNICHROME_CX700:
1446 plvds_chip_info->output_interface = INTERFACE_DVP1;
1447 break;
1448 case UNICHROME_CN700:
1449 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1450 break;
1451 default:
1452 plvds_chip_info->output_interface = INTERFACE_DVP0;
1453 break;
1454 }
1455 break;
1456
1457 case INTEGRATED_LVDS:
1458 check_diport_of_integrated_lvds(plvds_chip_info,
1459 plvds_setting_info);
1460 break;
1461
1462 default:
1463 switch (viaparinfo->chip_info->gfx_chip_name) {
1464 case UNICHROME_K8M890:
1465 case UNICHROME_P4M900:
1466 case UNICHROME_P4M890:
1467 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1468 break;
1469 default:
1470 plvds_chip_info->output_interface = INTERFACE_DFP;
1471 break;
1472 }
1473 break;
1474 }
1475}
1476
1477static struct display_timing lcd_centering_timging(struct display_timing
1478 mode_crt_reg,
1479 struct display_timing panel_crt_reg)
1480{
1481 struct display_timing crt_reg;
1482
1483 crt_reg.hor_total = panel_crt_reg.hor_total;
1484 crt_reg.hor_addr = mode_crt_reg.hor_addr;
1485 crt_reg.hor_blank_start =
1486 (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
1487 crt_reg.hor_addr;
1488 crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1489 crt_reg.hor_sync_start =
1490 (panel_crt_reg.hor_sync_start -
1491 panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1492 crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1493
1494 crt_reg.ver_total = panel_crt_reg.ver_total;
1495 crt_reg.ver_addr = mode_crt_reg.ver_addr;
1496 crt_reg.ver_blank_start =
1497 (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1498 crt_reg.ver_addr;
1499 crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1500 crt_reg.ver_sync_start =
1501 (panel_crt_reg.ver_sync_start -
1502 panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1503 crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1504
1505 return crt_reg;
1506}
1507
1508static void load_crtc_shadow_timing(struct display_timing mode_timing,
1509 struct display_timing panel_timing)
1510{
1511 struct io_register *reg = NULL;
1512 int i;
1513 int viafb_load_reg_Num = 0;
1514 int reg_value = 0;
1515
1516 if (viaparinfo->lvds_setting_info->display_method == LCD_EXPANDSION) {
1517 /* Expansion */
1518 for (i = 12; i < 20; i++) {
1519 switch (i) {
1520 case H_TOTAL_SHADOW_INDEX:
1521 reg_value =
1522 IGA2_HOR_TOTAL_SHADOW_FORMULA
1523 (panel_timing.hor_total);
1524 viafb_load_reg_Num =
1525 iga2_shadow_crtc_reg.hor_total_shadow.
1526 reg_num;
1527 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1528 break;
1529 case H_BLANK_END_SHADOW_INDEX:
1530 reg_value =
1531 IGA2_HOR_BLANK_END_SHADOW_FORMULA
1532 (panel_timing.hor_blank_start,
1533 panel_timing.hor_blank_end);
1534 viafb_load_reg_Num =
1535 iga2_shadow_crtc_reg.
1536 hor_blank_end_shadow.reg_num;
1537 reg =
1538 iga2_shadow_crtc_reg.
1539 hor_blank_end_shadow.reg;
1540 break;
1541 case V_TOTAL_SHADOW_INDEX:
1542 reg_value =
1543 IGA2_VER_TOTAL_SHADOW_FORMULA
1544 (panel_timing.ver_total);
1545 viafb_load_reg_Num =
1546 iga2_shadow_crtc_reg.ver_total_shadow.
1547 reg_num;
1548 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1549 break;
1550 case V_ADDR_SHADOW_INDEX:
1551 reg_value =
1552 IGA2_VER_ADDR_SHADOW_FORMULA
1553 (panel_timing.ver_addr);
1554 viafb_load_reg_Num =
1555 iga2_shadow_crtc_reg.ver_addr_shadow.
1556 reg_num;
1557 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1558 break;
1559 case V_BLANK_SATRT_SHADOW_INDEX:
1560 reg_value =
1561 IGA2_VER_BLANK_START_SHADOW_FORMULA
1562 (panel_timing.ver_blank_start);
1563 viafb_load_reg_Num =
1564 iga2_shadow_crtc_reg.
1565 ver_blank_start_shadow.reg_num;
1566 reg =
1567 iga2_shadow_crtc_reg.
1568 ver_blank_start_shadow.reg;
1569 break;
1570 case V_BLANK_END_SHADOW_INDEX:
1571 reg_value =
1572 IGA2_VER_BLANK_END_SHADOW_FORMULA
1573 (panel_timing.ver_blank_start,
1574 panel_timing.ver_blank_end);
1575 viafb_load_reg_Num =
1576 iga2_shadow_crtc_reg.
1577 ver_blank_end_shadow.reg_num;
1578 reg =
1579 iga2_shadow_crtc_reg.
1580 ver_blank_end_shadow.reg;
1581 break;
1582 case V_SYNC_SATRT_SHADOW_INDEX:
1583 reg_value =
1584 IGA2_VER_SYNC_START_SHADOW_FORMULA
1585 (panel_timing.ver_sync_start);
1586 viafb_load_reg_Num =
1587 iga2_shadow_crtc_reg.
1588 ver_sync_start_shadow.reg_num;
1589 reg =
1590 iga2_shadow_crtc_reg.
1591 ver_sync_start_shadow.reg;
1592 break;
1593 case V_SYNC_END_SHADOW_INDEX:
1594 reg_value =
1595 IGA2_VER_SYNC_END_SHADOW_FORMULA
1596 (panel_timing.ver_sync_start,
1597 panel_timing.ver_sync_end);
1598 viafb_load_reg_Num =
1599 iga2_shadow_crtc_reg.
1600 ver_sync_end_shadow.reg_num;
1601 reg =
1602 iga2_shadow_crtc_reg.
1603 ver_sync_end_shadow.reg;
1604 break;
1605 }
1606 viafb_load_reg(reg_value,
1607 viafb_load_reg_Num, reg, VIACR);
1608 }
1609 } else { /* Centering */
1610 for (i = 12; i < 20; i++) {
1611 switch (i) {
1612 case H_TOTAL_SHADOW_INDEX:
1613 reg_value =
1614 IGA2_HOR_TOTAL_SHADOW_FORMULA
1615 (panel_timing.hor_total);
1616 viafb_load_reg_Num =
1617 iga2_shadow_crtc_reg.hor_total_shadow.
1618 reg_num;
1619 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1620 break;
1621 case H_BLANK_END_SHADOW_INDEX:
1622 reg_value =
1623 IGA2_HOR_BLANK_END_SHADOW_FORMULA
1624 (panel_timing.hor_blank_start,
1625 panel_timing.hor_blank_end);
1626 viafb_load_reg_Num =
1627 iga2_shadow_crtc_reg.
1628 hor_blank_end_shadow.reg_num;
1629 reg =
1630 iga2_shadow_crtc_reg.
1631 hor_blank_end_shadow.reg;
1632 break;
1633 case V_TOTAL_SHADOW_INDEX:
1634 reg_value =
1635 IGA2_VER_TOTAL_SHADOW_FORMULA
1636 (panel_timing.ver_total);
1637 viafb_load_reg_Num =
1638 iga2_shadow_crtc_reg.ver_total_shadow.
1639 reg_num;
1640 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1641 break;
1642 case V_ADDR_SHADOW_INDEX:
1643 reg_value =
1644 IGA2_VER_ADDR_SHADOW_FORMULA
1645 (mode_timing.ver_addr);
1646 viafb_load_reg_Num =
1647 iga2_shadow_crtc_reg.ver_addr_shadow.
1648 reg_num;
1649 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1650 break;
1651 case V_BLANK_SATRT_SHADOW_INDEX:
1652 reg_value =
1653 IGA2_VER_BLANK_START_SHADOW_FORMULA
1654 (mode_timing.ver_blank_start);
1655 viafb_load_reg_Num =
1656 iga2_shadow_crtc_reg.
1657 ver_blank_start_shadow.reg_num;
1658 reg =
1659 iga2_shadow_crtc_reg.
1660 ver_blank_start_shadow.reg;
1661 break;
1662 case V_BLANK_END_SHADOW_INDEX:
1663 reg_value =
1664 IGA2_VER_BLANK_END_SHADOW_FORMULA
1665 (panel_timing.ver_blank_start,
1666 panel_timing.ver_blank_end);
1667 viafb_load_reg_Num =
1668 iga2_shadow_crtc_reg.
1669 ver_blank_end_shadow.reg_num;
1670 reg =
1671 iga2_shadow_crtc_reg.
1672 ver_blank_end_shadow.reg;
1673 break;
1674 case V_SYNC_SATRT_SHADOW_INDEX:
1675 reg_value =
1676 IGA2_VER_SYNC_START_SHADOW_FORMULA(
1677 (panel_timing.ver_sync_start -
1678 panel_timing.ver_blank_start) +
1679 (panel_timing.ver_addr -
1680 mode_timing.ver_addr) / 2 +
1681 mode_timing.ver_addr);
1682 viafb_load_reg_Num =
1683 iga2_shadow_crtc_reg.ver_sync_start_shadow.
1684 reg_num;
1685 reg =
1686 iga2_shadow_crtc_reg.ver_sync_start_shadow.
1687 reg;
1688 break;
1689 case V_SYNC_END_SHADOW_INDEX:
1690 reg_value =
1691 IGA2_VER_SYNC_END_SHADOW_FORMULA(
1692 (panel_timing.ver_sync_start -
1693 panel_timing.ver_blank_start) +
1694 (panel_timing.ver_addr -
1695 mode_timing.ver_addr) / 2 +
1696 mode_timing.ver_addr,
1697 panel_timing.ver_sync_end);
1698 viafb_load_reg_Num =
1699 iga2_shadow_crtc_reg.ver_sync_end_shadow.
1700 reg_num;
1701 reg =
1702 iga2_shadow_crtc_reg.ver_sync_end_shadow.
1703 reg;
1704 break;
1705 }
1706 viafb_load_reg(reg_value,
1707 viafb_load_reg_Num, reg, VIACR);
1708 }
1709 }
1710}
1711
1712bool viafb_lcd_get_mobile_state(bool *mobile)
1713{
1714 unsigned char *romptr, *tableptr;
1715 u8 core_base;
1716 unsigned char *biosptr;
1717 /* Rom address */
1718 u32 romaddr = 0x000C0000;
1719 u16 start_pattern = 0;
1720
1721 biosptr = ioremap(romaddr, 0x10000);
1722
1723 memcpy(&start_pattern, biosptr, 2);
1724 /* Compare pattern */
1725 if (start_pattern == 0xAA55) {
1726 /* Get the start of Table */
1727 /* 0x1B means BIOS offset position */
1728 romptr = biosptr + 0x1B;
1729 tableptr = biosptr + *((u16 *) romptr);
1730
1731 /* Get the start of biosver structure */
1732 /* 18 means BIOS version position. */
1733 romptr = tableptr + 18;
1734 romptr = biosptr + *((u16 *) romptr);
1735
1736 /* The offset should be 44, but the
1737 actual image is less three char. */
1738 /* pRom += 44; */
1739 romptr += 41;
1740
1741 core_base = *romptr++;
1742
1743 if (core_base & 0x8)
1744 *mobile = false;
1745 else
1746 *mobile = true;
1747 /* release memory */
1748 iounmap(biosptr);
1749
1750 return true;
1751 } else {
1752 iounmap(biosptr);
1753 return false;
1754 }
1755}
1756
1757static void viafb_load_scaling_factor_for_p4m900(int set_hres,
1758 int set_vres, int panel_hres, int panel_vres)
1759{
1760 int h_scaling_factor;
1761 int v_scaling_factor;
1762 u8 cra2 = 0;
1763 u8 cr77 = 0;
1764 u8 cr78 = 0;
1765 u8 cr79 = 0;
1766 u8 cr9f = 0;
1767 /* Check if expansion for horizontal */
1768 if (set_hres < panel_hres) {
1769 /* Load Horizontal Scaling Factor */
1770
1771 /* For VIA_K8M800 or later chipsets. */
1772 h_scaling_factor =
1773 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
1774 /* HSCaleFactor[1:0] at CR9F[1:0] */
1775 cr9f = h_scaling_factor & 0x0003;
1776 /* HSCaleFactor[9:2] at CR77[7:0] */
1777 cr77 = (h_scaling_factor & 0x03FC) >> 2;
1778 /* HSCaleFactor[11:10] at CR79[5:4] */
1779 cr79 = (h_scaling_factor & 0x0C00) >> 10;
1780 cr79 <<= 4;
1781
1782 /* Horizontal scaling enabled */
1783 cra2 = 0xC0;
1784
1785 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d\n",
1786 h_scaling_factor);
1787 } else {
1788 /* Horizontal scaling disabled */
1789 cra2 = 0x00;
1790 }
1791
1792 /* Check if expansion for vertical */
1793 if (set_vres < panel_vres) {
1794 /* Load Vertical Scaling Factor */
1795
1796 /* For VIA_K8M800 or later chipsets. */
1797 v_scaling_factor =
1798 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
1799
1800 /* Vertical scaling enabled */
1801 cra2 |= 0x08;
1802 /* VSCaleFactor[0] at CR79[3] */
1803 cr79 |= ((v_scaling_factor & 0x0001) << 3);
1804 /* VSCaleFactor[8:1] at CR78[7:0] */
1805 cr78 |= (v_scaling_factor & 0x01FE) >> 1;
1806 /* VSCaleFactor[10:9] at CR79[7:6] */
1807 cr79 |= ((v_scaling_factor & 0x0600) >> 9) << 6;
1808
1809 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d\n",
1810 v_scaling_factor);
1811 } else {
1812 /* Vertical scaling disabled */
1813 cra2 |= 0x00;
1814 }
1815
1816 viafb_write_reg_mask(CRA2, VIACR, cra2, BIT3 + BIT6 + BIT7);
1817 viafb_write_reg_mask(CR77, VIACR, cr77, 0xFF);
1818 viafb_write_reg_mask(CR78, VIACR, cr78, 0xFF);
1819 viafb_write_reg_mask(CR79, VIACR, cr79, 0xF8);
1820 viafb_write_reg_mask(CR9F, VIACR, cr9f, BIT0 + BIT1);
1821}
diff --git a/drivers/video/via/lcd.h b/drivers/video/via/lcd.h
new file mode 100644
index 000000000000..071f47cf5be1
--- /dev/null
+++ b/drivers/video/via/lcd.h
@@ -0,0 +1,94 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __LCD_H__
22#define __LCD_H__
23
24/*Definition TMDS Device ID register*/
25#define VT1631_DEVICE_ID_REG 0x02
26#define VT1631_DEVICE_ID 0x92
27
28#define VT3271_DEVICE_ID_REG 0x02
29#define VT3271_DEVICE_ID 0x71
30
31#define GET_LCD_SIZE_BY_SYSTEM_BIOS 0x01
32#define GET_LCD_SIZE_BY_VGA_BIOS 0x02
33#define GET_LCD_SZIE_BY_HW_STRAPPING 0x03
34#define GET_LCD_SIZE_BY_USER_SETTING 0x04
35
36/* Definition DVI Panel ID*/
37/* Resolution: 640x480, Channel: single, Dithering: Enable */
38#define LCD_PANEL_ID0_640X480 0x00
39/* Resolution: 800x600, Channel: single, Dithering: Enable */
40#define LCD_PANEL_ID1_800X600 0x01
41/* Resolution: 1024x768, Channel: single, Dithering: Enable */
42#define LCD_PANEL_ID2_1024X768 0x02
43/* Resolution: 1280x768, Channel: single, Dithering: Enable */
44#define LCD_PANEL_ID3_1280X768 0x03
45/* Resolution: 1280x1024, Channel: dual, Dithering: Enable */
46#define LCD_PANEL_ID4_1280X1024 0x04
47/* Resolution: 1400x1050, Channel: dual, Dithering: Enable */
48#define LCD_PANEL_ID5_1400X1050 0x05
49/* Resolution: 1600x1200, Channel: dual, Dithering: Enable */
50#define LCD_PANEL_ID6_1600X1200 0x06
51/* Resolution: 1366x768, Channel: single, Dithering: Disable */
52#define LCD_PANEL_ID7_1366X768 0x07
53/* Resolution: 1024x600, Channel: single, Dithering: Enable*/
54#define LCD_PANEL_ID8_1024X600 0x08
55/* Resolution: 1280x800, Channel: single, Dithering: Enable*/
56#define LCD_PANEL_ID9_1280X800 0x09
57/* Resolution: 800x480, Channel: single, Dithering: Enable*/
58#define LCD_PANEL_IDA_800X480 0x0A
59/* Resolution: 1360x768, Channel: single, Dithering: Disable*/
60#define LCD_PANEL_IDB_1360X768 0x0B
61/* Resolution: 480x640, Channel: single, Dithering: Enable */
62#define LCD_PANEL_IDC_480X640 0x0C
63
64
65extern int viafb_LCD2_ON;
66extern int viafb_LCD_ON;
67extern int viafb_DVI_ON;
68
69void viafb_disable_lvds_vt1636(struct lvds_setting_information
70 *plvds_setting_info,
71 struct lvds_chip_information *plvds_chip_info);
72void viafb_enable_lvds_vt1636(struct lvds_setting_information
73 *plvds_setting_info,
74 struct lvds_chip_information *plvds_chip_info);
75void viafb_lcd_disable(void);
76void viafb_lcd_enable(void);
77void viafb_init_lcd_size(void);
78void viafb_init_lvds_output_interface(struct lvds_chip_information
79 *plvds_chip_info,
80 struct lvds_setting_information
81 *plvds_setting_info);
82void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
83 struct lvds_setting_information *plvds_setting_info,
84 struct lvds_chip_information *plvds_chip_info);
85int viafb_lvds_trasmitter_identify(void);
86void viafb_init_lvds_output_interface(struct lvds_chip_information
87 *plvds_chip_info,
88 struct lvds_setting_information
89 *plvds_setting_info);
90bool viafb_lcd_get_mobile_state(bool *mobile);
91void viafb_load_crtc_timing(struct display_timing device_timing,
92 int set_iga);
93
94#endif /* __LCD_H__ */
diff --git a/drivers/video/via/lcdtbl.h b/drivers/video/via/lcdtbl.h
new file mode 100644
index 000000000000..6f3dd800be59
--- /dev/null
+++ b/drivers/video/via/lcdtbl.h
@@ -0,0 +1,591 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __LCDTBL_H__
22#define __LCDTBL_H__
23
24#include "share.h"
25
26/* CLE266 Software Power Sequence */
27/* {Mask}, {Data}, {Delay} */
28int PowerSequenceOn[3][3] =
29 { {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01} };
30int PowerSequenceOff[3][3] =
31 { {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01} };
32
33/* ++++++ P880 ++++++ */
34/* Panel 1600x1200 */
35struct io_reg P880_LCD_RES_6X4_16X12[] = {
36 /*IGA2 Horizontal Total */
37 {VIACR, CR50, 0xFF, 0x73}, {VIACR, CR55, 0x0F, 0x08},
38 /*IGA2 Horizontal Blank End */
39 {VIACR, CR53, 0xFF, 0x73}, {VIACR, CR54, 0x38, 0x00},
40 {VIACR, CR5D, 0x40, 0x40},
41 /*IGA2 Horizontal Total Shadow */
42 {VIACR, CR6D, 0xFF, 0x5A}, {VIACR, CR71, 0x08, 0x00},
43 /*IGA2 Horizontal Blank End Shadow */
44 {VIACR, CR6E, 0xFF, 0x5E},
45 /*IGA2 Offset */
46 {VIACR, CR66, 0xFF, 0xD6}, {VIACR, CR67, 0x03, 0x00},
47 /*VCLK*/ {VIASR, SR44, 0xFF, 0x7D}, {VIASR, SR45, 0xFF, 0x8C},
48 {VIASR, SR46, 0xFF, 0x02}
49
50};
51
52#define NUM_TOTAL_P880_LCD_RES_6X4_16X12 ARRAY_SIZE(P880_LCD_RES_6X4_16X12)
53
54struct io_reg P880_LCD_RES_7X4_16X12[] = {
55 /*IGA2 Horizontal Total */
56 {VIACR, CR50, 0xFF, 0x67}, {VIACR, CR55, 0x0F, 0x08},
57 /*IGA2 Horizontal Blank End */
58 {VIACR, CR53, 0xFF, 0x67}, {VIACR, CR54, 0x38, 0x00},
59 {VIACR, CR5D, 0x40, 0x40},
60 /*IGA2 Horizontal Total Shadow */
61 {VIACR, CR6D, 0xFF, 0x74}, {VIACR, CR71, 0x08, 0x00},
62 /*IGA2 Horizontal Blank End Shadow */
63 {VIACR, CR6E, 0xFF, 0x78},
64 /*IGA2 Offset */
65 {VIACR, CR66, 0xFF, 0xF5}, {VIACR, CR67, 0x03, 0x00},
66 /*VCLK*/ {VIASR, SR44, 0xFF, 0x78}, {VIASR, SR45, 0xFF, 0x8C},
67 {VIASR, SR46, 0xFF, 0x01}
68
69};
70
71#define NUM_TOTAL_P880_LCD_RES_7X4_16X12 ARRAY_SIZE(P880_LCD_RES_7X4_16X12)
72
73struct io_reg P880_LCD_RES_8X6_16X12[] = {
74 /*IGA2 Horizontal Total */
75 {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08},
76 /*IGA2 Horizontal Blank End */
77 {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00},
78 {VIACR, CR5D, 0x40, 0x40},
79 /*IGA2 Horizontal Total Shadow */
80 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x00},
81 /*IGA2 Horizontal Blank End Shadow */
82 {VIACR, CR6E, 0xFF, 0x83},
83 /*IGA2 Offset */
84 {VIACR, CR66, 0xFF, 0xE1}, {VIACR, CR67, 0x03, 0x00},
85 /*VCLK*/ {VIASR, SR44, 0xFF, 0x6D}, {VIASR, SR45, 0xFF, 0x88},
86 {VIASR, SR46, 0xFF, 0x03}
87
88};
89
90#define NUM_TOTAL_P880_LCD_RES_8X6_16X12 ARRAY_SIZE(P880_LCD_RES_8X6_16X12)
91
92struct io_reg P880_LCD_RES_10X7_16X12[] = {
93 /*IGA2 Horizontal Total */
94 {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08},
95 /*IGA2 Horizontal Blank End */
96 {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00},
97 {VIACR, CR5D, 0x40, 0x40},
98 /*IGA2 Horizontal Total Shadow */
99 {VIACR, CR6D, 0xFF, 0xAB}, {VIACR, CR71, 0x08, 0x00},
100 /*IGA2 Horizontal Blank End Shadow */
101 {VIACR, CR6E, 0xFF, 0xAF},
102 /*IGA2 Offset */
103 {VIACR, CR66, 0xFF, 0xF0}, {VIACR, CR67, 0x03, 0x00},
104 /*VCLK*/ {VIASR, SR44, 0xFF, 0x92}, {VIASR, SR45, 0xFF, 0x88},
105 {VIASR, SR46, 0xFF, 0x03}
106
107};
108
109#define NUM_TOTAL_P880_LCD_RES_10X7_16X12 ARRAY_SIZE(P880_LCD_RES_10X7_16X12)
110
111struct io_reg P880_LCD_RES_12X10_16X12[] = {
112 /*IGA2 Horizontal Total */
113 {VIACR, CR50, 0xFF, 0x7D}, {VIACR, CR55, 0x0F, 0x08},
114 /*IGA2 Horizontal Blank End */
115 {VIACR, CR53, 0xFF, 0x7D}, {VIACR, CR54, 0x38, 0x00},
116 {VIACR, CR5D, 0x40, 0x40},
117 /*IGA2 Horizontal Total Shadow */
118 {VIACR, CR6D, 0xFF, 0xD0}, {VIACR, CR71, 0x08, 0x00},
119 /*IGA2 Horizontal Blank End Shadow */
120 {VIACR, CR6E, 0xFF, 0xD4},
121 /*IGA2 Offset */
122 {VIACR, CR66, 0xFF, 0xFA}, {VIACR, CR67, 0x03, 0x00},
123 /*VCLK*/ {VIASR, SR44, 0xFF, 0xF6}, {VIASR, SR45, 0xFF, 0x88},
124 {VIASR, SR46, 0xFF, 0x05}
125
126};
127
128#define NUM_TOTAL_P880_LCD_RES_12X10_16X12 ARRAY_SIZE(P880_LCD_RES_12X10_16X12)
129
130/* Panel 1400x1050 */
131struct io_reg P880_LCD_RES_6X4_14X10[] = {
132 /* 640x480 */
133 /* IGA2 Horizontal Total */
134 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
135 /* IGA2 Horizontal Blank End */
136 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
137 {VIACR, CR5D, 0x40, 0x24},
138 /* IGA2 Horizontal Total Shadow */
139 {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x44},
140 /* IGA2 Horizontal Blank End Shadow */
141 {VIACR, CR6E, 0xFF, 0x63},
142 /* IGA2 Offset */
143 {VIACR, CR66, 0xFF, 0xB4}, {VIACR, CR67, 0x03, 0x00},
144 /* VCLK */
145 {VIASR, SR44, 0xFF, 0xC6}, {VIASR, SR45, 0xFF, 0x8C},
146 {VIASR, SR46, 0xFF, 0x05}
147};
148
149#define NUM_TOTAL_P880_LCD_RES_6X4_14X10 ARRAY_SIZE(P880_LCD_RES_6X4_14X10)
150
151struct io_reg P880_LCD_RES_8X6_14X10[] = {
152 /* 800x600 */
153 /* IGA2 Horizontal Total */
154 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
155 /* IGA2 Horizontal Blank End */
156 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
157 {VIACR, CR5D, 0x40, 0x24},
158 /* IGA2 Horizontal Total Shadow */
159 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x44},
160 /* IGA2 Horizontal Blank End Shadow */
161 {VIACR, CR6E, 0xFF, 0x83},
162 /* IGA2 Offset */
163 {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00},
164 /* VCLK */
165 {VIASR, SR44, 0xFF, 0x06}, {VIASR, SR45, 0xFF, 0x8D},
166 {VIASR, SR46, 0xFF, 0x05}
167};
168
169#define NUM_TOTAL_P880_LCD_RES_8X6_14X10 ARRAY_SIZE(P880_LCD_RES_8X6_14X10)
170
171/* ++++++ K400 ++++++ */
172/* Panel 1600x1200 */
173struct io_reg K400_LCD_RES_6X4_16X12[] = {
174 /*IGA2 Horizontal Total */
175 {VIACR, CR50, 0xFF, 0x73}, {VIACR, CR55, 0x0F, 0x08},
176 /*IGA2 Horizontal Blank End */
177 {VIACR, CR53, 0xFF, 0x73}, {VIACR, CR54, 0x38, 0x00},
178 {VIACR, CR5D, 0x40, 0x40},
179 /*IGA2 Horizontal Total Shadow */
180 {VIACR, CR6D, 0xFF, 0x5A}, {VIACR, CR71, 0x08, 0x00},
181 /*IGA2 Horizontal Blank End Shadow */
182 {VIACR, CR6E, 0xFF, 0x5E},
183 /*IGA2 Offset */
184 {VIACR, CR66, 0xFF, 0xDA}, {VIACR, CR67, 0x03, 0x00},
185 /*VCLK*/ {VIASR, SR46, 0xFF, 0xC4}, {VIASR, SR47, 0xFF, 0x7F}
186};
187
188#define NUM_TOTAL_K400_LCD_RES_6X4_16X12 ARRAY_SIZE(K400_LCD_RES_6X4_16X12)
189
190struct io_reg K400_LCD_RES_7X4_16X12[] = {
191 /*IGA2 Horizontal Total */
192 {VIACR, CR50, 0xFF, 0x67}, {VIACR, CR55, 0x0F, 0x08},
193 /*IGA2 Horizontal Blank End */
194 {VIACR, CR53, 0xFF, 0x67}, {VIACR, CR54, 0x38, 0x00},
195 {VIACR, CR5D, 0x40, 0x40},
196 /*IGA2 Horizontal Total Shadow */
197 {VIACR, CR6D, 0xFF, 0x74}, {VIACR, CR71, 0x08, 0x00},
198 /*IGA2 Horizontal Blank End Shadow */
199 {VIACR, CR6E, 0xFF, 0x78},
200 /*IGA2 Offset */
201 {VIACR, CR66, 0xFF, 0xF5}, {VIACR, CR67, 0x03, 0x00},
202 /*VCLK*/ {VIASR, SR46, 0xFF, 0x46}, {VIASR, SR47, 0xFF, 0x3D}
203};
204
205#define NUM_TOTAL_K400_LCD_RES_7X4_16X12 ARRAY_SIZE(K400_LCD_RES_7X4_16X12)
206
207struct io_reg K400_LCD_RES_8X6_16X12[] = {
208 /*IGA2 Horizontal Total */
209 {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08},
210 /*IGA2 Horizontal Blank End */
211 {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00},
212 {VIACR, CR5D, 0x40, 0x40},
213 /*IGA2 Horizontal Total Shadow */
214 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x00},
215 /*IGA2 Horizontal Blank End Shadow */
216 {VIACR, CR6E, 0xFF, 0x83},
217 /*IGA2 Offset */
218 {VIACR, CR66, 0xFF, 0xE1}, {VIACR, CR67, 0x03, 0x00},
219 /*VCLK*/ {VIASR, SR46, 0xFF, 0x85}, {VIASR, SR47, 0xFF, 0x6F}
220};
221
222#define NUM_TOTAL_K400_LCD_RES_8X6_16X12 ARRAY_SIZE(K400_LCD_RES_8X6_16X12)
223
224struct io_reg K400_LCD_RES_10X7_16X12[] = {
225 /*IGA2 Horizontal Total */
226 {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08},
227 /*IGA2 Horizontal Blank End */
228 {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00},
229 {VIACR, CR5D, 0x40, 0x40},
230 /*IGA2 Horizontal Total Shadow */
231 {VIACR, CR6D, 0xFF, 0xAB}, {VIACR, CR71, 0x08, 0x00},
232 /*IGA2 Horizontal Blank End Shadow */
233 {VIACR, CR6E, 0xFF, 0xAF},
234 /*IGA2 Offset */
235 {VIACR, CR66, 0xFF, 0xF0}, {VIACR, CR67, 0x03, 0x00},
236 /*VCLK*/ {VIASR, SR46, 0xFF, 0x45}, {VIASR, SR47, 0xFF, 0x4A}
237};
238
239#define NUM_TOTAL_K400_LCD_RES_10X7_16X12 ARRAY_SIZE(K400_LCD_RES_10X7_16X12)
240
241struct io_reg K400_LCD_RES_12X10_16X12[] = {
242 /*IGA2 Horizontal Total */
243 {VIACR, CR50, 0xFF, 0x7D}, {VIACR, CR55, 0x0F, 0x08},
244 /*IGA2 Horizontal Blank End */
245 {VIACR, CR53, 0xFF, 0x7D}, {VIACR, CR54, 0x38, 0x00},
246 {VIACR, CR5D, 0x40, 0x40},
247 /*IGA2 Horizontal Total Shadow */
248 {VIACR, CR6D, 0xFF, 0xD0}, {VIACR, CR71, 0x08, 0x00},
249 /*IGA2 Horizontal Blank End Shadow */
250 {VIACR, CR6E, 0xFF, 0xD4},
251 /*IGA2 Offset */
252 {VIACR, CR66, 0xFF, 0xFA}, {VIACR, CR67, 0x03, 0x00},
253 /*VCLK*/ {VIASR, SR46, 0xFF, 0x47}, {VIASR, SR47, 0xFF, 0x7C}
254};
255
256#define NUM_TOTAL_K400_LCD_RES_12X10_16X12 ARRAY_SIZE(K400_LCD_RES_12X10_16X12)
257
258/* Panel 1400x1050 */
259struct io_reg K400_LCD_RES_6X4_14X10[] = {
260 /* 640x400 */
261 /* IGA2 Horizontal Total */
262 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
263 /* IGA2 Horizontal Blank End */
264 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
265 {VIACR, CR5D, 0x40, 0x24},
266 /* IGA2 Horizontal Total Shadow */
267 {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x44},
268 /* IGA2 Horizontal Blank End Shadow */
269 {VIACR, CR6E, 0xFF, 0x63},
270 /* IGA2 Offset */
271 {VIACR, CR66, 0xFF, 0xB4}, {VIACR, CR67, 0x03, 0x00},
272 /* VCLK */
273 {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x19}
274};
275
276#define NUM_TOTAL_K400_LCD_RES_6X4_14X10 ARRAY_SIZE(K400_LCD_RES_6X4_14X10)
277
278struct io_reg K400_LCD_RES_8X6_14X10[] = {
279 /* 800x600 */
280 /* IGA2 Horizontal Total */
281 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
282 /* IGA2 Horizontal Blank End */
283 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
284 {VIACR, CR5D, 0x40, 0x24},
285 /* IGA2 Horizontal Total Shadow */
286 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x44},
287 /* IGA2 Horizontal Blank End Shadow */
288 {VIACR, CR6E, 0xFF, 0x83},
289 /* IGA2 Offset */
290 {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00},
291 /* VCLK */
292 {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x21}
293};
294
295#define NUM_TOTAL_K400_LCD_RES_8X6_14X10 ARRAY_SIZE(K400_LCD_RES_8X6_14X10)
296
297struct io_reg K400_LCD_RES_10X7_14X10[] = {
298 /* 1024x768 */
299 /* IGA2 Horizontal Total */
300 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
301 /* IGA2 Horizontal Blank End */
302 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
303 {VIACR, CR5D, 0x40, 0x24},
304 /* IGA2 Horizontal Total Shadow */
305 {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x44},
306 /* IGA2 Horizontal Blank End Shadow */
307 {VIACR, CR6E, 0xFF, 0xA7},
308 /* IGA2 Offset */
309 {VIACR, CR66, 0xFF, 0xC3}, {VIACR, CR67, 0x03, 0x04},
310 /* VCLK */
311 {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E}
312};
313
314#define NUM_TOTAL_K400_LCD_RES_10X7_14X10 ARRAY_SIZE(K400_LCD_RES_10X7_14X10)
315
316struct io_reg K400_LCD_RES_12X10_14X10[] = {
317 /* 1280x768, 1280x960, 1280x1024 */
318 /* IGA2 Horizontal Total */
319 {VIACR, CR50, 0xFF, 0x97}, {VIACR, CR55, 0x0F, 0x56},
320 /* IGA2 Horizontal Blank End */
321 {VIACR, CR53, 0xFF, 0x97}, {VIACR, CR54, 0x38, 0x75},
322 {VIACR, CR5D, 0x40, 0x24},
323 /* IGA2 Horizontal Total Shadow */
324 {VIACR, CR6D, 0xFF, 0xCE}, {VIACR, CR71, 0x08, 0x44},
325 /* IGA2 Horizontal Blank End Shadow */
326 {VIACR, CR6E, 0xFF, 0xD2},
327 /* IGA2 Offset */
328 {VIACR, CR66, 0xFF, 0xC9}, {VIACR, CR67, 0x03, 0x04},
329 /* VCLK */
330 {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0x79}
331};
332
333#define NUM_TOTAL_K400_LCD_RES_12X10_14X10 ARRAY_SIZE(K400_LCD_RES_12X10_14X10)
334
335/* ++++++ K400 ++++++ */
336/* Panel 1366x768 */
337struct io_reg K400_LCD_RES_6X4_1366X7[] = {
338 /* 640x400 */
339 /* IGA2 Horizontal Total */
340 {VIACR, CR50, 0xFF, 0x47}, {VIACR, CR55, 0x0F, 0x35},
341 /* IGA2 Horizontal Blank End */
342 {VIACR, CR53, 0xFF, 0x47}, {VIACR, CR54, 0x38, 0x2B},
343 {VIACR, CR5D, 0x40, 0x13},
344 /* IGA2 Horizontal Total Shadow */
345 {VIACR, CR6D, 0xFF, 0x60}, {VIACR, CR71, 0x08, 0x23},
346 /* IGA2 Horizontal Blank End Shadow */
347 {VIACR, CR6E, 0xFF, 0x64},
348 /* IGA2 Offset */
349 {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00},
350 /* VCLK */
351 {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0x4C}
352};
353
354#define NUM_TOTAL_K400_LCD_RES_6X4_1366X7 ARRAY_SIZE(K400_LCD_RES_6X4_1366X7)
355
356struct io_reg K400_LCD_RES_7X4_1366X7[] = {
357 /* IGA2 Horizontal Total */
358 {VIACR, CR50, 0xFF, 0x3B}, {VIACR, CR55, 0x0F, 0x35},
359 /* IGA2 Horizontal Blank End */
360 {VIACR, CR53, 0xFF, 0x3B}, {VIACR, CR54, 0x38, 0x2B},
361 {VIACR, CR5D, 0x40, 0x13},
362 /* IGA2 Horizontal Total Shadow */
363 {VIACR, CR6D, 0xFF, 0x71}, {VIACR, CR71, 0x08, 0x23},
364 /* IGA2 Horizontal Blank End Shadow */
365 {VIACR, CR6E, 0xFF, 0x75},
366 /* IGA2 Offset */
367 {VIACR, CR66, 0xFF, 0x96}, {VIACR, CR67, 0x03, 0x00},
368 /* VCLK */
369 {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x10}
370};
371
372#define NUM_TOTAL_K400_LCD_RES_7X4_1366X7 ARRAY_SIZE(K400_LCD_RES_7X4_1366X7)
373
374struct io_reg K400_LCD_RES_8X6_1366X7[] = {
375 /* 800x600 */
376 /* IGA2 Horizontal Total */
377 {VIACR, CR50, 0xFF, 0x37}, {VIACR, CR55, 0x0F, 0x35},
378 /* IGA2 Horizontal Blank End */
379 {VIACR, CR53, 0xFF, 0x37}, {VIACR, CR54, 0x38, 0x2B},
380 {VIACR, CR5D, 0x40, 0x13},
381 /* IGA2 Horizontal Total Shadow */
382 {VIACR, CR6D, 0xFF, 0x7E}, {VIACR, CR71, 0x08, 0x23},
383 /* IGA2 Horizontal Blank End Shadow */
384 {VIACR, CR6E, 0xFF, 0x82},
385 /* IGA2 Offset */
386 {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00},
387 /* VCLK */
388 {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0xB9}
389};
390
391#define NUM_TOTAL_K400_LCD_RES_8X6_1366X7 ARRAY_SIZE(K400_LCD_RES_8X6_1366X7)
392
393struct io_reg K400_LCD_RES_10X7_1366X7[] = {
394 /* 1024x768 */
395 /* IGA2 Horizontal Total */
396 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
397 /* IGA2 Horizontal Blank End */
398 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
399 {VIACR, CR5D, 0x40, 0x24},
400 /* IGA2 Horizontal Total Shadow */
401 {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x44},
402 /* IGA2 Horizontal Blank End Shadow */
403 {VIACR, CR6E, 0xFF, 0xA7},
404 /* IGA2 Offset */
405 {VIACR, CR66, 0xFF, 0xC3}, {VIACR, CR67, 0x03, 0x04},
406 /* VCLK */
407 {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E}
408};
409
410#define NUM_TOTAL_K400_LCD_RES_10X7_1366X7 ARRAY_SIZE(K400_LCD_RES_10X7_1366X7)
411
412struct io_reg K400_LCD_RES_12X10_1366X7[] = {
413 /* 1280x768, 1280x960, 1280x1024 */
414 /* IGA2 Horizontal Total */
415 {VIACR, CR50, 0xFF, 0x97}, {VIACR, CR55, 0x0F, 0x56},
416 /* IGA2 Horizontal Blank End */
417 {VIACR, CR53, 0xFF, 0x97}, {VIACR, CR54, 0x38, 0x75},
418 {VIACR, CR5D, 0x40, 0x24},
419 /* IGA2 Horizontal Total Shadow */
420 {VIACR, CR6D, 0xFF, 0xCE}, {VIACR, CR71, 0x08, 0x44},
421 /* IGA2 Horizontal Blank End Shadow */
422 {VIACR, CR6E, 0xFF, 0xD2},
423 /* IGA2 Offset */
424 {VIACR, CR66, 0xFF, 0xC9}, {VIACR, CR67, 0x03, 0x04},
425 /* VCLK */
426 {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0x79}
427};
428
429#define NUM_TOTAL_K400_LCD_RES_12X10_1366X7\
430 ARRAY_SIZE(K400_LCD_RES_12X10_1366X7)
431
432/* ++++++ K400 ++++++ */
433/* Panel 1280x1024 */
434struct io_reg K400_LCD_RES_6X4_12X10[] = {
435 /*IGA2 Horizontal Total */
436 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46},
437 /*IGA2 Horizontal Blank End */
438 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74},
439 {VIACR, CR5D, 0x40, 0x1C},
440 /*IGA2 Horizontal Total Shadow */
441 {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x34},
442 /*IGA2 Horizontal Blank End Shadow */
443 {VIACR, CR6E, 0xFF, 0x63},
444 /*IGA2 Offset */
445 {VIACR, CR66, 0xFF, 0xAA}, {VIACR, CR67, 0x03, 0x00},
446 /*VCLK*/ {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x19}
447};
448
449#define NUM_TOTAL_K400_LCD_RES_6X4_12X10 ARRAY_SIZE(K400_LCD_RES_6X4_12X10)
450
451struct io_reg K400_LCD_RES_7X4_12X10[] = {
452 /*IGA2 Horizontal Total */
453 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46},
454 /*IGA2 Horizontal Blank End */
455 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74},
456 {VIACR, CR5D, 0x40, 0x1C},
457 /*IGA2 Horizontal Total Shadow */
458 {VIACR, CR6D, 0xFF, 0x68}, {VIACR, CR71, 0x08, 0x34},
459 /*IGA2 Horizontal Blank End Shadow */
460 {VIACR, CR6E, 0xFF, 0x6C},
461 /*IGA2 Offset */
462 {VIACR, CR66, 0xFF, 0xA8}, {VIACR, CR67, 0x03, 0x00},
463 /*VCLK*/ {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0xED}
464};
465
466#define NUM_TOTAL_K400_LCD_RES_7X4_12X10 ARRAY_SIZE(K400_LCD_RES_7X4_12X10)
467
468struct io_reg K400_LCD_RES_8X6_12X10[] = {
469 /*IGA2 Horizontal Total */
470 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46},
471 /*IGA2 Horizontal Blank End */
472 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74},
473 {VIACR, CR5D, 0x40, 0x1C},
474 /*IGA2 Horizontal Total Shadow */
475 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x34},
476 /*IGA2 Horizontal Blank End Shadow */
477 {VIACR, CR6E, 0xFF, 0x83},
478 /*IGA2 Offset */
479 {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00},
480 /*VCLK*/ {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x21}
481};
482
483#define NUM_TOTAL_K400_LCD_RES_8X6_12X10 ARRAY_SIZE(K400_LCD_RES_8X6_12X10)
484
485struct io_reg K400_LCD_RES_10X7_12X10[] = {
486 /*IGA2 Horizontal Total */
487 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46},
488 /*IGA2 Horizontal Blank End */
489 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74},
490 {VIACR, CR5D, 0x40, 0x1C},
491 /*IGA2 Horizontal Total Shadow */
492 {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x34},
493 /*IGA2 Horizontal Blank End Shadow */
494 {VIACR, CR6E, 0xFF, 0xA7},
495 /*IGA2 Offset */
496 {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x04},
497 /*VCLK*/ {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E}
498};
499
500#define NUM_TOTAL_K400_LCD_RES_10X7_12X10 ARRAY_SIZE(K400_LCD_RES_10X7_12X10)
501
502/* ++++++ K400 ++++++ */
503/* Panel 1024x768 */
504struct io_reg K400_LCD_RES_6X4_10X7[] = {
505 /*IGA2 Horizontal Total */
506 {VIACR, CR50, 0xFF, 0x47}, {VIACR, CR55, 0x0F, 0x35},
507 /*IGA2 Horizontal Blank End */
508 {VIACR, CR53, 0xFF, 0x47}, {VIACR, CR54, 0x38, 0x2B},
509 {VIACR, CR5D, 0x40, 0x13},
510 /*IGA2 Horizontal Total Shadow */
511 {VIACR, CR6D, 0xFF, 0x60}, {VIACR, CR71, 0x08, 0x23},
512 /*IGA2 Horizontal Blank End Shadow */
513 {VIACR, CR6E, 0xFF, 0x64},
514 /*IGA2 Offset */
515 {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00},
516 /*VCLK*/ {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0x4C}
517};
518
519#define NUM_TOTAL_K400_LCD_RES_6X4_10X7 ARRAY_SIZE(K400_LCD_RES_6X4_10X7)
520
521struct io_reg K400_LCD_RES_7X4_10X7[] = {
522 /*IGA2 Horizontal Total */
523 {VIACR, CR50, 0xFF, 0x3B}, {VIACR, CR55, 0x0F, 0x35},
524 /*IGA2 Horizontal Blank End */
525 {VIACR, CR53, 0xFF, 0x3B}, {VIACR, CR54, 0x38, 0x2B},
526 {VIACR, CR5D, 0x40, 0x13},
527 /*IGA2 Horizontal Total Shadow */
528 {VIACR, CR6D, 0xFF, 0x71}, {VIACR, CR71, 0x08, 0x23},
529 /*IGA2 Horizontal Blank End Shadow */
530 {VIACR, CR6E, 0xFF, 0x75},
531 /*IGA2 Offset */
532 {VIACR, CR66, 0xFF, 0x96}, {VIACR, CR67, 0x03, 0x00},
533 /*VCLK*/ {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x10}
534};
535
536#define NUM_TOTAL_K400_LCD_RES_7X4_10X7 ARRAY_SIZE(K400_LCD_RES_7X4_10X7)
537
538struct io_reg K400_LCD_RES_8X6_10X7[] = {
539 /*IGA2 Horizontal Total */
540 {VIACR, CR50, 0xFF, 0x37}, {VIACR, CR55, 0x0F, 0x35},
541 /*IGA2 Horizontal Blank End */
542 {VIACR, CR53, 0xFF, 0x37}, {VIACR, CR54, 0x38, 0x2B},
543 {VIACR, CR5D, 0x40, 0x13},
544 /*IGA2 Horizontal Total Shadow */
545 {VIACR, CR6D, 0xFF, 0x7E}, {VIACR, CR71, 0x08, 0x23},
546 /*IGA2 Horizontal Blank End Shadow */
547 {VIACR, CR6E, 0xFF, 0x82},
548 /*IGA2 Offset */
549 {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00},
550 /*VCLK*/ {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0xB9}
551};
552
553#define NUM_TOTAL_K400_LCD_RES_8X6_10X7 ARRAY_SIZE(K400_LCD_RES_8X6_10X7)
554
555/* ++++++ K400 ++++++ */
556/* Panel 800x600 */
557struct io_reg K400_LCD_RES_6X4_8X6[] = {
558 /*IGA2 Horizontal Total */
559 {VIACR, CR50, 0xFF, 0x1A}, {VIACR, CR55, 0x0F, 0x34},
560 /*IGA2 Horizontal Blank End */
561 {VIACR, CR53, 0xFF, 0x1A}, {VIACR, CR54, 0x38, 0xE3},
562 {VIACR, CR5D, 0x40, 0x12},
563 /*IGA2 Horizontal Total Shadow */
564 {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x22},
565 /*IGA2 Horizontal Blank End Shadow */
566 {VIACR, CR6E, 0xFF, 0x63},
567 /*IGA2 Offset */
568 {VIACR, CR66, 0xFF, 0x6E}, {VIACR, CR67, 0x03, 0x00},
569 /*VCLK*/ {VIASR, SR46, 0xFF, 0x86}, {VIASR, SR47, 0xFF, 0xB3}
570};
571
572#define NUM_TOTAL_K400_LCD_RES_6X4_8X6 ARRAY_SIZE(K400_LCD_RES_6X4_8X6)
573
574struct io_reg K400_LCD_RES_7X4_8X6[] = {
575 /*IGA2 Horizontal Total */
576 {VIACR, CR50, 0xFF, 0x1F}, {VIACR, CR55, 0x0F, 0x34},
577 /*IGA2 Horizontal Blank End */
578 {VIACR, CR53, 0xFF, 0x1F}, {VIACR, CR54, 0x38, 0xE3},
579 {VIACR, CR5D, 0x40, 0x12},
580 /*IGA2 Horizontal Total Shadow */
581 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x22},
582 /*IGA2 Horizontal Blank End Shadow */
583 {VIACR, CR6E, 0xFF, 0x83},
584 /*IGA2 Offset */
585 {VIACR, CR66, 0xFF, 0x78}, {VIACR, CR67, 0x03, 0x00},
586 /*VCLK*/ {VIASR, SR46, 0xFF, 0xC4}, {VIASR, SR47, 0xFF, 0x59}
587};
588
589#define NUM_TOTAL_K400_LCD_RES_7X4_8X6 ARRAY_SIZE(K400_LCD_RES_7X4_8X6)
590
591#endif /* __LCDTBL_H__ */
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h
new file mode 100644
index 000000000000..2e1254da9c8c
--- /dev/null
+++ b/drivers/video/via/share.h
@@ -0,0 +1,1105 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __SHARE_H__
23#define __SHARE_H__
24
25/* Define Return Value */
26#define FAIL -1
27#define OK 1
28
29#ifndef NULL
30#define NULL 0
31#endif
32
33/* Define Bit Field */
34#define BIT0 0x01
35#define BIT1 0x02
36#define BIT2 0x04
37#define BIT3 0x08
38#define BIT4 0x10
39#define BIT5 0x20
40#define BIT6 0x40
41#define BIT7 0x80
42
43/* Video Memory Size */
44#define VIDEO_MEMORY_SIZE_16M 0x1000000
45
46/* Definition Mode Index
47*/
48#define VIA_RES_640X480 0
49#define VIA_RES_800X600 1
50#define VIA_RES_1024X768 2
51#define VIA_RES_1152X864 3
52#define VIA_RES_1280X1024 4
53#define VIA_RES_1600X1200 5
54#define VIA_RES_1440X1050 6
55#define VIA_RES_1280X768 7
56#define VIA_RES_1280X960 8
57#define VIA_RES_1920X1440 9
58#define VIA_RES_848X480 10
59#define VIA_RES_1400X1050 11
60#define VIA_RES_720X480 12
61#define VIA_RES_720X576 13
62#define VIA_RES_1024X512 14
63#define VIA_RES_856X480 15
64#define VIA_RES_1024X576 16
65#define VIA_RES_640X400 17
66#define VIA_RES_1280X720 18
67#define VIA_RES_1920X1080 19
68#define VIA_RES_800X480 20
69#define VIA_RES_1368X768 21
70#define VIA_RES_1024X600 22
71#define VIA_RES_1280X800 23
72#define VIA_RES_1680X1050 24
73#define VIA_RES_960X600 25
74#define VIA_RES_1000X600 26
75#define VIA_RES_1088X612 27
76#define VIA_RES_1152X720 28
77#define VIA_RES_1200X720 29
78#define VIA_RES_1280X600 30
79#define VIA_RES_1360X768 31
80#define VIA_RES_1366X768 32
81#define VIA_RES_1440X900 33
82#define VIA_RES_1600X900 34
83#define VIA_RES_1600X1024 35
84#define VIA_RES_1792X1344 36
85#define VIA_RES_1856X1392 37
86#define VIA_RES_1920X1200 38
87#define VIA_RES_2048X1536 39
88#define VIA_RES_480X640 40
89
90/*Reduce Blanking*/
91#define VIA_RES_1360X768_RB 131
92#define VIA_RES_1440X900_RB 133
93#define VIA_RES_1400X1050_RB 111
94#define VIA_RES_1600X900_RB 134
95#define VIA_RES_1680X1050_RB 124
96#define VIA_RES_1920X1080_RB 119
97#define VIA_RES_1920X1200_RB 138
98
99#define VIA_RES_INVALID 255
100
101/* standard VGA IO port
102*/
103#define VIARMisc 0x3CC
104#define VIAWMisc 0x3C2
105#define VIAStatus 0x3DA
106#define VIACR 0x3D4
107#define VIASR 0x3C4
108#define VIAGR 0x3CE
109#define VIAAR 0x3C0
110
111#define StdCR 0x19
112#define StdSR 0x04
113#define StdGR 0x09
114#define StdAR 0x14
115
116#define PatchCR 11
117
118/* Display path */
119#define IGA1 1
120#define IGA2 2
121#define IGA1_IGA2 3
122
123/* Define Color Depth */
124#define MODE_8BPP 1
125#define MODE_16BPP 2
126#define MODE_32BPP 4
127
128#define GR20 0x20
129#define GR21 0x21
130#define GR22 0x22
131
132/* Sequencer Registers */
133#define SR01 0x01
134#define SR10 0x10
135#define SR12 0x12
136#define SR15 0x15
137#define SR16 0x16
138#define SR17 0x17
139#define SR18 0x18
140#define SR1B 0x1B
141#define SR1A 0x1A
142#define SR1C 0x1C
143#define SR1D 0x1D
144#define SR1E 0x1E
145#define SR1F 0x1F
146#define SR20 0x20
147#define SR21 0x21
148#define SR22 0x22
149#define SR2A 0x2A
150#define SR2D 0x2D
151#define SR2E 0x2E
152
153#define SR30 0x30
154#define SR39 0x39
155#define SR3D 0x3D
156#define SR3E 0x3E
157#define SR3F 0x3F
158#define SR40 0x40
159#define SR43 0x43
160#define SR44 0x44
161#define SR45 0x45
162#define SR46 0x46
163#define SR47 0x47
164#define SR48 0x48
165#define SR49 0x49
166#define SR4A 0x4A
167#define SR4B 0x4B
168#define SR4C 0x4C
169#define SR52 0x52
170#define SR5E 0x5E
171#define SR65 0x65
172
173/* CRT Controller Registers */
174#define CR00 0x00
175#define CR01 0x01
176#define CR02 0x02
177#define CR03 0x03
178#define CR04 0x04
179#define CR05 0x05
180#define CR06 0x06
181#define CR07 0x07
182#define CR08 0x08
183#define CR09 0x09
184#define CR0A 0x0A
185#define CR0B 0x0B
186#define CR0C 0x0C
187#define CR0D 0x0D
188#define CR0E 0x0E
189#define CR0F 0x0F
190#define CR10 0x10
191#define CR11 0x11
192#define CR12 0x12
193#define CR13 0x13
194#define CR14 0x14
195#define CR15 0x15
196#define CR16 0x16
197#define CR17 0x17
198#define CR18 0x18
199
200/* Extend CRT Controller Registers */
201#define CR30 0x30
202#define CR31 0x31
203#define CR32 0x32
204#define CR33 0x33
205#define CR34 0x34
206#define CR35 0x35
207#define CR36 0x36
208#define CR37 0x37
209#define CR38 0x38
210#define CR39 0x39
211#define CR3A 0x3A
212#define CR3B 0x3B
213#define CR3C 0x3C
214#define CR3D 0x3D
215#define CR3E 0x3E
216#define CR3F 0x3F
217#define CR40 0x40
218#define CR41 0x41
219#define CR42 0x42
220#define CR43 0x43
221#define CR44 0x44
222#define CR45 0x45
223#define CR46 0x46
224#define CR47 0x47
225#define CR48 0x48
226#define CR49 0x49
227#define CR4A 0x4A
228#define CR4B 0x4B
229#define CR4C 0x4C
230#define CR4D 0x4D
231#define CR4E 0x4E
232#define CR4F 0x4F
233#define CR50 0x50
234#define CR51 0x51
235#define CR52 0x52
236#define CR53 0x53
237#define CR54 0x54
238#define CR55 0x55
239#define CR56 0x56
240#define CR57 0x57
241#define CR58 0x58
242#define CR59 0x59
243#define CR5A 0x5A
244#define CR5B 0x5B
245#define CR5C 0x5C
246#define CR5D 0x5D
247#define CR5E 0x5E
248#define CR5F 0x5F
249#define CR60 0x60
250#define CR61 0x61
251#define CR62 0x62
252#define CR63 0x63
253#define CR64 0x64
254#define CR65 0x65
255#define CR66 0x66
256#define CR67 0x67
257#define CR68 0x68
258#define CR69 0x69
259#define CR6A 0x6A
260#define CR6B 0x6B
261#define CR6C 0x6C
262#define CR6D 0x6D
263#define CR6E 0x6E
264#define CR6F 0x6F
265#define CR70 0x70
266#define CR71 0x71
267#define CR72 0x72
268#define CR73 0x73
269#define CR74 0x74
270#define CR75 0x75
271#define CR76 0x76
272#define CR77 0x77
273#define CR78 0x78
274#define CR79 0x79
275#define CR7A 0x7A
276#define CR7B 0x7B
277#define CR7C 0x7C
278#define CR7D 0x7D
279#define CR7E 0x7E
280#define CR7F 0x7F
281#define CR80 0x80
282#define CR81 0x81
283#define CR82 0x82
284#define CR83 0x83
285#define CR84 0x84
286#define CR85 0x85
287#define CR86 0x86
288#define CR87 0x87
289#define CR88 0x88
290#define CR89 0x89
291#define CR8A 0x8A
292#define CR8B 0x8B
293#define CR8C 0x8C
294#define CR8D 0x8D
295#define CR8E 0x8E
296#define CR8F 0x8F
297#define CR90 0x90
298#define CR91 0x91
299#define CR92 0x92
300#define CR93 0x93
301#define CR94 0x94
302#define CR95 0x95
303#define CR96 0x96
304#define CR97 0x97
305#define CR98 0x98
306#define CR99 0x99
307#define CR9A 0x9A
308#define CR9B 0x9B
309#define CR9C 0x9C
310#define CR9D 0x9D
311#define CR9E 0x9E
312#define CR9F 0x9F
313#define CRA0 0xA0
314#define CRA1 0xA1
315#define CRA2 0xA2
316#define CRA3 0xA3
317#define CRD2 0xD2
318#define CRD3 0xD3
319#define CRD4 0xD4
320
321/* LUT Table*/
322#define LUT_DATA 0x3C9 /* DACDATA */
323#define LUT_INDEX_READ 0x3C7 /* DACRX */
324#define LUT_INDEX_WRITE 0x3C8 /* DACWX */
325#define DACMASK 0x3C6
326
327/* Definition Device */
328#define DEVICE_CRT 0x01
329#define DEVICE_DVI 0x03
330#define DEVICE_LCD 0x04
331
332/* Device output interface */
333#define INTERFACE_NONE 0x00
334#define INTERFACE_ANALOG_RGB 0x01
335#define INTERFACE_DVP0 0x02
336#define INTERFACE_DVP1 0x03
337#define INTERFACE_DFP_HIGH 0x04
338#define INTERFACE_DFP_LOW 0x05
339#define INTERFACE_DFP 0x06
340#define INTERFACE_LVDS0 0x07
341#define INTERFACE_LVDS1 0x08
342#define INTERFACE_LVDS0LVDS1 0x09
343#define INTERFACE_TMDS 0x0A
344
345#define HW_LAYOUT_LCD_ONLY 0x01
346#define HW_LAYOUT_DVI_ONLY 0x02
347#define HW_LAYOUT_LCD_DVI 0x03
348#define HW_LAYOUT_LCD1_LCD2 0x04
349#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
350
351/* Definition Refresh Rate */
352#define REFRESH_50 50
353#define REFRESH_60 60
354#define REFRESH_75 75
355#define REFRESH_85 85
356#define REFRESH_100 100
357#define REFRESH_120 120
358
359/* Definition Sync Polarity*/
360#define NEGATIVE 1
361#define POSITIVE 0
362
363/*480x640@60 Sync Polarity (GTF)
364*/
365#define M480X640_R60_HSP NEGATIVE
366#define M480X640_R60_VSP POSITIVE
367
368/*640x480@60 Sync Polarity (VESA Mode)
369*/
370#define M640X480_R60_HSP NEGATIVE
371#define M640X480_R60_VSP NEGATIVE
372
373/*640x480@75 Sync Polarity (VESA Mode)
374*/
375#define M640X480_R75_HSP NEGATIVE
376#define M640X480_R75_VSP NEGATIVE
377
378/*640x480@85 Sync Polarity (VESA Mode)
379*/
380#define M640X480_R85_HSP NEGATIVE
381#define M640X480_R85_VSP NEGATIVE
382
383/*640x480@100 Sync Polarity (GTF Mode)
384*/
385#define M640X480_R100_HSP NEGATIVE
386#define M640X480_R100_VSP POSITIVE
387
388/*640x480@120 Sync Polarity (GTF Mode)
389*/
390#define M640X480_R120_HSP NEGATIVE
391#define M640X480_R120_VSP POSITIVE
392
393/*720x480@60 Sync Polarity (GTF Mode)
394*/
395#define M720X480_R60_HSP NEGATIVE
396#define M720X480_R60_VSP POSITIVE
397
398/*720x576@60 Sync Polarity (GTF Mode)
399*/
400#define M720X576_R60_HSP NEGATIVE
401#define M720X576_R60_VSP POSITIVE
402
403/*800x600@60 Sync Polarity (VESA Mode)
404*/
405#define M800X600_R60_HSP POSITIVE
406#define M800X600_R60_VSP POSITIVE
407
408/*800x600@75 Sync Polarity (VESA Mode)
409*/
410#define M800X600_R75_HSP POSITIVE
411#define M800X600_R75_VSP POSITIVE
412
413/*800x600@85 Sync Polarity (VESA Mode)
414*/
415#define M800X600_R85_HSP POSITIVE
416#define M800X600_R85_VSP POSITIVE
417
418/*800x600@100 Sync Polarity (GTF Mode)
419*/
420#define M800X600_R100_HSP NEGATIVE
421#define M800X600_R100_VSP POSITIVE
422
423/*800x600@120 Sync Polarity (GTF Mode)
424*/
425#define M800X600_R120_HSP NEGATIVE
426#define M800X600_R120_VSP POSITIVE
427
428/*800x480@60 Sync Polarity (CVT Mode)
429*/
430#define M800X480_R60_HSP NEGATIVE
431#define M800X480_R60_VSP POSITIVE
432
433/*848x480@60 Sync Polarity (CVT Mode)
434*/
435#define M848X480_R60_HSP NEGATIVE
436#define M848X480_R60_VSP POSITIVE
437
438/*852x480@60 Sync Polarity (GTF Mode)
439*/
440#define M852X480_R60_HSP NEGATIVE
441#define M852X480_R60_VSP POSITIVE
442
443/*1024x512@60 Sync Polarity (GTF Mode)
444*/
445#define M1024X512_R60_HSP NEGATIVE
446#define M1024X512_R60_VSP POSITIVE
447
448/*1024x600@60 Sync Polarity (GTF Mode)
449*/
450#define M1024X600_R60_HSP NEGATIVE
451#define M1024X600_R60_VSP POSITIVE
452
453/*1024x768@60 Sync Polarity (VESA Mode)
454*/
455#define M1024X768_R60_HSP NEGATIVE
456#define M1024X768_R60_VSP NEGATIVE
457
458/*1024x768@75 Sync Polarity (VESA Mode)
459*/
460#define M1024X768_R75_HSP POSITIVE
461#define M1024X768_R75_VSP POSITIVE
462
463/*1024x768@85 Sync Polarity (VESA Mode)
464*/
465#define M1024X768_R85_HSP POSITIVE
466#define M1024X768_R85_VSP POSITIVE
467
468/*1024x768@100 Sync Polarity (GTF Mode)
469*/
470#define M1024X768_R100_HSP NEGATIVE
471#define M1024X768_R100_VSP POSITIVE
472
473/*1152x864@75 Sync Polarity (VESA Mode)
474*/
475#define M1152X864_R75_HSP POSITIVE
476#define M1152X864_R75_VSP POSITIVE
477
478/*1280x720@60 Sync Polarity (GTF Mode)
479*/
480#define M1280X720_R60_HSP NEGATIVE
481#define M1280X720_R60_VSP POSITIVE
482
483/* 1280x768@50 Sync Polarity (GTF Mode) */
484#define M1280X768_R50_HSP NEGATIVE
485#define M1280X768_R50_VSP POSITIVE
486
487/*1280x768@60 Sync Polarity (GTF Mode)
488*/
489#define M1280X768_R60_HSP NEGATIVE
490#define M1280X768_R60_VSP POSITIVE
491
492/*1280x800@60 Sync Polarity (CVT Mode)
493*/
494#define M1280X800_R60_HSP NEGATIVE
495#define M1280X800_R60_VSP POSITIVE
496
497/*1280x960@60 Sync Polarity (VESA Mode)
498*/
499#define M1280X960_R60_HSP POSITIVE
500#define M1280X960_R60_VSP POSITIVE
501
502/*1280x1024@60 Sync Polarity (VESA Mode)
503*/
504#define M1280X1024_R60_HSP POSITIVE
505#define M1280X1024_R60_VSP POSITIVE
506
507/* 1360x768@60 Sync Polarity (CVT Mode) */
508#define M1360X768_R60_HSP POSITIVE
509#define M1360X768_R60_VSP POSITIVE
510
511/* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */
512#define M1360X768_RB_R60_HSP POSITIVE
513#define M1360X768_RB_R60_VSP NEGATIVE
514
515/* 1368x768@50 Sync Polarity (GTF Mode) */
516#define M1368X768_R50_HSP NEGATIVE
517#define M1368X768_R50_VSP POSITIVE
518
519/* 1368x768@60 Sync Polarity (VESA Mode) */
520#define M1368X768_R60_HSP NEGATIVE
521#define M1368X768_R60_VSP POSITIVE
522
523/*1280x1024@75 Sync Polarity (VESA Mode)
524*/
525#define M1280X1024_R75_HSP POSITIVE
526#define M1280X1024_R75_VSP POSITIVE
527
528/*1280x1024@85 Sync Polarity (VESA Mode)
529*/
530#define M1280X1024_R85_HSP POSITIVE
531#define M1280X1024_R85_VSP POSITIVE
532
533/*1440x1050@60 Sync Polarity (GTF Mode)
534*/
535#define M1440X1050_R60_HSP NEGATIVE
536#define M1440X1050_R60_VSP POSITIVE
537
538/*1600x1200@60 Sync Polarity (VESA Mode)
539*/
540#define M1600X1200_R60_HSP POSITIVE
541#define M1600X1200_R60_VSP POSITIVE
542
543/*1600x1200@75 Sync Polarity (VESA Mode)
544*/
545#define M1600X1200_R75_HSP POSITIVE
546#define M1600X1200_R75_VSP POSITIVE
547
548/* 1680x1050@60 Sync Polarity (CVT Mode) */
549#define M1680x1050_R60_HSP NEGATIVE
550#define M1680x1050_R60_VSP NEGATIVE
551
552/* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
553#define M1680x1050_RB_R60_HSP POSITIVE
554#define M1680x1050_RB_R60_VSP NEGATIVE
555
556/* 1680x1050@75 Sync Polarity (CVT Mode) */
557#define M1680x1050_R75_HSP NEGATIVE
558#define M1680x1050_R75_VSP POSITIVE
559
560/*1920x1080@60 Sync Polarity (CVT Mode)
561*/
562#define M1920X1080_R60_HSP NEGATIVE
563#define M1920X1080_R60_VSP POSITIVE
564
565/* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */
566#define M1920X1080_RB_R60_HSP POSITIVE
567#define M1920X1080_RB_R60_VSP NEGATIVE
568
569/*1920x1440@60 Sync Polarity (VESA Mode)
570*/
571#define M1920X1440_R60_HSP NEGATIVE
572#define M1920X1440_R60_VSP POSITIVE
573
574/*1920x1440@75 Sync Polarity (VESA Mode)
575*/
576#define M1920X1440_R75_HSP NEGATIVE
577#define M1920X1440_R75_VSP POSITIVE
578
579#if 0
580/* 1400x1050@60 Sync Polarity (VESA Mode) */
581#define M1400X1050_R60_HSP NEGATIVE
582#define M1400X1050_R60_VSP NEGATIVE
583#endif
584
585/* 1400x1050@60 Sync Polarity (CVT Mode) */
586#define M1400X1050_R60_HSP NEGATIVE
587#define M1400X1050_R60_VSP POSITIVE
588
589/* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
590#define M1400X1050_RB_R60_HSP POSITIVE
591#define M1400X1050_RB_R60_VSP NEGATIVE
592
593/* 1400x1050@75 Sync Polarity (CVT Mode) */
594#define M1400X1050_R75_HSP NEGATIVE
595#define M1400X1050_R75_VSP POSITIVE
596
597/* 960x600@60 Sync Polarity (CVT Mode) */
598#define M960X600_R60_HSP NEGATIVE
599#define M960X600_R60_VSP POSITIVE
600
601/* 1000x600@60 Sync Polarity (GTF Mode) */
602#define M1000X600_R60_HSP NEGATIVE
603#define M1000X600_R60_VSP POSITIVE
604
605/* 1024x576@60 Sync Polarity (GTF Mode) */
606#define M1024X576_R60_HSP NEGATIVE
607#define M1024X576_R60_VSP POSITIVE
608
609/*1024x600@60 Sync Polarity (GTF Mode)*/
610#define M1024X600_R60_HSP NEGATIVE
611#define M1024X600_R60_VSP POSITIVE
612
613/* 1088x612@60 Sync Polarity (CVT Mode) */
614#define M1088X612_R60_HSP NEGATIVE
615#define M1088X612_R60_VSP POSITIVE
616
617/* 1152x720@60 Sync Polarity (CVT Mode) */
618#define M1152X720_R60_HSP NEGATIVE
619#define M1152X720_R60_VSP POSITIVE
620
621/* 1200x720@60 Sync Polarity (GTF Mode) */
622#define M1200X720_R60_HSP NEGATIVE
623#define M1200X720_R60_VSP POSITIVE
624
625/* 1280x600@60 Sync Polarity (GTF Mode) */
626#define M1280x600_R60_HSP NEGATIVE
627#define M1280x600_R60_VSP POSITIVE
628
629/* 1280x720@50 Sync Polarity (GTF Mode) */
630#define M1280X720_R50_HSP NEGATIVE
631#define M1280X720_R50_VSP POSITIVE
632
633/* 1280x720@60 Sync Polarity (CEA Mode) */
634#define M1280X720_CEA_R60_HSP POSITIVE
635#define M1280X720_CEA_R60_VSP POSITIVE
636
637/* 1440x900@60 Sync Polarity (CVT Mode) */
638#define M1440X900_R60_HSP NEGATIVE
639#define M1440X900_R60_VSP POSITIVE
640
641/* 1440x900@75 Sync Polarity (CVT Mode) */
642#define M1440X900_R75_HSP NEGATIVE
643#define M1440X900_R75_VSP POSITIVE
644
645/* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
646#define M1440X900_RB_R60_HSP POSITIVE
647#define M1440X900_RB_R60_VSP NEGATIVE
648
649/* 1600x900@60 Sync Polarity (CVT Mode) */
650#define M1600X900_R60_HSP NEGATIVE
651#define M1600X900_R60_VSP POSITIVE
652
653/* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
654#define M1600X900_RB_R60_HSP POSITIVE
655#define M1600X900_RB_R60_VSP NEGATIVE
656
657/* 1600x1024@60 Sync Polarity (GTF Mode) */
658#define M1600X1024_R60_HSP NEGATIVE
659#define M1600X1024_R60_VSP POSITIVE
660
661/* 1792x1344@60 Sync Polarity (DMT Mode) */
662#define M1792x1344_R60_HSP NEGATIVE
663#define M1792x1344_R60_VSP POSITIVE
664
665/* 1856x1392@60 Sync Polarity (DMT Mode) */
666#define M1856x1392_R60_HSP NEGATIVE
667#define M1856x1392_R60_VSP POSITIVE
668
669/* 1920x1200@60 Sync Polarity (CVT Mode) */
670#define M1920X1200_R60_HSP NEGATIVE
671#define M1920X1200_R60_VSP POSITIVE
672
673/* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */
674#define M1920X1200_RB_R60_HSP POSITIVE
675#define M1920X1200_RB_R60_VSP NEGATIVE
676
677/* 1920x1080@60 Sync Polarity (CEA Mode) */
678#define M1920X1080_CEA_R60_HSP POSITIVE
679#define M1920X1080_CEA_R60_VSP POSITIVE
680
681/* 2048x1536@60 Sync Polarity (CVT Mode) */
682#define M2048x1536_R60_HSP NEGATIVE
683#define M2048x1536_R60_VSP POSITIVE
684
685/* define PLL index: */
686#define CLK_25_175M 25175000
687#define CLK_26_880M 26880000
688#define CLK_29_581M 29581000
689#define CLK_31_490M 31490000
690#define CLK_31_500M 31500000
691#define CLK_31_728M 31728000
692#define CLK_32_668M 32688000
693#define CLK_36_000M 36000000
694#define CLK_40_000M 40000000
695#define CLK_41_291M 41291000
696#define CLK_43_163M 43163000
697#define CLK_45_250M 45250000 /* 45.46MHz */
698#define CLK_46_000M 46000000
699#define CLK_46_996M 46996000
700#define CLK_48_000M 48000000
701#define CLK_48_875M 48875000
702#define CLK_49_500M 49500000
703#define CLK_52_406M 52406000
704#define CLK_52_977M 52977000
705#define CLK_56_250M 56250000
706#define CLK_60_466M 60466000
707#define CLK_61_500M 61500000
708#define CLK_65_000M 65000000
709#define CLK_65_178M 65178000
710#define CLK_66_750M 66750000 /* 67.116MHz */
711#define CLK_68_179M 68179000
712#define CLK_69_924M 69924000
713#define CLK_70_159M 70159000
714#define CLK_72_000M 72000000
715#define CLK_74_270M 74270000
716#define CLK_78_750M 78750000
717#define CLK_80_136M 80136000
718#define CLK_83_375M 83375000
719#define CLK_83_950M 83950000
720#define CLK_84_750M 84750000 /* 84.537Mhz */
721#define CLK_85_860M 85860000
722#define CLK_88_750M 88750000
723#define CLK_94_500M 94500000
724#define CLK_97_750M 97750000
725#define CLK_101_000M 101000000
726#define CLK_106_500M 106500000
727#define CLK_108_000M 108000000
728#define CLK_113_309M 113309000
729#define CLK_118_840M 118840000
730#define CLK_119_000M 119000000
731#define CLK_121_750M 121750000 /* 121.704MHz */
732#define CLK_125_104M 125104000
733#define CLK_133_308M 133308000
734#define CLK_135_000M 135000000
735#define CLK_136_700M 136700000
736#define CLK_138_400M 138400000
737#define CLK_146_760M 146760000
738#define CLK_148_500M 148500000
739
740#define CLK_153_920M 153920000
741#define CLK_156_000M 156000000
742#define CLK_157_500M 157500000
743#define CLK_162_000M 162000000
744#define CLK_187_000M 187000000
745#define CLK_193_295M 193295000
746#define CLK_202_500M 202500000
747#define CLK_204_000M 204000000
748#define CLK_218_500M 218500000
749#define CLK_234_000M 234000000
750#define CLK_267_250M 267250000
751#define CLK_297_500M 297500000
752#define CLK_74_481M 74481000
753#define CLK_172_798M 172798000
754#define CLK_122_614M 122614000
755
756/* CLE266 PLL value
757*/
758#define CLE266_PLL_25_175M 0x0000C763
759#define CLE266_PLL_26_880M 0x0000440F
760#define CLE266_PLL_29_581M 0x00008421
761#define CLE266_PLL_31_490M 0x00004721
762#define CLE266_PLL_31_500M 0x0000C3B5
763#define CLE266_PLL_31_728M 0x0000471F
764#define CLE266_PLL_32_668M 0x0000C449
765#define CLE266_PLL_36_000M 0x0000C5E5
766#define CLE266_PLL_40_000M 0x0000C459
767#define CLE266_PLL_41_291M 0x00004417
768#define CLE266_PLL_43_163M 0x0000C579
769#define CLE266_PLL_45_250M 0x0000C57F /* 45.46MHz */
770#define CLE266_PLL_46_000M 0x0000875A
771#define CLE266_PLL_46_996M 0x0000C4E9
772#define CLE266_PLL_48_000M 0x00001443
773#define CLE266_PLL_48_875M 0x00001D63
774#define CLE266_PLL_49_500M 0x00008653
775#define CLE266_PLL_52_406M 0x0000C475
776#define CLE266_PLL_52_977M 0x00004525
777#define CLE266_PLL_56_250M 0x000047B7
778#define CLE266_PLL_60_466M 0x0000494C
779#define CLE266_PLL_61_500M 0x00001456
780#define CLE266_PLL_65_000M 0x000086ED
781#define CLE266_PLL_65_178M 0x0000855B
782#define CLE266_PLL_66_750M 0x0000844B /* 67.116MHz */
783#define CLE266_PLL_68_179M 0x00000413
784#define CLE266_PLL_69_924M 0x00001153
785#define CLE266_PLL_70_159M 0x00001462
786#define CLE266_PLL_72_000M 0x00001879
787#define CLE266_PLL_74_270M 0x00004853
788#define CLE266_PLL_78_750M 0x00004321
789#define CLE266_PLL_80_136M 0x0000051C
790#define CLE266_PLL_83_375M 0x0000C25D
791#define CLE266_PLL_83_950M 0x00000729
792#define CLE266_PLL_84_750M 0x00008576 /* 84.537MHz */
793#define CLE266_PLL_85_860M 0x00004754
794#define CLE266_PLL_88_750M 0x0000051F
795#define CLE266_PLL_94_500M 0x00000521
796#define CLE266_PLL_97_750M 0x00004652
797#define CLE266_PLL_101_000M 0x0000497F
798#define CLE266_PLL_106_500M 0x00008477 /* 106.491463 MHz */
799#define CLE266_PLL_108_000M 0x00008479
800#define CLE266_PLL_113_309M 0x00000C5F
801#define CLE266_PLL_118_840M 0x00004553
802#define CLE266_PLL_119_000M 0x00000D6C
803#define CLE266_PLL_121_750M 0x00004555 /* 121.704MHz */
804#define CLE266_PLL_125_104M 0x000006B5
805#define CLE266_PLL_133_308M 0x0000465F
806#define CLE266_PLL_135_000M 0x0000455E
807#define CLE266_PLL_136_700M 0x00000C73
808#define CLE266_PLL_138_400M 0x00000957
809#define CLE266_PLL_146_760M 0x00004567
810#define CLE266_PLL_148_500M 0x00000853
811#define CLE266_PLL_153_920M 0x00000856
812#define CLE266_PLL_156_000M 0x0000456D
813#define CLE266_PLL_157_500M 0x000005B7
814#define CLE266_PLL_162_000M 0x00004571
815#define CLE266_PLL_187_000M 0x00000976
816#define CLE266_PLL_193_295M 0x0000086C
817#define CLE266_PLL_202_500M 0x00000763
818#define CLE266_PLL_204_000M 0x00000764
819#define CLE266_PLL_218_500M 0x0000065C
820#define CLE266_PLL_234_000M 0x00000662
821#define CLE266_PLL_267_250M 0x00000670
822#define CLE266_PLL_297_500M 0x000005E6
823#define CLE266_PLL_74_481M 0x0000051A
824#define CLE266_PLL_172_798M 0x00004579
825#define CLE266_PLL_122_614M 0x0000073C
826
827/* K800 PLL value
828*/
829#define K800_PLL_25_175M 0x00539001
830#define K800_PLL_26_880M 0x001C8C80
831#define K800_PLL_29_581M 0x00409080
832#define K800_PLL_31_490M 0x006F9001
833#define K800_PLL_31_500M 0x008B9002
834#define K800_PLL_31_728M 0x00AF9003
835#define K800_PLL_32_668M 0x00909002
836#define K800_PLL_36_000M 0x009F9002
837#define K800_PLL_40_000M 0x00578C02
838#define K800_PLL_41_291M 0x00438C01
839#define K800_PLL_43_163M 0x00778C03
840#define K800_PLL_45_250M 0x007D8C83 /* 45.46MHz */
841#define K800_PLL_46_000M 0x00658C02
842#define K800_PLL_46_996M 0x00818C83
843#define K800_PLL_48_000M 0x00848C83
844#define K800_PLL_48_875M 0x00508C81
845#define K800_PLL_49_500M 0x00518C01
846#define K800_PLL_52_406M 0x00738C02
847#define K800_PLL_52_977M 0x00928C83
848#define K800_PLL_56_250M 0x007C8C02
849#define K800_PLL_60_466M 0x00A78C83
850#define K800_PLL_61_500M 0x00AA8C83
851#define K800_PLL_65_000M 0x006B8C01
852#define K800_PLL_65_178M 0x00B48C83
853#define K800_PLL_66_750M 0x00948C82 /* 67.116MHz */
854#define K800_PLL_68_179M 0x00708C01
855#define K800_PLL_69_924M 0x00C18C83
856#define K800_PLL_70_159M 0x00C28C83
857#define K800_PLL_72_000M 0x009F8C82
858#define K800_PLL_74_270M 0x00ce0c03
859#define K800_PLL_78_750M 0x00408801
860#define K800_PLL_80_136M 0x00428801
861#define K800_PLL_83_375M 0x005B0882
862#define K800_PLL_83_950M 0x00738803
863#define K800_PLL_84_750M 0x00748883 /* 84.477MHz */
864#define K800_PLL_85_860M 0x00768883
865#define K800_PLL_88_750M 0x007A8883
866#define K800_PLL_94_500M 0x00828803
867#define K800_PLL_97_750M 0x00878883
868#define K800_PLL_101_000M 0x008B8883
869#define K800_PLL_106_500M 0x00758882 /* 106.491463 MHz */
870#define K800_PLL_108_000M 0x00778882
871#define K800_PLL_113_309M 0x005D8881
872#define K800_PLL_118_840M 0x00A48883
873#define K800_PLL_119_000M 0x00838882
874#define K800_PLL_121_750M 0x00A88883 /* 121.704MHz */
875#define K800_PLL_125_104M 0x00688801
876#define K800_PLL_133_308M 0x005D8801
877#define K800_PLL_135_000M 0x001A4081
878#define K800_PLL_136_700M 0x00BD8883
879#define K800_PLL_138_400M 0x00728881
880#define K800_PLL_146_760M 0x00CC8883
881#define K800_PLL_148_500M 0x00ce0803
882#define K800_PLL_153_920M 0x00548482
883#define K800_PLL_156_000M 0x006B8483
884#define K800_PLL_157_500M 0x00142080
885#define K800_PLL_162_000M 0x006F8483
886#define K800_PLL_187_000M 0x00818483
887#define K800_PLL_193_295M 0x004F8481
888#define K800_PLL_202_500M 0x00538481
889#define K800_PLL_204_000M 0x008D8483
890#define K800_PLL_218_500M 0x00978483
891#define K800_PLL_234_000M 0x00608401
892#define K800_PLL_267_250M 0x006E8481
893#define K800_PLL_297_500M 0x00A48402
894#define K800_PLL_74_481M 0x007B8C81
895#define K800_PLL_172_798M 0x00778483
896#define K800_PLL_122_614M 0x00878882
897
898/* PLL for VT3324 */
899#define CX700_25_175M 0x008B1003
900#define CX700_26_719M 0x00931003
901#define CX700_26_880M 0x00941003
902#define CX700_29_581M 0x00A49003
903#define CX700_31_490M 0x00AE1003
904#define CX700_31_500M 0x00AE1003
905#define CX700_31_728M 0x00AF1003
906#define CX700_32_668M 0x00B51003
907#define CX700_36_000M 0x00C81003
908#define CX700_40_000M 0x006E0C03
909#define CX700_41_291M 0x00710C03
910#define CX700_43_163M 0x00770C03
911#define CX700_45_250M 0x007D0C03 /* 45.46MHz */
912#define CX700_46_000M 0x007F0C03
913#define CX700_46_996M 0x00818C83
914#define CX700_48_000M 0x00840C03
915#define CX700_48_875M 0x00508C81
916#define CX700_49_500M 0x00880C03
917#define CX700_52_406M 0x00730C02
918#define CX700_52_977M 0x00920C03
919#define CX700_56_250M 0x009B0C03
920#define CX700_60_466M 0x00460C00
921#define CX700_61_500M 0x00AA0C03
922#define CX700_65_000M 0x006B0C01
923#define CX700_65_178M 0x006B0C01
924#define CX700_66_750M 0x00940C02 /*67.116MHz */
925#define CX700_68_179M 0x00BC0C03
926#define CX700_69_924M 0x00C10C03
927#define CX700_70_159M 0x00C20C03
928#define CX700_72_000M 0x009F0C02
929#define CX700_74_270M 0x00CE0C03
930#define CX700_74_481M 0x00CE0C03
931#define CX700_78_750M 0x006C0803
932#define CX700_80_136M 0x006E0803
933#define CX700_83_375M 0x005B0882
934#define CX700_83_950M 0x00730803
935#define CX700_84_750M 0x00740803 /* 84.537Mhz */
936#define CX700_85_860M 0x00760803
937#define CX700_88_750M 0x00AC8885
938#define CX700_94_500M 0x00820803
939#define CX700_97_750M 0x00870803
940#define CX700_101_000M 0x008B0803
941#define CX700_106_500M 0x00750802
942#define CX700_108_000M 0x00950803
943#define CX700_113_309M 0x005D0801
944#define CX700_118_840M 0x00A40803
945#define CX700_119_000M 0x00830802
946#define CX700_121_750M 0x00420800 /* 121.704MHz */
947#define CX700_125_104M 0x00AD0803
948#define CX700_133_308M 0x00930802
949#define CX700_135_000M 0x00950802
950#define CX700_136_700M 0x00BD0803
951#define CX700_138_400M 0x00720801
952#define CX700_146_760M 0x00CC0803
953#define CX700_148_500M 0x00a40802
954#define CX700_153_920M 0x00540402
955#define CX700_156_000M 0x006B0403
956#define CX700_157_500M 0x006C0403
957#define CX700_162_000M 0x006F0403
958#define CX700_172_798M 0x00770403
959#define CX700_187_000M 0x00810403
960#define CX700_193_295M 0x00850403
961#define CX700_202_500M 0x008C0403
962#define CX700_204_000M 0x008D0403
963#define CX700_218_500M 0x00970403
964#define CX700_234_000M 0x00600401
965#define CX700_267_250M 0x00B90403
966#define CX700_297_500M 0x00CE0403
967#define CX700_122_614M 0x00870802
968
969/* Definition CRTC Timing Index */
970#define H_TOTAL_INDEX 0
971#define H_ADDR_INDEX 1
972#define H_BLANK_START_INDEX 2
973#define H_BLANK_END_INDEX 3
974#define H_SYNC_START_INDEX 4
975#define H_SYNC_END_INDEX 5
976#define V_TOTAL_INDEX 6
977#define V_ADDR_INDEX 7
978#define V_BLANK_START_INDEX 8
979#define V_BLANK_END_INDEX 9
980#define V_SYNC_START_INDEX 10
981#define V_SYNC_END_INDEX 11
982#define H_TOTAL_SHADOW_INDEX 12
983#define H_BLANK_END_SHADOW_INDEX 13
984#define V_TOTAL_SHADOW_INDEX 14
985#define V_ADDR_SHADOW_INDEX 15
986#define V_BLANK_SATRT_SHADOW_INDEX 16
987#define V_BLANK_END_SHADOW_INDEX 17
988#define V_SYNC_SATRT_SHADOW_INDEX 18
989#define V_SYNC_END_SHADOW_INDEX 19
990
991/* Definition Video Mode Pixel Clock (picoseconds)
992*/
993#define RES_480X640_60HZ_PIXCLOCK 39722
994#define RES_640X480_60HZ_PIXCLOCK 39722
995#define RES_640X480_75HZ_PIXCLOCK 31747
996#define RES_640X480_85HZ_PIXCLOCK 27777
997#define RES_640X480_100HZ_PIXCLOCK 23168
998#define RES_640X480_120HZ_PIXCLOCK 19081
999#define RES_720X480_60HZ_PIXCLOCK 37020
1000#define RES_720X576_60HZ_PIXCLOCK 30611
1001#define RES_800X600_60HZ_PIXCLOCK 25000
1002#define RES_800X600_75HZ_PIXCLOCK 20203
1003#define RES_800X600_85HZ_PIXCLOCK 17777
1004#define RES_800X600_100HZ_PIXCLOCK 14667
1005#define RES_800X600_120HZ_PIXCLOCK 11912
1006#define RES_800X480_60HZ_PIXCLOCK 33805
1007#define RES_848X480_60HZ_PIXCLOCK 31756
1008#define RES_856X480_60HZ_PIXCLOCK 31518
1009#define RES_1024X512_60HZ_PIXCLOCK 24218
1010#define RES_1024X600_60HZ_PIXCLOCK 20460
1011#define RES_1024X768_60HZ_PIXCLOCK 15385
1012#define RES_1024X768_75HZ_PIXCLOCK 12699
1013#define RES_1024X768_85HZ_PIXCLOCK 10582
1014#define RES_1024X768_100HZ_PIXCLOCK 8825
1015#define RES_1152X864_75HZ_PIXCLOCK 9259
1016#define RES_1280X768_60HZ_PIXCLOCK 12480
1017#define RES_1280X800_60HZ_PIXCLOCK 11994
1018#define RES_1280X960_60HZ_PIXCLOCK 9259
1019#define RES_1280X1024_60HZ_PIXCLOCK 9260
1020#define RES_1280X1024_75HZ_PIXCLOCK 7408
1021#define RES_1280X768_85HZ_PIXCLOCK 6349
1022#define RES_1440X1050_60HZ_PIXCLOCK 7993
1023#define RES_1600X1200_60HZ_PIXCLOCK 6172
1024#define RES_1600X1200_75HZ_PIXCLOCK 4938
1025#define RES_1280X720_60HZ_PIXCLOCK 13426
1026#define RES_1920X1080_60HZ_PIXCLOCK 5787
1027#define RES_1400X1050_60HZ_PIXCLOCK 8214
1028#define RES_1400X1050_75HZ_PIXCLOCK 6410
1029#define RES_1368X768_60HZ_PIXCLOCK 11647
1030#define RES_960X600_60HZ_PIXCLOCK 22099
1031#define RES_1000X600_60HZ_PIXCLOCK 20834
1032#define RES_1024X576_60HZ_PIXCLOCK 21278
1033#define RES_1088X612_60HZ_PIXCLOCK 18877
1034#define RES_1152X720_60HZ_PIXCLOCK 14981
1035#define RES_1200X720_60HZ_PIXCLOCK 14253
1036#define RES_1280X600_60HZ_PIXCLOCK 16260
1037#define RES_1280X720_50HZ_PIXCLOCK 16538
1038#define RES_1280X768_50HZ_PIXCLOCK 15342
1039#define RES_1366X768_50HZ_PIXCLOCK 14301
1040#define RES_1366X768_60HZ_PIXCLOCK 11646
1041#define RES_1360X768_60HZ_PIXCLOCK 11799
1042#define RES_1440X900_60HZ_PIXCLOCK 9390
1043#define RES_1440X900_75HZ_PIXCLOCK 7315
1044#define RES_1600X900_60HZ_PIXCLOCK 8415
1045#define RES_1600X1024_60HZ_PIXCLOCK 7315
1046#define RES_1680X1050_60HZ_PIXCLOCK 6814
1047#define RES_1680X1050_75HZ_PIXCLOCK 5348
1048#define RES_1792X1344_60HZ_PIXCLOCK 4902
1049#define RES_1856X1392_60HZ_PIXCLOCK 4577
1050#define RES_1920X1200_60HZ_PIXCLOCK 5173
1051#define RES_1920X1440_60HZ_PIXCLOCK 4274
1052#define RES_1920X1440_75HZ_PIXCLOCK 3367
1053#define RES_2048X1536_60HZ_PIXCLOCK 3742
1054
1055#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
1056#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
1057#define RES_1440X900_RB_60HZ_PIXCLOCK 11268
1058#define RES_1600X900_RB_60HZ_PIXCLOCK 10230
1059#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
1060#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
1061#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
1062
1063/* LCD display method
1064*/
1065#define LCD_EXPANDSION 0x00
1066#define LCD_CENTERING 0x01
1067
1068/* LCD mode
1069*/
1070#define LCD_OPENLDI 0x00
1071#define LCD_SPWG 0x01
1072
1073/* Define display timing
1074*/
1075struct display_timing {
1076 u16 hor_total;
1077 u16 hor_addr;
1078 u16 hor_blank_start;
1079 u16 hor_blank_end;
1080 u16 hor_sync_start;
1081 u16 hor_sync_end;
1082 u16 ver_total;
1083 u16 ver_addr;
1084 u16 ver_blank_start;
1085 u16 ver_blank_end;
1086 u16 ver_sync_start;
1087 u16 ver_sync_end;
1088};
1089
1090struct crt_mode_table {
1091 int refresh_rate;
1092 unsigned long clk;
1093 int h_sync_polarity;
1094 int v_sync_polarity;
1095 struct display_timing crtc;
1096};
1097
1098struct io_reg {
1099 int port;
1100 u8 index;
1101 u8 mask;
1102 u8 value;
1103};
1104
1105#endif /* __SHARE_H__ */
diff --git a/drivers/video/via/tbl1636.c b/drivers/video/via/tbl1636.c
new file mode 100644
index 000000000000..2d8453429d4a
--- /dev/null
+++ b/drivers/video/via/tbl1636.c
@@ -0,0 +1,71 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23struct IODATA COMMON_INIT_TBL_VT1636[] = {
24/* Index, Mask, Value */
25 /* Set panel power sequence timing */
26 {0x10, 0xC0, 0x00},
27 /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
28 {0x0B, 0xFF, 0x40},
29 /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
30 {0x0C, 0xFF, 0x31},
31 /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
32 {0x0D, 0xFF, 0x31},
33 /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
34 {0x0E, 0xFF, 0x68},
35 /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
36 {0x0F, 0xFF, 0x68},
37 /* LVDS output power up */
38 {0x09, 0xA0, 0xA0},
39 /* turn on back light */
40 {0x10, 0x33, 0x13}
41};
42
43struct IODATA DUAL_CHANNEL_ENABLE_TBL_VT1636[] = {
44/* Index, Mask, Value */
45 {0x08, 0xF0, 0xE0} /* Input Data Mode Select */
46};
47
48struct IODATA SINGLE_CHANNEL_ENABLE_TBL_VT1636[] = {
49/* Index, Mask, Value */
50 {0x08, 0xF0, 0x00} /* Input Data Mode Select */
51};
52
53struct IODATA DITHERING_ENABLE_TBL_VT1636[] = {
54/* Index, Mask, Value */
55 {0x0A, 0x70, 0x50}
56};
57
58struct IODATA DITHERING_DISABLE_TBL_VT1636[] = {
59/* Index, Mask, Value */
60 {0x0A, 0x70, 0x00}
61};
62
63struct IODATA VDD_ON_TBL_VT1636[] = {
64/* Index, Mask, Value */
65 {0x10, 0x20, 0x20}
66};
67
68struct IODATA VDD_OFF_TBL_VT1636[] = {
69/* Index, Mask, Value */
70 {0x10, 0x20, 0x00}
71};
diff --git a/drivers/video/via/tbl1636.h b/drivers/video/via/tbl1636.h
new file mode 100644
index 000000000000..d906055f1511
--- /dev/null
+++ b/drivers/video/via/tbl1636.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _TBL1636_H_
23#define _TBL1636_H_
24#include "hw.h"
25
26extern struct IODATA COMMON_INIT_TBL_VT1636[8];
27extern struct IODATA DUAL_CHANNEL_ENABLE_TBL_VT1636[1];
28extern struct IODATA SINGLE_CHANNEL_ENABLE_TBL_VT1636[1];
29extern struct IODATA DITHERING_ENABLE_TBL_VT1636[1];
30extern struct IODATA DITHERING_DISABLE_TBL_VT1636[1];
31extern struct IODATA VDD_ON_TBL_VT1636[1];
32extern struct IODATA VDD_OFF_TBL_VT1636[1];
33
34#endif /* _VIA_TBL1636_H_ */
diff --git a/drivers/video/via/tblDPASetting.c b/drivers/video/via/tblDPASetting.c
new file mode 100644
index 000000000000..0c4c8cc712f4
--- /dev/null
+++ b/drivers/video/via/tblDPASetting.c
@@ -0,0 +1,109 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23/* For VT3324: */
24struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[] = {
25 /* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */
26 {LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */
27 {LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */
28 {LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */
29 {LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */
30 {LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */
31 {LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */
32 {LCD_PANEL_ID6_1600X1200, 0x0B, 0x03} /* For 1600x1200 */
33};
34
35struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
36/* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
37 DVP1Driving, DFPHigh, DFPLow */
38/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
39 SR65, CR97, CR99 */
40 /* LCK/VCK < 30000000 will use this value */
41 {DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
42 0x00},
43 /* 30000000 < LCK/VCK < 50000000 will use this value */
44 {DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
45 0x00},
46 /* 50000000 < LCK/VCK < 70000000 will use this value */
47 {DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
48 0x00},
49 /* 70000000 < LCK/VCK < 100000000 will use this value */
50 {DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
51 0x00},
52 /* 100000000 < LCK/VCK < 15000000 will use this value */
53 {DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
54 0x00},
55 /* 15000000 < LCK/VCK will use this value */
56 {DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00,
57 0x00},
58};
59
60/* For VT3327: */
61struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[] = {
62 /* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */
63 {LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */
64 {LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */
65 {LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */
66 {LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */
67 {LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */
68 {LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */
69 {LCD_PANEL_ID6_1600X1200, 0x00, 0x00} /* For 1600x1200 */
70};
71
72struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
73/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
74 DVP1Driving, DFPHigh, DFPLow */
75/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
76 SR65, CR97, CR99 */
77/* LCK/VCK < 30000000 will use this value */
78{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
79/* 30000000 < LCK/VCK < 50000000 will use this value */
80{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
81/* 50000000 < LCK/VCK < 70000000 will use this value */
82{DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
83/* 70000000 < LCK/VCK < 100000000 will use this value */
84{DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03},
85/* 100000000 < LCK/VCK < 15000000 will use this value */
86{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02},
87/* 15000000 < LCK/VCK will use this value */
88{DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03},
89};
90
91/* For VT3364: */
92struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = {
93/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
94 DVP1Driving, DFPHigh, DFPLow */
95/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
96 SR65, CR97, CR99 */
97/* LCK/VCK < 30000000 will use this value */
98{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
99/* 30000000 < LCK/VCK < 50000000 will use this value */
100{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
101/* 50000000 < LCK/VCK < 70000000 will use this value */
102{DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
103/* 70000000 < LCK/VCK < 100000000 will use this value */
104{DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
105/* 100000000 < LCK/VCK < 15000000 will use this value */
106{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
107/* 15000000 < LCK/VCK will use this value */
108{DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08},
109};
diff --git a/drivers/video/via/tblDPASetting.h b/drivers/video/via/tblDPASetting.h
new file mode 100644
index 000000000000..b065a83481d3
--- /dev/null
+++ b/drivers/video/via/tblDPASetting.h
@@ -0,0 +1,47 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _TBLDPASETTING_H_
23#define _TBLDPASETTING_H_
24#include "global.h"
25
26#define DPA_CLK_30M 30000000
27#define DPA_CLK_50M 50000000
28#define DPA_CLK_70M 70000000
29#define DPA_CLK_100M 100000000
30#define DPA_CLK_150M 150000000
31
32enum DPA_RANGE {
33 DPA_CLK_RANGE_30M,
34 DPA_CLK_RANGE_30_50M,
35 DPA_CLK_RANGE_50_70M,
36 DPA_CLK_RANGE_70_100M,
37 DPA_CLK_RANGE_100_150M,
38 DPA_CLK_RANGE_150M
39};
40
41extern struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[7];
42extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[6];
43extern struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[7];
44extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[];
45extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[6];
46
47#endif
diff --git a/drivers/video/via/via_i2c.c b/drivers/video/via/via_i2c.c
new file mode 100644
index 000000000000..0f3ed4eb236d
--- /dev/null
+++ b/drivers/video/via/via_i2c.c
@@ -0,0 +1,177 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24static void via_i2c_setscl(void *data, int state)
25{
26 u8 val;
27 struct via_i2c_stuff *via_i2c_chan = (struct via_i2c_stuff *)data;
28
29 val = viafb_read_reg(VIASR, via_i2c_chan->i2c_port) & 0xF0;
30 if (state)
31 val |= 0x20;
32 else
33 val &= ~0x20;
34 switch (via_i2c_chan->i2c_port) {
35 case I2CPORTINDEX:
36 val |= 0x01;
37 break;
38 case GPIOPORTINDEX:
39 val |= 0x80;
40 break;
41 default:
42 DEBUG_MSG("via_i2c: specify wrong i2c port.\n");
43 }
44 viafb_write_reg(via_i2c_chan->i2c_port, VIASR, val);
45}
46
47static int via_i2c_getscl(void *data)
48{
49 struct via_i2c_stuff *via_i2c_chan = (struct via_i2c_stuff *)data;
50
51 if (viafb_read_reg(VIASR, via_i2c_chan->i2c_port) & 0x08)
52 return 1;
53 return 0;
54}
55
56static int via_i2c_getsda(void *data)
57{
58 struct via_i2c_stuff *via_i2c_chan = (struct via_i2c_stuff *)data;
59
60 if (viafb_read_reg(VIASR, via_i2c_chan->i2c_port) & 0x04)
61 return 1;
62 return 0;
63}
64
65static void via_i2c_setsda(void *data, int state)
66{
67 u8 val;
68 struct via_i2c_stuff *via_i2c_chan = (struct via_i2c_stuff *)data;
69
70 val = viafb_read_reg(VIASR, via_i2c_chan->i2c_port) & 0xF0;
71 if (state)
72 val |= 0x10;
73 else
74 val &= ~0x10;
75 switch (via_i2c_chan->i2c_port) {
76 case I2CPORTINDEX:
77 val |= 0x01;
78 break;
79 case GPIOPORTINDEX:
80 val |= 0x40;
81 break;
82 default:
83 DEBUG_MSG("via_i2c: specify wrong i2c port.\n");
84 }
85 viafb_write_reg(via_i2c_chan->i2c_port, VIASR, val);
86}
87
88int viafb_i2c_readbyte(u8 slave_addr, u8 index, u8 *pdata)
89{
90 u8 mm1[] = {0x00};
91 struct i2c_msg msgs[2];
92
93 *pdata = 0;
94 msgs[0].flags = 0;
95 msgs[1].flags = I2C_M_RD;
96 msgs[0].addr = msgs[1].addr = slave_addr / 2;
97 mm1[0] = index;
98 msgs[0].len = 1; msgs[1].len = 1;
99 msgs[0].buf = mm1; msgs[1].buf = pdata;
100 i2c_transfer(&viaparinfo->i2c_stuff.adapter, msgs, 2);
101
102 return 0;
103}
104
105int viafb_i2c_writebyte(u8 slave_addr, u8 index, u8 data)
106{
107 u8 msg[2] = { index, data };
108 struct i2c_msg msgs;
109
110 msgs.flags = 0;
111 msgs.addr = slave_addr / 2;
112 msgs.len = 2;
113 msgs.buf = msg;
114 return i2c_transfer(&viaparinfo->i2c_stuff.adapter, &msgs, 1);
115}
116
117int viafb_i2c_readbytes(u8 slave_addr, u8 index, u8 *buff, int buff_len)
118{
119 u8 mm1[] = {0x00};
120 struct i2c_msg msgs[2];
121
122 msgs[0].flags = 0;
123 msgs[1].flags = I2C_M_RD;
124 msgs[0].addr = msgs[1].addr = slave_addr / 2;
125 mm1[0] = index;
126 msgs[0].len = 1; msgs[1].len = buff_len;
127 msgs[0].buf = mm1; msgs[1].buf = buff;
128 i2c_transfer(&viaparinfo->i2c_stuff.adapter, msgs, 2);
129 return 0;
130}
131
132int viafb_create_i2c_bus(void *viapar)
133{
134 int ret;
135 struct viafb_par *par = (struct viafb_par *)viapar;
136
137 strcpy(par->i2c_stuff.adapter.name, "via_i2c");
138 par->i2c_stuff.i2c_port = 0x0;
139 par->i2c_stuff.adapter.owner = THIS_MODULE;
140 par->i2c_stuff.adapter.id = 0x01FFFF;
141 par->i2c_stuff.adapter.class = 0;
142 par->i2c_stuff.adapter.algo_data = &par->i2c_stuff.algo;
143 par->i2c_stuff.adapter.dev.parent = NULL;
144 par->i2c_stuff.algo.setsda = via_i2c_setsda;
145 par->i2c_stuff.algo.setscl = via_i2c_setscl;
146 par->i2c_stuff.algo.getsda = via_i2c_getsda;
147 par->i2c_stuff.algo.getscl = via_i2c_getscl;
148 par->i2c_stuff.algo.udelay = 40;
149 par->i2c_stuff.algo.timeout = 20;
150 par->i2c_stuff.algo.data = &par->i2c_stuff;
151
152 i2c_set_adapdata(&par->i2c_stuff.adapter, &par->i2c_stuff);
153
154 /* Raise SCL and SDA */
155 par->i2c_stuff.i2c_port = I2CPORTINDEX;
156 via_i2c_setsda(&par->i2c_stuff, 1);
157 via_i2c_setscl(&par->i2c_stuff, 1);
158
159 par->i2c_stuff.i2c_port = GPIOPORTINDEX;
160 via_i2c_setsda(&par->i2c_stuff, 1);
161 via_i2c_setscl(&par->i2c_stuff, 1);
162 udelay(20);
163
164 ret = i2c_bit_add_bus(&par->i2c_stuff.adapter);
165 if (ret == 0)
166 DEBUG_MSG("I2C bus %s registered.\n",
167 par->i2c_stuff.adapter.name);
168 else
169 DEBUG_MSG("Failed to register I2C bus %s.\n",
170 par->i2c_stuff.adapter.name);
171 return ret;
172}
173
174void viafb_delete_i2c_buss(void *par)
175{
176 i2c_del_adapter(&((struct viafb_par *)par)->i2c_stuff.adapter);
177}
diff --git a/drivers/video/via/via_i2c.h b/drivers/video/via/via_i2c.h
new file mode 100644
index 000000000000..3a13242a3152
--- /dev/null
+++ b/drivers/video/via/via_i2c.h
@@ -0,0 +1,46 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __VIA_I2C_H__
22#define __VIA_I2C_H__
23
24#include <linux/i2c.h>
25#include <linux/i2c-algo-bit.h>
26
27struct via_i2c_stuff {
28 u16 i2c_port; /* GPIO or I2C port */
29 struct i2c_adapter adapter;
30 struct i2c_algo_bit_data algo;
31};
32
33#define I2CPORT 0x3c4
34#define I2CPORTINDEX 0x31
35#define GPIOPORT 0x3C4
36#define GPIOPORTINDEX 0x2C
37#define I2C_BUS 1
38#define GPIO_BUS 2
39#define DELAYPORT 0x3C3
40
41int viafb_i2c_readbyte(u8 slave_addr, u8 index, u8 *pdata);
42int viafb_i2c_writebyte(u8 slave_addr, u8 index, u8 data);
43int viafb_i2c_readbytes(u8 slave_addr, u8 index, u8 *buff, int buff_len);
44int viafb_create_i2c_bus(void *par);
45void viafb_delete_i2c_buss(void *par);
46#endif /* __VIA_I2C_H__ */
diff --git a/drivers/video/via/via_utility.c b/drivers/video/via/via_utility.c
new file mode 100644
index 000000000000..d53c3d54ed8e
--- /dev/null
+++ b/drivers/video/via/via_utility.c
@@ -0,0 +1,253 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24void viafb_get_device_support_state(u32 *support_state)
25{
26 *support_state = CRT_Device;
27
28 if (viaparinfo->chip_info->tmds_chip_info.tmds_chip_name == VT1632_TMDS)
29 *support_state |= DVI_Device;
30
31 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name == VT1631_LVDS)
32 *support_state |= LCD_Device;
33}
34
35void viafb_get_device_connect_state(u32 *connect_state)
36{
37 bool mobile = false;
38
39 *connect_state = CRT_Device;
40
41 if (viafb_dvi_sense())
42 *connect_state |= DVI_Device;
43
44 viafb_lcd_get_mobile_state(&mobile);
45 if (mobile)
46 *connect_state |= LCD_Device;
47}
48
49bool viafb_lcd_get_support_expand_state(u32 xres, u32 yres)
50{
51 unsigned int support_state = 0;
52
53 switch (viafb_lcd_panel_id) {
54 case LCD_PANEL_ID0_640X480:
55 if ((xres < 640) && (yres < 480))
56 support_state = true;
57 break;
58
59 case LCD_PANEL_ID1_800X600:
60 if ((xres < 800) && (yres < 600))
61 support_state = true;
62 break;
63
64 case LCD_PANEL_ID2_1024X768:
65 if ((xres < 1024) && (yres < 768))
66 support_state = true;
67 break;
68
69 case LCD_PANEL_ID3_1280X768:
70 if ((xres < 1280) && (yres < 768))
71 support_state = true;
72 break;
73
74 case LCD_PANEL_ID4_1280X1024:
75 if ((xres < 1280) && (yres < 1024))
76 support_state = true;
77 break;
78
79 case LCD_PANEL_ID5_1400X1050:
80 if ((xres < 1400) && (yres < 1050))
81 support_state = true;
82 break;
83
84 case LCD_PANEL_ID6_1600X1200:
85 if ((xres < 1600) && (yres < 1200))
86 support_state = true;
87 break;
88
89 case LCD_PANEL_ID7_1366X768:
90 if ((xres < 1366) && (yres < 768))
91 support_state = true;
92 break;
93
94 case LCD_PANEL_ID8_1024X600:
95 if ((xres < 1024) && (yres < 600))
96 support_state = true;
97 break;
98
99 case LCD_PANEL_ID9_1280X800:
100 if ((xres < 1280) && (yres < 800))
101 support_state = true;
102 break;
103
104 case LCD_PANEL_IDA_800X480:
105 if ((xres < 800) && (yres < 480))
106 support_state = true;
107 break;
108
109 case LCD_PANEL_IDB_1360X768:
110 if ((xres < 1360) && (yres < 768))
111 support_state = true;
112 break;
113
114 case LCD_PANEL_IDC_480X640:
115 if ((xres < 480) && (yres < 640))
116 support_state = true;
117 break;
118
119 default:
120 support_state = false;
121 break;
122 }
123
124 return support_state;
125}
126
127/*====================================================================*/
128/* Gamma Function Implementation*/
129/*====================================================================*/
130
131void viafb_set_gamma_table(int bpp, unsigned int *gamma_table)
132{
133 int i, sr1a;
134 int active_device_amount = 0;
135 int device_status = viafb_DeviceStatus;
136
137 for (i = 0; i < sizeof(viafb_DeviceStatus) * 8; i++) {
138 if (device_status & 1)
139 active_device_amount++;
140 device_status >>= 1;
141 }
142
143 /* 8 bpp mode can't adjust gamma */
144 if (bpp == 8)
145 return ;
146
147 /* Enable Gamma */
148 switch (viaparinfo->chip_info->gfx_chip_name) {
149 case UNICHROME_CLE266:
150 case UNICHROME_K400:
151 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
152 break;
153
154 case UNICHROME_K800:
155 case UNICHROME_PM800:
156 case UNICHROME_CN700:
157 case UNICHROME_CX700:
158 case UNICHROME_K8M890:
159 case UNICHROME_P4M890:
160 case UNICHROME_P4M900:
161 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
162 break;
163 }
164 sr1a = (unsigned int)viafb_read_reg(VIASR, SR1A);
165 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
166
167 /* Fill IGA1 Gamma Table */
168 outb(0, LUT_INDEX_WRITE);
169 for (i = 0; i < 256; i++) {
170 outb(gamma_table[i] >> 16, LUT_DATA);
171 outb(gamma_table[i] >> 8 & 0xFF, LUT_DATA);
172 outb(gamma_table[i] & 0xFF, LUT_DATA);
173 }
174
175 /* If adjust Gamma value in SAMM, fill IGA1,
176 IGA2 Gamma table simultanous. */
177 /* Switch to IGA2 Gamma Table */
178 if ((active_device_amount > 1) &&
179 !((viaparinfo->chip_info->gfx_chip_name ==
180 UNICHROME_CLE266) &&
181 (viaparinfo->chip_info->gfx_chip_revision < 15))) {
182 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
183 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1);
184
185 /* Fill IGA2 Gamma Table */
186 outb(0, LUT_INDEX_WRITE);
187 for (i = 0; i < 256; i++) {
188 outb(gamma_table[i] >> 16, LUT_DATA);
189 outb(gamma_table[i] >> 8 & 0xFF, LUT_DATA);
190 outb(gamma_table[i] & 0xFF, LUT_DATA);
191 }
192 }
193 viafb_write_reg(SR1A, VIASR, sr1a);
194}
195
196void viafb_get_gamma_table(unsigned int *gamma_table)
197{
198 unsigned char color_r, color_g, color_b;
199 unsigned char sr1a = 0;
200 int i;
201
202 /* Enable Gamma */
203 switch (viaparinfo->chip_info->gfx_chip_name) {
204 case UNICHROME_CLE266:
205 case UNICHROME_K400:
206 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
207 break;
208
209 case UNICHROME_K800:
210 case UNICHROME_PM800:
211 case UNICHROME_CN700:
212 case UNICHROME_CX700:
213 case UNICHROME_K8M890:
214 case UNICHROME_P4M890:
215 case UNICHROME_P4M900:
216 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
217 break;
218 }
219 sr1a = viafb_read_reg(VIASR, SR1A);
220 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
221
222 /* Reading gamma table to get color value */
223 outb(0, LUT_INDEX_READ);
224 for (i = 0; i < 256; i++) {
225 color_r = inb(LUT_DATA);
226 color_g = inb(LUT_DATA);
227 color_b = inb(LUT_DATA);
228 gamma_table[i] =
229 ((((u32) color_r) << 16) |
230 (((u16) color_g) << 8)) | color_b;
231 }
232 viafb_write_reg(SR1A, VIASR, sr1a);
233}
234
235void viafb_get_gamma_support_state(int bpp, unsigned int *support_state)
236{
237 if (bpp == 8)
238 *support_state = None_Device;
239 else
240 *support_state = CRT_Device | DVI_Device | LCD_Device;
241}
242
243int viafb_input_parameter_converter(int parameter_value)
244{
245 int result;
246
247 if (parameter_value >= 1 && parameter_value <= 9)
248 result = 1 << (parameter_value - 1);
249 else
250 result = 1;
251
252 return result;
253}
diff --git a/drivers/video/via/via_utility.h b/drivers/video/via/via_utility.h
new file mode 100644
index 000000000000..2fd455202ebd
--- /dev/null
+++ b/drivers/video/via/via_utility.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __VIAUTILITY_H__
22#define __VIAUTILITY_H__
23
24/* These functions are used to get infomation about device's state */
25void viafb_get_device_support_state(u32 *support_state);
26void viafb_get_device_connect_state(u32 *connect_state);
27bool viafb_lcd_get_support_expand_state(u32 xres, u32 yres);
28
29/* These function are used to access gamma table */
30void viafb_set_gamma_table(int bpp, unsigned int *gamma_table);
31void viafb_get_gamma_table(unsigned int *gamma_table);
32void viafb_get_gamma_support_state(int bpp, unsigned int *support_state);
33int viafb_input_parameter_converter(int parameter_value);
34
35#endif /* __VIAUTILITY_H__ */
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
new file mode 100644
index 000000000000..0132eae06f55
--- /dev/null
+++ b/drivers/video/via/viafbdev.c
@@ -0,0 +1,2571 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include <linux/module.h>
23#define _MASTER_FILE
24
25#include "global.h"
26
27static int MAX_CURS = 32;
28static struct fb_var_screeninfo default_var;
29static char *viafb_name = "Via";
30static u32 pseudo_pal[17];
31
32/* video mode */
33static char *viafb_mode = "640x480";
34static char *viafb_mode1 = "640x480";
35static int viafb_resMode = VIA_RES_640X480;
36
37/* Added for specifying active devices.*/
38char *viafb_active_dev = "";
39
40/* Added for specifying video on devices.*/
41char *viafb_video_dev = "";
42
43/*Added for specify lcd output port*/
44char *viafb_lcd_port = "";
45char *viafb_dvi_port = "";
46
47static void viafb_set_device(struct device_t active_dev);
48static int apply_device_setting(struct viafb_ioctl_setting setting_info,
49 struct fb_info *info);
50static void apply_second_mode_setting(struct fb_var_screeninfo
51 *sec_var);
52static void retrieve_device_setting(struct viafb_ioctl_setting
53 *setting_info);
54static void viafb_set_video_device(u32 video_dev_info);
55static void viafb_get_video_device(u32 *video_dev_info);
56
57/* Mode information */
58static const struct viafb_modeinfo viafb_modentry[] = {
59 {480, 640, VIA_RES_480X640, "480x640"},
60 {640, 480, VIA_RES_640X480, "640x480"},
61 {800, 480, VIA_RES_800X480, "800x480"},
62 {800, 600, VIA_RES_800X600, "800x600"},
63 {1024, 768, VIA_RES_1024X768, "1024x768"},
64 {1152, 864, VIA_RES_1152X864, "1152x864"},
65 {1280, 1024, VIA_RES_1280X1024, "1280x1024"},
66 {1600, 1200, VIA_RES_1600X1200, "1600x1200"},
67 {1440, 1050, VIA_RES_1440X1050, "1440x1050"},
68 {1280, 768, VIA_RES_1280X768, "1280x768"},
69 {1280, 800, VIA_RES_1280X800, "1280x800"},
70 {1280, 960, VIA_RES_1280X960, "1280x960"},
71 {1920, 1440, VIA_RES_1920X1440, "1920x1440"},
72 {848, 480, VIA_RES_848X480, "848x480"},
73 {1400, 1050, VIA_RES_1400X1050, "1400x1050"},
74 {720, 480, VIA_RES_720X480, "720x480"},
75 {720, 576, VIA_RES_720X576, "720x576"},
76 {1024, 512, VIA_RES_1024X512, "1024x512"},
77 {1024, 576, VIA_RES_1024X576, "1024x576"},
78 {1024, 600, VIA_RES_1024X600, "1024x600"},
79 {1280, 720, VIA_RES_1280X720, "1280x720"},
80 {1920, 1080, VIA_RES_1920X1080, "1920x1080"},
81 {1366, 768, VIA_RES_1368X768, "1368x768"},
82 {1680, 1050, VIA_RES_1680X1050, "1680x1050"},
83 {960, 600, VIA_RES_960X600, "960x600"},
84 {1000, 600, VIA_RES_1000X600, "1000x600"},
85 {1024, 576, VIA_RES_1024X576, "1024x576"},
86 {1024, 600, VIA_RES_1024X600, "1024x600"},
87 {1088, 612, VIA_RES_1088X612, "1088x612"},
88 {1152, 720, VIA_RES_1152X720, "1152x720"},
89 {1200, 720, VIA_RES_1200X720, "1200x720"},
90 {1280, 600, VIA_RES_1280X600, "1280x600"},
91 {1360, 768, VIA_RES_1360X768, "1360x768"},
92 {1440, 900, VIA_RES_1440X900, "1440x900"},
93 {1600, 900, VIA_RES_1600X900, "1600x900"},
94 {1600, 1024, VIA_RES_1600X1024, "1600x1024"},
95 {1792, 1344, VIA_RES_1792X1344, "1792x1344"},
96 {1856, 1392, VIA_RES_1856X1392, "1856x1392"},
97 {1920, 1200, VIA_RES_1920X1200, "1920x1200"},
98 {2048, 1536, VIA_RES_2048X1536, "2048x1536"},
99 {0, 0, VIA_RES_INVALID, "640x480"}
100};
101
102static struct fb_ops viafb_ops;
103
104static int viafb_update_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
105{
106 struct viafb_par *ppar;
107 ppar = info->par;
108
109 DEBUG_MSG(KERN_INFO "viafb_update_fix!\n");
110
111 fix->visual =
112 ppar->bpp == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
113 fix->line_length = ppar->linelength;
114
115 return 0;
116}
117
118
119static void viafb_setup_fixinfo(struct fb_fix_screeninfo *fix,
120 struct viafb_par *viaparinfo)
121{
122 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
123 strcpy(fix->id, viafb_name);
124
125 fix->smem_start = viaparinfo->fbmem;
126 fix->smem_len = viaparinfo->fbmem_free;
127 fix->mmio_start = viaparinfo->mmio_base;
128 fix->mmio_len = viaparinfo->mmio_len;
129
130 fix->type = FB_TYPE_PACKED_PIXELS;
131 fix->type_aux = 0;
132
133 fix->xpanstep = fix->ywrapstep = 0;
134 fix->ypanstep = 1;
135
136 /* Just tell the accel name */
137 viafbinfo->fix.accel = FB_ACCEL_VIA_UNICHROME;
138}
139static int viafb_open(struct fb_info *info, int user)
140{
141 DEBUG_MSG(KERN_INFO "viafb_open!\n");
142 return 0;
143}
144
145static int viafb_release(struct fb_info *info, int user)
146{
147 DEBUG_MSG(KERN_INFO "viafb_release!\n");
148 return 0;
149}
150
151static void viafb_update_viafb_par(struct fb_info *info)
152{
153 struct viafb_par *ppar;
154
155 ppar = info->par;
156 ppar->bpp = info->var.bits_per_pixel;
157 ppar->linelength = ((info->var.xres_virtual + 7) & ~7) * ppar->bpp / 8;
158 ppar->hres = info->var.xres;
159 ppar->vres = info->var.yres;
160 ppar->xoffset = info->var.xoffset;
161 ppar->yoffset = info->var.yoffset;
162}
163
164static int viafb_check_var(struct fb_var_screeninfo *var,
165 struct fb_info *info)
166{
167 int vmode_index, htotal, vtotal;
168 struct viafb_par *ppar;
169 u32 long_refresh;
170 struct viafb_par *p_viafb_par;
171 ppar = info->par;
172
173
174 DEBUG_MSG(KERN_INFO "viafb_check_var!\n");
175 /* Sanity check */
176 /* HW neither support interlacte nor double-scaned mode */
177 if (var->vmode & FB_VMODE_INTERLACED || var->vmode & FB_VMODE_DOUBLE)
178 return -EINVAL;
179
180 vmode_index = viafb_get_mode_index(var->xres, var->yres, 0);
181 if (vmode_index == VIA_RES_INVALID) {
182 DEBUG_MSG(KERN_INFO
183 "viafb: Mode %dx%dx%d not supported!!\n",
184 var->xres, var->yres, var->bits_per_pixel);
185 return -EINVAL;
186 }
187
188 if (24 == var->bits_per_pixel)
189 var->bits_per_pixel = 32;
190
191 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
192 var->bits_per_pixel != 32)
193 return -EINVAL;
194
195 if ((var->xres_virtual * (var->bits_per_pixel >> 3)) & 0x1F)
196 /*32 pixel alignment */
197 var->xres_virtual = (var->xres_virtual + 31) & ~31;
198 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
199 ppar->memsize)
200 return -EINVAL;
201
202 /* Based on var passed in to calculate the refresh,
203 * because our driver use some modes special.
204 */
205 htotal = var->xres + var->left_margin +
206 var->right_margin + var->hsync_len;
207 vtotal = var->yres + var->upper_margin +
208 var->lower_margin + var->vsync_len;
209 long_refresh = 1000000000UL / var->pixclock * 1000;
210 long_refresh /= (htotal * vtotal);
211
212 viafb_refresh = viafb_get_refresh(var->xres, var->yres, long_refresh);
213
214 /* Adjust var according to our driver's own table */
215 viafb_fill_var_timing_info(var, viafb_refresh, vmode_index);
216
217 /* This is indeed a patch for VT3353 */
218 if (!info->par)
219 return -1;
220 p_viafb_par = (struct viafb_par *)info->par;
221 if (p_viafb_par->chip_info->gfx_chip_name == UNICHROME_VX800)
222 var->accel_flags = 0;
223
224 return 0;
225}
226
227static int viafb_set_par(struct fb_info *info)
228{
229 int vmode_index;
230 int vmode_index1 = 0;
231 DEBUG_MSG(KERN_INFO "viafb_set_par!\n");
232
233 viafb_update_device_setting(info->var.xres, info->var.yres,
234 info->var.bits_per_pixel, viafb_refresh, 0);
235
236 vmode_index = viafb_get_mode_index(info->var.xres, info->var.yres, 0);
237
238 if (viafb_SAMM_ON == 1) {
239 DEBUG_MSG(KERN_INFO
240 "viafb_second_xres = %d, viafb_second_yres = %d, bpp = %d\n",
241 viafb_second_xres, viafb_second_yres, viafb_bpp1);
242 vmode_index1 = viafb_get_mode_index(viafb_second_xres,
243 viafb_second_yres, 1);
244 DEBUG_MSG(KERN_INFO "->viafb_SAMM_ON: index=%d\n",
245 vmode_index1);
246
247 viafb_update_device_setting(viafb_second_xres,
248 viafb_second_yres, viafb_bpp1, viafb_refresh1, 1);
249 }
250
251 if (vmode_index != VIA_RES_INVALID) {
252 viafb_setmode(vmode_index, info->var.xres, info->var.yres,
253 info->var.bits_per_pixel, vmode_index1,
254 viafb_second_xres, viafb_second_yres, viafb_bpp1);
255
256 /*We should set memory offset according virtual_x */
257 /*Fix me:put this function into viafb_setmode */
258 viafb_memory_pitch_patch(info);
259
260 /* Update ***fb_par information */
261 viafb_update_viafb_par(info);
262
263 /* Update other fixed information */
264 viafb_update_fix(&info->fix, info);
265 viafb_bpp = info->var.bits_per_pixel;
266 /* Update viafb_accel, it is necessary to our 2D accelerate */
267 viafb_accel = info->var.accel_flags;
268
269 if (viafb_accel)
270 viafb_set_2d_color_depth(info->var.bits_per_pixel);
271 }
272
273 return 0;
274}
275
276/* Set one color register */
277static int viafb_setcolreg(unsigned regno, unsigned red, unsigned green,
278unsigned blue, unsigned transp, struct fb_info *info)
279{
280 u8 sr1a, sr1b, cr67, cr6a, rev = 0, shift = 10;
281 unsigned cmap_entries = (info->var.bits_per_pixel == 8) ? 256 : 16;
282 DEBUG_MSG(KERN_INFO "viafb_setcolreg!\n");
283 if (regno >= cmap_entries)
284 return 1;
285 if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name) {
286 /*
287 * Read PCI bus 0,dev 0,function 0,index 0xF6 to get chip rev.
288 */
289 outl(0x80000000 | (0xf6 & ~3), (unsigned long)0xCF8);
290 rev = (inl((unsigned long)0xCFC) >> ((0xf6 & 3) * 8)) & 0xff;
291 }
292 switch (info->var.bits_per_pixel) {
293 case 8:
294 outb(0x1A, 0x3C4);
295 sr1a = inb(0x3C5);
296 outb(0x1B, 0x3C4);
297 sr1b = inb(0x3C5);
298 outb(0x67, 0x3D4);
299 cr67 = inb(0x3D5);
300 outb(0x6A, 0x3D4);
301 cr6a = inb(0x3D5);
302
303 /* Map the 3C6/7/8/9 to the IGA2 */
304 outb(0x1A, 0x3C4);
305 outb(sr1a | 0x01, 0x3C5);
306 /* Second Display Engine colck always on */
307 outb(0x1B, 0x3C4);
308 outb(sr1b | 0x80, 0x3C5);
309 /* Second Display Color Depth 8 */
310 outb(0x67, 0x3D4);
311 outb(cr67 & 0x3F, 0x3D5);
312 outb(0x6A, 0x3D4);
313 /* Second Display Channel Reset CR6A[6]) */
314 outb(cr6a & 0xBF, 0x3D5);
315 /* Second Display Channel Enable CR6A[7] */
316 outb(cr6a | 0x80, 0x3D5);
317 /* Second Display Channel stop reset) */
318 outb(cr6a | 0x40, 0x3D5);
319
320 /* Bit mask of palette */
321 outb(0xFF, 0x3c6);
322 /* Write one register of IGA2 */
323 outb(regno, 0x3C8);
324 if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name &&
325 rev >= 15) {
326 shift = 8;
327 viafb_write_reg_mask(CR6A, VIACR, BIT5, BIT5);
328 viafb_write_reg_mask(SR15, VIASR, BIT7, BIT7);
329 } else {
330 shift = 10;
331 viafb_write_reg_mask(CR6A, VIACR, 0, BIT5);
332 viafb_write_reg_mask(SR15, VIASR, 0, BIT7);
333 }
334 outb(red >> shift, 0x3C9);
335 outb(green >> shift, 0x3C9);
336 outb(blue >> shift, 0x3C9);
337
338 /* Map the 3C6/7/8/9 to the IGA1 */
339 outb(0x1A, 0x3C4);
340 outb(sr1a & 0xFE, 0x3C5);
341 /* Bit mask of palette */
342 outb(0xFF, 0x3c6);
343 /* Write one register of IGA1 */
344 outb(regno, 0x3C8);
345 outb(red >> shift, 0x3C9);
346 outb(green >> shift, 0x3C9);
347 outb(blue >> shift, 0x3C9);
348
349 outb(0x1A, 0x3C4);
350 outb(sr1a, 0x3C5);
351 outb(0x1B, 0x3C4);
352 outb(sr1b, 0x3C5);
353 outb(0x67, 0x3D4);
354 outb(cr67, 0x3D5);
355 outb(0x6A, 0x3D4);
356 outb(cr6a, 0x3D5);
357 break;
358 case 16:
359 ((u32 *) info->pseudo_palette)[regno] = (red & 0xF800) |
360 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
361 break;
362 case 32:
363 ((u32 *) info->pseudo_palette)[regno] =
364 ((transp & 0xFF00) << 16) |
365 ((red & 0xFF00) << 8) |
366 ((green & 0xFF00)) | ((blue & 0xFF00) >> 8);
367 break;
368 }
369
370 return 0;
371
372}
373
374/*CALLED BY: fb_set_cmap */
375/* fb_set_var, pass 256 colors */
376/*CALLED BY: fb_set_cmap */
377/* fbcon_set_palette, pass 16 colors */
378static int viafb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
379{
380 u32 len = cmap->len;
381 u32 i;
382 u16 *pred = cmap->red;
383 u16 *pgreen = cmap->green;
384 u16 *pblue = cmap->blue;
385 u16 *ptransp = cmap->transp;
386 u8 sr1a, sr1b, cr67, cr6a, rev = 0, shift = 10;
387 if (len > 256)
388 return 1;
389 if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name) {
390 /*
391 * Read PCI bus 0, dev 0, function 0, index 0xF6 to get chip
392 * rev.
393 */
394 outl(0x80000000 | (0xf6 & ~3), (unsigned long)0xCF8);
395 rev = (inl((unsigned long)0xCFC) >> ((0xf6 & 3) * 8)) & 0xff;
396 }
397 switch (info->var.bits_per_pixel) {
398 case 8:
399 outb(0x1A, 0x3C4);
400 sr1a = inb(0x3C5);
401 outb(0x1B, 0x3C4);
402 sr1b = inb(0x3C5);
403 outb(0x67, 0x3D4);
404 cr67 = inb(0x3D5);
405 outb(0x6A, 0x3D4);
406 cr6a = inb(0x3D5);
407 /* Map the 3C6/7/8/9 to the IGA2 */
408 outb(0x1A, 0x3C4);
409 outb(sr1a | 0x01, 0x3C5);
410 outb(0x1B, 0x3C4);
411 /* Second Display Engine colck always on */
412 outb(sr1b | 0x80, 0x3C5);
413 outb(0x67, 0x3D4);
414 /* Second Display Color Depth 8 */
415 outb(cr67 & 0x3F, 0x3D5);
416 outb(0x6A, 0x3D4);
417 /* Second Display Channel Reset CR6A[6]) */
418 outb(cr6a & 0xBF, 0x3D5);
419 /* Second Display Channel Enable CR6A[7] */
420 outb(cr6a | 0x80, 0x3D5);
421 /* Second Display Channel stop reset) */
422 outb(cr6a | 0xC0, 0x3D5);
423
424 /* Bit mask of palette */
425 outb(0xFF, 0x3c6);
426 outb(0x00, 0x3C8);
427 if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name &&
428 rev >= 15) {
429 shift = 8;
430 viafb_write_reg_mask(CR6A, VIACR, BIT5, BIT5);
431 viafb_write_reg_mask(SR15, VIASR, BIT7, BIT7);
432 } else {
433 shift = 10;
434 viafb_write_reg_mask(CR6A, VIACR, 0, BIT5);
435 viafb_write_reg_mask(SR15, VIASR, 0, BIT7);
436 }
437 for (i = 0; i < len; i++) {
438 outb((*(pred + i)) >> shift, 0x3C9);
439 outb((*(pgreen + i)) >> shift, 0x3C9);
440 outb((*(pblue + i)) >> shift, 0x3C9);
441 }
442
443 outb(0x1A, 0x3C4);
444 /* Map the 3C6/7/8/9 to the IGA1 */
445 outb(sr1a & 0xFE, 0x3C5);
446 /* Bit mask of palette */
447 outb(0xFF, 0x3c6);
448 outb(0x00, 0x3C8);
449 for (i = 0; i < len; i++) {
450 outb((*(pred + i)) >> shift, 0x3C9);
451 outb((*(pgreen + i)) >> shift, 0x3C9);
452 outb((*(pblue + i)) >> shift, 0x3C9);
453 }
454
455 outb(0x1A, 0x3C4);
456 outb(sr1a, 0x3C5);
457 outb(0x1B, 0x3C4);
458 outb(sr1b, 0x3C5);
459 outb(0x67, 0x3D4);
460 outb(cr67, 0x3D5);
461 outb(0x6A, 0x3D4);
462 outb(cr6a, 0x3D5);
463 break;
464 case 16:
465 if (len > 17)
466 return 0; /* Because static u32 pseudo_pal[17]; */
467 for (i = 0; i < len; i++)
468 ((u32 *) info->pseudo_palette)[i] =
469 (*(pred + i) & 0xF800) |
470 ((*(pgreen + i) & 0xFC00) >> 5) |
471 ((*(pblue + i) & 0xF800) >> 11);
472 break;
473 case 32:
474 if (len > 17)
475 return 0;
476 if (ptransp) {
477 for (i = 0; i < len; i++)
478 ((u32 *) info->pseudo_palette)[i] =
479 ((*(ptransp + i) & 0xFF00) << 16) |
480 ((*(pred + i) & 0xFF00) << 8) |
481 ((*(pgreen + i) & 0xFF00)) |
482 ((*(pblue + i) & 0xFF00) >> 8);
483 } else {
484 for (i = 0; i < len; i++)
485 ((u32 *) info->pseudo_palette)[i] =
486 0x00000000 |
487 ((*(pred + i) & 0xFF00) << 8) |
488 ((*(pgreen + i) & 0xFF00)) |
489 ((*(pblue + i) & 0xFF00) >> 8);
490 }
491 break;
492 }
493 return 0;
494}
495
496static int viafb_pan_display(struct fb_var_screeninfo *var,
497 struct fb_info *info)
498{
499 unsigned int offset;
500
501 DEBUG_MSG(KERN_INFO "viafb_pan_display!\n");
502
503 offset = (var->xoffset + (var->yoffset * var->xres_virtual)) *
504 var->bits_per_pixel / 16;
505
506 DEBUG_MSG(KERN_INFO "\nviafb_pan_display,offset =%d ", offset);
507
508 viafb_write_reg_mask(0x48, 0x3d4, ((offset >> 24) & 0x3), 0x3);
509 viafb_write_reg_mask(0x34, 0x3d4, ((offset >> 16) & 0xff), 0xff);
510 viafb_write_reg_mask(0x0c, 0x3d4, ((offset >> 8) & 0xff), 0xff);
511 viafb_write_reg_mask(0x0d, 0x3d4, (offset & 0xff), 0xff);
512
513 return 0;
514}
515
516static int viafb_blank(int blank_mode, struct fb_info *info)
517{
518 DEBUG_MSG(KERN_INFO "viafb_blank!\n");
519 /* clear DPMS setting */
520
521 switch (blank_mode) {
522 case FB_BLANK_UNBLANK:
523 /* Screen: On, HSync: On, VSync: On */
524 /* control CRT monitor power management */
525 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
526 break;
527 case FB_BLANK_HSYNC_SUSPEND:
528 /* Screen: Off, HSync: Off, VSync: On */
529 /* control CRT monitor power management */
530 viafb_write_reg_mask(CR36, VIACR, 0x10, BIT4 + BIT5);
531 break;
532 case FB_BLANK_VSYNC_SUSPEND:
533 /* Screen: Off, HSync: On, VSync: Off */
534 /* control CRT monitor power management */
535 viafb_write_reg_mask(CR36, VIACR, 0x20, BIT4 + BIT5);
536 break;
537 case FB_BLANK_POWERDOWN:
538 /* Screen: Off, HSync: Off, VSync: Off */
539 /* control CRT monitor power management */
540 viafb_write_reg_mask(CR36, VIACR, 0x30, BIT4 + BIT5);
541 break;
542 }
543
544 return 0;
545}
546
547static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
548{
549 struct viafb_ioctl_mode viamode;
550 struct viafb_ioctl_samm viasamm;
551 struct viafb_driver_version driver_version;
552 struct fb_var_screeninfo sec_var;
553 struct _panel_size_pos_info panel_pos_size_para;
554 u32 state_info = 0;
555 u32 viainfo_size = sizeof(struct viafb_ioctl_info);
556 u32 *viafb_gamma_table;
557 char driver_name[] = "viafb";
558
559 u32 __user *argp = (u32 __user *) arg;
560 u32 gpu32;
561 u32 video_dev_info = 0;
562 struct viafb_ioctl_setting viafb_setting = {};
563 struct device_t active_dev = {};
564
565 DEBUG_MSG(KERN_INFO "viafb_ioctl: 0x%X !!\n", cmd);
566
567 switch (cmd) {
568 case VIAFB_GET_CHIP_INFO:
569 if (copy_to_user(argp, viaparinfo->chip_info,
570 sizeof(struct chip_information)))
571 return -EFAULT;
572 break;
573 case VIAFB_GET_INFO_SIZE:
574 return put_user(viainfo_size, argp);
575 case VIAFB_GET_INFO:
576 return viafb_ioctl_get_viafb_info(arg);
577 case VIAFB_HOTPLUG:
578 return put_user(viafb_ioctl_hotplug(info->var.xres,
579 info->var.yres,
580 info->var.bits_per_pixel), argp);
581 case VIAFB_SET_HOTPLUG_FLAG:
582 if (copy_from_user(&gpu32, argp, sizeof(gpu32)))
583 return -EFAULT;
584 viafb_hotplug = (gpu32) ? 1 : 0;
585 break;
586 case VIAFB_GET_RESOLUTION:
587 viamode.xres = (u32) viafb_hotplug_Xres;
588 viamode.yres = (u32) viafb_hotplug_Yres;
589 viamode.refresh = (u32) viafb_hotplug_refresh;
590 viamode.bpp = (u32) viafb_hotplug_bpp;
591 if (viafb_SAMM_ON == 1) {
592 viamode.xres_sec = viafb_second_xres;
593 viamode.yres_sec = viafb_second_yres;
594 viamode.virtual_xres_sec = viafb_second_virtual_xres;
595 viamode.virtual_yres_sec = viafb_second_virtual_yres;
596 viamode.refresh_sec = viafb_refresh1;
597 viamode.bpp_sec = viafb_bpp1;
598 } else {
599 viamode.xres_sec = 0;
600 viamode.yres_sec = 0;
601 viamode.virtual_xres_sec = 0;
602 viamode.virtual_yres_sec = 0;
603 viamode.refresh_sec = 0;
604 viamode.bpp_sec = 0;
605 }
606 if (copy_to_user(argp, &viamode, sizeof(viamode)))
607 return -EFAULT;
608 break;
609 case VIAFB_GET_SAMM_INFO:
610 viasamm.samm_status = viafb_SAMM_ON;
611
612 if (viafb_SAMM_ON == 1) {
613 if (viafb_dual_fb) {
614 viasamm.size_prim = viaparinfo->fbmem_free;
615 viasamm.size_sec = viaparinfo1->fbmem_free;
616 } else {
617 if (viafb_second_size) {
618 viasamm.size_prim =
619 viaparinfo->fbmem_free -
620 viafb_second_size * 1024 * 1024;
621 viasamm.size_sec =
622 viafb_second_size * 1024 * 1024;
623 } else {
624 viasamm.size_prim =
625 viaparinfo->fbmem_free >> 1;
626 viasamm.size_sec =
627 (viaparinfo->fbmem_free >> 1);
628 }
629 }
630 viasamm.mem_base = viaparinfo->fbmem;
631 viasamm.offset_sec = viafb_second_offset;
632 } else {
633 viasamm.size_prim =
634 viaparinfo->memsize - viaparinfo->fbmem_used;
635 viasamm.size_sec = 0;
636 viasamm.mem_base = viaparinfo->fbmem;
637 viasamm.offset_sec = 0;
638 }
639
640 if (copy_to_user(argp, &viasamm, sizeof(viasamm)))
641 return -EFAULT;
642
643 break;
644 case VIAFB_TURN_ON_OUTPUT_DEVICE:
645 if (copy_from_user(&gpu32, argp, sizeof(gpu32)))
646 return -EFAULT;
647 if (gpu32 & CRT_Device)
648 viafb_crt_enable();
649 if (gpu32 & DVI_Device)
650 viafb_dvi_enable();
651 if (gpu32 & LCD_Device)
652 viafb_lcd_enable();
653 break;
654 case VIAFB_TURN_OFF_OUTPUT_DEVICE:
655 if (copy_from_user(&gpu32, argp, sizeof(gpu32)))
656 return -EFAULT;
657 if (gpu32 & CRT_Device)
658 viafb_crt_disable();
659 if (gpu32 & DVI_Device)
660 viafb_dvi_disable();
661 if (gpu32 & LCD_Device)
662 viafb_lcd_disable();
663 break;
664 case VIAFB_SET_DEVICE:
665 if (copy_from_user(&active_dev, (void *)argp,
666 sizeof(active_dev)))
667 return -EFAULT;
668 viafb_set_device(active_dev);
669 viafb_set_par(info);
670 break;
671 case VIAFB_GET_DEVICE:
672 active_dev.crt = viafb_CRT_ON;
673 active_dev.dvi = viafb_DVI_ON;
674 active_dev.lcd = viafb_LCD_ON;
675 active_dev.samm = viafb_SAMM_ON;
676 active_dev.primary_dev = viafb_primary_dev;
677
678 active_dev.lcd_dsp_cent = viafb_lcd_dsp_method;
679 active_dev.lcd_panel_id = viafb_lcd_panel_id;
680 active_dev.lcd_mode = viafb_lcd_mode;
681
682 active_dev.xres = viafb_hotplug_Xres;
683 active_dev.yres = viafb_hotplug_Yres;
684
685 active_dev.xres1 = viafb_second_xres;
686 active_dev.yres1 = viafb_second_yres;
687
688 active_dev.bpp = viafb_bpp;
689 active_dev.bpp1 = viafb_bpp1;
690 active_dev.refresh = viafb_refresh;
691 active_dev.refresh1 = viafb_refresh1;
692
693 active_dev.epia_dvi = viafb_platform_epia_dvi;
694 active_dev.lcd_dual_edge = viafb_device_lcd_dualedge;
695 active_dev.bus_width = viafb_bus_width;
696
697 if (copy_to_user(argp, &active_dev, sizeof(active_dev)))
698 return -EFAULT;
699 break;
700
701 case VIAFB_GET_DRIVER_VERSION:
702 driver_version.iMajorNum = VERSION_MAJOR;
703 driver_version.iKernelNum = VERSION_KERNEL;
704 driver_version.iOSNum = VERSION_OS;
705 driver_version.iMinorNum = VERSION_MINOR;
706
707 if (copy_to_user(argp, &driver_version,
708 sizeof(driver_version)))
709 return -EFAULT;
710
711 break;
712
713 case VIAFB_SET_DEVICE_INFO:
714 if (copy_from_user(&viafb_setting,
715 argp, sizeof(viafb_setting)))
716 return -EFAULT;
717 if (apply_device_setting(viafb_setting, info) < 0)
718 return -EINVAL;
719
720 break;
721
722 case VIAFB_SET_SECOND_MODE:
723 if (copy_from_user(&sec_var, argp, sizeof(sec_var)))
724 return -EFAULT;
725 apply_second_mode_setting(&sec_var);
726 break;
727
728 case VIAFB_GET_DEVICE_INFO:
729
730 retrieve_device_setting(&viafb_setting);
731
732 if (copy_to_user(argp, &viafb_setting, sizeof(viafb_setting)))
733 return -EFAULT;
734
735 break;
736
737 case VIAFB_GET_DEVICE_SUPPORT:
738 viafb_get_device_support_state(&state_info);
739 if (put_user(state_info, argp))
740 return -EFAULT;
741 break;
742
743 case VIAFB_GET_DEVICE_CONNECT:
744 viafb_get_device_connect_state(&state_info);
745 if (put_user(state_info, argp))
746 return -EFAULT;
747 break;
748
749 case VIAFB_GET_PANEL_SUPPORT_EXPAND:
750 state_info =
751 viafb_lcd_get_support_expand_state(info->var.xres,
752 info->var.yres);
753 if (put_user(state_info, argp))
754 return -EFAULT;
755 break;
756
757 case VIAFB_GET_DRIVER_NAME:
758 if (copy_to_user(argp, driver_name, sizeof(driver_name)))
759 return -EFAULT;
760 break;
761
762 case VIAFB_SET_GAMMA_LUT:
763 viafb_gamma_table = kmalloc(256 * sizeof(u32), GFP_KERNEL);
764 if (!viafb_gamma_table)
765 return -ENOMEM;
766 if (copy_from_user(viafb_gamma_table, argp,
767 sizeof(viafb_gamma_table))) {
768 kfree(viafb_gamma_table);
769 return -EFAULT;
770 }
771 viafb_set_gamma_table(viafb_bpp, viafb_gamma_table);
772 kfree(viafb_gamma_table);
773 break;
774
775 case VIAFB_GET_GAMMA_LUT:
776 viafb_gamma_table = kmalloc(256 * sizeof(u32), GFP_KERNEL);
777 if (!viafb_gamma_table)
778 return -ENOMEM;
779 viafb_get_gamma_table(viafb_gamma_table);
780 if (copy_to_user(argp, viafb_gamma_table,
781 sizeof(viafb_gamma_table))) {
782 kfree(viafb_gamma_table);
783 return -EFAULT;
784 }
785 kfree(viafb_gamma_table);
786 break;
787
788 case VIAFB_GET_GAMMA_SUPPORT_STATE:
789 viafb_get_gamma_support_state(viafb_bpp, &state_info);
790 if (put_user(state_info, argp))
791 return -EFAULT;
792 break;
793 case VIAFB_SET_VIDEO_DEVICE:
794 get_user(video_dev_info, argp);
795 viafb_set_video_device(video_dev_info);
796 break;
797 case VIAFB_GET_VIDEO_DEVICE:
798 viafb_get_video_device(&video_dev_info);
799 if (put_user(video_dev_info, argp))
800 return -EFAULT;
801 break;
802 case VIAFB_SYNC_SURFACE:
803 DEBUG_MSG(KERN_INFO "lobo VIAFB_SYNC_SURFACE\n");
804 break;
805 case VIAFB_GET_DRIVER_CAPS:
806 break;
807
808 case VIAFB_GET_PANEL_MAX_SIZE:
809 if (copy_from_user
810 (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
811 return -EFAULT;
812 panel_pos_size_para.x = panel_pos_size_para.y = 0;
813 if (copy_to_user(argp, &panel_pos_size_para,
814 sizeof(panel_pos_size_para)))
815 return -EFAULT;
816 break;
817 case VIAFB_GET_PANEL_MAX_POSITION:
818 if (copy_from_user
819 (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
820 return -EFAULT;
821 panel_pos_size_para.x = panel_pos_size_para.y = 0;
822 if (copy_to_user(argp, &panel_pos_size_para,
823 sizeof(panel_pos_size_para)))
824 return -EFAULT;
825 break;
826
827 case VIAFB_GET_PANEL_POSITION:
828 if (copy_from_user
829 (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
830 return -EFAULT;
831 panel_pos_size_para.x = panel_pos_size_para.y = 0;
832 if (copy_to_user(argp, &panel_pos_size_para,
833 sizeof(panel_pos_size_para)))
834 return -EFAULT;
835 break;
836 case VIAFB_GET_PANEL_SIZE:
837 if (copy_from_user
838 (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
839 return -EFAULT;
840 panel_pos_size_para.x = panel_pos_size_para.y = 0;
841 if (copy_to_user(argp, &panel_pos_size_para,
842 sizeof(panel_pos_size_para)))
843 return -EFAULT;
844 break;
845
846 case VIAFB_SET_PANEL_POSITION:
847 if (copy_from_user
848 (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
849 return -EFAULT;
850 break;
851 case VIAFB_SET_PANEL_SIZE:
852 if (copy_from_user
853 (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
854 return -EFAULT;
855 break;
856
857 default:
858 return -EINVAL;
859 }
860
861 return 0;
862}
863
864static void viafb_fillrect(struct fb_info *info,
865 const struct fb_fillrect *rect)
866{
867 u32 col = 0, rop = 0;
868 int pitch;
869
870 if (!viafb_accel)
871 return cfb_fillrect(info, rect);
872
873 if (!rect->width || !rect->height)
874 return;
875
876 switch (rect->rop) {
877 case ROP_XOR:
878 rop = 0x5A;
879 break;
880 case ROP_COPY:
881 default:
882 rop = 0xF0;
883 break;
884 }
885
886 switch (info->var.bits_per_pixel) {
887 case 8:
888 col = rect->color;
889 break;
890 case 16:
891 col = ((u32 *) (info->pseudo_palette))[rect->color];
892 break;
893 case 32:
894 col = ((u32 *) (info->pseudo_palette))[rect->color];
895 break;
896 }
897
898 /* BitBlt Source Address */
899 writel(0x0, viaparinfo->io_virt + VIA_REG_SRCPOS);
900 /* Source Base Address */
901 writel(0x0, viaparinfo->io_virt + VIA_REG_SRCBASE);
902 /* Destination Base Address */
903 writel(((unsigned long) (info->screen_base) -
904 (unsigned long) viafb_FB_MM) >> 3,
905 viaparinfo->io_virt + VIA_REG_DSTBASE);
906 /* Pitch */
907 pitch = (info->var.xres_virtual + 7) & ~7;
908 writel(VIA_PITCH_ENABLE |
909 (((pitch *
910 info->var.bits_per_pixel >> 3) >> 3) |
911 (((pitch * info->
912 var.bits_per_pixel >> 3) >> 3) << 16)),
913 viaparinfo->io_virt + VIA_REG_PITCH);
914 /* BitBlt Destination Address */
915 writel(((rect->dy << 16) | rect->dx),
916 viaparinfo->io_virt + VIA_REG_DSTPOS);
917 /* Dimension: width & height */
918 writel((((rect->height - 1) << 16) | (rect->width - 1)),
919 viaparinfo->io_virt + VIA_REG_DIMENSION);
920 /* Forground color or Destination color */
921 writel(col, viaparinfo->io_virt + VIA_REG_FGCOLOR);
922 /* GE Command */
923 writel((0x01 | 0x2000 | (rop << 24)),
924 viaparinfo->io_virt + VIA_REG_GECMD);
925
926}
927
928static void viafb_copyarea(struct fb_info *info,
929 const struct fb_copyarea *area)
930{
931 u32 dy = area->dy, sy = area->sy, direction = 0x0;
932 u32 sx = area->sx, dx = area->dx, width = area->width;
933 int pitch;
934
935 DEBUG_MSG(KERN_INFO "viafb_copyarea!!\n");
936
937 if (!viafb_accel)
938 return cfb_copyarea(info, area);
939
940 if (!area->width || !area->height)
941 return;
942
943 if (sy < dy) {
944 dy += area->height - 1;
945 sy += area->height - 1;
946 direction |= 0x4000;
947 }
948
949 if (sx < dx) {
950 dx += width - 1;
951 sx += width - 1;
952 direction |= 0x8000;
953 }
954
955 /* Source Base Address */
956 writel(((unsigned long) (info->screen_base) -
957 (unsigned long) viafb_FB_MM) >> 3,
958 viaparinfo->io_virt + VIA_REG_SRCBASE);
959 /* Destination Base Address */
960 writel(((unsigned long) (info->screen_base) -
961 (unsigned long) viafb_FB_MM) >> 3,
962 viaparinfo->io_virt + VIA_REG_DSTBASE);
963 /* Pitch */
964 pitch = (info->var.xres_virtual + 7) & ~7;
965 /* VIA_PITCH_ENABLE can be omitted now. */
966 writel(VIA_PITCH_ENABLE |
967 (((pitch *
968 info->var.bits_per_pixel >> 3) >> 3) | (((pitch *
969 info->var.
970 bits_per_pixel
971 >> 3) >> 3)
972 << 16)),
973 viaparinfo->io_virt + VIA_REG_PITCH);
974 /* BitBlt Source Address */
975 writel(((sy << 16) | sx), viaparinfo->io_virt + VIA_REG_SRCPOS);
976 /* BitBlt Destination Address */
977 writel(((dy << 16) | dx), viaparinfo->io_virt + VIA_REG_DSTPOS);
978 /* Dimension: width & height */
979 writel((((area->height - 1) << 16) | (area->width - 1)),
980 viaparinfo->io_virt + VIA_REG_DIMENSION);
981 /* GE Command */
982 writel((0x01 | direction | (0xCC << 24)),
983 viaparinfo->io_virt + VIA_REG_GECMD);
984
985}
986
987static void viafb_imageblit(struct fb_info *info,
988 const struct fb_image *image)
989{
990 u32 size, bg_col = 0, fg_col = 0, *udata;
991 int i;
992 int pitch;
993
994 if (!viafb_accel)
995 return cfb_imageblit(info, image);
996
997 udata = (u32 *) image->data;
998
999 switch (info->var.bits_per_pixel) {
1000 case 8:
1001 bg_col = image->bg_color;
1002 fg_col = image->fg_color;
1003 break;
1004 case 16:
1005 bg_col = ((u32 *) (info->pseudo_palette))[image->bg_color];
1006 fg_col = ((u32 *) (info->pseudo_palette))[image->fg_color];
1007 break;
1008 case 32:
1009 bg_col = ((u32 *) (info->pseudo_palette))[image->bg_color];
1010 fg_col = ((u32 *) (info->pseudo_palette))[image->fg_color];
1011 break;
1012 }
1013 size = image->width * image->height;
1014
1015 /* Source Base Address */
1016 writel(0x0, viaparinfo->io_virt + VIA_REG_SRCBASE);
1017 /* Destination Base Address */
1018 writel(((unsigned long) (info->screen_base) -
1019 (unsigned long) viafb_FB_MM) >> 3,
1020 viaparinfo->io_virt + VIA_REG_DSTBASE);
1021 /* Pitch */
1022 pitch = (info->var.xres_virtual + 7) & ~7;
1023 writel(VIA_PITCH_ENABLE |
1024 (((pitch *
1025 info->var.bits_per_pixel >> 3) >> 3) | (((pitch *
1026 info->var.
1027 bits_per_pixel
1028 >> 3) >> 3)
1029 << 16)),
1030 viaparinfo->io_virt + VIA_REG_PITCH);
1031 /* BitBlt Source Address */
1032 writel(0x0, viaparinfo->io_virt + VIA_REG_SRCPOS);
1033 /* BitBlt Destination Address */
1034 writel(((image->dy << 16) | image->dx),
1035 viaparinfo->io_virt + VIA_REG_DSTPOS);
1036 /* Dimension: width & height */
1037 writel((((image->height - 1) << 16) | (image->width - 1)),
1038 viaparinfo->io_virt + VIA_REG_DIMENSION);
1039 /* fb color */
1040 writel(fg_col, viaparinfo->io_virt + VIA_REG_FGCOLOR);
1041 /* bg color */
1042 writel(bg_col, viaparinfo->io_virt + VIA_REG_BGCOLOR);
1043 /* GE Command */
1044 writel(0xCC020142, viaparinfo->io_virt + VIA_REG_GECMD);
1045
1046 for (i = 0; i < size / 4; i++) {
1047 writel(*udata, viaparinfo->io_virt + VIA_MMIO_BLTBASE);
1048 udata++;
1049 }
1050
1051}
1052
1053static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1054{
1055 u8 data[CURSOR_SIZE / 8];
1056 u32 data_bak[CURSOR_SIZE / 32];
1057 u32 temp, xx, yy, bg_col = 0, fg_col = 0;
1058 int size, i, j = 0;
1059 static int hw_cursor;
1060 struct viafb_par *p_viafb_par;
1061
1062 if (viafb_accel)
1063 hw_cursor = 1;
1064
1065 if (!viafb_accel) {
1066 if (hw_cursor) {
1067 viafb_show_hw_cursor(info, HW_Cursor_OFF);
1068 hw_cursor = 0;
1069 }
1070 return -ENODEV;
1071 }
1072
1073 if ((((struct viafb_par *)(info->par))->iga_path == IGA2)
1074 && (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266))
1075 return -ENODEV;
1076
1077 /* When duoview and using lcd , use soft cursor */
1078 if (viafb_LCD_ON || ((struct viafb_par *)(info->par))->duoview)
1079 return -ENODEV;
1080
1081 viafb_show_hw_cursor(info, HW_Cursor_OFF);
1082 viacursor = *cursor;
1083
1084 if (cursor->set & FB_CUR_SETHOT) {
1085 viacursor.hot = cursor->hot;
1086 temp = ((viacursor.hot.x) << 16) + viacursor.hot.y;
1087 writel(temp, viaparinfo->io_virt + VIA_REG_CURSOR_ORG);
1088 }
1089
1090 if (cursor->set & FB_CUR_SETPOS) {
1091 viacursor.image.dx = cursor->image.dx;
1092 viacursor.image.dy = cursor->image.dy;
1093 yy = cursor->image.dy - info->var.yoffset;
1094 xx = cursor->image.dx - info->var.xoffset;
1095 temp = yy & 0xFFFF;
1096 temp |= (xx << 16);
1097 writel(temp, viaparinfo->io_virt + VIA_REG_CURSOR_POS);
1098 }
1099
1100 if (cursor->set & FB_CUR_SETSIZE) {
1101 temp = readl(viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
1102
1103 if ((cursor->image.width <= 32)
1104 && (cursor->image.height <= 32)) {
1105 MAX_CURS = 32;
1106 temp |= 0x2;
1107 } else if ((cursor->image.width <= 64)
1108 && (cursor->image.height <= 64)) {
1109 MAX_CURS = 64;
1110 temp &= 0xFFFFFFFD;
1111 } else {
1112 DEBUG_MSG(KERN_INFO
1113 "The cursor image is biger than 64x64 bits...\n");
1114 return -ENXIO;
1115 }
1116 writel(temp, viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
1117
1118 viacursor.image.height = cursor->image.height;
1119 viacursor.image.width = cursor->image.width;
1120 }
1121
1122 if (cursor->set & FB_CUR_SETCMAP) {
1123 viacursor.image.fg_color = cursor->image.fg_color;
1124 viacursor.image.bg_color = cursor->image.bg_color;
1125
1126 switch (info->var.bits_per_pixel) {
1127 case 8:
1128 case 16:
1129 case 32:
1130 bg_col =
1131 (0xFF << 24) |
1132 (((info->cmap.red)[viacursor.image.bg_color] &
1133 0xFF00) << 8) |
1134 ((info->cmap.green)[viacursor.image.bg_color] &
1135 0xFF00) |
1136 (((info->cmap.blue)[viacursor.image.bg_color] &
1137 0xFF00) >> 8);
1138 fg_col =
1139 (0xFF << 24) |
1140 (((info->cmap.red)[viacursor.image.fg_color] &
1141 0xFF00) << 8) |
1142 ((info->cmap.green)[viacursor.image.fg_color] &
1143 0xFF00) |
1144 (((info->cmap.blue)[viacursor.image.fg_color] &
1145 0xFF00) >> 8);
1146 break;
1147 default:
1148 return 0;
1149 }
1150
1151 /* This is indeed a patch for VT3324/VT3353 */
1152 if (!info->par)
1153 return 0;
1154 p_viafb_par = (struct viafb_par *)info->par;
1155
1156 if ((p_viafb_par->chip_info->gfx_chip_name ==
1157 UNICHROME_CX700) ||
1158 ((p_viafb_par->chip_info->gfx_chip_name ==
1159 UNICHROME_VX800))) {
1160 bg_col =
1161 (((info->cmap.red)[viacursor.image.bg_color] &
1162 0xFFC0) << 14) |
1163 (((info->cmap.green)[viacursor.image.bg_color] &
1164 0xFFC0) << 4) |
1165 (((info->cmap.blue)[viacursor.image.bg_color] &
1166 0xFFC0) >> 6);
1167 fg_col =
1168 (((info->cmap.red)[viacursor.image.fg_color] &
1169 0xFFC0) << 14) |
1170 (((info->cmap.green)[viacursor.image.fg_color] &
1171 0xFFC0) << 4) |
1172 (((info->cmap.blue)[viacursor.image.fg_color] &
1173 0xFFC0) >> 6);
1174 }
1175
1176 writel(bg_col, viaparinfo->io_virt + VIA_REG_CURSOR_BG);
1177 writel(fg_col, viaparinfo->io_virt + VIA_REG_CURSOR_FG);
1178 }
1179
1180 if (cursor->set & FB_CUR_SETSHAPE) {
1181 size =
1182 ((viacursor.image.width + 7) >> 3) *
1183 viacursor.image.height;
1184
1185 if (MAX_CURS == 32) {
1186 for (i = 0; i < (CURSOR_SIZE / 32); i++) {
1187 data_bak[i] = 0x0;
1188 data_bak[i + 1] = 0xFFFFFFFF;
1189 i += 1;
1190 }
1191 } else if (MAX_CURS == 64) {
1192 for (i = 0; i < (CURSOR_SIZE / 32); i++) {
1193 data_bak[i] = 0x0;
1194 data_bak[i + 1] = 0x0;
1195 data_bak[i + 2] = 0xFFFFFFFF;
1196 data_bak[i + 3] = 0xFFFFFFFF;
1197 i += 3;
1198 }
1199 }
1200
1201 switch (viacursor.rop) {
1202 case ROP_XOR:
1203 for (i = 0; i < size; i++)
1204 data[i] = viacursor.mask[i];
1205 break;
1206 case ROP_COPY:
1207
1208 for (i = 0; i < size; i++)
1209 data[i] = viacursor.mask[i];
1210 break;
1211 default:
1212 break;
1213 }
1214
1215 if (MAX_CURS == 32) {
1216 for (i = 0; i < size; i++) {
1217 data_bak[j] = (u32) data[i];
1218 data_bak[j + 1] = ~data_bak[j];
1219 j += 2;
1220 }
1221 } else if (MAX_CURS == 64) {
1222 for (i = 0; i < size; i++) {
1223 data_bak[j] = (u32) data[i];
1224 data_bak[j + 1] = 0x0;
1225 data_bak[j + 2] = ~data_bak[j];
1226 data_bak[j + 3] = ~data_bak[j + 1];
1227 j += 4;
1228 }
1229 }
1230
1231 memcpy(((struct viafb_par *)(info->par))->fbmem_virt +
1232 ((struct viafb_par *)(info->par))->cursor_start,
1233 data_bak, CURSOR_SIZE);
1234 }
1235
1236 if (viacursor.enable)
1237 viafb_show_hw_cursor(info, HW_Cursor_ON);
1238
1239 return 0;
1240}
1241
1242static int viafb_sync(struct fb_info *info)
1243{
1244 if (viafb_accel)
1245 viafb_wait_engine_idle();
1246 return 0;
1247}
1248
1249int viafb_get_mode_index(int hres, int vres, int flag)
1250{
1251 u32 i;
1252 DEBUG_MSG(KERN_INFO "viafb_get_mode_index!\n");
1253
1254 for (i = 0; viafb_modentry[i].mode_index != VIA_RES_INVALID; i++)
1255 if (viafb_modentry[i].xres == hres &&
1256 viafb_modentry[i].yres == vres)
1257 break;
1258
1259 viafb_resMode = viafb_modentry[i].mode_index;
1260 if (flag)
1261 viafb_mode1 = viafb_modentry[i].mode_res;
1262 else
1263 viafb_mode = viafb_modentry[i].mode_res;
1264
1265 return viafb_resMode;
1266}
1267
1268static void check_available_device_to_enable(int device_id)
1269{
1270 int device_num = 0;
1271
1272 /* Initialize: */
1273 viafb_CRT_ON = STATE_OFF;
1274 viafb_DVI_ON = STATE_OFF;
1275 viafb_LCD_ON = STATE_OFF;
1276 viafb_LCD2_ON = STATE_OFF;
1277 viafb_DeviceStatus = None_Device;
1278
1279 if ((device_id & CRT_Device) && (device_num < MAX_ACTIVE_DEV_NUM)) {
1280 viafb_CRT_ON = STATE_ON;
1281 device_num++;
1282 viafb_DeviceStatus |= CRT_Device;
1283 }
1284
1285 if ((device_id & DVI_Device) && (device_num < MAX_ACTIVE_DEV_NUM)) {
1286 viafb_DVI_ON = STATE_ON;
1287 device_num++;
1288 viafb_DeviceStatus |= DVI_Device;
1289 }
1290
1291 if ((device_id & LCD_Device) && (device_num < MAX_ACTIVE_DEV_NUM)) {
1292 viafb_LCD_ON = STATE_ON;
1293 device_num++;
1294 viafb_DeviceStatus |= LCD_Device;
1295 }
1296
1297 if ((device_id & LCD2_Device) && (device_num < MAX_ACTIVE_DEV_NUM)) {
1298 viafb_LCD2_ON = STATE_ON;
1299 device_num++;
1300 viafb_DeviceStatus |= LCD2_Device;
1301 }
1302
1303 if (viafb_DeviceStatus == None_Device) {
1304 /* Use CRT as default active device: */
1305 viafb_CRT_ON = STATE_ON;
1306 viafb_DeviceStatus = CRT_Device;
1307 }
1308 DEBUG_MSG(KERN_INFO "Device Status:%x", viafb_DeviceStatus);
1309}
1310
1311static void viafb_set_device(struct device_t active_dev)
1312{
1313 /* Check available device to enable: */
1314 int device_id = None_Device;
1315 if (active_dev.crt)
1316 device_id |= CRT_Device;
1317 if (active_dev.dvi)
1318 device_id |= DVI_Device;
1319 if (active_dev.lcd)
1320 device_id |= LCD_Device;
1321
1322 check_available_device_to_enable(device_id);
1323
1324 /* Check property of LCD: */
1325 if (viafb_LCD_ON) {
1326 if (active_dev.lcd_dsp_cent) {
1327 viaparinfo->lvds_setting_info->display_method =
1328 viafb_lcd_dsp_method = LCD_CENTERING;
1329 } else {
1330 viaparinfo->lvds_setting_info->display_method =
1331 viafb_lcd_dsp_method = LCD_EXPANDSION;
1332 }
1333
1334 if (active_dev.lcd_mode == LCD_SPWG) {
1335 viaparinfo->lvds_setting_info->lcd_mode =
1336 viafb_lcd_mode = LCD_SPWG;
1337 } else {
1338 viaparinfo->lvds_setting_info->lcd_mode =
1339 viafb_lcd_mode = LCD_OPENLDI;
1340 }
1341
1342 if (active_dev.lcd_panel_id <= LCD_PANEL_ID_MAXIMUM) {
1343 viafb_lcd_panel_id = active_dev.lcd_panel_id;
1344 viafb_init_lcd_size();
1345 }
1346 }
1347
1348 /* Check property of mode: */
1349 if (!active_dev.xres1)
1350 viafb_second_xres = 640;
1351 else
1352 viafb_second_xres = active_dev.xres1;
1353 if (!active_dev.yres1)
1354 viafb_second_yres = 480;
1355 else
1356 viafb_second_yres = active_dev.yres1;
1357 if (active_dev.bpp != 0)
1358 viafb_bpp = active_dev.bpp;
1359 if (active_dev.bpp1 != 0)
1360 viafb_bpp1 = active_dev.bpp1;
1361 if (active_dev.refresh != 0)
1362 viafb_refresh = active_dev.refresh;
1363 if (active_dev.refresh1 != 0)
1364 viafb_refresh1 = active_dev.refresh1;
1365 if ((active_dev.samm == STATE_OFF) || (active_dev.samm == STATE_ON))
1366 viafb_SAMM_ON = active_dev.samm;
1367 viafb_primary_dev = active_dev.primary_dev;
1368
1369 viafb_set_start_addr();
1370 viafb_set_iga_path();
1371}
1372
1373static void viafb_set_video_device(u32 video_dev_info)
1374{
1375 viaparinfo->video_on_crt = STATE_OFF;
1376 viaparinfo->video_on_dvi = STATE_OFF;
1377 viaparinfo->video_on_lcd = STATE_OFF;
1378
1379 /* Check available device to enable: */
1380 if ((video_dev_info & CRT_Device) == CRT_Device)
1381 viaparinfo->video_on_crt = STATE_ON;
1382 else if ((video_dev_info & DVI_Device) == DVI_Device)
1383 viaparinfo->video_on_dvi = STATE_ON;
1384 else if ((video_dev_info & LCD_Device) == LCD_Device)
1385 viaparinfo->video_on_lcd = STATE_ON;
1386}
1387
1388static void viafb_get_video_device(u32 *video_dev_info)
1389{
1390 *video_dev_info = None_Device;
1391 if (viaparinfo->video_on_crt == STATE_ON)
1392 *video_dev_info |= CRT_Device;
1393 else if (viaparinfo->video_on_dvi == STATE_ON)
1394 *video_dev_info |= DVI_Device;
1395 else if (viaparinfo->video_on_lcd == STATE_ON)
1396 *video_dev_info |= LCD_Device;
1397}
1398
1399static int get_primary_device(void)
1400{
1401 int primary_device = 0;
1402 /* Rule: device on iga1 path are the primary device. */
1403 if (viafb_SAMM_ON) {
1404 if (viafb_CRT_ON) {
1405 if (viaparinfo->crt_setting_info->iga_path == IGA1) {
1406 DEBUG_MSG(KERN_INFO "CRT IGA Path:%d\n",
1407 viaparinfo->
1408 crt_setting_info->iga_path);
1409 primary_device = CRT_Device;
1410 }
1411 }
1412 if (viafb_DVI_ON) {
1413 if (viaparinfo->tmds_setting_info->iga_path == IGA1) {
1414 DEBUG_MSG(KERN_INFO "DVI IGA Path:%d\n",
1415 viaparinfo->
1416 tmds_setting_info->iga_path);
1417 primary_device = DVI_Device;
1418 }
1419 }
1420 if (viafb_LCD_ON) {
1421 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
1422 DEBUG_MSG(KERN_INFO "LCD IGA Path:%d\n",
1423 viaparinfo->
1424 lvds_setting_info->iga_path);
1425 primary_device = LCD_Device;
1426 }
1427 }
1428 if (viafb_LCD2_ON) {
1429 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
1430 DEBUG_MSG(KERN_INFO "LCD2 IGA Path:%d\n",
1431 viaparinfo->
1432 lvds_setting_info2->iga_path);
1433 primary_device = LCD2_Device;
1434 }
1435 }
1436 }
1437 return primary_device;
1438}
1439
1440static u8 is_duoview(void)
1441{
1442 if (0 == viafb_SAMM_ON) {
1443 if (viafb_LCD_ON + viafb_LCD2_ON +
1444 viafb_DVI_ON + viafb_CRT_ON == 2)
1445 return true;
1446 return false;
1447 } else {
1448 return false;
1449 }
1450}
1451
1452static void apply_second_mode_setting(struct fb_var_screeninfo
1453 *sec_var)
1454{
1455 u32 htotal, vtotal, long_refresh;
1456
1457 htotal = sec_var->xres + sec_var->left_margin +
1458 sec_var->right_margin + sec_var->hsync_len;
1459 vtotal = sec_var->yres + sec_var->upper_margin +
1460 sec_var->lower_margin + sec_var->vsync_len;
1461 if ((sec_var->xres_virtual * (sec_var->bits_per_pixel >> 3)) & 0x1F) {
1462 /*Is 32 bytes alignment? */
1463 /*32 pixel alignment */
1464 sec_var->xres_virtual = (sec_var->xres_virtual + 31) & ~31;
1465 }
1466
1467 htotal = sec_var->xres + sec_var->left_margin +
1468 sec_var->right_margin + sec_var->hsync_len;
1469 vtotal = sec_var->yres + sec_var->upper_margin +
1470 sec_var->lower_margin + sec_var->vsync_len;
1471 long_refresh = 1000000000UL / sec_var->pixclock * 1000;
1472 long_refresh /= (htotal * vtotal);
1473
1474 viafb_second_xres = sec_var->xres;
1475 viafb_second_yres = sec_var->yres;
1476 viafb_second_virtual_xres = sec_var->xres_virtual;
1477 viafb_second_virtual_yres = sec_var->yres_virtual;
1478 viafb_bpp1 = sec_var->bits_per_pixel;
1479 viafb_refresh1 = viafb_get_refresh(sec_var->xres, sec_var->yres,
1480 long_refresh);
1481}
1482
1483static int apply_device_setting(struct viafb_ioctl_setting setting_info,
1484 struct fb_info *info)
1485{
1486 int need_set_mode = 0;
1487 DEBUG_MSG(KERN_INFO "apply_device_setting\n");
1488
1489 if (setting_info.device_flag) {
1490 need_set_mode = 1;
1491 check_available_device_to_enable(setting_info.device_status);
1492 }
1493
1494 /* Unlock LCD's operation according to LCD flag
1495 and check if the setting value is valid. */
1496 /* If the value is valid, apply the new setting value to the device. */
1497 if (viafb_LCD_ON) {
1498 if (setting_info.lcd_operation_flag & OP_LCD_CENTERING) {
1499 need_set_mode = 1;
1500 if (setting_info.lcd_attributes.display_center) {
1501 /* Centering */
1502 viaparinfo->lvds_setting_info->display_method =
1503 LCD_CENTERING;
1504 viafb_lcd_dsp_method = LCD_CENTERING;
1505 viaparinfo->lvds_setting_info2->display_method =
1506 viafb_lcd_dsp_method = LCD_CENTERING;
1507 } else {
1508 /* expandsion */
1509 viaparinfo->lvds_setting_info->display_method =
1510 LCD_EXPANDSION;
1511 viafb_lcd_dsp_method = LCD_EXPANDSION;
1512 viaparinfo->lvds_setting_info2->display_method =
1513 LCD_EXPANDSION;
1514 viafb_lcd_dsp_method = LCD_EXPANDSION;
1515 }
1516 }
1517
1518 if (setting_info.lcd_operation_flag & OP_LCD_MODE) {
1519 need_set_mode = 1;
1520 if (setting_info.lcd_attributes.lcd_mode ==
1521 LCD_SPWG) {
1522 viaparinfo->lvds_setting_info->lcd_mode =
1523 viafb_lcd_mode = LCD_SPWG;
1524 } else {
1525 viaparinfo->lvds_setting_info->lcd_mode =
1526 viafb_lcd_mode = LCD_OPENLDI;
1527 }
1528 viaparinfo->lvds_setting_info2->lcd_mode =
1529 viaparinfo->lvds_setting_info->lcd_mode;
1530 }
1531
1532 if (setting_info.lcd_operation_flag & OP_LCD_PANEL_ID) {
1533 need_set_mode = 1;
1534 if (setting_info.lcd_attributes.panel_id <=
1535 LCD_PANEL_ID_MAXIMUM) {
1536 viafb_lcd_panel_id =
1537 setting_info.lcd_attributes.panel_id;
1538 viafb_init_lcd_size();
1539 }
1540 }
1541 }
1542
1543 if (0 != (setting_info.samm_status & OP_SAMM)) {
1544 setting_info.samm_status =
1545 setting_info.samm_status & (~OP_SAMM);
1546 if (setting_info.samm_status == 0
1547 || setting_info.samm_status == 1) {
1548 viafb_SAMM_ON = setting_info.samm_status;
1549
1550 if (viafb_SAMM_ON)
1551 viafb_primary_dev = setting_info.primary_device;
1552
1553 viafb_set_start_addr();
1554 viafb_set_iga_path();
1555 }
1556 need_set_mode = 1;
1557 }
1558
1559 viaparinfo->duoview = is_duoview();
1560
1561 if (!need_set_mode) {
1562 ;
1563 } else {
1564 viafb_set_iga_path();
1565 viafb_set_par(info);
1566 }
1567 return true;
1568}
1569
1570static void retrieve_device_setting(struct viafb_ioctl_setting
1571 *setting_info)
1572{
1573
1574 /* get device status */
1575 if (viafb_CRT_ON == 1)
1576 setting_info->device_status = CRT_Device;
1577 if (viafb_DVI_ON == 1)
1578 setting_info->device_status |= DVI_Device;
1579 if (viafb_LCD_ON == 1)
1580 setting_info->device_status |= LCD_Device;
1581 if (viafb_LCD2_ON == 1)
1582 setting_info->device_status |= LCD2_Device;
1583 if ((viaparinfo->video_on_crt == 1) && (viafb_CRT_ON == 1)) {
1584 setting_info->video_device_status =
1585 viaparinfo->crt_setting_info->iga_path;
1586 } else if ((viaparinfo->video_on_dvi == 1) && (viafb_DVI_ON == 1)) {
1587 setting_info->video_device_status =
1588 viaparinfo->tmds_setting_info->iga_path;
1589 } else if ((viaparinfo->video_on_lcd == 1) && (viafb_LCD_ON == 1)) {
1590 setting_info->video_device_status =
1591 viaparinfo->lvds_setting_info->iga_path;
1592 } else {
1593 setting_info->video_device_status = 0;
1594 }
1595
1596 setting_info->samm_status = viafb_SAMM_ON;
1597 setting_info->primary_device = get_primary_device();
1598
1599 setting_info->first_dev_bpp = viafb_bpp;
1600 setting_info->second_dev_bpp = viafb_bpp1;
1601
1602 setting_info->first_dev_refresh = viafb_refresh;
1603 setting_info->second_dev_refresh = viafb_refresh1;
1604
1605 setting_info->first_dev_hor_res = viafb_hotplug_Xres;
1606 setting_info->first_dev_ver_res = viafb_hotplug_Yres;
1607 setting_info->second_dev_hor_res = viafb_second_xres;
1608 setting_info->second_dev_ver_res = viafb_second_yres;
1609
1610 /* Get lcd attributes */
1611 setting_info->lcd_attributes.display_center = viafb_lcd_dsp_method;
1612 setting_info->lcd_attributes.panel_id = viafb_lcd_panel_id;
1613 setting_info->lcd_attributes.lcd_mode = viafb_lcd_mode;
1614}
1615
1616static void parse_active_dev(void)
1617{
1618 viafb_CRT_ON = STATE_OFF;
1619 viafb_DVI_ON = STATE_OFF;
1620 viafb_LCD_ON = STATE_OFF;
1621 viafb_LCD2_ON = STATE_OFF;
1622 /* 1. Modify the active status of devices. */
1623 /* 2. Keep the order of devices, so we can set corresponding
1624 IGA path to devices in SAMM case. */
1625 /* Note: The previous of active_dev is primary device,
1626 and the following is secondary device. */
1627 if (!strncmp(viafb_active_dev, "CRT+DVI", 7)) {
1628 /* CRT+DVI */
1629 viafb_CRT_ON = STATE_ON;
1630 viafb_DVI_ON = STATE_ON;
1631 viafb_primary_dev = CRT_Device;
1632 } else if (!strncmp(viafb_active_dev, "DVI+CRT", 7)) {
1633 /* DVI+CRT */
1634 viafb_CRT_ON = STATE_ON;
1635 viafb_DVI_ON = STATE_ON;
1636 viafb_primary_dev = DVI_Device;
1637 } else if (!strncmp(viafb_active_dev, "CRT+LCD", 7)) {
1638 /* CRT+LCD */
1639 viafb_CRT_ON = STATE_ON;
1640 viafb_LCD_ON = STATE_ON;
1641 viafb_primary_dev = CRT_Device;
1642 } else if (!strncmp(viafb_active_dev, "LCD+CRT", 7)) {
1643 /* LCD+CRT */
1644 viafb_CRT_ON = STATE_ON;
1645 viafb_LCD_ON = STATE_ON;
1646 viafb_primary_dev = LCD_Device;
1647 } else if (!strncmp(viafb_active_dev, "DVI+LCD", 7)) {
1648 /* DVI+LCD */
1649 viafb_DVI_ON = STATE_ON;
1650 viafb_LCD_ON = STATE_ON;
1651 viafb_primary_dev = DVI_Device;
1652 } else if (!strncmp(viafb_active_dev, "LCD+DVI", 7)) {
1653 /* LCD+DVI */
1654 viafb_DVI_ON = STATE_ON;
1655 viafb_LCD_ON = STATE_ON;
1656 viafb_primary_dev = LCD_Device;
1657 } else if (!strncmp(viafb_active_dev, "LCD+LCD2", 8)) {
1658 viafb_LCD_ON = STATE_ON;
1659 viafb_LCD2_ON = STATE_ON;
1660 viafb_primary_dev = LCD_Device;
1661 } else if (!strncmp(viafb_active_dev, "LCD2+LCD", 8)) {
1662 viafb_LCD_ON = STATE_ON;
1663 viafb_LCD2_ON = STATE_ON;
1664 viafb_primary_dev = LCD2_Device;
1665 } else if (!strncmp(viafb_active_dev, "CRT", 3)) {
1666 /* CRT only */
1667 viafb_CRT_ON = STATE_ON;
1668 viafb_SAMM_ON = STATE_OFF;
1669 } else if (!strncmp(viafb_active_dev, "DVI", 3)) {
1670 /* DVI only */
1671 viafb_DVI_ON = STATE_ON;
1672 viafb_SAMM_ON = STATE_OFF;
1673 } else if (!strncmp(viafb_active_dev, "LCD", 3)) {
1674 /* LCD only */
1675 viafb_LCD_ON = STATE_ON;
1676 viafb_SAMM_ON = STATE_OFF;
1677 } else {
1678 viafb_CRT_ON = STATE_ON;
1679 viafb_SAMM_ON = STATE_OFF;
1680 }
1681 viaparinfo->duoview = is_duoview();
1682}
1683
1684static void parse_video_dev(void)
1685{
1686 viaparinfo->video_on_crt = STATE_OFF;
1687 viaparinfo->video_on_dvi = STATE_OFF;
1688 viaparinfo->video_on_lcd = STATE_OFF;
1689
1690 if (!strncmp(viafb_video_dev, "CRT", 3)) {
1691 /* Video on CRT */
1692 viaparinfo->video_on_crt = STATE_ON;
1693 } else if (!strncmp(viafb_video_dev, "DVI", 3)) {
1694 /* Video on DVI */
1695 viaparinfo->video_on_dvi = STATE_ON;
1696 } else if (!strncmp(viafb_video_dev, "LCD", 3)) {
1697 /* Video on LCD */
1698 viaparinfo->video_on_lcd = STATE_ON;
1699 }
1700}
1701
1702static int parse_port(char *opt_str, int *output_interface)
1703{
1704 if (!strncmp(opt_str, "DVP0", 4))
1705 *output_interface = INTERFACE_DVP0;
1706 else if (!strncmp(opt_str, "DVP1", 4))
1707 *output_interface = INTERFACE_DVP1;
1708 else if (!strncmp(opt_str, "DFP_HIGHLOW", 11))
1709 *output_interface = INTERFACE_DFP;
1710 else if (!strncmp(opt_str, "DFP_HIGH", 8))
1711 *output_interface = INTERFACE_DFP_HIGH;
1712 else if (!strncmp(opt_str, "DFP_LOW", 7))
1713 *output_interface = INTERFACE_DFP_LOW;
1714 else
1715 *output_interface = INTERFACE_NONE;
1716 return 0;
1717}
1718
1719static void parse_lcd_port(void)
1720{
1721 parse_port(viafb_lcd_port, &viaparinfo->chip_info->lvds_chip_info.
1722 output_interface);
1723 /*Initialize to avoid unexpected behavior */
1724 viaparinfo->chip_info->lvds_chip_info2.output_interface =
1725 INTERFACE_NONE;
1726
1727 DEBUG_MSG(KERN_INFO "parse_lcd_port: viafb_lcd_port:%s,interface:%d\n",
1728 viafb_lcd_port, viaparinfo->chip_info->lvds_chip_info.
1729 output_interface);
1730}
1731
1732static void parse_dvi_port(void)
1733{
1734 parse_port(viafb_dvi_port, &viaparinfo->chip_info->tmds_chip_info.
1735 output_interface);
1736
1737 DEBUG_MSG(KERN_INFO "parse_dvi_port: viafb_dvi_port:%s,interface:%d\n",
1738 viafb_dvi_port, viaparinfo->chip_info->tmds_chip_info.
1739 output_interface);
1740}
1741
1742/*
1743 * The proc filesystem read/write function, a simple proc implement to
1744 * get/set the value of DPA DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
1745 * DVP1Driving, DFPHigh, DFPLow CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2],
1746 * CR9B, SR65, CR97, CR99
1747 */
1748static int viafb_dvp0_proc_read(char *buf, char **start, off_t offset,
1749int count, int *eof, void *data)
1750{
1751 int len = 0;
1752 u8 dvp0_data_dri = 0, dvp0_clk_dri = 0, dvp0 = 0;
1753 dvp0_data_dri =
1754 (viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 |
1755 (viafb_read_reg(VIASR, SR1B) & BIT1) >> 1;
1756 dvp0_clk_dri =
1757 (viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 |
1758 (viafb_read_reg(VIASR, SR1E) & BIT2) >> 2;
1759 dvp0 = viafb_read_reg(VIACR, CR96) & 0x0f;
1760 len +=
1761 sprintf(buf + len, "%x %x %x\n", dvp0, dvp0_data_dri, dvp0_clk_dri);
1762 *eof = 1; /*Inform kernel end of data */
1763 return len;
1764}
1765static int viafb_dvp0_proc_write(struct file *file,
1766 const char __user *buffer, unsigned long count, void *data)
1767{
1768 char buf[20], *value, *pbuf;
1769 u8 reg_val = 0;
1770 unsigned long length, i;
1771 if (count < 1)
1772 return -EINVAL;
1773 length = count > 20 ? 20 : count;
1774 if (copy_from_user(&buf[0], buffer, length))
1775 return -EFAULT;
1776 buf[length - 1] = '\0'; /*Ensure end string */
1777 pbuf = &buf[0];
1778 for (i = 0; i < 3; i++) {
1779 value = strsep(&pbuf, " ");
1780 if (value != NULL) {
1781 strict_strtoul(value, 0, (unsigned long *)&reg_val);
1782 DEBUG_MSG(KERN_INFO "DVP0:reg_val[%l]=:%x\n", i,
1783 reg_val);
1784 switch (i) {
1785 case 0:
1786 viafb_write_reg_mask(CR96, VIACR,
1787 reg_val, 0x0f);
1788 break;
1789 case 1:
1790 viafb_write_reg_mask(SR2A, VIASR,
1791 reg_val << 4, BIT5);
1792 viafb_write_reg_mask(SR1B, VIASR,
1793 reg_val << 1, BIT1);
1794 break;
1795 case 2:
1796 viafb_write_reg_mask(SR2A, VIASR,
1797 reg_val << 3, BIT4);
1798 viafb_write_reg_mask(SR1E, VIASR,
1799 reg_val << 2, BIT2);
1800 break;
1801 default:
1802 break;
1803 }
1804 } else {
1805 break;
1806 }
1807 }
1808 return count;
1809}
1810static int viafb_dvp1_proc_read(char *buf, char **start, off_t offset,
1811 int count, int *eof, void *data)
1812{
1813 int len = 0;
1814 u8 dvp1 = 0, dvp1_data_dri = 0, dvp1_clk_dri = 0;
1815 dvp1 = viafb_read_reg(VIACR, CR9B) & 0x0f;
1816 dvp1_data_dri = (viafb_read_reg(VIASR, SR65) & 0x0c) >> 2;
1817 dvp1_clk_dri = viafb_read_reg(VIASR, SR65) & 0x03;
1818 len +=
1819 sprintf(buf + len, "%x %x %x\n", dvp1, dvp1_data_dri, dvp1_clk_dri);
1820 *eof = 1; /*Inform kernel end of data */
1821 return len;
1822}
1823static int viafb_dvp1_proc_write(struct file *file,
1824 const char __user *buffer, unsigned long count, void *data)
1825{
1826 char buf[20], *value, *pbuf;
1827 u8 reg_val = 0;
1828 unsigned long length, i;
1829 if (count < 1)
1830 return -EINVAL;
1831 length = count > 20 ? 20 : count;
1832 if (copy_from_user(&buf[0], buffer, length))
1833 return -EFAULT;
1834 buf[length - 1] = '\0'; /*Ensure end string */
1835 pbuf = &buf[0];
1836 for (i = 0; i < 3; i++) {
1837 value = strsep(&pbuf, " ");
1838 if (value != NULL) {
1839 strict_strtoul(value, 0, (unsigned long *)&reg_val);
1840 switch (i) {
1841 case 0:
1842 viafb_write_reg_mask(CR9B, VIACR,
1843 reg_val, 0x0f);
1844 break;
1845 case 1:
1846 viafb_write_reg_mask(SR65, VIASR,
1847 reg_val << 2, 0x0c);
1848 break;
1849 case 2:
1850 viafb_write_reg_mask(SR65, VIASR,
1851 reg_val, 0x03);
1852 break;
1853 default:
1854 break;
1855 }
1856 } else {
1857 break;
1858 }
1859 }
1860 return count;
1861}
1862
1863static int viafb_dfph_proc_read(char *buf, char **start, off_t offset,
1864 int count, int *eof, void *data)
1865{
1866 int len = 0;
1867 u8 dfp_high = 0;
1868 dfp_high = viafb_read_reg(VIACR, CR97) & 0x0f;
1869 len += sprintf(buf + len, "%x\n", dfp_high);
1870 *eof = 1; /*Inform kernel end of data */
1871 return len;
1872}
1873static int viafb_dfph_proc_write(struct file *file,
1874 const char __user *buffer, unsigned long count, void *data)
1875{
1876 char buf[20];
1877 u8 reg_val = 0;
1878 unsigned long length;
1879 if (count < 1)
1880 return -EINVAL;
1881 length = count > 20 ? 20 : count;
1882 if (copy_from_user(&buf[0], buffer, length))
1883 return -EFAULT;
1884 buf[length - 1] = '\0'; /*Ensure end string */
1885 strict_strtoul(&buf[0], 0, (unsigned long *)&reg_val);
1886 viafb_write_reg_mask(CR97, VIACR, reg_val, 0x0f);
1887 return count;
1888}
1889static int viafb_dfpl_proc_read(char *buf, char **start, off_t offset,
1890 int count, int *eof, void *data)
1891{
1892 int len = 0;
1893 u8 dfp_low = 0;
1894 dfp_low = viafb_read_reg(VIACR, CR99) & 0x0f;
1895 len += sprintf(buf + len, "%x\n", dfp_low);
1896 *eof = 1; /*Inform kernel end of data */
1897 return len;
1898}
1899static int viafb_dfpl_proc_write(struct file *file,
1900 const char __user *buffer, unsigned long count, void *data)
1901{
1902 char buf[20];
1903 u8 reg_val = 0;
1904 unsigned long length;
1905 if (count < 1)
1906 return -EINVAL;
1907 length = count > 20 ? 20 : count;
1908 if (copy_from_user(&buf[0], buffer, length))
1909 return -EFAULT;
1910 buf[length - 1] = '\0'; /*Ensure end string */
1911 strict_strtoul(&buf[0], 0, (unsigned long *)&reg_val);
1912 viafb_write_reg_mask(CR99, VIACR, reg_val, 0x0f);
1913 return count;
1914}
1915static int viafb_vt1636_proc_read(char *buf, char **start,
1916 off_t offset, int count, int *eof, void *data)
1917{
1918 int len = 0;
1919 u8 vt1636_08 = 0, vt1636_09 = 0;
1920 switch (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1921 case VT1636_LVDS:
1922 vt1636_08 =
1923 viafb_gpio_i2c_read_lvds(viaparinfo->lvds_setting_info,
1924 &viaparinfo->chip_info->lvds_chip_info, 0x08) & 0x0f;
1925 vt1636_09 =
1926 viafb_gpio_i2c_read_lvds(viaparinfo->lvds_setting_info,
1927 &viaparinfo->chip_info->lvds_chip_info, 0x09) & 0x1f;
1928 len += sprintf(buf + len, "%x %x\n", vt1636_08, vt1636_09);
1929 break;
1930 default:
1931 break;
1932 }
1933 switch (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
1934 case VT1636_LVDS:
1935 vt1636_08 =
1936 viafb_gpio_i2c_read_lvds(viaparinfo->lvds_setting_info2,
1937 &viaparinfo->chip_info->lvds_chip_info2, 0x08) & 0x0f;
1938 vt1636_09 =
1939 viafb_gpio_i2c_read_lvds(viaparinfo->lvds_setting_info2,
1940 &viaparinfo->chip_info->lvds_chip_info2, 0x09) & 0x1f;
1941 len += sprintf(buf + len, " %x %x\n", vt1636_08, vt1636_09);
1942 break;
1943 default:
1944 break;
1945 }
1946 *eof = 1; /*Inform kernel end of data */
1947 return len;
1948}
1949static int viafb_vt1636_proc_write(struct file *file,
1950 const char __user *buffer, unsigned long count, void *data)
1951{
1952 char buf[30], *value, *pbuf;
1953 struct IODATA reg_val;
1954 unsigned long length, i;
1955 if (count < 1)
1956 return -EINVAL;
1957 length = count > 30 ? 30 : count;
1958 if (copy_from_user(&buf[0], buffer, length))
1959 return -EFAULT;
1960 buf[length - 1] = '\0'; /*Ensure end string */
1961 pbuf = &buf[0];
1962 switch (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1963 case VT1636_LVDS:
1964 for (i = 0; i < 2; i++) {
1965 value = strsep(&pbuf, " ");
1966 if (value != NULL) {
1967 strict_strtoul(value, 0,
1968 (unsigned long *)&reg_val.Data);
1969 switch (i) {
1970 case 0:
1971 reg_val.Index = 0x08;
1972 reg_val.Mask = 0x0f;
1973 viafb_gpio_i2c_write_mask_lvds
1974 (viaparinfo->lvds_setting_info,
1975 &viaparinfo->
1976 chip_info->lvds_chip_info,
1977 reg_val);
1978 break;
1979 case 1:
1980 reg_val.Index = 0x09;
1981 reg_val.Mask = 0x1f;
1982 viafb_gpio_i2c_write_mask_lvds
1983 (viaparinfo->lvds_setting_info,
1984 &viaparinfo->
1985 chip_info->lvds_chip_info,
1986 reg_val);
1987 break;
1988 default:
1989 break;
1990 }
1991 } else {
1992 break;
1993 }
1994 }
1995 break;
1996 default:
1997 break;
1998 }
1999 switch (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2000 case VT1636_LVDS:
2001 for (i = 0; i < 2; i++) {
2002 value = strsep(&pbuf, " ");
2003 if (value != NULL) {
2004 strict_strtoul(value, 0,
2005 (unsigned long *)&reg_val.Data);
2006 switch (i) {
2007 case 0:
2008 reg_val.Index = 0x08;
2009 reg_val.Mask = 0x0f;
2010 viafb_gpio_i2c_write_mask_lvds
2011 (viaparinfo->lvds_setting_info2,
2012 &viaparinfo->
2013 chip_info->lvds_chip_info2,
2014 reg_val);
2015 break;
2016 case 1:
2017 reg_val.Index = 0x09;
2018 reg_val.Mask = 0x1f;
2019 viafb_gpio_i2c_write_mask_lvds
2020 (viaparinfo->lvds_setting_info2,
2021 &viaparinfo->
2022 chip_info->lvds_chip_info2,
2023 reg_val);
2024 break;
2025 default:
2026 break;
2027 }
2028 } else {
2029 break;
2030 }
2031 }
2032 break;
2033 default:
2034 break;
2035 }
2036 return count;
2037}
2038
2039static void viafb_init_proc(struct proc_dir_entry *viafb_entry)
2040{
2041 struct proc_dir_entry *entry;
2042 viafb_entry = proc_mkdir("viafb", NULL);
2043 if (viafb_entry) {
2044 entry = create_proc_entry("dvp0", 0, viafb_entry);
2045 if (entry) {
2046 entry->owner = THIS_MODULE;
2047 entry->read_proc = viafb_dvp0_proc_read;
2048 entry->write_proc = viafb_dvp0_proc_write;
2049 }
2050 entry = create_proc_entry("dvp1", 0, viafb_entry);
2051 if (entry) {
2052 entry->owner = THIS_MODULE;
2053 entry->read_proc = viafb_dvp1_proc_read;
2054 entry->write_proc = viafb_dvp1_proc_write;
2055 }
2056 entry = create_proc_entry("dfph", 0, viafb_entry);
2057 if (entry) {
2058 entry->owner = THIS_MODULE;
2059 entry->read_proc = viafb_dfph_proc_read;
2060 entry->write_proc = viafb_dfph_proc_write;
2061 }
2062 entry = create_proc_entry("dfpl", 0, viafb_entry);
2063 if (entry) {
2064 entry->owner = THIS_MODULE;
2065 entry->read_proc = viafb_dfpl_proc_read;
2066 entry->write_proc = viafb_dfpl_proc_write;
2067 }
2068 if (VT1636_LVDS == viaparinfo->chip_info->lvds_chip_info.
2069 lvds_chip_name || VT1636_LVDS ==
2070 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2071 entry = create_proc_entry("vt1636", 0, viafb_entry);
2072 if (entry) {
2073 entry->owner = THIS_MODULE;
2074 entry->read_proc = viafb_vt1636_proc_read;
2075 entry->write_proc = viafb_vt1636_proc_write;
2076 }
2077 }
2078
2079 }
2080}
2081static void viafb_remove_proc(struct proc_dir_entry *viafb_entry)
2082{
2083 /* no problem if it was not registered */
2084 remove_proc_entry("dvp0", viafb_entry);/* parent dir */
2085 remove_proc_entry("dvp1", viafb_entry);
2086 remove_proc_entry("dfph", viafb_entry);
2087 remove_proc_entry("dfpl", viafb_entry);
2088 remove_proc_entry("vt1636", viafb_entry);
2089 remove_proc_entry("vt1625", viafb_entry);
2090}
2091
2092static int __devinit via_pci_probe(void)
2093{
2094 unsigned int default_xres, default_yres;
2095 char *tmpc, *tmpm;
2096 char *tmpc_sec, *tmpm_sec;
2097 int vmode_index;
2098 u32 tmds_length, lvds_length, crt_length, chip_length, viafb_par_length;
2099
2100 DEBUG_MSG(KERN_INFO "VIAFB PCI Probe!!\n");
2101
2102 viafb_par_length = ALIGN(sizeof(struct viafb_par), BITS_PER_LONG/8);
2103 tmds_length = ALIGN(sizeof(struct tmds_setting_information),
2104 BITS_PER_LONG/8);
2105 lvds_length = ALIGN(sizeof(struct lvds_setting_information),
2106 BITS_PER_LONG/8);
2107 crt_length = ALIGN(sizeof(struct lvds_setting_information),
2108 BITS_PER_LONG/8);
2109 chip_length = ALIGN(sizeof(struct chip_information), BITS_PER_LONG/8);
2110
2111 /* Allocate fb_info and ***_par here, also including some other needed
2112 * variables
2113 */
2114 viafbinfo = framebuffer_alloc(viafb_par_length + 2 * lvds_length +
2115 tmds_length + crt_length + chip_length, NULL);
2116 if (!viafbinfo) {
2117 printk(KERN_ERR"Could not allocate memory for viafb_info.\n");
2118 return -ENODEV;
2119 }
2120
2121 viaparinfo = (struct viafb_par *)viafbinfo->par;
2122 viaparinfo->tmds_setting_info = (struct tmds_setting_information *)
2123 ((unsigned long)viaparinfo + viafb_par_length);
2124 viaparinfo->lvds_setting_info = (struct lvds_setting_information *)
2125 ((unsigned long)viaparinfo->tmds_setting_info + tmds_length);
2126 viaparinfo->lvds_setting_info2 = (struct lvds_setting_information *)
2127 ((unsigned long)viaparinfo->lvds_setting_info + lvds_length);
2128 viaparinfo->crt_setting_info = (struct crt_setting_information *)
2129 ((unsigned long)viaparinfo->lvds_setting_info2 + lvds_length);
2130 viaparinfo->chip_info = (struct chip_information *)
2131 ((unsigned long)viaparinfo->crt_setting_info + crt_length);
2132
2133 if (viafb_dual_fb)
2134 viafb_SAMM_ON = 1;
2135 parse_active_dev();
2136 parse_video_dev();
2137 parse_lcd_port();
2138 parse_dvi_port();
2139
2140 /* for dual-fb must viafb_SAMM_ON=1 and viafb_dual_fb=1 */
2141 if (!viafb_SAMM_ON)
2142 viafb_dual_fb = 0;
2143
2144 /* Set up I2C bus stuff */
2145 viafb_create_i2c_bus(viaparinfo);
2146
2147 viafb_init_chip_info();
2148 viafb_get_fb_info(&viaparinfo->fbmem, &viaparinfo->memsize);
2149 viaparinfo->fbmem_free = viaparinfo->memsize;
2150 viaparinfo->fbmem_used = 0;
2151 viaparinfo->fbmem_virt = ioremap_nocache(viaparinfo->fbmem,
2152 viaparinfo->memsize);
2153 viafbinfo->screen_base = (char *)viaparinfo->fbmem_virt;
2154
2155 if (!viaparinfo->fbmem_virt) {
2156 printk(KERN_INFO "ioremap failed\n");
2157 return -1;
2158 }
2159
2160 viafb_get_mmio_info(&viaparinfo->mmio_base, &viaparinfo->mmio_len);
2161 viaparinfo->io_virt = ioremap_nocache(viaparinfo->mmio_base,
2162 viaparinfo->mmio_len);
2163
2164 viafbinfo->node = 0;
2165 viafbinfo->fbops = &viafb_ops;
2166 viafbinfo->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
2167
2168 viafbinfo->pseudo_palette = pseudo_pal;
2169 if (viafb_accel) {
2170 viafb_init_accel();
2171 viafb_init_2d_engine();
2172 viafb_hw_cursor_init();
2173 }
2174
2175 if (viafb_second_size && (viafb_second_size < 8)) {
2176 viafb_second_offset = viaparinfo->fbmem_free -
2177 viafb_second_size * 1024 * 1024;
2178 } else {
2179 viafb_second_size = 8;
2180 viafb_second_offset = viaparinfo->fbmem_free -
2181 viafb_second_size * 1024 * 1024;
2182 }
2183
2184 viafb_FB_MM = viaparinfo->fbmem_virt;
2185 tmpm = viafb_mode;
2186 tmpc = strsep(&tmpm, "x");
2187 strict_strtoul(tmpc, 0, (unsigned long *)&default_xres);
2188 strict_strtoul(tmpm, 0, (unsigned long *)&default_yres);
2189
2190 vmode_index = viafb_get_mode_index(default_xres, default_yres, 0);
2191 DEBUG_MSG(KERN_INFO "0->index=%d\n", vmode_index);
2192
2193 if (viafb_SAMM_ON == 1) {
2194 if (strcmp(viafb_mode, viafb_mode1)) {
2195 tmpm_sec = viafb_mode1;
2196 tmpc_sec = strsep(&tmpm_sec, "x");
2197 strict_strtoul(tmpc_sec, 0,
2198 (unsigned long *)&viafb_second_xres);
2199 strict_strtoul(tmpm_sec, 0,
2200 (unsigned long *)&viafb_second_yres);
2201 } else {
2202 viafb_second_xres = default_xres;
2203 viafb_second_yres = default_yres;
2204 }
2205 if (0 == viafb_second_virtual_xres) {
2206 switch (viafb_second_xres) {
2207 case 1400:
2208 viafb_second_virtual_xres = 1408;
2209 break;
2210 default:
2211 viafb_second_virtual_xres = viafb_second_xres;
2212 break;
2213 }
2214 }
2215 if (0 == viafb_second_virtual_yres)
2216 viafb_second_virtual_yres = viafb_second_yres;
2217 }
2218
2219 switch (viafb_bpp) {
2220 case 0 ... 8:
2221 viafb_bpp = 8;
2222 break;
2223 case 9 ... 16:
2224 viafb_bpp = 16;
2225 break;
2226 case 17 ... 32:
2227 viafb_bpp = 32;
2228 break;
2229 default:
2230 viafb_bpp = 8;
2231 }
2232 default_var.xres = default_xres;
2233 default_var.yres = default_yres;
2234 switch (default_xres) {
2235 case 1400:
2236 default_var.xres_virtual = 1408;
2237 break;
2238 default:
2239 default_var.xres_virtual = default_xres;
2240 break;
2241 }
2242 default_var.yres_virtual = default_yres;
2243 default_var.bits_per_pixel = viafb_bpp;
2244 if (default_var.bits_per_pixel == 15)
2245 default_var.bits_per_pixel = 16;
2246 default_var.pixclock =
2247 viafb_get_pixclock(default_xres, default_yres, viafb_refresh);
2248 default_var.left_margin = (default_xres >> 3) & 0xf8;
2249 default_var.right_margin = 32;
2250 default_var.upper_margin = 16;
2251 default_var.lower_margin = 4;
2252 default_var.hsync_len = default_var.left_margin;
2253 default_var.vsync_len = 4;
2254 default_var.accel_flags = 0;
2255
2256 if (viafb_accel) {
2257 viafbinfo->flags |=
2258 (FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
2259 FBINFO_HWACCEL_IMAGEBLIT);
2260 default_var.accel_flags |= FB_ACCELF_TEXT;
2261 } else
2262 viafbinfo->flags |= FBINFO_HWACCEL_DISABLED;
2263
2264 if (viafb_dual_fb) {
2265 viafbinfo1 = framebuffer_alloc(viafb_par_length, NULL);
2266 if (!viafbinfo1) {
2267 printk(KERN_ERR
2268 "allocate the second framebuffer struct error\n");
2269 framebuffer_release(viafbinfo);
2270 return -ENOMEM;
2271 }
2272 viaparinfo1 = viafbinfo1->par;
2273 memcpy(viaparinfo1, viaparinfo, viafb_par_length);
2274 viaparinfo1->memsize = viaparinfo->memsize -
2275 viafb_second_offset;
2276 viaparinfo->memsize = viafb_second_offset;
2277 viaparinfo1->fbmem_virt = viaparinfo->fbmem_virt +
2278 viafb_second_offset;
2279 viaparinfo1->fbmem = viaparinfo->fbmem + viafb_second_offset;
2280
2281 viaparinfo1->fbmem_used = viaparinfo->fbmem_used;
2282 viaparinfo1->fbmem_free = viaparinfo1->memsize -
2283 viaparinfo1->fbmem_used;
2284 viaparinfo->fbmem_free = viaparinfo->memsize;
2285 viaparinfo->fbmem_used = 0;
2286 if (viafb_accel) {
2287 viaparinfo1->cursor_start =
2288 viaparinfo->cursor_start - viafb_second_offset;
2289 viaparinfo1->VQ_start = viaparinfo->VQ_start -
2290 viafb_second_offset;
2291 viaparinfo1->VQ_end = viaparinfo->VQ_end -
2292 viafb_second_offset;
2293 }
2294
2295 memcpy(viafbinfo1, viafbinfo, sizeof(struct fb_info));
2296 viafbinfo1->screen_base = viafbinfo->screen_base +
2297 viafb_second_offset;
2298 viafbinfo1->fix.smem_start = viaparinfo1->fbmem;
2299 viafbinfo1->fix.smem_len = viaparinfo1->fbmem_free;
2300
2301 default_var.xres = viafb_second_xres;
2302 default_var.yres = viafb_second_yres;
2303 default_var.xres_virtual = viafb_second_virtual_xres;
2304 default_var.yres_virtual = viafb_second_virtual_yres;
2305 if (viafb_bpp1 != viafb_bpp)
2306 viafb_bpp1 = viafb_bpp;
2307 default_var.bits_per_pixel = viafb_bpp1;
2308 default_var.pixclock =
2309 viafb_get_pixclock(viafb_second_xres, viafb_second_yres,
2310 viafb_refresh);
2311 default_var.left_margin = (viafb_second_xres >> 3) & 0xf8;
2312 default_var.right_margin = 32;
2313 default_var.upper_margin = 16;
2314 default_var.lower_margin = 4;
2315 default_var.hsync_len = default_var.left_margin;
2316 default_var.vsync_len = 4;
2317
2318 viafb_setup_fixinfo(&viafbinfo1->fix, viaparinfo1);
2319 viafb_check_var(&default_var, viafbinfo1);
2320 viafbinfo1->var = default_var;
2321 viafb_update_viafb_par(viafbinfo);
2322 viafb_update_fix(&viafbinfo1->fix, viafbinfo1);
2323 }
2324
2325 viafb_setup_fixinfo(&viafbinfo->fix, viaparinfo);
2326 viafb_check_var(&default_var, viafbinfo);
2327 viafbinfo->var = default_var;
2328 viafb_update_viafb_par(viafbinfo);
2329 viafb_update_fix(&viafbinfo->fix, viafbinfo);
2330 default_var.activate = FB_ACTIVATE_NOW;
2331 fb_alloc_cmap(&viafbinfo->cmap, 256, 0);
2332
2333 if (viafb_dual_fb && (viafb_primary_dev == LCD_Device)
2334 && (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)) {
2335 if (register_framebuffer(viafbinfo1) < 0)
2336 return -EINVAL;
2337 }
2338 if (register_framebuffer(viafbinfo) < 0)
2339 return -EINVAL;
2340
2341 if (viafb_dual_fb && ((viafb_primary_dev != LCD_Device)
2342 || (viaparinfo->chip_info->gfx_chip_name !=
2343 UNICHROME_CLE266))) {
2344 if (register_framebuffer(viafbinfo1) < 0)
2345 return -EINVAL;
2346 }
2347 DEBUG_MSG(KERN_INFO "fb%d: %s frame buffer device %dx%d-%dbpp\n",
2348 viafbinfo->node, viafbinfo->fix.id, default_var.xres,
2349 default_var.yres, default_var.bits_per_pixel);
2350
2351 viafb_init_proc(viaparinfo->proc_entry);
2352 viafb_init_dac(IGA2);
2353 return 0;
2354}
2355
2356static void __devexit via_pci_remove(void)
2357{
2358 DEBUG_MSG(KERN_INFO "via_pci_remove!\n");
2359 fb_dealloc_cmap(&viafbinfo->cmap);
2360 unregister_framebuffer(viafbinfo);
2361 if (viafb_dual_fb)
2362 unregister_framebuffer(viafbinfo1);
2363 iounmap((void *)viaparinfo->fbmem_virt);
2364 iounmap(viaparinfo->io_virt);
2365
2366 viafb_delete_i2c_buss(viaparinfo);
2367
2368 framebuffer_release(viafbinfo);
2369 if (viafb_dual_fb)
2370 framebuffer_release(viafbinfo1);
2371
2372 viafb_remove_proc(viaparinfo->proc_entry);
2373}
2374
2375#ifndef MODULE
2376static int __init viafb_setup(char *options)
2377{
2378 char *this_opt;
2379 DEBUG_MSG(KERN_INFO "viafb_setup!\n");
2380
2381 if (!options || !*options)
2382 return 0;
2383
2384 while ((this_opt = strsep(&options, ",")) != NULL) {
2385 if (!*this_opt)
2386 continue;
2387
2388 if (!strncmp(this_opt, "viafb_mode1=", 12))
2389 viafb_mode1 = kstrdup(this_opt + 12, GFP_KERNEL);
2390 else if (!strncmp(this_opt, "viafb_mode=", 11))
2391 viafb_mode = kstrdup(this_opt + 11, GFP_KERNEL);
2392 else if (!strncmp(this_opt, "viafb_bpp1=", 11))
2393 strict_strtoul(this_opt + 11, 0,
2394 (unsigned long *)&viafb_bpp1);
2395 else if (!strncmp(this_opt, "viafb_bpp=", 10))
2396 strict_strtoul(this_opt + 10, 0,
2397 (unsigned long *)&viafb_bpp);
2398 else if (!strncmp(this_opt, "viafb_refresh1=", 15))
2399 strict_strtoul(this_opt + 15, 0,
2400 (unsigned long *)&viafb_refresh1);
2401 else if (!strncmp(this_opt, "viafb_refresh=", 14))
2402 strict_strtoul(this_opt + 14, 0,
2403 (unsigned long *)&viafb_refresh);
2404 else if (!strncmp(this_opt, "viafb_lcd_dsp_method=", 21))
2405 strict_strtoul(this_opt + 21, 0,
2406 (unsigned long *)&viafb_lcd_dsp_method);
2407 else if (!strncmp(this_opt, "viafb_lcd_panel_id=", 19))
2408 strict_strtoul(this_opt + 19, 0,
2409 (unsigned long *)&viafb_lcd_panel_id);
2410 else if (!strncmp(this_opt, "viafb_accel=", 12))
2411 strict_strtoul(this_opt + 12, 0,
2412 (unsigned long *)&viafb_accel);
2413 else if (!strncmp(this_opt, "viafb_SAMM_ON=", 14))
2414 strict_strtoul(this_opt + 14, 0,
2415 (unsigned long *)&viafb_SAMM_ON);
2416 else if (!strncmp(this_opt, "viafb_active_dev=", 17))
2417 viafb_active_dev = kstrdup(this_opt + 17, GFP_KERNEL);
2418 else if (!strncmp(this_opt,
2419 "viafb_display_hardware_layout=", 30))
2420 strict_strtoul(this_opt + 30, 0,
2421 (unsigned long *)&viafb_display_hardware_layout);
2422 else if (!strncmp(this_opt, "viafb_second_size=", 18))
2423 strict_strtoul(this_opt + 18, 0,
2424 (unsigned long *)&viafb_second_size);
2425 else if (!strncmp(this_opt,
2426 "viafb_platform_epia_dvi=", 24))
2427 strict_strtoul(this_opt + 24, 0,
2428 (unsigned long *)&viafb_platform_epia_dvi);
2429 else if (!strncmp(this_opt,
2430 "viafb_device_lcd_dualedge=", 26))
2431 strict_strtoul(this_opt + 26, 0,
2432 (unsigned long *)&viafb_device_lcd_dualedge);
2433 else if (!strncmp(this_opt, "viafb_bus_width=", 16))
2434 strict_strtoul(this_opt + 16, 0,
2435 (unsigned long *)&viafb_bus_width);
2436 else if (!strncmp(this_opt, "viafb_lcd_mode=", 15))
2437 strict_strtoul(this_opt + 15, 0,
2438 (unsigned long *)&viafb_lcd_mode);
2439 else if (!strncmp(this_opt, "viafb_video_dev=", 16))
2440 viafb_video_dev = kstrdup(this_opt + 16, GFP_KERNEL);
2441 else if (!strncmp(this_opt, "viafb_lcd_port=", 15))
2442 viafb_lcd_port = kstrdup(this_opt + 15, GFP_KERNEL);
2443 else if (!strncmp(this_opt, "viafb_dvi_port=", 15))
2444 viafb_dvi_port = kstrdup(this_opt + 15, GFP_KERNEL);
2445 }
2446 return 0;
2447}
2448#endif
2449
2450static int __init viafb_init(void)
2451{
2452#ifndef MODULE
2453 char *option = NULL;
2454 if (fb_get_options("viafb", &option))
2455 return -ENODEV;
2456 viafb_setup(option);
2457#endif
2458 printk(KERN_INFO
2459 "VIA Graphics Intergration Chipset framebuffer %d.%d initializing\n",
2460 VERSION_MAJOR, VERSION_MINOR);
2461 return via_pci_probe();
2462}
2463
2464static void __exit viafb_exit(void)
2465{
2466 DEBUG_MSG(KERN_INFO "viafb_exit!\n");
2467 via_pci_remove();
2468}
2469
2470static struct fb_ops viafb_ops = {
2471 .owner = THIS_MODULE,
2472 .fb_open = viafb_open,
2473 .fb_release = viafb_release,
2474 .fb_check_var = viafb_check_var,
2475 .fb_set_par = viafb_set_par,
2476 .fb_setcolreg = viafb_setcolreg,
2477 .fb_pan_display = viafb_pan_display,
2478 .fb_blank = viafb_blank,
2479 .fb_fillrect = viafb_fillrect,
2480 .fb_copyarea = viafb_copyarea,
2481 .fb_imageblit = viafb_imageblit,
2482 .fb_cursor = viafb_cursor,
2483 .fb_ioctl = viafb_ioctl,
2484 .fb_sync = viafb_sync,
2485 .fb_setcmap = viafb_setcmap,
2486};
2487
2488module_init(viafb_init);
2489module_exit(viafb_exit);
2490
2491#ifdef MODULE
2492module_param(viafb_memsize, int, 0);
2493
2494module_param(viafb_mode, charp, 0);
2495MODULE_PARM_DESC(viafb_mode, "Set resolution (default=640x480)");
2496
2497module_param(viafb_mode1, charp, 0);
2498MODULE_PARM_DESC(viafb_mode1, "Set resolution (default=640x480)");
2499
2500module_param(viafb_bpp, int, 0);
2501MODULE_PARM_DESC(viafb_bpp, "Set color depth (default=32bpp)");
2502
2503module_param(viafb_bpp1, int, 0);
2504MODULE_PARM_DESC(viafb_bpp1, "Set color depth (default=32bpp)");
2505
2506module_param(viafb_refresh, int, 0);
2507MODULE_PARM_DESC(viafb_refresh,
2508 "Set CRT viafb_refresh rate (default = 60)");
2509
2510module_param(viafb_refresh1, int, 0);
2511MODULE_PARM_DESC(viafb_refresh1,
2512 "Set CRT refresh rate (default = 60)");
2513
2514module_param(viafb_lcd_panel_id, int, 0);
2515MODULE_PARM_DESC(viafb_lcd_panel_id,
2516 "Set Flat Panel type(Default=1024x768)");
2517
2518module_param(viafb_lcd_dsp_method, int, 0);
2519MODULE_PARM_DESC(viafb_lcd_dsp_method,
2520 "Set Flat Panel display scaling method.(Default=Expandsion)");
2521
2522module_param(viafb_SAMM_ON, int, 0);
2523MODULE_PARM_DESC(viafb_SAMM_ON,
2524 "Turn on/off flag of SAMM(Default=OFF)");
2525
2526module_param(viafb_accel, int, 0);
2527MODULE_PARM_DESC(viafb_accel,
2528 "Set 2D Hardware Acceleration.(Default = OFF)");
2529
2530module_param(viafb_active_dev, charp, 0);
2531MODULE_PARM_DESC(viafb_active_dev, "Specify active devices.");
2532
2533module_param(viafb_display_hardware_layout, int, 0);
2534MODULE_PARM_DESC(viafb_display_hardware_layout,
2535 "Display Hardware Layout (LCD Only, DVI Only...,etc)");
2536
2537module_param(viafb_second_size, int, 0);
2538MODULE_PARM_DESC(viafb_second_size,
2539 "Set secondary device memory size");
2540
2541module_param(viafb_dual_fb, int, 0);
2542MODULE_PARM_DESC(viafb_dual_fb,
2543 "Turn on/off flag of dual framebuffer devices.(Default = OFF)");
2544
2545module_param(viafb_platform_epia_dvi, int, 0);
2546MODULE_PARM_DESC(viafb_platform_epia_dvi,
2547 "Turn on/off flag of DVI devices on EPIA board.(Default = OFF)");
2548
2549module_param(viafb_device_lcd_dualedge, int, 0);
2550MODULE_PARM_DESC(viafb_device_lcd_dualedge,
2551 "Turn on/off flag of dual edge panel.(Default = OFF)");
2552
2553module_param(viafb_bus_width, int, 0);
2554MODULE_PARM_DESC(viafb_bus_width,
2555 "Set bus width of panel.(Default = 12)");
2556
2557module_param(viafb_lcd_mode, int, 0);
2558MODULE_PARM_DESC(viafb_lcd_mode,
2559 "Set Flat Panel mode(Default=OPENLDI)");
2560
2561module_param(viafb_video_dev, charp, 0);
2562MODULE_PARM_DESC(viafb_video_dev, "Specify video devices.");
2563
2564module_param(viafb_lcd_port, charp, 0);
2565MODULE_PARM_DESC(viafb_lcd_port, "Specify LCD output port.");
2566
2567module_param(viafb_dvi_port, charp, 0);
2568MODULE_PARM_DESC(viafb_dvi_port, "Specify DVI output port.");
2569
2570MODULE_LICENSE("GPL");
2571#endif
diff --git a/drivers/video/via/viafbdev.h b/drivers/video/via/viafbdev.h
new file mode 100644
index 000000000000..a4158e872878
--- /dev/null
+++ b/drivers/video/via/viafbdev.h
@@ -0,0 +1,112 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __VIAFBDEV_H__
23#define __VIAFBDEV_H__
24
25#include <linux/proc_fs.h>
26#include <linux/fb.h>
27
28#include "ioctl.h"
29#include "share.h"
30#include "chip.h"
31#include "hw.h"
32#include "via_i2c.h"
33
34#define VERSION_MAJOR 2
35#define VERSION_KERNEL 6 /* For kernel 2.6 */
36
37#define VERSION_OS 0 /* 0: for 32 bits OS, 1: for 64 bits OS */
38#define VERSION_MINOR 4
39
40struct viafb_par {
41 int bpp;
42 int hres;
43 int vres;
44 int linelength;
45 u32 xoffset;
46 u32 yoffset;
47
48 void __iomem *fbmem_virt; /*framebuffer virtual memory address */
49 void __iomem *io_virt; /*iospace virtual memory address */
50 unsigned int fbmem; /*framebuffer physical memory address */
51 unsigned int memsize; /*size of fbmem */
52 unsigned int io; /*io space address */
53 unsigned long mmio_base; /*mmio base address */
54 unsigned long mmio_len; /*mmio base length */
55 u32 fbmem_free; /* Free FB memory */
56 u32 fbmem_used; /* Use FB memory size */
57 u32 cursor_start; /* Cursor Start Address */
58 u32 VQ_start; /* Virtual Queue Start Address */
59 u32 VQ_end; /* Virtual Queue End Address */
60 u32 iga_path;
61 struct proc_dir_entry *proc_entry; /*viafb proc entry */
62 u8 duoview; /*Is working in duoview mode? */
63
64 /* I2C stuff */
65 struct via_i2c_stuff i2c_stuff;
66
67 /* All the information will be needed to set engine */
68 struct tmds_setting_information *tmds_setting_info;
69 struct crt_setting_information *crt_setting_info;
70 struct lvds_setting_information *lvds_setting_info;
71 struct lvds_setting_information *lvds_setting_info2;
72 struct chip_information *chip_info;
73
74 /* some information related to video playing */
75 int video_on_crt;
76 int video_on_dvi;
77 int video_on_lcd;
78
79};
80struct viafb_modeinfo {
81 u32 xres;
82 u32 yres;
83 int mode_index;
84 char *mode_res;
85};
86extern unsigned int viafb_second_virtual_yres;
87extern unsigned int viafb_second_virtual_xres;
88extern unsigned int viafb_second_offset;
89extern int viafb_second_size;
90extern int viafb_SAMM_ON;
91extern int viafb_dual_fb;
92extern int viafb_LCD2_ON;
93extern int viafb_LCD_ON;
94extern int viafb_DVI_ON;
95extern int viafb_accel;
96extern int viafb_hotplug;
97extern int viafb_memsize;
98
99extern int strict_strtoul(const char *cp, unsigned int base,
100 unsigned long *res);
101
102void viafb_memory_pitch_patch(struct fb_info *info);
103void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
104 int mode_index);
105int viafb_get_mode_index(int hres, int vres, int flag);
106u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
107 *plvds_setting_info, struct lvds_chip_information
108 *plvds_chip_info, u8 index);
109void viafb_gpio_i2c_write_mask_lvds(struct lvds_setting_information
110 *plvds_setting_info, struct lvds_chip_information
111 *plvds_chip_info, struct IODATA io_data);
112#endif /* __VIAFBDEV_H__ */
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
new file mode 100644
index 000000000000..6dcf583a837d
--- /dev/null
+++ b/drivers/video/via/viamode.c
@@ -0,0 +1,1086 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23struct res_map_refresh res_map_refresh_tbl[] = {
24/*hres, vres, vclock, vmode_refresh*/
25 {480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
26 {640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
27 {640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
28 {640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
29 {640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
30 {640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
31 {720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
32 {720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
33 {800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
34 {800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
35 {800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
36 {800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
37 {800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
38 {800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
39 {848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
40 {856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
41 {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
42 {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
43 {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
44 {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
45 {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
46 {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
47/* {1152,864, RES_1152X864_70HZ_PIXCLOCK, 70},*/
48 {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
49 {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
50 {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
51 {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
52 {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
53 {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
54 {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
55 {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
56 {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
57 {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
58 {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
59 {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
60 {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
61 {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
62 {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
63 {960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
64 {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
65 {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
66 {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
67 {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
68 {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
69 {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
70 {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
71 {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
72 {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
73 {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
74 {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
75 {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
76 {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
77 {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
78 {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
79 {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
80 {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
81 {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
82 {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
83 {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
84 {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
85 {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
86 {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
87};
88
89struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
90{VIASR, SR15, 0x02, 0x02},
91{VIASR, SR16, 0xBF, 0x08},
92{VIASR, SR17, 0xFF, 0x1F},
93{VIASR, SR18, 0xFF, 0x4E},
94{VIASR, SR1A, 0xFB, 0x08},
95{VIASR, SR1E, 0x0F, 0x01},
96{VIASR, SR2A, 0xFF, 0x00},
97{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
98{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
99{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
100{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
101{VIACR, CR32, 0xFF, 0x00},
102{VIACR, CR33, 0xFF, 0x00},
103{VIACR, CR34, 0xFF, 0x00},
104{VIACR, CR35, 0xFF, 0x00},
105{VIACR, CR36, 0x08, 0x00},
106{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
107{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
108{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
109{VIACR, CR69, 0xFF, 0x00},
110{VIACR, CR6A, 0xFF, 0x40},
111{VIACR, CR6B, 0xFF, 0x00},
112{VIACR, CR6C, 0xFF, 0x00},
113{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
114{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
115{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
116{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
117{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
118{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
119{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
120{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
121{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
122{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
123{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
124{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
125{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
126{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
127{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
128{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
129{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
130{VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */
131{VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */
132{VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */
133{VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */
134{VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */
135{VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */
136{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
137{VIACR, CR96, 0xFF, 0x00},
138{VIACR, CR97, 0xFF, 0x00},
139{VIACR, CR99, 0xFF, 0x00},
140{VIACR, CR9B, 0xFF, 0x00}
141};
142
143/* Video Mode Table for VT3314 chipset*/
144/* Common Setting for Video Mode */
145struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
146{VIASR, SR15, 0x02, 0x02},
147{VIASR, SR16, 0xBF, 0x08},
148{VIASR, SR17, 0xFF, 0x1F},
149{VIASR, SR18, 0xFF, 0x4E},
150{VIASR, SR1A, 0xFB, 0x82},
151{VIASR, SR1B, 0xFF, 0xF0},
152{VIASR, SR1F, 0xFF, 0x00},
153{VIASR, SR1E, 0xFF, 0x01},
154{VIASR, SR22, 0xFF, 0x1F},
155{VIASR, SR2A, 0x0F, 0x00},
156{VIASR, SR2E, 0xFF, 0xFF},
157{VIASR, SR3F, 0xFF, 0xFF},
158{VIASR, SR40, 0xF7, 0x00},
159{VIASR, CR30, 0xFF, 0x04},
160{VIACR, CR32, 0xFF, 0x00},
161{VIACR, CR33, 0x7F, 0x00},
162{VIACR, CR34, 0xFF, 0x00},
163{VIACR, CR35, 0xFF, 0x00},
164{VIACR, CR36, 0xFF, 0x31},
165{VIACR, CR41, 0xFF, 0x80},
166{VIACR, CR42, 0xFF, 0x00},
167{VIACR, CR55, 0x80, 0x00},
168{VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/
169{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
170{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
171{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
172{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
173{VIACR, CR69, 0xFF, 0x00},
174{VIACR, CR6A, 0xFD, 0x40},
175{VIACR, CR6B, 0xFF, 0x00},
176{VIACR, CR6C, 0xFF, 0x00},
177{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */
178{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */
179{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */
180{VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */
181{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
182{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
183{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
184{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
185{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
186{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
187{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
188{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
189{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
190{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
191{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
192{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
193{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
194{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
195{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
196{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
197{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
198{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
199{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
200{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
201{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
202{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
203{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
204{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
205{VIACR, CR96, 0xFF, 0x00},
206{VIACR, CR97, 0xFF, 0x00},
207{VIACR, CR99, 0xFF, 0x00},
208{VIACR, CR9B, 0xFF, 0x00},
209{VIACR, CR9D, 0xFF, 0x80},
210{VIACR, CR9E, 0xFF, 0x80}
211};
212
213struct io_reg KM400_ModeXregs[] = {
214 {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
215 {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
216 {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
217 {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
218 {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
219 {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
220 {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
221 {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */
222 {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
223 {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
224 {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
225 {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */
226 {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
227 {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
228 {VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
229 {VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
230 {VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
231 {VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
232 {VIACR, CR33, 0xFF, 0x00},
233 {VIACR, CR55, 0x80, 0x00},
234 {VIACR, CR5D, 0x80, 0x00},
235 {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */
236 {VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
237 {VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
238 {VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
239 {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
240 {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */
241 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
242 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
243 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
244 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
245 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
246 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
247 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
248 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
249 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
250 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
251 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
252 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
253 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
254 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
255 {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
256 {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
257 {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
258 {VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */
259 {VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */
260 {VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */
261 {VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */
262 {VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */
263 {VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */
264 {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
265 {VIACR, CR96, 0xFF, 0x03}, /* DVP0 ; DVP0 Clock Skew */
266 {VIACR, CR97, 0xFF, 0x03}, /* DFP high ; DFPH Clock Skew */
267 {VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/
268 {VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew*/
269};
270
271/* For VT3324: Common Setting for Video Mode */
272struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
273{VIASR, SR15, 0x02, 0x02},
274{VIASR, SR16, 0xBF, 0x08},
275{VIASR, SR17, 0xFF, 0x1F},
276{VIASR, SR18, 0xFF, 0x4E},
277{VIASR, SR1A, 0xFB, 0x08},
278{VIASR, SR1B, 0xFF, 0xF0},
279{VIASR, SR1E, 0xFF, 0x01},
280{VIASR, SR2A, 0xFF, 0x00},
281{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
282{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
283{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
284{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
285{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
286{VIACR, CR32, 0xFF, 0x00},
287{VIACR, CR33, 0xFF, 0x00},
288{VIACR, CR34, 0xFF, 0x00},
289{VIACR, CR35, 0xFF, 0x00},
290{VIACR, CR36, 0x08, 0x00},
291{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
292{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
293{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
294{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
295{VIACR, CRA3, 0xFF, 0x00}, /* Secondary Display Starting Address */
296{VIACR, CR69, 0xFF, 0x00},
297{VIACR, CR6A, 0xFF, 0x40},
298{VIACR, CR6B, 0xFF, 0x00},
299{VIACR, CR6C, 0xFF, 0x00},
300{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
301{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
302{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
303{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
304{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
305{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
306{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
307{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
308{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
309{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
310{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
311{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
312{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
313{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
314{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
315{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
316{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
317{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
318{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
319{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
320{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
321{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
322{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
323{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
324{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
325{VIACR, CR96, 0xFF, 0x00},
326{VIACR, CR97, 0xFF, 0x00},
327{VIACR, CR99, 0xFF, 0x00},
328{VIACR, CR9B, 0xFF, 0x00},
329{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
330};
331
332/* For VT3353: Common Setting for Video Mode */
333struct io_reg VX800_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
334{VIASR, SR15, 0x02, 0x02},
335{VIASR, SR16, 0xBF, 0x08},
336{VIASR, SR17, 0xFF, 0x1F},
337{VIASR, SR18, 0xFF, 0x4E},
338{VIASR, SR1A, 0xFB, 0x08},
339{VIASR, SR1B, 0xFF, 0xF0},
340{VIASR, SR1E, 0xFF, 0x01},
341{VIASR, SR2A, 0xFF, 0x00},
342{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
343{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
344{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
345{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
346{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
347{VIACR, CR32, 0xFF, 0x00},
348{VIACR, CR33, 0xFF, 0x00},
349{VIACR, CR34, 0xFF, 0x00},
350{VIACR, CR35, 0xFF, 0x00},
351{VIACR, CR36, 0x08, 0x00},
352{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
353{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
354{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
355{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
356{VIACR, CRA3, 0xFF, 0x00}, /* Secondary Display Starting Address */
357{VIACR, CR69, 0xFF, 0x00},
358{VIACR, CR6A, 0xFF, 0x40},
359{VIACR, CR6B, 0xFF, 0x00},
360{VIACR, CR6C, 0xFF, 0x00},
361{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
362{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
363{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
364{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
365{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
366{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
367{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
368{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
369{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
370{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
371{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
372{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
373{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
374{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
375{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
376{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
377{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
378{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
379{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
380{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
381{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
382{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
383{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
384{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
385{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
386{VIACR, CR96, 0xFF, 0x00},
387{VIACR, CR97, 0xFF, 0x00},
388{VIACR, CR99, 0xFF, 0x00},
389{VIACR, CR9B, 0xFF, 0x00},
390{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
391};
392
393/* Video Mode Table */
394/* Common Setting for Video Mode */
395struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
396{VIASR, SR2A, 0x0F, 0x00},
397{VIASR, SR15, 0x02, 0x02},
398{VIASR, SR16, 0xBF, 0x08},
399{VIASR, SR17, 0xFF, 0x1F},
400{VIASR, SR18, 0xFF, 0x4E},
401{VIASR, SR1A, 0xFB, 0x08},
402
403{VIACR, CR32, 0xFF, 0x00},
404{VIACR, CR34, 0xFF, 0x00},
405{VIACR, CR35, 0xFF, 0x00},
406{VIACR, CR36, 0x08, 0x00},
407{VIACR, CR6A, 0xFF, 0x80},
408{VIACR, CR6A, 0xFF, 0xC0},
409
410{VIACR, CR55, 0x80, 0x00},
411{VIACR, CR5D, 0x80, 0x00},
412
413{VIAGR, GR20, 0xFF, 0x00},
414{VIAGR, GR21, 0xFF, 0x00},
415{VIAGR, GR22, 0xFF, 0x00},
416 /* LCD Parameters */
417{VIACR, CR7A, 0xFF, 0x01}, /* LCD Parameter 1 */
418{VIACR, CR7B, 0xFF, 0x02}, /* LCD Parameter 2 */
419{VIACR, CR7C, 0xFF, 0x03}, /* LCD Parameter 3 */
420{VIACR, CR7D, 0xFF, 0x04}, /* LCD Parameter 4 */
421{VIACR, CR7E, 0xFF, 0x07}, /* LCD Parameter 5 */
422{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Parameter 6 */
423{VIACR, CR80, 0xFF, 0x0D}, /* LCD Parameter 7 */
424{VIACR, CR81, 0xFF, 0x13}, /* LCD Parameter 8 */
425{VIACR, CR82, 0xFF, 0x16}, /* LCD Parameter 9 */
426{VIACR, CR83, 0xFF, 0x19}, /* LCD Parameter 10 */
427{VIACR, CR84, 0xFF, 0x1C}, /* LCD Parameter 11 */
428{VIACR, CR85, 0xFF, 0x1D}, /* LCD Parameter 12 */
429{VIACR, CR86, 0xFF, 0x1E}, /* LCD Parameter 13 */
430{VIACR, CR87, 0xFF, 0x1F}, /* LCD Parameter 14 */
431
432};
433
434/* Mode:1024X768 */
435struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
436{VIASR, 0x18, 0xFF, 0x4C}
437};
438
439struct patch_table res_patch_table[] = {
440 {VIA_RES_1024X768, ARRAY_SIZE(PM1024x768), PM1024x768}
441};
442
443/* struct VPITTable {
444 unsigned char Misc;
445 unsigned char SR[StdSR];
446 unsigned char CR[StdCR];
447 unsigned char GR[StdGR];
448 unsigned char AR[StdAR];
449 };*/
450
451struct VPITTable VPIT = {
452 /* Msic */
453 0xC7,
454 /* Sequencer */
455 {0x01, 0x0F, 0x00, 0x0E},
456 /* Graphic Controller */
457 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
458 /* Attribute Controller */
459 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
460 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
461 0x01, 0x00, 0x0F, 0x00}
462};
463
464/********************/
465/* Mode Table */
466/********************/
467
468/* 480x640 */
469struct crt_mode_table CRTM480x640[] = {
470 /* r_rate, vclk, hsp, vsp */
471 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
472 {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP,
473 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/
474};
475
476/* 640x480*/
477struct crt_mode_table CRTM640x480[] = {
478 /*r_rate,vclk,hsp,vsp */
479 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
480 {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP,
481 {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
482 {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP,
483 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
484 {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP,
485 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
486 {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP,
487 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
488 {REFRESH_120, CLK_52_406M, M640X480_R120_HSP,
489 M640X480_R120_VSP,
490 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481,
491 3} } /*GTF*/
492};
493
494/*720x480 (GTF)*/
495struct crt_mode_table CRTM720x480[] = {
496 /*r_rate,vclk,hsp,vsp */
497 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
498 {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP,
499 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
500
501};
502
503/*720x576 (GTF)*/
504struct crt_mode_table CRTM720x576[] = {
505 /*r_rate,vclk,hsp,vsp */
506 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
507 {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP,
508 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
509};
510
511/* 800x480 (CVT) */
512struct crt_mode_table CRTM800x480[] = {
513 /* r_rate, vclk, hsp, vsp */
514 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
515 {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP,
516 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
517};
518
519/* 800x600*/
520struct crt_mode_table CRTM800x600[] = {
521 /*r_rate,vclk,hsp,vsp */
522 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
523 {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP,
524 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
525 {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP,
526 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
527 {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP,
528 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
529 {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP,
530 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
531 {REFRESH_120, CLK_83_950M, M800X600_R120_HSP,
532 M800X600_R120_VSP,
533 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601,
534 3} }
535};
536
537/* 848x480 (CVT) */
538struct crt_mode_table CRTM848x480[] = {
539 /* r_rate, vclk, hsp, vsp */
540 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
541 {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP,
542 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
543};
544
545/*856x480 (GTF) convert to 852x480*/
546struct crt_mode_table CRTM852x480[] = {
547 /*r_rate,vclk,hsp,vsp */
548 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
549 {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP,
550 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
551};
552
553/*1024x512 (GTF)*/
554struct crt_mode_table CRTM1024x512[] = {
555 /*r_rate,vclk,hsp,vsp */
556 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
557 {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP,
558 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
559
560};
561
562/* 1024x600*/
563struct crt_mode_table CRTM1024x600[] = {
564 /*r_rate,vclk,hsp,vsp */
565 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
566 {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP,
567 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
568};
569
570/* 1024x768*/
571struct crt_mode_table CRTM1024x768[] = {
572 /*r_rate,vclk,hsp,vsp */
573 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
574 {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP,
575 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
576 {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP,
577 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
578 {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP,
579 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
580 {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP,
581 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
582};
583
584/* 1152x864*/
585struct crt_mode_table CRTM1152x864[] = {
586 /*r_rate,vclk,hsp,vsp */
587 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
588 {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP,
589 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
590
591};
592
593/* 1280x720 (HDMI 720P)*/
594struct crt_mode_table CRTM1280x720[] = {
595 /*r_rate,vclk,hsp,vsp */
596 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
597 {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP,
598 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
599 {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP,
600 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
601};
602
603/*1280x768 (GTF)*/
604struct crt_mode_table CRTM1280x768[] = {
605 /*r_rate,vclk,hsp,vsp */
606 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
607 {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP,
608 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
609 {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP,
610 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
611};
612
613/* 1280x800 (CVT) */
614struct crt_mode_table CRTM1280x800[] = {
615 /* r_rate, vclk, hsp, vsp */
616 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
617 {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP,
618 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
619};
620
621/*1280x960*/
622struct crt_mode_table CRTM1280x960[] = {
623 /*r_rate,vclk,hsp,vsp */
624 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
625 {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP,
626 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
627};
628
629/* 1280x1024*/
630struct crt_mode_table CRTM1280x1024[] = {
631 /*r_rate,vclk,,hsp,vsp */
632 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
633 {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
634 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
635 3} },
636 {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
637 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
638 3} },
639 {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
640 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
641};
642
643/* 1368x768 (GTF) */
644struct crt_mode_table CRTM1368x768[] = {
645 /* r_rate, vclk, hsp, vsp */
646 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
647 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
648 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
649};
650
651/*1440x1050 (GTF)*/
652struct crt_mode_table CRTM1440x1050[] = {
653 /*r_rate,vclk,hsp,vsp */
654 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
655 {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
656 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
657};
658
659/* 1600x1200*/
660struct crt_mode_table CRTM1600x1200[] = {
661 /*r_rate,vclk,hsp,vsp */
662 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
663 {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
664 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
665 3} },
666 {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
667 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
668
669};
670
671/* 1680x1050 (CVT) */
672struct crt_mode_table CRTM1680x1050[] = {
673 /* r_rate, vclk, hsp, vsp */
674 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
675 {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
676 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
677 6} },
678 {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
679 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
680};
681
682/* 1680x1050 (CVT Reduce Blanking) */
683struct crt_mode_table CRTM1680x1050_RB[] = {
684 /* r_rate, vclk, hsp, vsp */
685 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
686 {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP,
687 M1680x1050_RB_R60_VSP,
688 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
689};
690
691/* 1920x1080 (CVT)*/
692struct crt_mode_table CRTM1920x1080[] = {
693 /*r_rate,vclk,hsp,vsp */
694 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
695 {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
696 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
697};
698
699/* 1920x1080 (CVT with Reduce Blanking) */
700struct crt_mode_table CRTM1920x1080_RB[] = {
701 /* r_rate, vclk, hsp, vsp */
702 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
703 {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP,
704 M1920X1080_RB_R60_VSP,
705 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
706};
707
708/* 1920x1440*/
709struct crt_mode_table CRTM1920x1440[] = {
710 /*r_rate,vclk,hsp,vsp */
711 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
712 {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
713 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
714 3} },
715 {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
716 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
717};
718
719/* 1400x1050 (CVT) */
720struct crt_mode_table CRTM1400x1050[] = {
721 /* r_rate, vclk, hsp, vsp */
722 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
723 {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
724 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
725 4} },
726 {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
727 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
728};
729
730/* 1400x1050 (CVT Reduce Blanking) */
731struct crt_mode_table CRTM1400x1050_RB[] = {
732 /* r_rate, vclk, hsp, vsp */
733 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
734 {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP,
735 M1400X1050_RB_R60_VSP,
736 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
737};
738
739/* 960x600 (CVT) */
740struct crt_mode_table CRTM960x600[] = {
741 /* r_rate, vclk, hsp, vsp */
742 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
743 {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP,
744 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
745};
746
747/* 1000x600 (GTF) */
748struct crt_mode_table CRTM1000x600[] = {
749 /* r_rate, vclk, hsp, vsp */
750 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
751 {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP,
752 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
753};
754
755/* 1024x576 (GTF) */
756struct crt_mode_table CRTM1024x576[] = {
757 /* r_rate, vclk, hsp, vsp */
758 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
759 {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP,
760 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
761};
762
763/* 1088x612 (CVT) */
764struct crt_mode_table CRTM1088x612[] = {
765 /* r_rate, vclk, hsp, vsp */
766 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
767 {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP,
768 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
769};
770
771/* 1152x720 (CVT) */
772struct crt_mode_table CRTM1152x720[] = {
773 /* r_rate, vclk, hsp, vsp */
774 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
775 {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP,
776 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
777};
778
779/* 1200x720 (GTF) */
780struct crt_mode_table CRTM1200x720[] = {
781 /* r_rate, vclk, hsp, vsp */
782 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
783 {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP,
784 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
785};
786
787/* 1280x600 (GTF) */
788struct crt_mode_table CRTM1280x600[] = {
789 /* r_rate, vclk, hsp, vsp */
790 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
791 {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP,
792 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
793};
794
795/* 1360x768 (CVT) */
796struct crt_mode_table CRTM1360x768[] = {
797 /* r_rate, vclk, hsp, vsp */
798 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
799 {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP,
800 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
801};
802
803/* 1360x768 (CVT Reduce Blanking) */
804struct crt_mode_table CRTM1360x768_RB[] = {
805 /* r_rate, vclk, hsp, vsp */
806 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
807 {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP,
808 M1360X768_RB_R60_VSP,
809 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
810};
811
812/* 1366x768 (GTF) */
813struct crt_mode_table CRTM1366x768[] = {
814 /* r_rate, vclk, hsp, vsp */
815 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
816 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
817 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
818 {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP,
819 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
820};
821
822/* 1440x900 (CVT) */
823struct crt_mode_table CRTM1440x900[] = {
824 /* r_rate, vclk, hsp, vsp */
825 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
826 {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP,
827 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
828 {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP,
829 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
830};
831
832/* 1440x900 (CVT Reduce Blanking) */
833struct crt_mode_table CRTM1440x900_RB[] = {
834 /* r_rate, vclk, hsp, vsp */
835 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
836 {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP,
837 M1440X900_RB_R60_VSP,
838 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
839};
840
841/* 1600x900 (CVT) */
842struct crt_mode_table CRTM1600x900[] = {
843 /* r_rate, vclk, hsp, vsp */
844 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
845 {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP,
846 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
847};
848
849/* 1600x900 (CVT Reduce Blanking) */
850struct crt_mode_table CRTM1600x900_RB[] = {
851 /* r_rate, vclk, hsp, vsp */
852 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
853 {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP,
854 M1600X900_RB_R60_VSP,
855 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
856};
857
858/* 1600x1024 (GTF) */
859struct crt_mode_table CRTM1600x1024[] = {
860 /* r_rate, vclk, hsp, vsp */
861 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
862 {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
863 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
864};
865
866/* 1792x1344 (DMT) */
867struct crt_mode_table CRTM1792x1344[] = {
868 /* r_rate, vclk, hsp, vsp */
869 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
870 {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
871 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
872};
873
874/* 1856x1392 (DMT) */
875struct crt_mode_table CRTM1856x1392[] = {
876 /* r_rate, vclk, hsp, vsp */
877 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
878 {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
879 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
880};
881
882/* 1920x1200 (CVT) */
883struct crt_mode_table CRTM1920x1200[] = {
884 /* r_rate, vclk, hsp, vsp */
885 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
886 {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
887 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
888};
889
890/* 1920x1200 (CVT with Reduce Blanking) */
891struct crt_mode_table CRTM1920x1200_RB[] = {
892 /* r_rate, vclk, hsp, vsp */
893 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
894 {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP,
895 M1920X1200_RB_R60_VSP,
896 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
897};
898
899/* 2048x1536 (CVT) */
900struct crt_mode_table CRTM2048x1536[] = {
901 /* r_rate, vclk, hsp, vsp */
902 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
903 {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
904 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
905};
906
907/* Video Mode Table */
908/* struct VideoModeTable {*/
909/* int ModeIndex;*/
910/* struct crt_mode_table *crtc;*/
911/* int mode_array;*/
912/* };*/
913struct VideoModeTable CLE266Modes[] = {
914 /* Display : 480x640 (GTF) */
915 {VIA_RES_480X640, CRTM480x640, ARRAY_SIZE(CRTM480x640)},
916
917 /* Display : 640x480 */
918 {VIA_RES_640X480, CRTM640x480, ARRAY_SIZE(CRTM640x480)},
919
920 /* Display : 720x480 (GTF) */
921 {VIA_RES_720X480, CRTM720x480, ARRAY_SIZE(CRTM720x480)},
922
923 /* Display : 720x576 (GTF) */
924 {VIA_RES_720X576, CRTM720x576, ARRAY_SIZE(CRTM720x576)},
925
926 /* Display : 800x600 */
927 {VIA_RES_800X600, CRTM800x600, ARRAY_SIZE(CRTM800x600)},
928
929 /* Display : 800x480 (CVT) */
930 {VIA_RES_800X480, CRTM800x480, ARRAY_SIZE(CRTM800x480)},
931
932 /* Display : 848x480 (CVT) */
933 {VIA_RES_848X480, CRTM848x480, ARRAY_SIZE(CRTM848x480)},
934
935 /* Display : 852x480 (GTF) */
936 {VIA_RES_856X480, CRTM852x480, ARRAY_SIZE(CRTM852x480)},
937
938 /* Display : 1024x512 (GTF) */
939 {VIA_RES_1024X512, CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
940
941 /* Display : 1024x600 */
942 {VIA_RES_1024X600, CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
943
944 /* Display : 1024x576 (GTF) */
945 /*{ VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)}, */
946
947 /* Display : 1024x768 */
948 {VIA_RES_1024X768, CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
949
950 /* Display : 1152x864 */
951 {VIA_RES_1152X864, CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
952
953 /* Display : 1280x768 (GTF) */
954 {VIA_RES_1280X768, CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
955
956 /* Display : 960x600 (CVT) */
957 {VIA_RES_960X600, CRTM960x600, ARRAY_SIZE(CRTM960x600)},
958
959 /* Display : 1000x600 (GTF) */
960 {VIA_RES_1000X600, CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
961
962 /* Display : 1024x576 (GTF) */
963 {VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
964
965 /* Display : 1088x612 (GTF) */
966 {VIA_RES_1088X612, CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
967
968 /* Display : 1152x720 (CVT) */
969 {VIA_RES_1152X720, CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
970
971 /* Display : 1200x720 (GTF) */
972 {VIA_RES_1200X720, CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
973
974 /* Display : 1280x600 (GTF) */
975 {VIA_RES_1280X600, CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
976
977 /* Display : 1280x800 (CVT) */
978 {VIA_RES_1280X800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
979
980 /* Display : 1280x800 (GTF) */
981 /*{ M1280x800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)}, */
982
983 /* Display : 1280x960 */
984 {VIA_RES_1280X960, CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
985
986 /* Display : 1280x1024 */
987 {VIA_RES_1280X1024, CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
988
989 /* Display : 1360x768 (CVT) */
990 {VIA_RES_1360X768, CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
991
992 /* Display : 1360x768 (CVT Reduce Blanking) */
993 {VIA_RES_1360X768_RB, CRTM1360x768_RB,
994 ARRAY_SIZE(CRTM1360x768_RB)},
995
996 /* Display : 1366x768 */
997 {VIA_RES_1366X768, CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
998
999 /* Display : 1368x768 (GTF) */
1000 /*{ M1368x768,CRTM1368x768,ARRAY_SIZE(CRTM1368x768)}, */
1001 /* Display : 1368x768 (GTF) */
1002 {VIA_RES_1368X768, CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
1003
1004 /* Display : 1440x900 (CVT) */
1005 {VIA_RES_1440X900, CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
1006
1007 /* Display : 1440x900 (CVT Reduce Blanking) */
1008 {VIA_RES_1440X900_RB, CRTM1440x900_RB,
1009 ARRAY_SIZE(CRTM1440x900_RB)},
1010
1011 /* Display : 1440x1050 (GTF) */
1012 {VIA_RES_1440X1050, CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
1013
1014 /* Display : 1400x1050 (CVT Reduce Blanking) */
1015 {VIA_RES_1400X1050_RB, CRTM1400x1050_RB,
1016 ARRAY_SIZE(CRTM1400x1050_RB)},
1017
1018 /* Display : 1600x900 (CVT) */
1019 {VIA_RES_1600X900, CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
1020
1021 /* Display : 1600x900 (CVT Reduce Blanking) */
1022 {VIA_RES_1600X900_RB, CRTM1600x900_RB,
1023 ARRAY_SIZE(CRTM1600x900_RB)},
1024
1025 /* Display : 1600x1024 (GTF) */
1026 {VIA_RES_1600X1024, CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
1027
1028 /* Display : 1600x1200 */
1029 {VIA_RES_1600X1200, CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
1030
1031 /* Display : 1680x1050 (CVT) */
1032 {VIA_RES_1680X1050, CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
1033
1034 /* Display : 1680x1050 (CVT Reduce Blanking) */
1035 {VIA_RES_1680X1050_RB, CRTM1680x1050_RB,
1036 ARRAY_SIZE(CRTM1680x1050_RB)},
1037
1038 /* Display : 1792x1344 (DMT) */
1039 {VIA_RES_1792X1344, CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
1040
1041 /* Display : 1856x1392 (DMT) */
1042 {VIA_RES_1856X1392, CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
1043
1044 /* Display : 1920x1440 */
1045 {VIA_RES_1920X1440, CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
1046
1047 /* Display : 2048x1536 */
1048 {VIA_RES_2048X1536, CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
1049
1050 /* Display : 1280x720 */
1051 {VIA_RES_1280X720, CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
1052
1053 /* Display : 1920x1080 (CVT) */
1054 {VIA_RES_1920X1080, CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
1055
1056 /* Display : 1920x1080 (CVT Reduce Blanking) */
1057 {VIA_RES_1920X1080_RB, CRTM1920x1080_RB,
1058 ARRAY_SIZE(CRTM1920x1080_RB)},
1059
1060 /* Display : 1920x1200 (CVT) */
1061 {VIA_RES_1920X1200, CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
1062
1063 /* Display : 1920x1200 (CVT Reduce Blanking) */
1064 {VIA_RES_1920X1200_RB, CRTM1920x1200_RB,
1065 ARRAY_SIZE(CRTM1920x1200_RB)},
1066
1067 /* Display : 1400x1050 (CVT) */
1068 {VIA_RES_1400X1050, CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
1069};
1070struct crt_mode_table CEAM1280x720[] = {
1071 {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP,
1072 M1280X720_CEA_R60_VSP,
1073 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
1074 {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
1075};
1076struct crt_mode_table CEAM1920x1080[] = {
1077 {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP,
1078 M1920X1080_CEA_R60_VSP,
1079 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
1080 {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
1081};
1082struct VideoModeTable CEA_HDMI_Modes[] = {
1083 /* Display : 1280x720 */
1084 {VIA_RES_1280X720, CEAM1280x720, ARRAY_SIZE(CEAM1280x720)},
1085 {VIA_RES_1920X1080, CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
1086};
diff --git a/drivers/video/via/viamode.h b/drivers/video/via/viamode.h
new file mode 100644
index 000000000000..1a5de50a23a2
--- /dev/null
+++ b/drivers/video/via/viamode.h
@@ -0,0 +1,177 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __VIAMODE_H__
23#define __VIAMODE_H__
24
25#include "global.h"
26
27struct VPITTable {
28 unsigned char Misc;
29 unsigned char SR[StdSR];
30 unsigned char GR[StdGR];
31 unsigned char AR[StdAR];
32};
33
34struct VideoModeTable {
35 int ModeIndex;
36 struct crt_mode_table *crtc;
37 int mode_array;
38};
39
40struct patch_table {
41 int mode_index;
42 int table_length;
43 struct io_reg *io_reg_table;
44};
45
46struct res_map_refresh {
47 int hres;
48 int vres;
49 int pixclock;
50 int vmode_refresh;
51};
52
53#define NUM_TOTAL_RES_MAP_REFRESH ARRAY_SIZE(res_map_refresh_tbl)
54#define NUM_TOTAL_CEA_MODES ARRAY_SIZE(CEA_HDMI_Modes)
55#define NUM_TOTAL_CN400_ModeXregs ARRAY_SIZE(CN400_ModeXregs)
56#define NUM_TOTAL_CN700_ModeXregs ARRAY_SIZE(CN700_ModeXregs)
57#define NUM_TOTAL_KM400_ModeXregs ARRAY_SIZE(KM400_ModeXregs)
58#define NUM_TOTAL_CX700_ModeXregs ARRAY_SIZE(CX700_ModeXregs)
59#define NUM_TOTAL_VX800_ModeXregs ARRAY_SIZE(VX800_ModeXregs)
60#define NUM_TOTAL_CLE266_ModeXregs ARRAY_SIZE(CLE266_ModeXregs)
61#define NUM_TOTAL_PATCH_MODE ARRAY_SIZE(res_patch_table)
62#define NUM_TOTAL_MODETABLE ARRAY_SIZE(CLE266Modes)
63
64/********************/
65/* Mode Table */
66/********************/
67
68/* 480x640 */
69extern struct crt_mode_table CRTM480x640[1];
70/* 640x480*/
71extern struct crt_mode_table CRTM640x480[5];
72/*720x480 (GTF)*/
73extern struct crt_mode_table CRTM720x480[1];
74/*720x576 (GTF)*/
75extern struct crt_mode_table CRTM720x576[1];
76/* 800x480 (CVT) */
77extern struct crt_mode_table CRTM800x480[1];
78/* 800x600*/
79extern struct crt_mode_table CRTM800x600[5];
80/* 848x480 (CVT) */
81extern struct crt_mode_table CRTM848x480[1];
82/*856x480 (GTF) convert to 852x480*/
83extern struct crt_mode_table CRTM852x480[1];
84/*1024x512 (GTF)*/
85extern struct crt_mode_table CRTM1024x512[1];
86/* 1024x600*/
87extern struct crt_mode_table CRTM1024x600[1];
88/* 1024x768*/
89extern struct crt_mode_table CRTM1024x768[4];
90/* 1152x864*/
91extern struct crt_mode_table CRTM1152x864[1];
92/* 1280x720 (HDMI 720P)*/
93extern struct crt_mode_table CRTM1280x720[2];
94/*1280x768 (GTF)*/
95extern struct crt_mode_table CRTM1280x768[2];
96/* 1280x800 (CVT) */
97extern struct crt_mode_table CRTM1280x800[1];
98/*1280x960*/
99extern struct crt_mode_table CRTM1280x960[1];
100/* 1280x1024*/
101extern struct crt_mode_table CRTM1280x1024[3];
102/* 1368x768 (GTF) */
103extern struct crt_mode_table CRTM1368x768[1];
104/*1440x1050 (GTF)*/
105extern struct crt_mode_table CRTM1440x1050[1];
106/* 1600x1200*/
107extern struct crt_mode_table CRTM1600x1200[2];
108/* 1680x1050 (CVT) */
109extern struct crt_mode_table CRTM1680x1050[2];
110/* 1680x1050 (CVT Reduce Blanking) */
111extern struct crt_mode_table CRTM1680x1050_RB[1];
112/* 1920x1080 (CVT)*/
113extern struct crt_mode_table CRTM1920x1080[1];
114/* 1920x1080 (CVT with Reduce Blanking) */
115extern struct crt_mode_table CRTM1920x1080_RB[1];
116/* 1920x1440*/
117extern struct crt_mode_table CRTM1920x1440[2];
118/* 1400x1050 (CVT) */
119extern struct crt_mode_table CRTM1400x1050[2];
120/* 1400x1050 (CVT Reduce Blanking) */
121extern struct crt_mode_table CRTM1400x1050_RB[1];
122/* 960x600 (CVT) */
123extern struct crt_mode_table CRTM960x600[1];
124/* 1000x600 (GTF) */
125extern struct crt_mode_table CRTM1000x600[1];
126/* 1024x576 (GTF) */
127extern struct crt_mode_table CRTM1024x576[1];
128/* 1088x612 (CVT) */
129extern struct crt_mode_table CRTM1088x612[1];
130/* 1152x720 (CVT) */
131extern struct crt_mode_table CRTM1152x720[1];
132/* 1200x720 (GTF) */
133extern struct crt_mode_table CRTM1200x720[1];
134/* 1280x600 (GTF) */
135extern struct crt_mode_table CRTM1280x600[1];
136/* 1360x768 (CVT) */
137extern struct crt_mode_table CRTM1360x768[1];
138/* 1360x768 (CVT Reduce Blanking) */
139extern struct crt_mode_table CRTM1360x768_RB[1];
140/* 1366x768 (GTF) */
141extern struct crt_mode_table CRTM1366x768[2];
142/* 1440x900 (CVT) */
143extern struct crt_mode_table CRTM1440x900[2];
144/* 1440x900 (CVT Reduce Blanking) */
145extern struct crt_mode_table CRTM1440x900_RB[1];
146/* 1600x900 (CVT) */
147extern struct crt_mode_table CRTM1600x900[1];
148/* 1600x900 (CVT Reduce Blanking) */
149extern struct crt_mode_table CRTM1600x900_RB[1];
150/* 1600x1024 (GTF) */
151extern struct crt_mode_table CRTM1600x1024[1];
152/* 1792x1344 (DMT) */
153extern struct crt_mode_table CRTM1792x1344[1];
154/* 1856x1392 (DMT) */
155extern struct crt_mode_table CRTM1856x1392[1];
156/* 1920x1200 (CVT) */
157extern struct crt_mode_table CRTM1920x1200[1];
158/* 1920x1200 (CVT with Reduce Blanking) */
159extern struct crt_mode_table CRTM1920x1200_RB[1];
160/* 2048x1536 (CVT) */
161extern struct crt_mode_table CRTM2048x1536[1];
162extern struct VideoModeTable CLE266Modes[47];
163extern struct crt_mode_table CEAM1280x720[1];
164extern struct crt_mode_table CEAM1920x1080[1];
165extern struct VideoModeTable CEA_HDMI_Modes[2];
166
167extern struct res_map_refresh res_map_refresh_tbl[61];
168extern struct io_reg CN400_ModeXregs[52];
169extern struct io_reg CN700_ModeXregs[66];
170extern struct io_reg KM400_ModeXregs[55];
171extern struct io_reg CX700_ModeXregs[58];
172extern struct io_reg VX800_ModeXregs[58];
173extern struct io_reg CLE266_ModeXregs[32];
174extern struct io_reg PM1024x768[2];
175extern struct patch_table res_patch_table[1];
176extern struct VPITTable VPIT;
177#endif /* __VIAMODE_H__ */
diff --git a/drivers/video/via/vt1636.c b/drivers/video/via/vt1636.c
new file mode 100644
index 000000000000..322a9f993550
--- /dev/null
+++ b/drivers/video/via/vt1636.c
@@ -0,0 +1,306 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
25 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
26 u8 index)
27{
28 u8 data;
29
30 viaparinfo->i2c_stuff.i2c_port = plvds_chip_info->i2c_port;
31 viafb_i2c_readbyte(plvds_chip_info->lvds_chip_slave_addr, index, &data);
32
33 return data;
34}
35
36void viafb_gpio_i2c_write_mask_lvds(struct lvds_setting_information
37 *plvds_setting_info, struct lvds_chip_information
38 *plvds_chip_info, struct IODATA io_data)
39{
40 int index, data;
41
42 viaparinfo->i2c_stuff.i2c_port = plvds_chip_info->i2c_port;
43
44 index = io_data.Index;
45 data = viafb_gpio_i2c_read_lvds(plvds_setting_info, plvds_chip_info,
46 index);
47 data = (data & (~io_data.Mask)) | io_data.Data;
48
49 viafb_i2c_writebyte(plvds_chip_info->lvds_chip_slave_addr, index, data);
50}
51
52void viafb_init_lvds_vt1636(struct lvds_setting_information
53 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
54{
55 int reg_num, i;
56
57 /* Common settings: */
58 reg_num = ARRAY_SIZE(COMMON_INIT_TBL_VT1636);
59
60 for (i = 0; i < reg_num; i++) {
61 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
62 plvds_chip_info,
63 COMMON_INIT_TBL_VT1636[i]);
64 }
65
66 /* Input Data Mode Select */
67 if (plvds_setting_info->device_lcd_dualedge) {
68 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
69 plvds_chip_info,
70 DUAL_CHANNEL_ENABLE_TBL_VT1636[0]);
71 } else {
72 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
73 plvds_chip_info,
74 SINGLE_CHANNEL_ENABLE_TBL_VT1636[0]);
75 }
76
77 if (plvds_setting_info->LCDDithering) {
78 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
79 plvds_chip_info,
80 DITHERING_ENABLE_TBL_VT1636[0]);
81 } else {
82 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
83 plvds_chip_info,
84 DITHERING_DISABLE_TBL_VT1636[0]);
85 }
86}
87
88void viafb_enable_lvds_vt1636(struct lvds_setting_information
89 *plvds_setting_info,
90 struct lvds_chip_information *plvds_chip_info)
91{
92
93 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
94 VDD_ON_TBL_VT1636[0]);
95
96 /* Pad on: */
97 switch (plvds_chip_info->output_interface) {
98 case INTERFACE_DVP0:
99 {
100 viafb_write_reg_mask(SR1E, VIASR, 0xC0, 0xC0);
101 break;
102 }
103
104 case INTERFACE_DVP1:
105 {
106 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
107 break;
108 }
109
110 case INTERFACE_DFP_LOW:
111 {
112 viafb_write_reg_mask(SR2A, VIASR, 0x03, 0x03);
113 break;
114 }
115
116 case INTERFACE_DFP_HIGH:
117 {
118 viafb_write_reg_mask(SR2A, VIASR, 0x03, 0x0C);
119 break;
120 }
121
122 }
123}
124
125void viafb_disable_lvds_vt1636(struct lvds_setting_information
126 *plvds_setting_info,
127 struct lvds_chip_information *plvds_chip_info)
128{
129
130 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
131 VDD_OFF_TBL_VT1636[0]);
132
133 /* Pad off: */
134 switch (plvds_chip_info->output_interface) {
135 case INTERFACE_DVP0:
136 {
137 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0xC0);
138 break;
139 }
140
141 case INTERFACE_DVP1:
142 {
143 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
144 break;
145 }
146
147 case INTERFACE_DFP_LOW:
148 {
149 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x03);
150 break;
151 }
152
153 case INTERFACE_DFP_HIGH:
154 {
155 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0C);
156 break;
157 }
158
159 }
160}
161
162bool viafb_lvds_identify_vt1636(void)
163{
164 u8 Buffer[2];
165
166 DEBUG_MSG(KERN_INFO "viafb_lvds_identify_vt1636.\n");
167
168 /* Sense VT1636 LVDS Transmiter */
169 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
170 VT1636_LVDS_I2C_ADDR;
171
172 /* Check vendor ID first: */
173 viafb_i2c_readbyte((u8) viaparinfo->chip_info->lvds_chip_info.
174 lvds_chip_slave_addr,
175 0x00, &Buffer[0]);
176 viafb_i2c_readbyte((u8) viaparinfo->chip_info->lvds_chip_info.
177 lvds_chip_slave_addr,
178 0x01, &Buffer[1]);
179
180 if (!((Buffer[0] == 0x06) && (Buffer[1] == 0x11)))
181 return false;
182
183 /* Check Chip ID: */
184 viafb_i2c_readbyte((u8) viaparinfo->chip_info->lvds_chip_info.
185 lvds_chip_slave_addr,
186 0x02, &Buffer[0]);
187 viafb_i2c_readbyte((u8) viaparinfo->chip_info->lvds_chip_info.
188 lvds_chip_slave_addr,
189 0x03, &Buffer[1]);
190 if ((Buffer[0] == 0x45) && (Buffer[1] == 0x33)) {
191 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
192 VT1636_LVDS;
193 return true;
194 }
195
196 return false;
197}
198
199static int get_clk_range_index(u32 Clk)
200{
201 if (Clk < DPA_CLK_30M)
202 return DPA_CLK_RANGE_30M;
203 else if (Clk < DPA_CLK_50M)
204 return DPA_CLK_RANGE_30_50M;
205 else if (Clk < DPA_CLK_70M)
206 return DPA_CLK_RANGE_50_70M;
207 else if (Clk < DPA_CLK_100M)
208 return DPA_CLK_RANGE_70_100M;
209 else if (Clk < DPA_CLK_150M)
210 return DPA_CLK_RANGE_100_150M;
211 else
212 return DPA_CLK_RANGE_150M;
213}
214
215static int get_lvds_dpa_setting_index(int panel_size_id,
216 struct VT1636_DPA_SETTING *p_vt1636_dpasetting_tbl,
217 int tbl_size)
218{
219 int i;
220
221 for (i = 0; i < tbl_size; i++) {
222 if (panel_size_id == p_vt1636_dpasetting_tbl->PanelSizeID)
223 return i;
224
225 p_vt1636_dpasetting_tbl++;
226 }
227
228 return 0;
229}
230
231static void set_dpa_vt1636(struct lvds_setting_information
232 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
233 struct VT1636_DPA_SETTING *p_vt1636_dpa_setting)
234{
235 struct IODATA io_data;
236
237 io_data.Index = 0x09;
238 io_data.Mask = 0x1F;
239 io_data.Data = p_vt1636_dpa_setting->CLK_SEL_ST1;
240 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
241 plvds_chip_info, io_data);
242
243 io_data.Index = 0x08;
244 io_data.Mask = 0x0F;
245 io_data.Data = p_vt1636_dpa_setting->CLK_SEL_ST2;
246 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
247 io_data);
248}
249
250void viafb_vt1636_patch_skew_on_vt3324(
251 struct lvds_setting_information *plvds_setting_info,
252 struct lvds_chip_information *plvds_chip_info)
253{
254 int index, size;
255
256 DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3324.\n");
257
258 /* Graphics DPA settings: */
259 index = get_clk_range_index(plvds_setting_info->vclk);
260 viafb_set_dpa_gfx(plvds_chip_info->output_interface,
261 &GFX_DPA_SETTING_TBL_VT3324[index]);
262
263 /* LVDS Transmitter DPA settings: */
264 size = ARRAY_SIZE(VT1636_DPA_SETTING_TBL_VT3324);
265 index =
266 get_lvds_dpa_setting_index(plvds_setting_info->lcd_panel_id,
267 VT1636_DPA_SETTING_TBL_VT3324, size);
268 set_dpa_vt1636(plvds_setting_info, plvds_chip_info,
269 &VT1636_DPA_SETTING_TBL_VT3324[index]);
270}
271
272void viafb_vt1636_patch_skew_on_vt3327(
273 struct lvds_setting_information *plvds_setting_info,
274 struct lvds_chip_information *plvds_chip_info)
275{
276 int index, size;
277
278 DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3327.\n");
279
280 /* Graphics DPA settings: */
281 index = get_clk_range_index(plvds_setting_info->vclk);
282 viafb_set_dpa_gfx(plvds_chip_info->output_interface,
283 &GFX_DPA_SETTING_TBL_VT3327[index]);
284
285 /* LVDS Transmitter DPA settings: */
286 size = ARRAY_SIZE(VT1636_DPA_SETTING_TBL_VT3327);
287 index =
288 get_lvds_dpa_setting_index(plvds_setting_info->lcd_panel_id,
289 VT1636_DPA_SETTING_TBL_VT3327, size);
290 set_dpa_vt1636(plvds_setting_info, plvds_chip_info,
291 &VT1636_DPA_SETTING_TBL_VT3327[index]);
292}
293
294void viafb_vt1636_patch_skew_on_vt3364(
295 struct lvds_setting_information *plvds_setting_info,
296 struct lvds_chip_information *plvds_chip_info)
297{
298 int index;
299
300 DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3364.\n");
301
302 /* Graphics DPA settings: */
303 index = get_clk_range_index(plvds_setting_info->vclk);
304 viafb_set_dpa_gfx(plvds_chip_info->output_interface,
305 &GFX_DPA_SETTING_TBL_VT3364[index]);
306}
diff --git a/drivers/video/via/vt1636.h b/drivers/video/via/vt1636.h
new file mode 100644
index 000000000000..2a150c58c7ed
--- /dev/null
+++ b/drivers/video/via/vt1636.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _VT1636_H_
23#define _VT1636_H_
24#include "chip.h"
25bool viafb_lvds_identify_vt1636(void);
26void viafb_init_lvds_vt1636(struct lvds_setting_information
27 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
28void viafb_enable_lvds_vt1636(struct lvds_setting_information
29 *plvds_setting_info,
30 struct lvds_chip_information *plvds_chip_info);
31void viafb_disable_lvds_vt1636(struct lvds_setting_information
32 *plvds_setting_info,
33 struct lvds_chip_information *plvds_chip_info);
34void viafb_vt1636_patch_skew_on_vt3324(
35 struct lvds_setting_information *plvds_setting_info,
36 struct lvds_chip_information *plvds_chip_info);
37void viafb_vt1636_patch_skew_on_vt3327(
38 struct lvds_setting_information *plvds_setting_info,
39 struct lvds_chip_information *plvds_chip_info);
40void viafb_vt1636_patch_skew_on_vt3364(
41 struct lvds_setting_information *plvds_setting_info,
42 struct lvds_chip_information *plvds_chip_info);
43
44#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 17:02:01 -0500