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path: root/drivers/video/via/hw.c
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Diffstat (limited to 'drivers/video/via/hw.c')
-rw-r--r--drivers/video/via/hw.c330
1 files changed, 115 insertions, 215 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 3e083ff67ae2..f2583b1b527f 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -524,7 +524,6 @@ static void dvi_patch_skew_dvp1(void);
524static void dvi_patch_skew_dvp_low(void); 524static void dvi_patch_skew_dvp_low(void);
525static void set_dvi_output_path(int set_iga, int output_interface); 525static void set_dvi_output_path(int set_iga, int output_interface);
526static void set_lcd_output_path(int set_iga, int output_interface); 526static void set_lcd_output_path(int set_iga, int output_interface);
527static int search_mode_setting(int ModeInfoIndex);
528static void load_fix_bit_crtc_reg(void); 527static void load_fix_bit_crtc_reg(void);
529static void init_gfx_chip_info(struct pci_dev *pdev, 528static void init_gfx_chip_info(struct pci_dev *pdev,
530 const struct pci_device_id *pdi); 529 const struct pci_device_id *pdi);
@@ -686,6 +685,84 @@ void viafb_set_secondary_pitch(u32 pitch)
686 viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80); 685 viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
687} 686}
688 687
688void viafb_set_primary_color_depth(u8 depth)
689{
690 u8 value;
691
692 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth);
693 switch (depth) {
694 case 8:
695 value = 0x00;
696 break;
697 case 15:
698 value = 0x04;
699 break;
700 case 16:
701 value = 0x14;
702 break;
703 case 24:
704 value = 0x0C;
705 break;
706 case 30:
707 value = 0x08;
708 break;
709 default:
710 printk(KERN_WARNING "viafb_set_primary_color_depth: "
711 "Unsupported depth: %d\n", depth);
712 return;
713 }
714
715 viafb_write_reg_mask(0x15, VIASR, value, 0x1C);
716}
717
718void viafb_set_secondary_color_depth(u8 depth)
719{
720 u8 value;
721
722 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth);
723 switch (depth) {
724 case 8:
725 value = 0x00;
726 break;
727 case 16:
728 value = 0x40;
729 break;
730 case 24:
731 value = 0xC0;
732 break;
733 case 30:
734 value = 0x80;
735 break;
736 default:
737 printk(KERN_WARNING "viafb_set_secondary_color_depth: "
738 "Unsupported depth: %d\n", depth);
739 return;
740 }
741
742 viafb_write_reg_mask(0x67, VIACR, value, 0xC0);
743}
744
745static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
746{
747 outb(0xFF, 0x3C6); /* bit mask of palette */
748 outb(index, 0x3C8);
749 outb(red, 0x3C9);
750 outb(green, 0x3C9);
751 outb(blue, 0x3C9);
752}
753
754void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
755{
756 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
757 set_color_register(index, red, green, blue);
758}
759
760void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
761{
762 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
763 set_color_register(index, red, green, blue);
764}
765
689void viafb_set_output_path(int device, int set_iga, int output_interface) 766void viafb_set_output_path(int device, int set_iga, int output_interface)
690{ 767{
691 switch (device) { 768 switch (device) {
@@ -710,11 +787,8 @@ static void set_crt_output_path(int set_iga)
710 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6); 787 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
711 break; 788 break;
712 case IGA2: 789 case IGA2:
713 case IGA1_IGA2:
714 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); 790 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
715 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6); 791 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
716 if (set_iga == IGA1_IGA2)
717 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
718 break; 792 break;
719 } 793 }
720} 794}
@@ -904,13 +978,6 @@ static void set_lcd_output_path(int set_iga, int output_interface)
904 978
905 enable_second_display_channel(); 979 enable_second_display_channel();
906 break; 980 break;
907
908 case IGA1_IGA2:
909 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
910 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
911
912 disable_second_display_channel();
913 break;
914 } 981 }
915 982
916 switch (output_interface) { 983 switch (output_interface) {
@@ -987,49 +1054,6 @@ static void set_lcd_output_path(int set_iga, int output_interface)
987 } 1054 }
988} 1055}
989 1056
990/* Search Mode Index */
991static int search_mode_setting(int ModeInfoIndex)
992{
993 int i = 0;
994
995 while ((i < NUM_TOTAL_MODETABLE) &&
996 (ModeInfoIndex != CLE266Modes[i].ModeIndex))
997 i++;
998 if (i >= NUM_TOTAL_MODETABLE)
999 i = 0;
1000 return i;
1001
1002}
1003
1004struct VideoModeTable *viafb_get_modetbl_pointer(int Index)
1005{
1006 struct VideoModeTable *TmpTbl = NULL;
1007 TmpTbl = &CLE266Modes[search_mode_setting(Index)];
1008 return TmpTbl;
1009}
1010
1011struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index)
1012{
1013 struct VideoModeTable *TmpTbl = NULL;
1014 int i = 0;
1015 while ((i < NUM_TOTAL_CEA_MODES) &&
1016 (Index != CEA_HDMI_Modes[i].ModeIndex))
1017 i++;
1018 if ((i < NUM_TOTAL_CEA_MODES))
1019 TmpTbl = &CEA_HDMI_Modes[i];
1020 else {
1021 /*Still use general timing if don't find CEA timing */
1022 i = 0;
1023 while ((i < NUM_TOTAL_MODETABLE) &&
1024 (Index != CLE266Modes[i].ModeIndex))
1025 i++;
1026 if (i >= NUM_TOTAL_MODETABLE)
1027 i = 0;
1028 TmpTbl = &CLE266Modes[i];
1029 }
1030 return TmpTbl;
1031}
1032
1033static void load_fix_bit_crtc_reg(void) 1057static void load_fix_bit_crtc_reg(void)
1034{ 1058{
1035 /* always set to 1 */ 1059 /* always set to 1 */
@@ -1121,15 +1145,13 @@ void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1121 struct io_register *reg = NULL; 1145 struct io_register *reg = NULL;
1122 1146
1123 switch (set_iga) { 1147 switch (set_iga) {
1124 case IGA1_IGA2:
1125 case IGA1: 1148 case IGA1:
1126 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); 1149 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1127 viafb_load_reg_num = fetch_count_reg. 1150 viafb_load_reg_num = fetch_count_reg.
1128 iga1_fetch_count_reg.reg_num; 1151 iga1_fetch_count_reg.reg_num;
1129 reg = fetch_count_reg.iga1_fetch_count_reg.reg; 1152 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1130 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); 1153 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1131 if (set_iga == IGA1) 1154 break;
1132 break;
1133 case IGA2: 1155 case IGA2:
1134 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); 1156 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1135 viafb_load_reg_num = fetch_count_reg. 1157 viafb_load_reg_num = fetch_count_reg.
@@ -1499,7 +1521,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1499 /* H.W. Reset : ON */ 1521 /* H.W. Reset : ON */
1500 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); 1522 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1501 1523
1502 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) { 1524 if (set_iga == IGA1) {
1503 /* Change D,N FOR VCLK */ 1525 /* Change D,N FOR VCLK */
1504 switch (viaparinfo->chip_info->gfx_chip_name) { 1526 switch (viaparinfo->chip_info->gfx_chip_name) {
1505 case UNICHROME_CLE266: 1527 case UNICHROME_CLE266:
@@ -1528,7 +1550,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1528 } 1550 }
1529 } 1551 }
1530 1552
1531 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) { 1553 if (set_iga == IGA2) {
1532 /* Change D,N FOR LCK */ 1554 /* Change D,N FOR LCK */
1533 switch (viaparinfo->chip_info->gfx_chip_name) { 1555 switch (viaparinfo->chip_info->gfx_chip_name) {
1534 case UNICHROME_CLE266: 1556 case UNICHROME_CLE266:
@@ -1557,12 +1579,12 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1557 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); 1579 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1558 1580
1559 /* Reset PLL */ 1581 /* Reset PLL */
1560 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) { 1582 if (set_iga == IGA1) {
1561 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); 1583 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1562 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); 1584 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1563 } 1585 }
1564 1586
1565 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) { 1587 if (set_iga == IGA2) {
1566 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0); 1588 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1567 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0); 1589 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1568 } 1590 }
@@ -1805,47 +1827,15 @@ void viafb_load_crtc_timing(struct display_timing device_timing,
1805 viafb_lock_crt(); 1827 viafb_lock_crt();
1806} 1828}
1807 1829
1808void viafb_set_color_depth(int bpp_byte, int set_iga)
1809{
1810 if (set_iga == IGA1) {
1811 switch (bpp_byte) {
1812 case MODE_8BPP:
1813 viafb_write_reg_mask(SR15, VIASR, 0x22, 0x7E);
1814 break;
1815 case MODE_16BPP:
1816 viafb_write_reg_mask(SR15, VIASR, 0xB6, 0xFE);
1817 break;
1818 case MODE_32BPP:
1819 viafb_write_reg_mask(SR15, VIASR, 0xAE, 0xFE);
1820 break;
1821 }
1822 } else {
1823 switch (bpp_byte) {
1824 case MODE_8BPP:
1825 viafb_write_reg_mask(CR67, VIACR, 0x00, BIT6 + BIT7);
1826 break;
1827 case MODE_16BPP:
1828 viafb_write_reg_mask(CR67, VIACR, 0x40, BIT6 + BIT7);
1829 break;
1830 case MODE_32BPP:
1831 viafb_write_reg_mask(CR67, VIACR, 0xC0, BIT6 + BIT7);
1832 break;
1833 }
1834 }
1835}
1836
1837void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 1830void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1838 int mode_index, int bpp_byte, int set_iga) 1831 struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1839{ 1832{
1840 struct VideoModeTable *video_mode;
1841 struct display_timing crt_reg; 1833 struct display_timing crt_reg;
1842 int i; 1834 int i;
1843 int index = 0; 1835 int index = 0;
1844 int h_addr, v_addr; 1836 int h_addr, v_addr;
1845 u32 pll_D_N; 1837 u32 pll_D_N;
1846 1838
1847 video_mode = &CLE266Modes[search_mode_setting(mode_index)];
1848
1849 for (i = 0; i < video_mode->mode_array; i++) { 1839 for (i = 0; i < video_mode->mode_array; i++) {
1850 index = i; 1840 index = i;
1851 1841
@@ -1858,8 +1848,10 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1858 1848
1859 /* Mode 640x480 has border, but LCD/DFP didn't have border. */ 1849 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1860 /* So we would delete border. */ 1850 /* So we would delete border. */
1861 if ((viafb_LCD_ON | viafb_DVI_ON) && (mode_index == VIA_RES_640X480) 1851 if ((viafb_LCD_ON | viafb_DVI_ON)
1862 && (viaparinfo->crt_setting_info->refresh_rate == 60)) { 1852 && video_mode->crtc[0].crtc.hor_addr == 640
1853 && video_mode->crtc[0].crtc.ver_addr == 480
1854 && viaparinfo->crt_setting_info->refresh_rate == 60) {
1863 /* The border is 8 pixels. */ 1855 /* The border is 8 pixels. */
1864 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8; 1856 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1865 1857
@@ -1912,9 +1904,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1912 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) 1904 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1913 viafb_load_FIFO_reg(set_iga, h_addr, v_addr); 1905 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1914 1906
1915 /* load SR Register About Memory and Color part */
1916 viafb_set_color_depth(bpp_byte, set_iga);
1917
1918 pll_D_N = viafb_get_clk_value(crt_table[index].clk); 1907 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1919 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N); 1908 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1920 viafb_set_vclock(pll_D_N, set_iga); 1909 viafb_set_vclock(pll_D_N, set_iga);
@@ -1956,9 +1945,6 @@ void viafb_update_device_setting(int hres, int vres,
1956 1945
1957 viaparinfo->tmds_setting_info->h_active = hres; 1946 viaparinfo->tmds_setting_info->h_active = hres;
1958 viaparinfo->tmds_setting_info->v_active = vres; 1947 viaparinfo->tmds_setting_info->v_active = vres;
1959 viaparinfo->tmds_setting_info->bpp = bpp;
1960 viaparinfo->tmds_setting_info->refresh_rate =
1961 vmode_refresh;
1962 1948
1963 viaparinfo->lvds_setting_info->h_active = hres; 1949 viaparinfo->lvds_setting_info->h_active = hres;
1964 viaparinfo->lvds_setting_info->v_active = vres; 1950 viaparinfo->lvds_setting_info->v_active = vres;
@@ -1975,9 +1961,6 @@ void viafb_update_device_setting(int hres, int vres,
1975 if (viaparinfo->tmds_setting_info->iga_path == IGA2) { 1961 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1976 viaparinfo->tmds_setting_info->h_active = hres; 1962 viaparinfo->tmds_setting_info->h_active = hres;
1977 viaparinfo->tmds_setting_info->v_active = vres; 1963 viaparinfo->tmds_setting_info->v_active = vres;
1978 viaparinfo->tmds_setting_info->bpp = bpp;
1979 viaparinfo->tmds_setting_info->refresh_rate =
1980 vmode_refresh;
1981 } 1964 }
1982 1965
1983 if (viaparinfo->lvds_setting_info->iga_path == IGA2) { 1966 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
@@ -2076,9 +2059,8 @@ static void init_tmds_chip_info(void)
2076 2059
2077 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n", 2060 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2078 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name); 2061 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2079 viaparinfo->tmds_setting_info->get_dvi_size_method = 2062 viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2080 GET_DVI_SIZE_BY_VGA_BIOS; 2063 &viaparinfo->shared->tmds_setting_info);
2081 viafb_init_dvi_size();
2082} 2064}
2083 2065
2084static void init_lvds_chip_info(void) 2066static void init_lvds_chip_info(void)
@@ -2195,28 +2177,19 @@ static void set_display_channel(void)
2195 } 2177 }
2196} 2178}
2197 2179
2198int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp, 2180int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2199 int vmode_index1, int hor_res1, int ver_res1, int video_bpp1) 2181 struct VideoModeTable *vmode_tbl1, int video_bpp1)
2200{ 2182{
2201 int i, j; 2183 int i, j;
2202 int port; 2184 int port;
2203 u8 value, index, mask; 2185 u8 value, index, mask;
2204 struct VideoModeTable *vmode_tbl;
2205 struct crt_mode_table *crt_timing; 2186 struct crt_mode_table *crt_timing;
2206 struct VideoModeTable *vmode_tbl1 = NULL;
2207 struct crt_mode_table *crt_timing1 = NULL; 2187 struct crt_mode_table *crt_timing1 = NULL;
2208 2188
2209 DEBUG_MSG(KERN_INFO "Set Mode!!\n");
2210 DEBUG_MSG(KERN_INFO
2211 "vmode_index=%d hor_res=%d ver_res=%d video_bpp=%d\n",
2212 vmode_index, hor_res, ver_res, video_bpp);
2213
2214 device_screen_off(); 2189 device_screen_off();
2215 vmode_tbl = &CLE266Modes[search_mode_setting(vmode_index)];
2216 crt_timing = vmode_tbl->crtc; 2190 crt_timing = vmode_tbl->crtc;
2217 2191
2218 if (viafb_SAMM_ON == 1) { 2192 if (viafb_SAMM_ON == 1) {
2219 vmode_tbl1 = &CLE266Modes[search_mode_setting(vmode_index1)];
2220 crt_timing1 = vmode_tbl1->crtc; 2193 crt_timing1 = vmode_tbl1->crtc;
2221 } 2194 }
2222 2195
@@ -2267,12 +2240,11 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2267 outb(VPIT.SR[i - 1], VIASR + 1); 2240 outb(VPIT.SR[i - 1], VIASR + 1);
2268 } 2241 }
2269 2242
2270 viafb_set_primary_address(0); 2243 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2271 viafb_set_secondary_address(viafb_SAMM_ON ? viafb_second_offset : 0);
2272 viafb_set_iga_path(); 2244 viafb_set_iga_path();
2273 2245
2274 /* Write CRTC */ 2246 /* Write CRTC */
2275 viafb_fill_crtc_timing(crt_timing, vmode_index, video_bpp / 8, IGA1); 2247 viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2276 2248
2277 /* Write Graphic Controller */ 2249 /* Write Graphic Controller */
2278 for (i = 0; i < StdGR; i++) { 2250 for (i = 0; i < StdGR; i++) {
@@ -2292,65 +2264,25 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2292 2264
2293 /* Update Patch Register */ 2265 /* Update Patch Register */
2294 2266
2295 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) 2267 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2296 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)) { 2268 || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2297 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) { 2269 && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2298 if (res_patch_table[i].mode_index == vmode_index) { 2270 && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2299 for (j = 0; 2271 for (j = 0; j < res_patch_table[0].table_length; j++) {
2300 j < res_patch_table[i].table_length; j++) { 2272 index = res_patch_table[0].io_reg_table[j].index;
2301 index = 2273 port = res_patch_table[0].io_reg_table[j].port;
2302 res_patch_table[i]. 2274 value = res_patch_table[0].io_reg_table[j].value;
2303 io_reg_table[j].index; 2275 mask = res_patch_table[0].io_reg_table[j].mask;
2304 port = 2276 viafb_write_reg_mask(index, port, value, mask);
2305 res_patch_table[i].
2306 io_reg_table[j].port;
2307 value =
2308 res_patch_table[i].
2309 io_reg_table[j].value;
2310 mask =
2311 res_patch_table[i].
2312 io_reg_table[j].mask;
2313 viafb_write_reg_mask(index, port, value,
2314 mask);
2315 }
2316 }
2317 }
2318 }
2319
2320 if (viafb_SAMM_ON == 1) {
2321 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2322 || (viaparinfo->chip_info->gfx_chip_name ==
2323 UNICHROME_K400)) {
2324 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2325 if (res_patch_table[i].mode_index ==
2326 vmode_index1) {
2327 for (j = 0;
2328 j <
2329 res_patch_table[i].
2330 table_length; j++) {
2331 index =
2332 res_patch_table[i].
2333 io_reg_table[j].index;
2334 port =
2335 res_patch_table[i].
2336 io_reg_table[j].port;
2337 value =
2338 res_patch_table[i].
2339 io_reg_table[j].value;
2340 mask =
2341 res_patch_table[i].
2342 io_reg_table[j].mask;
2343 viafb_write_reg_mask(index,
2344 port, value, mask);
2345 }
2346 }
2347 }
2348 } 2277 }
2349 } 2278 }
2350 2279
2351 viafb_set_primary_pitch(viafbinfo->fix.line_length); 2280 viafb_set_primary_pitch(viafbinfo->fix.line_length);
2352 viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length 2281 viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2353 : viafbinfo->fix.line_length); 2282 : viafbinfo->fix.line_length);
2283 viafb_set_primary_color_depth(viaparinfo->depth);
2284 viafb_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2285 : viaparinfo->depth);
2354 /* Update Refresh Rate Setting */ 2286 /* Update Refresh Rate Setting */
2355 2287
2356 /* Clear On Screen */ 2288 /* Clear On Screen */
@@ -2359,11 +2291,11 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2359 if (viafb_CRT_ON) { 2291 if (viafb_CRT_ON) {
2360 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path == 2292 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2361 IGA2)) { 2293 IGA2)) {
2362 viafb_fill_crtc_timing(crt_timing1, vmode_index1, 2294 viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2363 video_bpp1 / 8, 2295 video_bpp1 / 8,
2364 viaparinfo->crt_setting_info->iga_path); 2296 viaparinfo->crt_setting_info->iga_path);
2365 } else { 2297 } else {
2366 viafb_fill_crtc_timing(crt_timing, vmode_index, 2298 viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2367 video_bpp / 8, 2299 video_bpp / 8,
2368 viaparinfo->crt_setting_info->iga_path); 2300 viaparinfo->crt_setting_info->iga_path);
2369 } 2301 }
@@ -2373,7 +2305,7 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2373 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode 2305 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2374 to 8 alignment (1368),there is several pixels (2 pixels) 2306 to 8 alignment (1368),there is several pixels (2 pixels)
2375 on right side of screen. */ 2307 on right side of screen. */
2376 if (hor_res % 8) { 2308 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2377 viafb_unlock_crt(); 2309 viafb_unlock_crt();
2378 viafb_write_reg(CR02, VIACR, 2310 viafb_write_reg(CR02, VIACR,
2379 viafb_read_reg(VIACR, CR02) - 1); 2311 viafb_read_reg(VIACR, CR02) - 1);
@@ -2384,14 +2316,14 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2384 if (viafb_DVI_ON) { 2316 if (viafb_DVI_ON) {
2385 if (viafb_SAMM_ON && 2317 if (viafb_SAMM_ON &&
2386 (viaparinfo->tmds_setting_info->iga_path == IGA2)) { 2318 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2387 viafb_dvi_set_mode(viafb_get_mode_index 2319 viafb_dvi_set_mode(viafb_get_mode
2388 (viaparinfo->tmds_setting_info->h_active, 2320 (viaparinfo->tmds_setting_info->h_active,
2389 viaparinfo->tmds_setting_info-> 2321 viaparinfo->tmds_setting_info->
2390 v_active), 2322 v_active),
2391 video_bpp1, viaparinfo-> 2323 video_bpp1, viaparinfo->
2392 tmds_setting_info->iga_path); 2324 tmds_setting_info->iga_path);
2393 } else { 2325 } else {
2394 viafb_dvi_set_mode(viafb_get_mode_index 2326 viafb_dvi_set_mode(viafb_get_mode
2395 (viaparinfo->tmds_setting_info->h_active, 2327 (viaparinfo->tmds_setting_info->h_active,
2396 viaparinfo-> 2328 viaparinfo->
2397 tmds_setting_info->v_active), 2329 tmds_setting_info->v_active),
@@ -2445,8 +2377,8 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2445 2377
2446 /* If set mode normally, save resolution information for hot-plug . */ 2378 /* If set mode normally, save resolution information for hot-plug . */
2447 if (!viafb_hotplug) { 2379 if (!viafb_hotplug) {
2448 viafb_hotplug_Xres = hor_res; 2380 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2449 viafb_hotplug_Yres = ver_res; 2381 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2450 viafb_hotplug_bpp = video_bpp; 2382 viafb_hotplug_bpp = video_bpp;
2451 viafb_hotplug_refresh = viafb_refresh; 2383 viafb_hotplug_refresh = viafb_refresh;
2452 2384
@@ -2706,13 +2638,11 @@ void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2706 2638
2707/*According var's xres, yres fill var's other timing information*/ 2639/*According var's xres, yres fill var's other timing information*/
2708void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, 2640void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2709 int mode_index) 2641 struct VideoModeTable *vmode_tbl)
2710{ 2642{
2711 struct VideoModeTable *vmode_tbl = NULL;
2712 struct crt_mode_table *crt_timing = NULL; 2643 struct crt_mode_table *crt_timing = NULL;
2713 struct display_timing crt_reg; 2644 struct display_timing crt_reg;
2714 int i = 0, index = 0; 2645 int i = 0, index = 0;
2715 vmode_tbl = &CLE266Modes[search_mode_setting(mode_index)];
2716 crt_timing = vmode_tbl->crtc; 2646 crt_timing = vmode_tbl->crtc;
2717 for (i = 0; i < vmode_tbl->mode_array; i++) { 2647 for (i = 0; i < vmode_tbl->mode_array; i++) {
2718 index = i; 2648 index = i;
@@ -2721,36 +2651,6 @@ void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2721 } 2651 }
2722 2652
2723 crt_reg = crt_timing[index].crtc; 2653 crt_reg = crt_timing[index].crtc;
2724 switch (var->bits_per_pixel) {
2725 case 8:
2726 var->red.offset = 0;
2727 var->green.offset = 0;
2728 var->blue.offset = 0;
2729 var->red.length = 6;
2730 var->green.length = 6;
2731 var->blue.length = 6;
2732 break;
2733 case 16:
2734 var->red.offset = 11;
2735 var->green.offset = 5;
2736 var->blue.offset = 0;
2737 var->red.length = 5;
2738 var->green.length = 6;
2739 var->blue.length = 5;
2740 break;
2741 case 32:
2742 var->red.offset = 16;
2743 var->green.offset = 8;
2744 var->blue.offset = 0;
2745 var->red.length = 8;
2746 var->green.length = 8;
2747 var->blue.length = 8;
2748 break;
2749 default:
2750 /* never happed, put here to keep consistent */
2751 break;
2752 }
2753
2754 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh); 2654 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2755 var->left_margin = 2655 var->left_margin =
2756 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end); 2656 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 14:38:25 -0500