diff options
Diffstat (limited to 'drivers/video/tridentfb.c')
-rw-r--r-- | drivers/video/tridentfb.c | 1350 |
1 files changed, 784 insertions, 566 deletions
diff --git a/drivers/video/tridentfb.c b/drivers/video/tridentfb.c index beefab2992c0..479b2e79ad68 100644 --- a/drivers/video/tridentfb.c +++ b/drivers/video/tridentfb.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Frame buffer driver for Trident Blade and Image series | 2 | * Frame buffer driver for Trident TGUI, Blade and Image series |
3 | * | 3 | * |
4 | * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro> | 4 | * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro> |
5 | * | 5 | * |
@@ -13,7 +13,6 @@ | |||
13 | * code, suggestions | 13 | * code, suggestions |
14 | * TODO: | 14 | * TODO: |
15 | * timing value tweaking so it looks good on every monitor in every mode | 15 | * timing value tweaking so it looks good on every monitor in every mode |
16 | * TGUI acceleration | ||
17 | */ | 16 | */ |
18 | 17 | ||
19 | #include <linux/module.h> | 18 | #include <linux/module.h> |
@@ -22,25 +21,26 @@ | |||
22 | #include <linux/pci.h> | 21 | #include <linux/pci.h> |
23 | 22 | ||
24 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
24 | #include <video/vga.h> | ||
25 | #include <video/trident.h> | 25 | #include <video/trident.h> |
26 | 26 | ||
27 | #define VERSION "0.7.8-NEWAPI" | ||
28 | |||
29 | struct tridentfb_par { | 27 | struct tridentfb_par { |
30 | void __iomem *io_virt; /* iospace virtual memory address */ | 28 | void __iomem *io_virt; /* iospace virtual memory address */ |
29 | u32 pseudo_pal[16]; | ||
30 | int chip_id; | ||
31 | int flatpanel; | ||
32 | void (*init_accel) (struct tridentfb_par *, int, int); | ||
33 | void (*wait_engine) (struct tridentfb_par *); | ||
34 | void (*fill_rect) | ||
35 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | ||
36 | void (*copy_rect) | ||
37 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | ||
38 | void (*image_blit) | ||
39 | (struct tridentfb_par *par, const char*, | ||
40 | u32, u32, u32, u32, u32, u32); | ||
41 | unsigned char eng_oper; /* engine operation... */ | ||
31 | }; | 42 | }; |
32 | 43 | ||
33 | static unsigned char eng_oper; /* engine operation... */ | ||
34 | static struct fb_ops tridentfb_ops; | ||
35 | |||
36 | static struct tridentfb_par default_par; | ||
37 | |||
38 | /* FIXME:kmalloc these 3 instead */ | ||
39 | static struct fb_info fb_info; | ||
40 | static u32 pseudo_pal[16]; | ||
41 | |||
42 | static struct fb_var_screeninfo default_var; | ||
43 | |||
44 | static struct fb_fix_screeninfo tridentfb_fix = { | 44 | static struct fb_fix_screeninfo tridentfb_fix = { |
45 | .id = "Trident", | 45 | .id = "Trident", |
46 | .type = FB_TYPE_PACKED_PIXELS, | 46 | .type = FB_TYPE_PACKED_PIXELS, |
@@ -49,27 +49,22 @@ static struct fb_fix_screeninfo tridentfb_fix = { | |||
49 | .accel = FB_ACCEL_NONE, | 49 | .accel = FB_ACCEL_NONE, |
50 | }; | 50 | }; |
51 | 51 | ||
52 | static int chip_id; | ||
53 | |||
54 | static int defaultaccel; | ||
55 | static int displaytype; | ||
56 | |||
57 | /* defaults which are normally overriden by user values */ | 52 | /* defaults which are normally overriden by user values */ |
58 | 53 | ||
59 | /* video mode */ | 54 | /* video mode */ |
60 | static char *mode_option __devinitdata = "640x480"; | 55 | static char *mode_option __devinitdata = "640x480-8@60"; |
61 | static int bpp = 8; | 56 | static int bpp __devinitdata = 8; |
62 | 57 | ||
63 | static int noaccel; | 58 | static int noaccel __devinitdata; |
64 | 59 | ||
65 | static int center; | 60 | static int center; |
66 | static int stretch; | 61 | static int stretch; |
67 | 62 | ||
68 | static int fp; | 63 | static int fp __devinitdata; |
69 | static int crt; | 64 | static int crt __devinitdata; |
70 | 65 | ||
71 | static int memsize; | 66 | static int memsize __devinitdata; |
72 | static int memdiff; | 67 | static int memdiff __devinitdata; |
73 | static int nativex; | 68 | static int nativex; |
74 | 69 | ||
75 | module_param(mode_option, charp, 0); | 70 | module_param(mode_option, charp, 0); |
@@ -84,25 +79,53 @@ module_param(memsize, int, 0); | |||
84 | module_param(memdiff, int, 0); | 79 | module_param(memdiff, int, 0); |
85 | module_param(nativex, int, 0); | 80 | module_param(nativex, int, 0); |
86 | module_param(fp, int, 0); | 81 | module_param(fp, int, 0); |
82 | MODULE_PARM_DESC(fp, "Define if flatpanel is connected"); | ||
87 | module_param(crt, int, 0); | 83 | module_param(crt, int, 0); |
84 | MODULE_PARM_DESC(crt, "Define if CRT is connected"); | ||
85 | |||
86 | static inline int is_oldclock(int id) | ||
87 | { | ||
88 | return (id == TGUI9440) || | ||
89 | (id == TGUI9660) || | ||
90 | (id == CYBER9320); | ||
91 | } | ||
92 | |||
93 | static inline int is_oldprotect(int id) | ||
94 | { | ||
95 | return is_oldclock(id) || | ||
96 | (id == PROVIDIA9685) || | ||
97 | (id == CYBER9382) || | ||
98 | (id == CYBER9385); | ||
99 | } | ||
100 | |||
101 | static inline int is_blade(int id) | ||
102 | { | ||
103 | return (id == BLADE3D) || | ||
104 | (id == CYBERBLADEE4) || | ||
105 | (id == CYBERBLADEi7) || | ||
106 | (id == CYBERBLADEi7D) || | ||
107 | (id == CYBERBLADEi1) || | ||
108 | (id == CYBERBLADEi1D) || | ||
109 | (id == CYBERBLADEAi1) || | ||
110 | (id == CYBERBLADEAi1D); | ||
111 | } | ||
88 | 112 | ||
89 | static int chip3D; | 113 | static inline int is_xp(int id) |
90 | static int chipcyber; | 114 | { |
115 | return (id == CYBERBLADEXPAi1) || | ||
116 | (id == CYBERBLADEXPm8) || | ||
117 | (id == CYBERBLADEXPm16); | ||
118 | } | ||
91 | 119 | ||
92 | static int is3Dchip(int id) | 120 | static inline int is3Dchip(int id) |
93 | { | 121 | { |
94 | return ((id == BLADE3D) || (id == CYBERBLADEE4) || | 122 | return is_blade(id) || is_xp(id) || |
95 | (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) || | ||
96 | (id == CYBER9397) || (id == CYBER9397DVD) || | 123 | (id == CYBER9397) || (id == CYBER9397DVD) || |
97 | (id == CYBER9520) || (id == CYBER9525DVD) || | 124 | (id == CYBER9520) || (id == CYBER9525DVD) || |
98 | (id == IMAGE975) || (id == IMAGE985) || | 125 | (id == IMAGE975) || (id == IMAGE985); |
99 | (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) || | ||
100 | (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) || | ||
101 | (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) || | ||
102 | (id == CYBERBLADEXPAi1)); | ||
103 | } | 126 | } |
104 | 127 | ||
105 | static int iscyber(int id) | 128 | static inline int iscyber(int id) |
106 | { | 129 | { |
107 | switch (id) { | 130 | switch (id) { |
108 | case CYBER9388: | 131 | case CYBER9388: |
@@ -122,12 +145,7 @@ static int iscyber(int id) | |||
122 | return 1; | 145 | return 1; |
123 | 146 | ||
124 | case CYBER9320: | 147 | case CYBER9320: |
125 | case TGUI9660: | ||
126 | case IMAGE975: | ||
127 | case IMAGE985: | ||
128 | case BLADE3D: | ||
129 | case CYBERBLADEi7: /* VIA MPV4 integrated version */ | 148 | case CYBERBLADEi7: /* VIA MPV4 integrated version */ |
130 | |||
131 | default: | 149 | default: |
132 | /* case CYBERBLDAEXPm8: Strange */ | 150 | /* case CYBERBLDAEXPm8: Strange */ |
133 | /* case CYBERBLDAEXPm16: Strange */ | 151 | /* case CYBERBLDAEXPm16: Strange */ |
@@ -135,147 +153,110 @@ static int iscyber(int id) | |||
135 | } | 153 | } |
136 | } | 154 | } |
137 | 155 | ||
138 | #define CRT 0x3D0 /* CRTC registers offset for color display */ | 156 | static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) |
139 | 157 | { | |
140 | #ifndef TRIDENT_MMIO | 158 | fb_writeb(val, p->io_virt + reg); |
141 | #define TRIDENT_MMIO 1 | 159 | } |
142 | #endif | ||
143 | |||
144 | #if TRIDENT_MMIO | ||
145 | #define t_outb(val, reg) writeb(val,((struct tridentfb_par *)(fb_info.par))->io_virt + reg) | ||
146 | #define t_inb(reg) readb(((struct tridentfb_par*)(fb_info.par))->io_virt + reg) | ||
147 | #else | ||
148 | #define t_outb(val, reg) outb(val, reg) | ||
149 | #define t_inb(reg) inb(reg) | ||
150 | #endif | ||
151 | 160 | ||
161 | static inline u8 t_inb(struct tridentfb_par *p, u16 reg) | ||
162 | { | ||
163 | return fb_readb(p->io_virt + reg); | ||
164 | } | ||
152 | 165 | ||
153 | static struct accel_switch { | 166 | static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) |
154 | void (*init_accel) (int, int); | 167 | { |
155 | void (*wait_engine) (void); | 168 | fb_writel(v, par->io_virt + r); |
156 | void (*fill_rect) (u32, u32, u32, u32, u32, u32); | 169 | } |
157 | void (*copy_rect) (u32, u32, u32, u32, u32, u32); | ||
158 | } *acc; | ||
159 | 170 | ||
160 | #define writemmr(r, v) writel(v, ((struct tridentfb_par *)fb_info.par)->io_virt + r) | 171 | static inline u32 readmmr(struct tridentfb_par *par, u16 r) |
161 | #define readmmr(r) readl(((struct tridentfb_par *)fb_info.par)->io_virt + r) | 172 | { |
173 | return fb_readl(par->io_virt + r); | ||
174 | } | ||
162 | 175 | ||
163 | /* | 176 | /* |
164 | * Blade specific acceleration. | 177 | * Blade specific acceleration. |
165 | */ | 178 | */ |
166 | 179 | ||
167 | #define point(x, y) ((y) << 16 | (x)) | 180 | #define point(x, y) ((y) << 16 | (x)) |
168 | #define STA 0x2120 | 181 | |
169 | #define CMD 0x2144 | 182 | static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
170 | #define ROP 0x2148 | ||
171 | #define CLR 0x2160 | ||
172 | #define SR1 0x2100 | ||
173 | #define SR2 0x2104 | ||
174 | #define DR1 0x2108 | ||
175 | #define DR2 0x210C | ||
176 | |||
177 | #define ROP_S 0xCC | ||
178 | |||
179 | static void blade_init_accel(int pitch, int bpp) | ||
180 | { | 183 | { |
181 | int v1 = (pitch >> 3) << 20; | 184 | int v1 = (pitch >> 3) << 20; |
182 | int tmp = 0, v2; | 185 | int tmp = bpp == 24 ? 2 : (bpp >> 4); |
183 | switch (bpp) { | 186 | int v2 = v1 | (tmp << 29); |
184 | case 8: | 187 | |
185 | tmp = 0; | 188 | writemmr(par, 0x21C0, v2); |
186 | break; | 189 | writemmr(par, 0x21C4, v2); |
187 | case 15: | 190 | writemmr(par, 0x21B8, v2); |
188 | tmp = 5; | 191 | writemmr(par, 0x21BC, v2); |
189 | break; | 192 | writemmr(par, 0x21D0, v1); |
190 | case 16: | 193 | writemmr(par, 0x21D4, v1); |
191 | tmp = 1; | 194 | writemmr(par, 0x21C8, v1); |
192 | break; | 195 | writemmr(par, 0x21CC, v1); |
193 | case 24: | 196 | writemmr(par, 0x216C, 0); |
194 | case 32: | ||
195 | tmp = 2; | ||
196 | break; | ||
197 | } | ||
198 | v2 = v1 | (tmp << 29); | ||
199 | writemmr(0x21C0, v2); | ||
200 | writemmr(0x21C4, v2); | ||
201 | writemmr(0x21B8, v2); | ||
202 | writemmr(0x21BC, v2); | ||
203 | writemmr(0x21D0, v1); | ||
204 | writemmr(0x21D4, v1); | ||
205 | writemmr(0x21C8, v1); | ||
206 | writemmr(0x21CC, v1); | ||
207 | writemmr(0x216C, 0); | ||
208 | } | 197 | } |
209 | 198 | ||
210 | static void blade_wait_engine(void) | 199 | static void blade_wait_engine(struct tridentfb_par *par) |
211 | { | 200 | { |
212 | while (readmmr(STA) & 0xFA800000) ; | 201 | while (readmmr(par, STATUS) & 0xFA800000) |
202 | cpu_relax(); | ||
213 | } | 203 | } |
214 | 204 | ||
215 | static void blade_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | 205 | static void blade_fill_rect(struct tridentfb_par *par, |
206 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | ||
216 | { | 207 | { |
217 | writemmr(CLR, c); | 208 | writemmr(par, COLOR, c); |
218 | writemmr(ROP, rop ? 0x66 : ROP_S); | 209 | writemmr(par, ROP, rop ? ROP_X : ROP_S); |
219 | writemmr(CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2); | 210 | writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2); |
220 | 211 | ||
221 | writemmr(DR1, point(x, y)); | 212 | writemmr(par, DST1, point(x, y)); |
222 | writemmr(DR2, point(x + w - 1, y + h - 1)); | 213 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); |
223 | } | 214 | } |
224 | 215 | ||
225 | static void blade_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | 216 | static void blade_image_blit(struct tridentfb_par *par, const char *data, |
217 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 b) | ||
218 | { | ||
219 | unsigned size = ((w + 31) >> 5) * h; | ||
220 | |||
221 | writemmr(par, COLOR, c); | ||
222 | writemmr(par, BGCOLOR, b); | ||
223 | writemmr(par, CMD, 0xa0000000 | 3 << 19); | ||
224 | |||
225 | writemmr(par, DST1, point(x, y)); | ||
226 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | ||
227 | |||
228 | memcpy(par->io_virt + 0x10000, data, 4 * size); | ||
229 | } | ||
230 | |||
231 | static void blade_copy_rect(struct tridentfb_par *par, | ||
232 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | ||
226 | { | 233 | { |
227 | u32 s1, s2, d1, d2; | ||
228 | int direction = 2; | 234 | int direction = 2; |
229 | s1 = point(x1, y1); | 235 | u32 s1 = point(x1, y1); |
230 | s2 = point(x1 + w - 1, y1 + h - 1); | 236 | u32 s2 = point(x1 + w - 1, y1 + h - 1); |
231 | d1 = point(x2, y2); | 237 | u32 d1 = point(x2, y2); |
232 | d2 = point(x2 + w - 1, y2 + h - 1); | 238 | u32 d2 = point(x2 + w - 1, y2 + h - 1); |
233 | 239 | ||
234 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) | 240 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) |
235 | direction = 0; | 241 | direction = 0; |
236 | 242 | ||
237 | writemmr(ROP, ROP_S); | 243 | writemmr(par, ROP, ROP_S); |
238 | writemmr(CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction); | 244 | writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction); |
239 | 245 | ||
240 | writemmr(SR1, direction ? s2 : s1); | 246 | writemmr(par, SRC1, direction ? s2 : s1); |
241 | writemmr(SR2, direction ? s1 : s2); | 247 | writemmr(par, SRC2, direction ? s1 : s2); |
242 | writemmr(DR1, direction ? d2 : d1); | 248 | writemmr(par, DST1, direction ? d2 : d1); |
243 | writemmr(DR2, direction ? d1 : d2); | 249 | writemmr(par, DST2, direction ? d1 : d2); |
244 | } | 250 | } |
245 | 251 | ||
246 | static struct accel_switch accel_blade = { | ||
247 | blade_init_accel, | ||
248 | blade_wait_engine, | ||
249 | blade_fill_rect, | ||
250 | blade_copy_rect, | ||
251 | }; | ||
252 | |||
253 | /* | 252 | /* |
254 | * BladeXP specific acceleration functions | 253 | * BladeXP specific acceleration functions |
255 | */ | 254 | */ |
256 | 255 | ||
257 | #define ROP_P 0xF0 | 256 | static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
258 | #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff)) | ||
259 | |||
260 | static void xp_init_accel(int pitch, int bpp) | ||
261 | { | 257 | { |
262 | int tmp = 0, v1; | 258 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); |
263 | unsigned char x = 0; | 259 | int v1 = pitch << (bpp == 24 ? 20 : (18 + x)); |
264 | |||
265 | switch (bpp) { | ||
266 | case 8: | ||
267 | x = 0; | ||
268 | break; | ||
269 | case 16: | ||
270 | x = 1; | ||
271 | break; | ||
272 | case 24: | ||
273 | x = 3; | ||
274 | break; | ||
275 | case 32: | ||
276 | x = 2; | ||
277 | break; | ||
278 | } | ||
279 | 260 | ||
280 | switch (pitch << (bpp >> 3)) { | 261 | switch (pitch << (bpp >> 3)) { |
281 | case 8192: | 262 | case 8192: |
@@ -293,42 +274,21 @@ static void xp_init_accel(int pitch, int bpp) | |||
293 | break; | 274 | break; |
294 | } | 275 | } |
295 | 276 | ||
296 | t_outb(x, 0x2125); | 277 | t_outb(par, x, 0x2125); |
297 | |||
298 | eng_oper = x | 0x40; | ||
299 | |||
300 | switch (bpp) { | ||
301 | case 8: | ||
302 | tmp = 18; | ||
303 | break; | ||
304 | case 15: | ||
305 | case 16: | ||
306 | tmp = 19; | ||
307 | break; | ||
308 | case 24: | ||
309 | case 32: | ||
310 | tmp = 20; | ||
311 | break; | ||
312 | } | ||
313 | 278 | ||
314 | v1 = pitch << tmp; | 279 | par->eng_oper = x | 0x40; |
315 | 280 | ||
316 | writemmr(0x2154, v1); | 281 | writemmr(par, 0x2154, v1); |
317 | writemmr(0x2150, v1); | 282 | writemmr(par, 0x2150, v1); |
318 | t_outb(3, 0x2126); | 283 | t_outb(par, 3, 0x2126); |
319 | } | 284 | } |
320 | 285 | ||
321 | static void xp_wait_engine(void) | 286 | static void xp_wait_engine(struct tridentfb_par *par) |
322 | { | 287 | { |
323 | int busy; | 288 | int count = 0; |
324 | int count, timeout; | 289 | int timeout = 0; |
325 | 290 | ||
326 | count = 0; | 291 | while (t_inb(par, STATUS) & 0x80) { |
327 | timeout = 0; | ||
328 | for (;;) { | ||
329 | busy = t_inb(STA) & 0x80; | ||
330 | if (busy != 0x80) | ||
331 | return; | ||
332 | count++; | 292 | count++; |
333 | if (count == 10000000) { | 293 | if (count == 10000000) { |
334 | /* Timeout */ | 294 | /* Timeout */ |
@@ -336,30 +296,31 @@ static void xp_wait_engine(void) | |||
336 | timeout++; | 296 | timeout++; |
337 | if (timeout == 8) { | 297 | if (timeout == 8) { |
338 | /* Reset engine */ | 298 | /* Reset engine */ |
339 | t_outb(0x00, 0x2120); | 299 | t_outb(par, 0x00, STATUS); |
340 | return; | 300 | return; |
341 | } | 301 | } |
342 | } | 302 | } |
303 | cpu_relax(); | ||
343 | } | 304 | } |
344 | } | 305 | } |
345 | 306 | ||
346 | static void xp_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | 307 | static void xp_fill_rect(struct tridentfb_par *par, |
308 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | ||
347 | { | 309 | { |
348 | writemmr(0x2127, ROP_P); | 310 | writemmr(par, 0x2127, ROP_P); |
349 | writemmr(0x2158, c); | 311 | writemmr(par, 0x2158, c); |
350 | writemmr(0x2128, 0x4000); | 312 | writemmr(par, DRAWFL, 0x4000); |
351 | writemmr(0x2140, masked_point(h, w)); | 313 | writemmr(par, OLDDIM, point(h, w)); |
352 | writemmr(0x2138, masked_point(y, x)); | 314 | writemmr(par, OLDDST, point(y, x)); |
353 | t_outb(0x01, 0x2124); | 315 | t_outb(par, 0x01, OLDCMD); |
354 | t_outb(eng_oper, 0x2125); | 316 | t_outb(par, par->eng_oper, 0x2125); |
355 | } | 317 | } |
356 | 318 | ||
357 | static void xp_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | 319 | static void xp_copy_rect(struct tridentfb_par *par, |
320 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | ||
358 | { | 321 | { |
359 | int direction; | ||
360 | u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; | 322 | u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; |
361 | 323 | int direction = 0x0004; | |
362 | direction = 0x0004; | ||
363 | 324 | ||
364 | if ((x1 < x2) && (y1 == y2)) { | 325 | if ((x1 < x2) && (y1 == y2)) { |
365 | direction |= 0x0200; | 326 | direction |= 0x0200; |
@@ -379,103 +340,152 @@ static void xp_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |||
379 | y2_tmp = y2; | 340 | y2_tmp = y2; |
380 | } | 341 | } |
381 | 342 | ||
382 | writemmr(0x2128, direction); | 343 | writemmr(par, DRAWFL, direction); |
383 | t_outb(ROP_S, 0x2127); | 344 | t_outb(par, ROP_S, 0x2127); |
384 | writemmr(0x213C, masked_point(y1_tmp, x1_tmp)); | 345 | writemmr(par, OLDSRC, point(y1_tmp, x1_tmp)); |
385 | writemmr(0x2138, masked_point(y2_tmp, x2_tmp)); | 346 | writemmr(par, OLDDST, point(y2_tmp, x2_tmp)); |
386 | writemmr(0x2140, masked_point(h, w)); | 347 | writemmr(par, OLDDIM, point(h, w)); |
387 | t_outb(0x01, 0x2124); | 348 | t_outb(par, 0x01, OLDCMD); |
388 | } | 349 | } |
389 | 350 | ||
390 | static struct accel_switch accel_xp = { | ||
391 | xp_init_accel, | ||
392 | xp_wait_engine, | ||
393 | xp_fill_rect, | ||
394 | xp_copy_rect, | ||
395 | }; | ||
396 | |||
397 | /* | 351 | /* |
398 | * Image specific acceleration functions | 352 | * Image specific acceleration functions |
399 | */ | 353 | */ |
400 | static void image_init_accel(int pitch, int bpp) | 354 | static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
401 | { | 355 | { |
402 | int tmp = 0; | 356 | int tmp = bpp == 24 ? 2: (bpp >> 4); |
403 | switch (bpp) { | 357 | |
404 | case 8: | 358 | writemmr(par, 0x2120, 0xF0000000); |
405 | tmp = 0; | 359 | writemmr(par, 0x2120, 0x40000000 | tmp); |
406 | break; | 360 | writemmr(par, 0x2120, 0x80000000); |
407 | case 15: | 361 | writemmr(par, 0x2144, 0x00000000); |
408 | tmp = 5; | 362 | writemmr(par, 0x2148, 0x00000000); |
409 | break; | 363 | writemmr(par, 0x2150, 0x00000000); |
410 | case 16: | 364 | writemmr(par, 0x2154, 0x00000000); |
411 | tmp = 1; | 365 | writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch); |
412 | break; | 366 | writemmr(par, 0x216C, 0x00000000); |
413 | case 24: | 367 | writemmr(par, 0x2170, 0x00000000); |
414 | case 32: | 368 | writemmr(par, 0x217C, 0x00000000); |
415 | tmp = 2; | 369 | writemmr(par, 0x2120, 0x10000000); |
416 | break; | 370 | writemmr(par, 0x2130, (2047 << 16) | 2047); |
417 | } | ||
418 | writemmr(0x2120, 0xF0000000); | ||
419 | writemmr(0x2120, 0x40000000 | tmp); | ||
420 | writemmr(0x2120, 0x80000000); | ||
421 | writemmr(0x2144, 0x00000000); | ||
422 | writemmr(0x2148, 0x00000000); | ||
423 | writemmr(0x2150, 0x00000000); | ||
424 | writemmr(0x2154, 0x00000000); | ||
425 | writemmr(0x2120, 0x60000000 | (pitch << 16) | pitch); | ||
426 | writemmr(0x216C, 0x00000000); | ||
427 | writemmr(0x2170, 0x00000000); | ||
428 | writemmr(0x217C, 0x00000000); | ||
429 | writemmr(0x2120, 0x10000000); | ||
430 | writemmr(0x2130, (2047 << 16) | 2047); | ||
431 | } | 371 | } |
432 | 372 | ||
433 | static void image_wait_engine(void) | 373 | static void image_wait_engine(struct tridentfb_par *par) |
434 | { | 374 | { |
435 | while (readmmr(0x2164) & 0xF0000000) ; | 375 | while (readmmr(par, 0x2164) & 0xF0000000) |
376 | cpu_relax(); | ||
436 | } | 377 | } |
437 | 378 | ||
438 | static void image_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | 379 | static void image_fill_rect(struct tridentfb_par *par, |
380 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | ||
439 | { | 381 | { |
440 | writemmr(0x2120, 0x80000000); | 382 | writemmr(par, 0x2120, 0x80000000); |
441 | writemmr(0x2120, 0x90000000 | ROP_S); | 383 | writemmr(par, 0x2120, 0x90000000 | ROP_S); |
442 | 384 | ||
443 | writemmr(0x2144, c); | 385 | writemmr(par, 0x2144, c); |
444 | 386 | ||
445 | writemmr(DR1, point(x, y)); | 387 | writemmr(par, DST1, point(x, y)); |
446 | writemmr(DR2, point(x + w - 1, y + h - 1)); | 388 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); |
447 | 389 | ||
448 | writemmr(0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9); | 390 | writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9); |
449 | } | 391 | } |
450 | 392 | ||
451 | static void image_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | 393 | static void image_copy_rect(struct tridentfb_par *par, |
394 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | ||
452 | { | 395 | { |
453 | u32 s1, s2, d1, d2; | 396 | int direction = 0x4; |
454 | int direction = 2; | 397 | u32 s1 = point(x1, y1); |
455 | s1 = point(x1, y1); | 398 | u32 s2 = point(x1 + w - 1, y1 + h - 1); |
456 | s2 = point(x1 + w - 1, y1 + h - 1); | 399 | u32 d1 = point(x2, y2); |
457 | d1 = point(x2, y2); | 400 | u32 d2 = point(x2 + w - 1, y2 + h - 1); |
458 | d2 = point(x2 + w - 1, y2 + h - 1); | ||
459 | 401 | ||
460 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) | 402 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) |
461 | direction = 0; | 403 | direction = 0; |
462 | 404 | ||
463 | writemmr(0x2120, 0x80000000); | 405 | writemmr(par, 0x2120, 0x80000000); |
464 | writemmr(0x2120, 0x90000000 | ROP_S); | 406 | writemmr(par, 0x2120, 0x90000000 | ROP_S); |
465 | 407 | ||
466 | writemmr(SR1, direction ? s2 : s1); | 408 | writemmr(par, SRC1, direction ? s2 : s1); |
467 | writemmr(SR2, direction ? s1 : s2); | 409 | writemmr(par, SRC2, direction ? s1 : s2); |
468 | writemmr(DR1, direction ? d2 : d1); | 410 | writemmr(par, DST1, direction ? d2 : d1); |
469 | writemmr(DR2, direction ? d1 : d2); | 411 | writemmr(par, DST2, direction ? d1 : d2); |
470 | writemmr(0x2124, 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction); | 412 | writemmr(par, 0x2124, |
413 | 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction); | ||
471 | } | 414 | } |
472 | 415 | ||
473 | static struct accel_switch accel_image = { | 416 | /* |
474 | image_init_accel, | 417 | * TGUI 9440/96XX acceleration |
475 | image_wait_engine, | 418 | */ |
476 | image_fill_rect, | 419 | |
477 | image_copy_rect, | 420 | static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
478 | }; | 421 | { |
422 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); | ||
423 | |||
424 | /* disable clipping */ | ||
425 | writemmr(par, 0x2148, 0); | ||
426 | writemmr(par, 0x214C, point(4095, 2047)); | ||
427 | |||
428 | switch ((pitch * bpp) / 8) { | ||
429 | case 8192: | ||
430 | case 512: | ||
431 | x |= 0x00; | ||
432 | break; | ||
433 | case 1024: | ||
434 | x |= 0x04; | ||
435 | break; | ||
436 | case 2048: | ||
437 | x |= 0x08; | ||
438 | break; | ||
439 | case 4096: | ||
440 | x |= 0x0C; | ||
441 | break; | ||
442 | } | ||
443 | |||
444 | fb_writew(x, par->io_virt + 0x2122); | ||
445 | } | ||
446 | |||
447 | static void tgui_fill_rect(struct tridentfb_par *par, | ||
448 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | ||
449 | { | ||
450 | t_outb(par, ROP_P, 0x2127); | ||
451 | writemmr(par, OLDCLR, c); | ||
452 | writemmr(par, DRAWFL, 0x4020); | ||
453 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | ||
454 | writemmr(par, OLDDST, point(x, y)); | ||
455 | t_outb(par, 1, OLDCMD); | ||
456 | } | ||
457 | |||
458 | static void tgui_copy_rect(struct tridentfb_par *par, | ||
459 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | ||
460 | { | ||
461 | int flags = 0; | ||
462 | u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp; | ||
463 | |||
464 | if ((x1 < x2) && (y1 == y2)) { | ||
465 | flags |= 0x0200; | ||
466 | x1_tmp = x1 + w - 1; | ||
467 | x2_tmp = x2 + w - 1; | ||
468 | } else { | ||
469 | x1_tmp = x1; | ||
470 | x2_tmp = x2; | ||
471 | } | ||
472 | |||
473 | if (y1 < y2) { | ||
474 | flags |= 0x0100; | ||
475 | y1_tmp = y1 + h - 1; | ||
476 | y2_tmp = y2 + h - 1; | ||
477 | } else { | ||
478 | y1_tmp = y1; | ||
479 | y2_tmp = y2; | ||
480 | } | ||
481 | |||
482 | writemmr(par, DRAWFL, 0x4 | flags); | ||
483 | t_outb(par, ROP_S, 0x2127); | ||
484 | writemmr(par, OLDSRC, point(x1_tmp, y1_tmp)); | ||
485 | writemmr(par, OLDDST, point(x2_tmp, y2_tmp)); | ||
486 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | ||
487 | t_outb(par, 1, OLDCMD); | ||
488 | } | ||
479 | 489 | ||
480 | /* | 490 | /* |
481 | * Accel functions called by the upper layers | 491 | * Accel functions called by the upper layers |
@@ -484,129 +494,162 @@ static struct accel_switch accel_image = { | |||
484 | static void tridentfb_fillrect(struct fb_info *info, | 494 | static void tridentfb_fillrect(struct fb_info *info, |
485 | const struct fb_fillrect *fr) | 495 | const struct fb_fillrect *fr) |
486 | { | 496 | { |
487 | int bpp = info->var.bits_per_pixel; | 497 | struct tridentfb_par *par = info->par; |
488 | int col = 0; | 498 | int col; |
489 | 499 | ||
490 | switch (bpp) { | 500 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
491 | default: | 501 | cfb_fillrect(info, fr); |
492 | case 8: | 502 | return; |
493 | col |= fr->color; | 503 | } |
504 | if (info->var.bits_per_pixel == 8) { | ||
505 | col = fr->color; | ||
494 | col |= col << 8; | 506 | col |= col << 8; |
495 | col |= col << 16; | 507 | col |= col << 16; |
496 | break; | 508 | } else |
497 | case 16: | ||
498 | col = ((u32 *)(info->pseudo_palette))[fr->color]; | 509 | col = ((u32 *)(info->pseudo_palette))[fr->color]; |
499 | break; | 510 | |
500 | case 32: | 511 | par->wait_engine(par); |
501 | col = ((u32 *)(info->pseudo_palette))[fr->color]; | 512 | par->fill_rect(par, fr->dx, fr->dy, fr->width, |
502 | break; | 513 | fr->height, col, fr->rop); |
514 | } | ||
515 | |||
516 | static void tridentfb_imageblit(struct fb_info *info, | ||
517 | const struct fb_image *img) | ||
518 | { | ||
519 | struct tridentfb_par *par = info->par; | ||
520 | int col, bgcol; | ||
521 | |||
522 | if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) { | ||
523 | cfb_imageblit(info, img); | ||
524 | return; | ||
525 | } | ||
526 | if (info->var.bits_per_pixel == 8) { | ||
527 | col = img->fg_color; | ||
528 | col |= col << 8; | ||
529 | col |= col << 16; | ||
530 | bgcol = img->bg_color; | ||
531 | bgcol |= bgcol << 8; | ||
532 | bgcol |= bgcol << 16; | ||
533 | } else { | ||
534 | col = ((u32 *)(info->pseudo_palette))[img->fg_color]; | ||
535 | bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color]; | ||
503 | } | 536 | } |
504 | 537 | ||
505 | acc->fill_rect(fr->dx, fr->dy, fr->width, fr->height, col, fr->rop); | 538 | par->wait_engine(par); |
506 | acc->wait_engine(); | 539 | if (par->image_blit) |
540 | par->image_blit(par, img->data, img->dx, img->dy, | ||
541 | img->width, img->height, col, bgcol); | ||
542 | else | ||
543 | cfb_imageblit(info, img); | ||
507 | } | 544 | } |
545 | |||
508 | static void tridentfb_copyarea(struct fb_info *info, | 546 | static void tridentfb_copyarea(struct fb_info *info, |
509 | const struct fb_copyarea *ca) | 547 | const struct fb_copyarea *ca) |
510 | { | 548 | { |
511 | acc->copy_rect(ca->sx, ca->sy, ca->dx, ca->dy, ca->width, ca->height); | 549 | struct tridentfb_par *par = info->par; |
512 | acc->wait_engine(); | 550 | |
551 | if (info->flags & FBINFO_HWACCEL_DISABLED) { | ||
552 | cfb_copyarea(info, ca); | ||
553 | return; | ||
554 | } | ||
555 | par->wait_engine(par); | ||
556 | par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy, | ||
557 | ca->width, ca->height); | ||
558 | } | ||
559 | |||
560 | static int tridentfb_sync(struct fb_info *info) | ||
561 | { | ||
562 | struct tridentfb_par *par = info->par; | ||
563 | |||
564 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | ||
565 | par->wait_engine(par); | ||
566 | return 0; | ||
513 | } | 567 | } |
514 | #else /* !CONFIG_FB_TRIDENT_ACCEL */ | 568 | #else |
515 | #define tridentfb_fillrect cfb_fillrect | 569 | #define tridentfb_fillrect cfb_fillrect |
516 | #define tridentfb_copyarea cfb_copyarea | 570 | #define tridentfb_copyarea cfb_copyarea |
571 | #define tridentfb_imageblit cfb_imageblit | ||
517 | #endif /* CONFIG_FB_TRIDENT_ACCEL */ | 572 | #endif /* CONFIG_FB_TRIDENT_ACCEL */ |
518 | 573 | ||
519 | |||
520 | /* | 574 | /* |
521 | * Hardware access functions | 575 | * Hardware access functions |
522 | */ | 576 | */ |
523 | 577 | ||
524 | static inline unsigned char read3X4(int reg) | 578 | static inline unsigned char read3X4(struct tridentfb_par *par, int reg) |
525 | { | 579 | { |
526 | struct tridentfb_par *par = (struct tridentfb_par *)fb_info.par; | 580 | return vga_mm_rcrt(par->io_virt, reg); |
527 | writeb(reg, par->io_virt + CRT + 4); | ||
528 | return readb(par->io_virt + CRT + 5); | ||
529 | } | 581 | } |
530 | 582 | ||
531 | static inline void write3X4(int reg, unsigned char val) | 583 | static inline void write3X4(struct tridentfb_par *par, int reg, |
584 | unsigned char val) | ||
532 | { | 585 | { |
533 | struct tridentfb_par *par = (struct tridentfb_par *)fb_info.par; | 586 | vga_mm_wcrt(par->io_virt, reg, val); |
534 | writeb(reg, par->io_virt + CRT + 4); | ||
535 | writeb(val, par->io_virt + CRT + 5); | ||
536 | } | 587 | } |
537 | 588 | ||
538 | static inline unsigned char read3C4(int reg) | 589 | static inline unsigned char read3CE(struct tridentfb_par *par, |
590 | unsigned char reg) | ||
539 | { | 591 | { |
540 | t_outb(reg, 0x3C4); | 592 | return vga_mm_rgfx(par->io_virt, reg); |
541 | return t_inb(0x3C5); | ||
542 | } | 593 | } |
543 | 594 | ||
544 | static inline void write3C4(int reg, unsigned char val) | 595 | static inline void writeAttr(struct tridentfb_par *par, int reg, |
596 | unsigned char val) | ||
545 | { | 597 | { |
546 | t_outb(reg, 0x3C4); | 598 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
547 | t_outb(val, 0x3C5); | 599 | vga_mm_wattr(par->io_virt, reg, val); |
548 | } | 600 | } |
549 | 601 | ||
550 | static inline unsigned char read3CE(int reg) | 602 | static inline void write3CE(struct tridentfb_par *par, int reg, |
603 | unsigned char val) | ||
551 | { | 604 | { |
552 | t_outb(reg, 0x3CE); | 605 | vga_mm_wgfx(par->io_virt, reg, val); |
553 | return t_inb(0x3CF); | ||
554 | } | 606 | } |
555 | 607 | ||
556 | static inline void writeAttr(int reg, unsigned char val) | 608 | static void enable_mmio(struct tridentfb_par *par) |
557 | { | ||
558 | readb(((struct tridentfb_par *)fb_info.par)->io_virt + CRT + 0x0A); /* flip-flop to index */ | ||
559 | t_outb(reg, 0x3C0); | ||
560 | t_outb(val, 0x3C0); | ||
561 | } | ||
562 | |||
563 | static inline void write3CE(int reg, unsigned char val) | ||
564 | { | ||
565 | t_outb(reg, 0x3CE); | ||
566 | t_outb(val, 0x3CF); | ||
567 | } | ||
568 | |||
569 | static void enable_mmio(void) | ||
570 | { | 609 | { |
571 | /* Goto New Mode */ | 610 | /* Goto New Mode */ |
572 | outb(0x0B, 0x3C4); | 611 | vga_io_rseq(0x0B); |
573 | inb(0x3C5); | ||
574 | 612 | ||
575 | /* Unprotect registers */ | 613 | /* Unprotect registers */ |
576 | outb(NewMode1, 0x3C4); | 614 | vga_io_wseq(NewMode1, 0x80); |
577 | outb(0x80, 0x3C5); | 615 | if (!is_oldprotect(par->chip_id)) |
616 | vga_io_wseq(Protection, 0x92); | ||
578 | 617 | ||
579 | /* Enable MMIO */ | 618 | /* Enable MMIO */ |
580 | outb(PCIReg, 0x3D4); | 619 | outb(PCIReg, 0x3D4); |
581 | outb(inb(0x3D5) | 0x01, 0x3D5); | 620 | outb(inb(0x3D5) | 0x01, 0x3D5); |
582 | } | 621 | } |
583 | 622 | ||
584 | static void disable_mmio(void) | 623 | static void disable_mmio(struct tridentfb_par *par) |
585 | { | 624 | { |
586 | /* Goto New Mode */ | 625 | /* Goto New Mode */ |
587 | t_outb(0x0B, 0x3C4); | 626 | vga_mm_rseq(par->io_virt, 0x0B); |
588 | t_inb(0x3C5); | ||
589 | 627 | ||
590 | /* Unprotect registers */ | 628 | /* Unprotect registers */ |
591 | t_outb(NewMode1, 0x3C4); | 629 | vga_mm_wseq(par->io_virt, NewMode1, 0x80); |
592 | t_outb(0x80, 0x3C5); | 630 | if (!is_oldprotect(par->chip_id)) |
631 | vga_mm_wseq(par->io_virt, Protection, 0x92); | ||
593 | 632 | ||
594 | /* Disable MMIO */ | 633 | /* Disable MMIO */ |
595 | t_outb(PCIReg, 0x3D4); | 634 | t_outb(par, PCIReg, 0x3D4); |
596 | t_outb(t_inb(0x3D5) & ~0x01, 0x3D5); | 635 | t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5); |
597 | } | 636 | } |
598 | 637 | ||
599 | #define crtc_unlock() write3X4(CRTVSyncEnd, read3X4(CRTVSyncEnd) & 0x7F) | 638 | static inline void crtc_unlock(struct tridentfb_par *par) |
639 | { | ||
640 | write3X4(par, VGA_CRTC_V_SYNC_END, | ||
641 | read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F); | ||
642 | } | ||
600 | 643 | ||
601 | /* Return flat panel's maximum x resolution */ | 644 | /* Return flat panel's maximum x resolution */ |
602 | static int __devinit get_nativex(void) | 645 | static int __devinit get_nativex(struct tridentfb_par *par) |
603 | { | 646 | { |
604 | int x, y, tmp; | 647 | int x, y, tmp; |
605 | 648 | ||
606 | if (nativex) | 649 | if (nativex) |
607 | return nativex; | 650 | return nativex; |
608 | 651 | ||
609 | tmp = (read3CE(VertStretch) >> 4) & 3; | 652 | tmp = (read3CE(par, VertStretch) >> 4) & 3; |
610 | 653 | ||
611 | switch (tmp) { | 654 | switch (tmp) { |
612 | case 0: | 655 | case 0: |
@@ -632,77 +675,92 @@ static int __devinit get_nativex(void) | |||
632 | } | 675 | } |
633 | 676 | ||
634 | /* Set pitch */ | 677 | /* Set pitch */ |
635 | static void set_lwidth(int width) | 678 | static inline void set_lwidth(struct tridentfb_par *par, int width) |
636 | { | 679 | { |
637 | write3X4(Offset, width & 0xFF); | 680 | write3X4(par, VGA_CRTC_OFFSET, width & 0xFF); |
638 | write3X4(AddColReg, | 681 | write3X4(par, AddColReg, |
639 | (read3X4(AddColReg) & 0xCF) | ((width & 0x300) >> 4)); | 682 | (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4)); |
640 | } | 683 | } |
641 | 684 | ||
642 | /* For resolutions smaller than FP resolution stretch */ | 685 | /* For resolutions smaller than FP resolution stretch */ |
643 | static void screen_stretch(void) | 686 | static void screen_stretch(struct tridentfb_par *par) |
644 | { | 687 | { |
645 | if (chip_id != CYBERBLADEXPAi1) | 688 | if (par->chip_id != CYBERBLADEXPAi1) |
646 | write3CE(BiosReg, 0); | 689 | write3CE(par, BiosReg, 0); |
647 | else | 690 | else |
648 | write3CE(BiosReg, 8); | 691 | write3CE(par, BiosReg, 8); |
649 | write3CE(VertStretch, (read3CE(VertStretch) & 0x7C) | 1); | 692 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1); |
650 | write3CE(HorStretch, (read3CE(HorStretch) & 0x7C) | 1); | 693 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1); |
651 | } | 694 | } |
652 | 695 | ||
653 | /* For resolutions smaller than FP resolution center */ | 696 | /* For resolutions smaller than FP resolution center */ |
654 | static void screen_center(void) | 697 | static inline void screen_center(struct tridentfb_par *par) |
655 | { | 698 | { |
656 | write3CE(VertStretch, (read3CE(VertStretch) & 0x7C) | 0x80); | 699 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80); |
657 | write3CE(HorStretch, (read3CE(HorStretch) & 0x7C) | 0x80); | 700 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80); |
658 | } | 701 | } |
659 | 702 | ||
660 | /* Address of first shown pixel in display memory */ | 703 | /* Address of first shown pixel in display memory */ |
661 | static void set_screen_start(int base) | 704 | static void set_screen_start(struct tridentfb_par *par, int base) |
662 | { | 705 | { |
663 | write3X4(StartAddrLow, base & 0xFF); | 706 | u8 tmp; |
664 | write3X4(StartAddrHigh, (base & 0xFF00) >> 8); | 707 | write3X4(par, VGA_CRTC_START_LO, base & 0xFF); |
665 | write3X4(CRTCModuleTest, | 708 | write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8); |
666 | (read3X4(CRTCModuleTest) & 0xDF) | ((base & 0x10000) >> 11)); | 709 | tmp = read3X4(par, CRTCModuleTest) & 0xDF; |
667 | write3X4(CRTHiOrd, | 710 | write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); |
668 | (read3X4(CRTHiOrd) & 0xF8) | ((base & 0xE0000) >> 17)); | 711 | tmp = read3X4(par, CRTHiOrd) & 0xF8; |
712 | write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17)); | ||
669 | } | 713 | } |
670 | 714 | ||
671 | /* Set dotclock frequency */ | 715 | /* Set dotclock frequency */ |
672 | static void set_vclk(unsigned long freq) | 716 | static void set_vclk(struct tridentfb_par *par, unsigned long freq) |
673 | { | 717 | { |
674 | int m, n, k; | 718 | int m, n, k; |
675 | unsigned long f, fi, d, di; | 719 | unsigned long fi, d, di; |
676 | unsigned char lo = 0, hi = 0; | 720 | unsigned char best_m = 0, best_n = 0, best_k = 0; |
721 | unsigned char hi, lo; | ||
722 | unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1; | ||
677 | 723 | ||
678 | d = 20000; | 724 | d = 20000; |
679 | for (k = 2; k >= 0; k--) | 725 | for (k = shift; k >= 0; k--) |
680 | for (m = 0; m < 63; m++) | 726 | for (m = 1; m < 32; m++) { |
681 | for (n = 0; n < 128; n++) { | 727 | n = ((m + 2) << shift) - 8; |
728 | for (n = (n < 0 ? 0 : n); n < 122; n++) { | ||
682 | fi = ((14318l * (n + 8)) / (m + 2)) >> k; | 729 | fi = ((14318l * (n + 8)) / (m + 2)) >> k; |
683 | if ((di = abs(fi - freq)) < d) { | 730 | di = abs(fi - freq); |
731 | if (di < d || (di == d && k == best_k)) { | ||
684 | d = di; | 732 | d = di; |
685 | f = fi; | 733 | best_n = n; |
686 | lo = n; | 734 | best_m = m; |
687 | hi = (k << 6) | m; | 735 | best_k = k; |
688 | } | 736 | } |
689 | if (fi > freq) | 737 | if (fi > freq) |
690 | break; | 738 | break; |
691 | } | 739 | } |
692 | if (chip3D) { | 740 | } |
693 | write3C4(ClockHigh, hi); | 741 | |
694 | write3C4(ClockLow, lo); | 742 | if (is_oldclock(par->chip_id)) { |
743 | lo = best_n | (best_m << 7); | ||
744 | hi = (best_m >> 1) | (best_k << 4); | ||
695 | } else { | 745 | } else { |
696 | outb(lo, 0x43C8); | 746 | lo = best_n; |
697 | outb(hi, 0x43C9); | 747 | hi = best_m | (best_k << 6); |
748 | } | ||
749 | |||
750 | if (is3Dchip(par->chip_id)) { | ||
751 | vga_mm_wseq(par->io_virt, ClockHigh, hi); | ||
752 | vga_mm_wseq(par->io_virt, ClockLow, lo); | ||
753 | } else { | ||
754 | t_outb(par, lo, 0x43C8); | ||
755 | t_outb(par, hi, 0x43C9); | ||
698 | } | 756 | } |
699 | debug("VCLK = %X %X\n", hi, lo); | 757 | debug("VCLK = %X %X\n", hi, lo); |
700 | } | 758 | } |
701 | 759 | ||
702 | /* Set number of lines for flat panels*/ | 760 | /* Set number of lines for flat panels*/ |
703 | static void set_number_of_lines(int lines) | 761 | static void set_number_of_lines(struct tridentfb_par *par, int lines) |
704 | { | 762 | { |
705 | int tmp = read3CE(CyberEnhance) & 0x8F; | 763 | int tmp = read3CE(par, CyberEnhance) & 0x8F; |
706 | if (lines > 1024) | 764 | if (lines > 1024) |
707 | tmp |= 0x50; | 765 | tmp |= 0x50; |
708 | else if (lines > 768) | 766 | else if (lines > 768) |
@@ -711,24 +769,24 @@ static void set_number_of_lines(int lines) | |||
711 | tmp |= 0x20; | 769 | tmp |= 0x20; |
712 | else if (lines > 480) | 770 | else if (lines > 480) |
713 | tmp |= 0x10; | 771 | tmp |= 0x10; |
714 | write3CE(CyberEnhance, tmp); | 772 | write3CE(par, CyberEnhance, tmp); |
715 | } | 773 | } |
716 | 774 | ||
717 | /* | 775 | /* |
718 | * If we see that FP is active we assume we have one. | 776 | * If we see that FP is active we assume we have one. |
719 | * Otherwise we have a CRT display.User can override. | 777 | * Otherwise we have a CRT display. User can override. |
720 | */ | 778 | */ |
721 | static unsigned int __devinit get_displaytype(void) | 779 | static int __devinit is_flatpanel(struct tridentfb_par *par) |
722 | { | 780 | { |
723 | if (fp) | 781 | if (fp) |
724 | return DISPLAY_FP; | 782 | return 1; |
725 | if (crt || !chipcyber) | 783 | if (crt || !iscyber(par->chip_id)) |
726 | return DISPLAY_CRT; | 784 | return 0; |
727 | return (read3CE(FPConfig) & 0x10) ? DISPLAY_FP : DISPLAY_CRT; | 785 | return (read3CE(par, FPConfig) & 0x10) ? 1 : 0; |
728 | } | 786 | } |
729 | 787 | ||
730 | /* Try detecting the video memory size */ | 788 | /* Try detecting the video memory size */ |
731 | static unsigned int __devinit get_memsize(void) | 789 | static unsigned int __devinit get_memsize(struct tridentfb_par *par) |
732 | { | 790 | { |
733 | unsigned char tmp, tmp2; | 791 | unsigned char tmp, tmp2; |
734 | unsigned int k; | 792 | unsigned int k; |
@@ -737,12 +795,12 @@ static unsigned int __devinit get_memsize(void) | |||
737 | if (memsize) | 795 | if (memsize) |
738 | k = memsize * Kb; | 796 | k = memsize * Kb; |
739 | else | 797 | else |
740 | switch (chip_id) { | 798 | switch (par->chip_id) { |
741 | case CYBER9525DVD: | 799 | case CYBER9525DVD: |
742 | k = 2560 * Kb; | 800 | k = 2560 * Kb; |
743 | break; | 801 | break; |
744 | default: | 802 | default: |
745 | tmp = read3X4(SPR) & 0x0F; | 803 | tmp = read3X4(par, SPR) & 0x0F; |
746 | switch (tmp) { | 804 | switch (tmp) { |
747 | 805 | ||
748 | case 0x01: | 806 | case 0x01: |
@@ -774,7 +832,7 @@ static unsigned int __devinit get_memsize(void) | |||
774 | break; | 832 | break; |
775 | case 0x0E: /* XP */ | 833 | case 0x0E: /* XP */ |
776 | 834 | ||
777 | tmp2 = read3C4(0xC1); | 835 | tmp2 = vga_mm_rseq(par->io_virt, 0xC1); |
778 | switch (tmp2) { | 836 | switch (tmp2) { |
779 | case 0x00: | 837 | case 0x00: |
780 | k = 20 * Mb; | 838 | k = 20 * Mb; |
@@ -812,26 +870,67 @@ static unsigned int __devinit get_memsize(void) | |||
812 | static int tridentfb_check_var(struct fb_var_screeninfo *var, | 870 | static int tridentfb_check_var(struct fb_var_screeninfo *var, |
813 | struct fb_info *info) | 871 | struct fb_info *info) |
814 | { | 872 | { |
873 | struct tridentfb_par *par = info->par; | ||
815 | int bpp = var->bits_per_pixel; | 874 | int bpp = var->bits_per_pixel; |
875 | int line_length; | ||
876 | int ramdac = 230000; /* 230MHz for most 3D chips */ | ||
816 | debug("enter\n"); | 877 | debug("enter\n"); |
817 | 878 | ||
818 | /* check color depth */ | 879 | /* check color depth */ |
819 | if (bpp == 24) | 880 | if (bpp == 24) |
820 | bpp = var->bits_per_pixel = 32; | 881 | bpp = var->bits_per_pixel = 32; |
882 | if (bpp != 8 && bpp != 16 && bpp != 32) | ||
883 | return -EINVAL; | ||
884 | if (par->chip_id == TGUI9440 && bpp == 32) | ||
885 | return -EINVAL; | ||
821 | /* check whether resolution fits on panel and in memory */ | 886 | /* check whether resolution fits on panel and in memory */ |
822 | if (flatpanel && nativex && var->xres > nativex) | 887 | if (par->flatpanel && nativex && var->xres > nativex) |
888 | return -EINVAL; | ||
889 | /* various resolution checks */ | ||
890 | var->xres = (var->xres + 7) & ~0x7; | ||
891 | if (var->xres > var->xres_virtual) | ||
892 | var->xres_virtual = var->xres; | ||
893 | if (var->yres > var->yres_virtual) | ||
894 | var->yres_virtual = var->yres; | ||
895 | if (var->xres_virtual > 4095 || var->yres > 2048) | ||
823 | return -EINVAL; | 896 | return -EINVAL; |
824 | if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len) | 897 | /* prevent from position overflow for acceleration */ |
898 | if (var->yres_virtual > 0xffff) | ||
899 | return -EINVAL; | ||
900 | line_length = var->xres_virtual * bpp / 8; | ||
901 | |||
902 | if (!is3Dchip(par->chip_id) && | ||
903 | !(info->flags & FBINFO_HWACCEL_DISABLED)) { | ||
904 | /* acceleration requires line length to be power of 2 */ | ||
905 | if (line_length <= 512) | ||
906 | var->xres_virtual = 512 * 8 / bpp; | ||
907 | else if (line_length <= 1024) | ||
908 | var->xres_virtual = 1024 * 8 / bpp; | ||
909 | else if (line_length <= 2048) | ||
910 | var->xres_virtual = 2048 * 8 / bpp; | ||
911 | else if (line_length <= 4096) | ||
912 | var->xres_virtual = 4096 * 8 / bpp; | ||
913 | else if (line_length <= 8192) | ||
914 | var->xres_virtual = 8192 * 8 / bpp; | ||
915 | else | ||
916 | return -EINVAL; | ||
917 | |||
918 | line_length = var->xres_virtual * bpp / 8; | ||
919 | } | ||
920 | |||
921 | /* datasheet specifies how to set panning only up to 4 MB */ | ||
922 | if (line_length * (var->yres_virtual - var->yres) > (4 << 20)) | ||
923 | var->yres_virtual = ((4 << 20) / line_length) + var->yres; | ||
924 | |||
925 | if (line_length * var->yres_virtual > info->fix.smem_len) | ||
825 | return -EINVAL; | 926 | return -EINVAL; |
826 | 927 | ||
827 | switch (bpp) { | 928 | switch (bpp) { |
828 | case 8: | 929 | case 8: |
829 | var->red.offset = 0; | 930 | var->red.offset = 0; |
830 | var->green.offset = 0; | 931 | var->red.length = 8; |
831 | var->blue.offset = 0; | 932 | var->green = var->red; |
832 | var->red.length = 6; | 933 | var->blue = var->red; |
833 | var->green.length = 6; | ||
834 | var->blue.length = 6; | ||
835 | break; | 934 | break; |
836 | case 16: | 935 | case 16: |
837 | var->red.offset = 11; | 936 | var->red.offset = 11; |
@@ -852,6 +951,33 @@ static int tridentfb_check_var(struct fb_var_screeninfo *var, | |||
852 | default: | 951 | default: |
853 | return -EINVAL; | 952 | return -EINVAL; |
854 | } | 953 | } |
954 | |||
955 | if (is_xp(par->chip_id)) | ||
956 | ramdac = 350000; | ||
957 | |||
958 | switch (par->chip_id) { | ||
959 | case TGUI9440: | ||
960 | ramdac = (bpp >= 16) ? 45000 : 90000; | ||
961 | break; | ||
962 | case CYBER9320: | ||
963 | case TGUI9660: | ||
964 | ramdac = 135000; | ||
965 | break; | ||
966 | case PROVIDIA9685: | ||
967 | case CYBER9388: | ||
968 | case CYBER9382: | ||
969 | case CYBER9385: | ||
970 | ramdac = 170000; | ||
971 | break; | ||
972 | } | ||
973 | |||
974 | /* The clock is doubled for 32 bpp */ | ||
975 | if (bpp == 32) | ||
976 | ramdac /= 2; | ||
977 | |||
978 | if (PICOS2KHZ(var->pixclock) > ramdac) | ||
979 | return -EINVAL; | ||
980 | |||
855 | debug("exit\n"); | 981 | debug("exit\n"); |
856 | 982 | ||
857 | return 0; | 983 | return 0; |
@@ -862,25 +988,31 @@ static int tridentfb_check_var(struct fb_var_screeninfo *var, | |||
862 | static int tridentfb_pan_display(struct fb_var_screeninfo *var, | 988 | static int tridentfb_pan_display(struct fb_var_screeninfo *var, |
863 | struct fb_info *info) | 989 | struct fb_info *info) |
864 | { | 990 | { |
991 | struct tridentfb_par *par = info->par; | ||
865 | unsigned int offset; | 992 | unsigned int offset; |
866 | 993 | ||
867 | debug("enter\n"); | 994 | debug("enter\n"); |
868 | offset = (var->xoffset + (var->yoffset * var->xres)) | 995 | offset = (var->xoffset + (var->yoffset * var->xres_virtual)) |
869 | * var->bits_per_pixel / 32; | 996 | * var->bits_per_pixel / 32; |
870 | info->var.xoffset = var->xoffset; | 997 | set_screen_start(par, offset); |
871 | info->var.yoffset = var->yoffset; | ||
872 | set_screen_start(offset); | ||
873 | debug("exit\n"); | 998 | debug("exit\n"); |
874 | return 0; | 999 | return 0; |
875 | } | 1000 | } |
876 | 1001 | ||
877 | #define shadowmode_on() write3CE(CyberControl, read3CE(CyberControl) | 0x81) | 1002 | static inline void shadowmode_on(struct tridentfb_par *par) |
878 | #define shadowmode_off() write3CE(CyberControl, read3CE(CyberControl) & 0x7E) | 1003 | { |
1004 | write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81); | ||
1005 | } | ||
1006 | |||
1007 | static inline void shadowmode_off(struct tridentfb_par *par) | ||
1008 | { | ||
1009 | write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E); | ||
1010 | } | ||
879 | 1011 | ||
880 | /* Set the hardware to the requested video mode */ | 1012 | /* Set the hardware to the requested video mode */ |
881 | static int tridentfb_set_par(struct fb_info *info) | 1013 | static int tridentfb_set_par(struct fb_info *info) |
882 | { | 1014 | { |
883 | struct tridentfb_par *par = (struct tridentfb_par *)(info->par); | 1015 | struct tridentfb_par *par = info->par; |
884 | u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend; | 1016 | u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend; |
885 | u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend; | 1017 | u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend; |
886 | struct fb_var_screeninfo *var = &info->var; | 1018 | struct fb_var_screeninfo *var = &info->var; |
@@ -891,58 +1023,73 @@ static int tridentfb_set_par(struct fb_info *info) | |||
891 | debug("enter\n"); | 1023 | debug("enter\n"); |
892 | hdispend = var->xres / 8 - 1; | 1024 | hdispend = var->xres / 8 - 1; |
893 | hsyncstart = (var->xres + var->right_margin) / 8; | 1025 | hsyncstart = (var->xres + var->right_margin) / 8; |
894 | hsyncend = var->hsync_len / 8; | 1026 | hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8; |
895 | htotal = | 1027 | htotal = (var->xres + var->left_margin + var->right_margin + |
896 | (var->xres + var->left_margin + var->right_margin + | 1028 | var->hsync_len) / 8 - 5; |
897 | var->hsync_len) / 8 - 10; | ||
898 | hblankstart = hdispend + 1; | 1029 | hblankstart = hdispend + 1; |
899 | hblankend = htotal + 5; | 1030 | hblankend = htotal + 3; |
900 | 1031 | ||
901 | vdispend = var->yres - 1; | 1032 | vdispend = var->yres - 1; |
902 | vsyncstart = var->yres + var->lower_margin; | 1033 | vsyncstart = var->yres + var->lower_margin; |
903 | vsyncend = var->vsync_len; | 1034 | vsyncend = vsyncstart + var->vsync_len; |
904 | vtotal = var->upper_margin + vsyncstart + vsyncend - 2; | 1035 | vtotal = var->upper_margin + vsyncend - 2; |
905 | vblankstart = var->yres; | 1036 | vblankstart = vdispend + 1; |
906 | vblankend = vtotal + 2; | 1037 | vblankend = vtotal; |
1038 | |||
1039 | if (info->var.vmode & FB_VMODE_INTERLACED) { | ||
1040 | vtotal /= 2; | ||
1041 | vdispend /= 2; | ||
1042 | vsyncstart /= 2; | ||
1043 | vsyncend /= 2; | ||
1044 | vblankstart /= 2; | ||
1045 | vblankend /= 2; | ||
1046 | } | ||
907 | 1047 | ||
908 | crtc_unlock(); | 1048 | enable_mmio(par); |
909 | write3CE(CyberControl, 8); | 1049 | crtc_unlock(par); |
1050 | write3CE(par, CyberControl, 8); | ||
1051 | tmp = 0xEB; | ||
1052 | if (var->sync & FB_SYNC_HOR_HIGH_ACT) | ||
1053 | tmp &= ~0x40; | ||
1054 | if (var->sync & FB_SYNC_VERT_HIGH_ACT) | ||
1055 | tmp &= ~0x80; | ||
910 | 1056 | ||
911 | if (flatpanel && var->xres < nativex) { | 1057 | if (par->flatpanel && var->xres < nativex) { |
912 | /* | 1058 | /* |
913 | * on flat panels with native size larger | 1059 | * on flat panels with native size larger |
914 | * than requested resolution decide whether | 1060 | * than requested resolution decide whether |
915 | * we stretch or center | 1061 | * we stretch or center |
916 | */ | 1062 | */ |
917 | t_outb(0xEB, 0x3C2); | 1063 | t_outb(par, tmp | 0xC0, VGA_MIS_W); |
918 | 1064 | ||
919 | shadowmode_on(); | 1065 | shadowmode_on(par); |
920 | 1066 | ||
921 | if (center) | 1067 | if (center) |
922 | screen_center(); | 1068 | screen_center(par); |
923 | else if (stretch) | 1069 | else if (stretch) |
924 | screen_stretch(); | 1070 | screen_stretch(par); |
925 | 1071 | ||
926 | } else { | 1072 | } else { |
927 | t_outb(0x2B, 0x3C2); | 1073 | t_outb(par, tmp, VGA_MIS_W); |
928 | write3CE(CyberControl, 8); | 1074 | write3CE(par, CyberControl, 8); |
929 | } | 1075 | } |
930 | 1076 | ||
931 | /* vertical timing values */ | 1077 | /* vertical timing values */ |
932 | write3X4(CRTVTotal, vtotal & 0xFF); | 1078 | write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF); |
933 | write3X4(CRTVDispEnd, vdispend & 0xFF); | 1079 | write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF); |
934 | write3X4(CRTVSyncStart, vsyncstart & 0xFF); | 1080 | write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF); |
935 | write3X4(CRTVSyncEnd, (vsyncend & 0x0F)); | 1081 | write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F)); |
936 | write3X4(CRTVBlankStart, vblankstart & 0xFF); | 1082 | write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF); |
937 | write3X4(CRTVBlankEnd, 0 /* p->vblankend & 0xFF */ ); | 1083 | write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF); |
938 | 1084 | ||
939 | /* horizontal timing values */ | 1085 | /* horizontal timing values */ |
940 | write3X4(CRTHTotal, htotal & 0xFF); | 1086 | write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF); |
941 | write3X4(CRTHDispEnd, hdispend & 0xFF); | 1087 | write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF); |
942 | write3X4(CRTHSyncStart, hsyncstart & 0xFF); | 1088 | write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF); |
943 | write3X4(CRTHSyncEnd, (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); | 1089 | write3X4(par, VGA_CRTC_H_SYNC_END, |
944 | write3X4(CRTHBlankStart, hblankstart & 0xFF); | 1090 | (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); |
945 | write3X4(CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */ ); | 1091 | write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF); |
1092 | write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F); | ||
946 | 1093 | ||
947 | /* higher bits of vertical timing values */ | 1094 | /* higher bits of vertical timing values */ |
948 | tmp = 0x10; | 1095 | tmp = 0x10; |
@@ -954,39 +1101,43 @@ static int tridentfb_set_par(struct fb_info *info) | |||
954 | if (vtotal & 0x200) tmp |= 0x20; | 1101 | if (vtotal & 0x200) tmp |= 0x20; |
955 | if (vdispend & 0x200) tmp |= 0x40; | 1102 | if (vdispend & 0x200) tmp |= 0x40; |
956 | if (vsyncstart & 0x200) tmp |= 0x80; | 1103 | if (vsyncstart & 0x200) tmp |= 0x80; |
957 | write3X4(CRTOverflow, tmp); | 1104 | write3X4(par, VGA_CRTC_OVERFLOW, tmp); |
958 | 1105 | ||
959 | tmp = read3X4(CRTHiOrd) | 0x08; /* line compare bit 10 */ | 1106 | tmp = read3X4(par, CRTHiOrd) & 0x07; |
1107 | tmp |= 0x08; /* line compare bit 10 */ | ||
960 | if (vtotal & 0x400) tmp |= 0x80; | 1108 | if (vtotal & 0x400) tmp |= 0x80; |
961 | if (vblankstart & 0x400) tmp |= 0x40; | 1109 | if (vblankstart & 0x400) tmp |= 0x40; |
962 | if (vsyncstart & 0x400) tmp |= 0x20; | 1110 | if (vsyncstart & 0x400) tmp |= 0x20; |
963 | if (vdispend & 0x400) tmp |= 0x10; | 1111 | if (vdispend & 0x400) tmp |= 0x10; |
964 | write3X4(CRTHiOrd, tmp); | 1112 | write3X4(par, CRTHiOrd, tmp); |
965 | 1113 | ||
966 | tmp = 0; | 1114 | tmp = (htotal >> 8) & 0x01; |
967 | if (htotal & 0x800) tmp |= 0x800 >> 11; | 1115 | tmp |= (hdispend >> 7) & 0x02; |
968 | if (hblankstart & 0x800) tmp |= 0x800 >> 7; | 1116 | tmp |= (hsyncstart >> 5) & 0x08; |
969 | write3X4(HorizOverflow, tmp); | 1117 | tmp |= (hblankstart >> 4) & 0x10; |
1118 | write3X4(par, HorizOverflow, tmp); | ||
970 | 1119 | ||
971 | tmp = 0x40; | 1120 | tmp = 0x40; |
972 | if (vblankstart & 0x200) tmp |= 0x20; | 1121 | if (vblankstart & 0x200) tmp |= 0x20; |
973 | //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ | 1122 | //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ |
974 | write3X4(CRTMaxScanLine, tmp); | 1123 | write3X4(par, VGA_CRTC_MAX_SCAN, tmp); |
975 | 1124 | ||
976 | write3X4(CRTLineCompare, 0xFF); | 1125 | write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF); |
977 | write3X4(CRTPRowScan, 0); | 1126 | write3X4(par, VGA_CRTC_PRESET_ROW, 0); |
978 | write3X4(CRTModeControl, 0xC3); | 1127 | write3X4(par, VGA_CRTC_MODE, 0xC3); |
979 | 1128 | ||
980 | write3X4(LinearAddReg, 0x20); /* enable linear addressing */ | 1129 | write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */ |
981 | 1130 | ||
982 | tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80; | 1131 | tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80; |
983 | write3X4(CRTCModuleTest, tmp); /* enable access extended memory */ | 1132 | /* enable access extended memory */ |
984 | 1133 | write3X4(par, CRTCModuleTest, tmp); | |
985 | write3X4(GraphEngReg, 0x80); /* enable GE for text acceleration */ | 1134 | tmp = read3CE(par, MiscIntContReg) & ~0x4; |
1135 | if (info->var.vmode & FB_VMODE_INTERLACED) | ||
1136 | tmp |= 0x4; | ||
1137 | write3CE(par, MiscIntContReg, tmp); | ||
986 | 1138 | ||
987 | #ifdef CONFIG_FB_TRIDENT_ACCEL | 1139 | /* enable GE for text acceleration */ |
988 | acc->init_accel(info->var.xres, bpp); | 1140 | write3X4(par, GraphEngReg, 0x80); |
989 | #endif | ||
990 | 1141 | ||
991 | switch (bpp) { | 1142 | switch (bpp) { |
992 | case 8: | 1143 | case 8: |
@@ -1003,57 +1154,59 @@ static int tridentfb_set_par(struct fb_info *info) | |||
1003 | break; | 1154 | break; |
1004 | } | 1155 | } |
1005 | 1156 | ||
1006 | write3X4(PixelBusReg, tmp); | 1157 | write3X4(par, PixelBusReg, tmp); |
1007 | 1158 | ||
1008 | tmp = 0x10; | 1159 | tmp = read3X4(par, DRAMControl); |
1009 | if (chipcyber) | 1160 | if (!is_oldprotect(par->chip_id)) |
1161 | tmp |= 0x10; | ||
1162 | if (iscyber(par->chip_id)) | ||
1010 | tmp |= 0x20; | 1163 | tmp |= 0x20; |
1011 | write3X4(DRAMControl, tmp); /* both IO, linear enable */ | 1164 | write3X4(par, DRAMControl, tmp); /* both IO, linear enable */ |
1012 | 1165 | ||
1013 | write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40); | 1166 | write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40); |
1014 | write3X4(Performance, 0x92); | 1167 | if (!is_xp(par->chip_id)) |
1015 | write3X4(PCIReg, 0x07); /* MMIO & PCI read and write burst enable */ | 1168 | write3X4(par, Performance, read3X4(par, Performance) | 0x10); |
1169 | /* MMIO & PCI read and write burst enable */ | ||
1170 | if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975) | ||
1171 | write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06); | ||
1172 | |||
1173 | vga_mm_wseq(par->io_virt, 0, 3); | ||
1174 | vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */ | ||
1175 | /* enable 4 maps because needed in chain4 mode */ | ||
1176 | vga_mm_wseq(par->io_virt, 2, 0x0F); | ||
1177 | vga_mm_wseq(par->io_virt, 3, 0); | ||
1178 | vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */ | ||
1016 | 1179 | ||
1017 | /* convert from picoseconds to kHz */ | 1180 | /* convert from picoseconds to kHz */ |
1018 | vclk = PICOS2KHZ(info->var.pixclock); | 1181 | vclk = PICOS2KHZ(info->var.pixclock); |
1019 | if (bpp == 32) | 1182 | |
1183 | /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ | ||
1184 | tmp = read3CE(par, MiscExtFunc) & 0xF0; | ||
1185 | if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) { | ||
1186 | tmp |= 8; | ||
1020 | vclk *= 2; | 1187 | vclk *= 2; |
1021 | set_vclk(vclk); | ||
1022 | |||
1023 | write3C4(0, 3); | ||
1024 | write3C4(1, 1); /* set char clock 8 dots wide */ | ||
1025 | write3C4(2, 0x0F); /* enable 4 maps because needed in chain4 mode */ | ||
1026 | write3C4(3, 0); | ||
1027 | write3C4(4, 0x0E); /* memory mode enable bitmaps ?? */ | ||
1028 | |||
1029 | write3CE(MiscExtFunc, (bpp == 32) ? 0x1A : 0x12); /* divide clock by 2 if 32bpp */ | ||
1030 | /* chain4 mode display and CPU path */ | ||
1031 | write3CE(0x5, 0x40); /* no CGA compat, allow 256 col */ | ||
1032 | write3CE(0x6, 0x05); /* graphics mode */ | ||
1033 | write3CE(0x7, 0x0F); /* planes? */ | ||
1034 | |||
1035 | if (chip_id == CYBERBLADEXPAi1) { | ||
1036 | /* This fixes snow-effect in 32 bpp */ | ||
1037 | write3X4(CRTHSyncStart, 0x84); | ||
1038 | } | 1188 | } |
1189 | set_vclk(par, vclk); | ||
1190 | write3CE(par, MiscExtFunc, tmp | 0x12); | ||
1191 | write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */ | ||
1192 | write3CE(par, 0x6, 0x05); /* graphics mode */ | ||
1193 | write3CE(par, 0x7, 0x0F); /* planes? */ | ||
1039 | 1194 | ||
1040 | writeAttr(0x10, 0x41); /* graphics mode and support 256 color modes */ | 1195 | /* graphics mode and support 256 color modes */ |
1041 | writeAttr(0x12, 0x0F); /* planes */ | 1196 | writeAttr(par, 0x10, 0x41); |
1042 | writeAttr(0x13, 0); /* horizontal pel panning */ | 1197 | writeAttr(par, 0x12, 0x0F); /* planes */ |
1198 | writeAttr(par, 0x13, 0); /* horizontal pel panning */ | ||
1043 | 1199 | ||
1044 | /* colors */ | 1200 | /* colors */ |
1045 | for (tmp = 0; tmp < 0x10; tmp++) | 1201 | for (tmp = 0; tmp < 0x10; tmp++) |
1046 | writeAttr(tmp, tmp); | 1202 | writeAttr(par, tmp, tmp); |
1047 | readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */ | 1203 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
1048 | t_outb(0x20, 0x3C0); /* enable attr */ | 1204 | t_outb(par, 0x20, VGA_ATT_W); /* enable attr */ |
1049 | 1205 | ||
1050 | switch (bpp) { | 1206 | switch (bpp) { |
1051 | case 8: | 1207 | case 8: |
1052 | tmp = 0; | 1208 | tmp = 0; |
1053 | break; | 1209 | break; |
1054 | case 15: | ||
1055 | tmp = 0x10; | ||
1056 | break; | ||
1057 | case 16: | 1210 | case 16: |
1058 | tmp = 0x30; | 1211 | tmp = 0x30; |
1059 | break; | 1212 | break; |
@@ -1063,19 +1216,23 @@ static int tridentfb_set_par(struct fb_info *info) | |||
1063 | break; | 1216 | break; |
1064 | } | 1217 | } |
1065 | 1218 | ||
1066 | t_inb(0x3C8); | 1219 | t_inb(par, VGA_PEL_IW); |
1067 | t_inb(0x3C6); | 1220 | t_inb(par, VGA_PEL_MSK); |
1068 | t_inb(0x3C6); | 1221 | t_inb(par, VGA_PEL_MSK); |
1069 | t_inb(0x3C6); | 1222 | t_inb(par, VGA_PEL_MSK); |
1070 | t_inb(0x3C6); | 1223 | t_inb(par, VGA_PEL_MSK); |
1071 | t_outb(tmp, 0x3C6); | 1224 | t_outb(par, tmp, VGA_PEL_MSK); |
1072 | t_inb(0x3C8); | 1225 | t_inb(par, VGA_PEL_IW); |
1073 | 1226 | ||
1074 | if (flatpanel) | 1227 | if (par->flatpanel) |
1075 | set_number_of_lines(info->var.yres); | 1228 | set_number_of_lines(par, info->var.yres); |
1076 | set_lwidth(info->var.xres * bpp / (4 * 16)); | 1229 | info->fix.line_length = info->var.xres_virtual * bpp / 8; |
1230 | set_lwidth(par, info->fix.line_length / 8); | ||
1231 | |||
1232 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | ||
1233 | par->init_accel(par, info->var.xres_virtual, bpp); | ||
1234 | |||
1077 | info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | 1235 | info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
1078 | info->fix.line_length = info->var.xres * (bpp >> 3); | ||
1079 | info->cmap.len = (bpp == 8) ? 256 : 16; | 1236 | info->cmap.len = (bpp == 8) ? 256 : 16; |
1080 | debug("exit\n"); | 1237 | debug("exit\n"); |
1081 | return 0; | 1238 | return 0; |
@@ -1087,17 +1244,18 @@ static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |||
1087 | struct fb_info *info) | 1244 | struct fb_info *info) |
1088 | { | 1245 | { |
1089 | int bpp = info->var.bits_per_pixel; | 1246 | int bpp = info->var.bits_per_pixel; |
1247 | struct tridentfb_par *par = info->par; | ||
1090 | 1248 | ||
1091 | if (regno >= info->cmap.len) | 1249 | if (regno >= info->cmap.len) |
1092 | return 1; | 1250 | return 1; |
1093 | 1251 | ||
1094 | if (bpp == 8) { | 1252 | if (bpp == 8) { |
1095 | t_outb(0xFF, 0x3C6); | 1253 | t_outb(par, 0xFF, VGA_PEL_MSK); |
1096 | t_outb(regno, 0x3C8); | 1254 | t_outb(par, regno, VGA_PEL_IW); |
1097 | 1255 | ||
1098 | t_outb(red >> 10, 0x3C9); | 1256 | t_outb(par, red >> 10, VGA_PEL_D); |
1099 | t_outb(green >> 10, 0x3C9); | 1257 | t_outb(par, green >> 10, VGA_PEL_D); |
1100 | t_outb(blue >> 10, 0x3C9); | 1258 | t_outb(par, blue >> 10, VGA_PEL_D); |
1101 | 1259 | ||
1102 | } else if (regno < 16) { | 1260 | } else if (regno < 16) { |
1103 | if (bpp == 16) { /* RGB 565 */ | 1261 | if (bpp == 16) { /* RGB 565 */ |
@@ -1108,28 +1266,28 @@ static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |||
1108 | col |= col << 16; | 1266 | col |= col << 16; |
1109 | ((u32 *)(info->pseudo_palette))[regno] = col; | 1267 | ((u32 *)(info->pseudo_palette))[regno] = col; |
1110 | } else if (bpp == 32) /* ARGB 8888 */ | 1268 | } else if (bpp == 32) /* ARGB 8888 */ |
1111 | ((u32*)info->pseudo_palette)[regno] = | 1269 | ((u32 *)info->pseudo_palette)[regno] = |
1112 | ((transp & 0xFF00) << 16) | | 1270 | ((transp & 0xFF00) << 16) | |
1113 | ((red & 0xFF00) << 8) | | 1271 | ((red & 0xFF00) << 8) | |
1114 | ((green & 0xFF00)) | | 1272 | ((green & 0xFF00)) | |
1115 | ((blue & 0xFF00) >> 8); | 1273 | ((blue & 0xFF00) >> 8); |
1116 | } | 1274 | } |
1117 | 1275 | ||
1118 | /* debug("exit\n"); */ | ||
1119 | return 0; | 1276 | return 0; |
1120 | } | 1277 | } |
1121 | 1278 | ||
1122 | /* Try blanking the screen.For flat panels it does nothing */ | 1279 | /* Try blanking the screen. For flat panels it does nothing */ |
1123 | static int tridentfb_blank(int blank_mode, struct fb_info *info) | 1280 | static int tridentfb_blank(int blank_mode, struct fb_info *info) |
1124 | { | 1281 | { |
1125 | unsigned char PMCont, DPMSCont; | 1282 | unsigned char PMCont, DPMSCont; |
1283 | struct tridentfb_par *par = info->par; | ||
1126 | 1284 | ||
1127 | debug("enter\n"); | 1285 | debug("enter\n"); |
1128 | if (flatpanel) | 1286 | if (par->flatpanel) |
1129 | return 0; | 1287 | return 0; |
1130 | t_outb(0x04, 0x83C8); /* Read DPMS Control */ | 1288 | t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */ |
1131 | PMCont = t_inb(0x83C6) & 0xFC; | 1289 | PMCont = t_inb(par, 0x83C6) & 0xFC; |
1132 | DPMSCont = read3CE(PowerStatus) & 0xFC; | 1290 | DPMSCont = read3CE(par, PowerStatus) & 0xFC; |
1133 | switch (blank_mode) { | 1291 | switch (blank_mode) { |
1134 | case FB_BLANK_UNBLANK: | 1292 | case FB_BLANK_UNBLANK: |
1135 | /* Screen: On, HSync: On, VSync: On */ | 1293 | /* Screen: On, HSync: On, VSync: On */ |
@@ -1155,9 +1313,9 @@ static int tridentfb_blank(int blank_mode, struct fb_info *info) | |||
1155 | break; | 1313 | break; |
1156 | } | 1314 | } |
1157 | 1315 | ||
1158 | write3CE(PowerStatus, DPMSCont); | 1316 | write3CE(par, PowerStatus, DPMSCont); |
1159 | t_outb(4, 0x83C8); | 1317 | t_outb(par, 4, 0x83C8); |
1160 | t_outb(PMCont, 0x83C6); | 1318 | t_outb(par, PMCont, 0x83C6); |
1161 | 1319 | ||
1162 | debug("exit\n"); | 1320 | debug("exit\n"); |
1163 | 1321 | ||
@@ -1174,33 +1332,46 @@ static struct fb_ops tridentfb_ops = { | |||
1174 | .fb_set_par = tridentfb_set_par, | 1332 | .fb_set_par = tridentfb_set_par, |
1175 | .fb_fillrect = tridentfb_fillrect, | 1333 | .fb_fillrect = tridentfb_fillrect, |
1176 | .fb_copyarea = tridentfb_copyarea, | 1334 | .fb_copyarea = tridentfb_copyarea, |
1177 | .fb_imageblit = cfb_imageblit, | 1335 | .fb_imageblit = tridentfb_imageblit, |
1336 | #ifdef CONFIG_FB_TRIDENT_ACCEL | ||
1337 | .fb_sync = tridentfb_sync, | ||
1338 | #endif | ||
1178 | }; | 1339 | }; |
1179 | 1340 | ||
1180 | static int __devinit trident_pci_probe(struct pci_dev * dev, | 1341 | static int __devinit trident_pci_probe(struct pci_dev *dev, |
1181 | const struct pci_device_id * id) | 1342 | const struct pci_device_id *id) |
1182 | { | 1343 | { |
1183 | int err; | 1344 | int err; |
1184 | unsigned char revision; | 1345 | unsigned char revision; |
1346 | struct fb_info *info; | ||
1347 | struct tridentfb_par *default_par; | ||
1348 | int chip3D; | ||
1349 | int chip_id; | ||
1185 | 1350 | ||
1186 | err = pci_enable_device(dev); | 1351 | err = pci_enable_device(dev); |
1187 | if (err) | 1352 | if (err) |
1188 | return err; | 1353 | return err; |
1189 | 1354 | ||
1190 | chip_id = id->device; | 1355 | info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev); |
1356 | if (!info) | ||
1357 | return -ENOMEM; | ||
1358 | default_par = info->par; | ||
1191 | 1359 | ||
1192 | if (chip_id == CYBERBLADEi1) | 1360 | chip_id = id->device; |
1193 | output("*** Please do use cyblafb, Cyberblade/i1 support " | ||
1194 | "will soon be removed from tridentfb!\n"); | ||
1195 | 1361 | ||
1362 | #ifndef CONFIG_FB_TRIDENT_ACCEL | ||
1363 | noaccel = 1; | ||
1364 | #endif | ||
1196 | 1365 | ||
1197 | /* If PCI id is 0x9660 then further detect chip type */ | 1366 | /* If PCI id is 0x9660 then further detect chip type */ |
1198 | 1367 | ||
1199 | if (chip_id == TGUI9660) { | 1368 | if (chip_id == TGUI9660) { |
1200 | outb(RevisionID, 0x3C4); | 1369 | revision = vga_io_rseq(RevisionID); |
1201 | revision = inb(0x3C5); | ||
1202 | 1370 | ||
1203 | switch (revision) { | 1371 | switch (revision) { |
1372 | case 0x21: | ||
1373 | chip_id = PROVIDIA9685; | ||
1374 | break; | ||
1204 | case 0x22: | 1375 | case 0x22: |
1205 | case 0x23: | 1376 | case 0x23: |
1206 | chip_id = CYBER9397; | 1377 | chip_id = CYBER9397; |
@@ -1229,123 +1400,170 @@ static int __devinit trident_pci_probe(struct pci_dev * dev, | |||
1229 | } | 1400 | } |
1230 | 1401 | ||
1231 | chip3D = is3Dchip(chip_id); | 1402 | chip3D = is3Dchip(chip_id); |
1232 | chipcyber = iscyber(chip_id); | ||
1233 | 1403 | ||
1234 | if (is_xp(chip_id)) { | 1404 | if (is_xp(chip_id)) { |
1235 | acc = &accel_xp; | 1405 | default_par->init_accel = xp_init_accel; |
1406 | default_par->wait_engine = xp_wait_engine; | ||
1407 | default_par->fill_rect = xp_fill_rect; | ||
1408 | default_par->copy_rect = xp_copy_rect; | ||
1409 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP; | ||
1236 | } else if (is_blade(chip_id)) { | 1410 | } else if (is_blade(chip_id)) { |
1237 | acc = &accel_blade; | 1411 | default_par->init_accel = blade_init_accel; |
1238 | } else { | 1412 | default_par->wait_engine = blade_wait_engine; |
1239 | acc = &accel_image; | 1413 | default_par->fill_rect = blade_fill_rect; |
1414 | default_par->copy_rect = blade_copy_rect; | ||
1415 | default_par->image_blit = blade_image_blit; | ||
1416 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D; | ||
1417 | } else if (chip3D) { /* 3DImage family left */ | ||
1418 | default_par->init_accel = image_init_accel; | ||
1419 | default_par->wait_engine = image_wait_engine; | ||
1420 | default_par->fill_rect = image_fill_rect; | ||
1421 | default_par->copy_rect = image_copy_rect; | ||
1422 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE; | ||
1423 | } else { /* TGUI 9440/96XX family */ | ||
1424 | default_par->init_accel = tgui_init_accel; | ||
1425 | default_par->wait_engine = xp_wait_engine; | ||
1426 | default_par->fill_rect = tgui_fill_rect; | ||
1427 | default_par->copy_rect = tgui_copy_rect; | ||
1428 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI; | ||
1240 | } | 1429 | } |
1241 | 1430 | ||
1242 | /* acceleration is on by default for 3D chips */ | 1431 | default_par->chip_id = chip_id; |
1243 | defaultaccel = chip3D && !noaccel; | ||
1244 | |||
1245 | fb_info.par = &default_par; | ||
1246 | 1432 | ||
1247 | /* setup MMIO region */ | 1433 | /* setup MMIO region */ |
1248 | tridentfb_fix.mmio_start = pci_resource_start(dev, 1); | 1434 | tridentfb_fix.mmio_start = pci_resource_start(dev, 1); |
1249 | tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000; | 1435 | tridentfb_fix.mmio_len = pci_resource_len(dev, 1); |
1250 | 1436 | ||
1251 | if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) { | 1437 | if (!request_mem_region(tridentfb_fix.mmio_start, |
1438 | tridentfb_fix.mmio_len, "tridentfb")) { | ||
1252 | debug("request_region failed!\n"); | 1439 | debug("request_region failed!\n"); |
1440 | framebuffer_release(info); | ||
1253 | return -1; | 1441 | return -1; |
1254 | } | 1442 | } |
1255 | 1443 | ||
1256 | default_par.io_virt = ioremap_nocache(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); | 1444 | default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start, |
1445 | tridentfb_fix.mmio_len); | ||
1257 | 1446 | ||
1258 | if (!default_par.io_virt) { | 1447 | if (!default_par->io_virt) { |
1259 | debug("ioremap failed\n"); | 1448 | debug("ioremap failed\n"); |
1260 | err = -1; | 1449 | err = -1; |
1261 | goto out_unmap1; | 1450 | goto out_unmap1; |
1262 | } | 1451 | } |
1263 | 1452 | ||
1264 | enable_mmio(); | 1453 | enable_mmio(default_par); |
1265 | 1454 | ||
1266 | /* setup framebuffer memory */ | 1455 | /* setup framebuffer memory */ |
1267 | tridentfb_fix.smem_start = pci_resource_start(dev, 0); | 1456 | tridentfb_fix.smem_start = pci_resource_start(dev, 0); |
1268 | tridentfb_fix.smem_len = get_memsize(); | 1457 | tridentfb_fix.smem_len = get_memsize(default_par); |
1269 | 1458 | ||
1270 | if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) { | 1459 | if (!request_mem_region(tridentfb_fix.smem_start, |
1460 | tridentfb_fix.smem_len, "tridentfb")) { | ||
1271 | debug("request_mem_region failed!\n"); | 1461 | debug("request_mem_region failed!\n"); |
1272 | disable_mmio(); | 1462 | disable_mmio(info->par); |
1273 | err = -1; | 1463 | err = -1; |
1274 | goto out_unmap1; | 1464 | goto out_unmap1; |
1275 | } | 1465 | } |
1276 | 1466 | ||
1277 | fb_info.screen_base = ioremap_nocache(tridentfb_fix.smem_start, | 1467 | info->screen_base = ioremap_nocache(tridentfb_fix.smem_start, |
1278 | tridentfb_fix.smem_len); | 1468 | tridentfb_fix.smem_len); |
1279 | 1469 | ||
1280 | if (!fb_info.screen_base) { | 1470 | if (!info->screen_base) { |
1281 | debug("ioremap failed\n"); | 1471 | debug("ioremap failed\n"); |
1282 | err = -1; | 1472 | err = -1; |
1283 | goto out_unmap2; | 1473 | goto out_unmap2; |
1284 | } | 1474 | } |
1285 | 1475 | ||
1286 | output("%s board found\n", pci_name(dev)); | 1476 | default_par->flatpanel = is_flatpanel(default_par); |
1287 | displaytype = get_displaytype(); | ||
1288 | 1477 | ||
1289 | if (flatpanel) | 1478 | if (default_par->flatpanel) |
1290 | nativex = get_nativex(); | 1479 | nativex = get_nativex(default_par); |
1291 | 1480 | ||
1292 | fb_info.fix = tridentfb_fix; | 1481 | info->fix = tridentfb_fix; |
1293 | fb_info.fbops = &tridentfb_ops; | 1482 | info->fbops = &tridentfb_ops; |
1483 | info->pseudo_palette = default_par->pseudo_pal; | ||
1294 | 1484 | ||
1485 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; | ||
1486 | if (!noaccel && default_par->init_accel) { | ||
1487 | info->flags &= ~FBINFO_HWACCEL_DISABLED; | ||
1488 | info->flags |= FBINFO_HWACCEL_COPYAREA; | ||
1489 | info->flags |= FBINFO_HWACCEL_FILLRECT; | ||
1490 | } else | ||
1491 | info->flags |= FBINFO_HWACCEL_DISABLED; | ||
1295 | 1492 | ||
1296 | fb_info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; | 1493 | info->pixmap.addr = kmalloc(4096, GFP_KERNEL); |
1297 | #ifdef CONFIG_FB_TRIDENT_ACCEL | 1494 | if (!info->pixmap.addr) { |
1298 | fb_info.flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT; | 1495 | err = -ENOMEM; |
1299 | #endif | 1496 | goto out_unmap2; |
1300 | fb_info.pseudo_palette = pseudo_pal; | 1497 | } |
1498 | |||
1499 | info->pixmap.size = 4096; | ||
1500 | info->pixmap.buf_align = 4; | ||
1501 | info->pixmap.scan_align = 1; | ||
1502 | info->pixmap.access_align = 32; | ||
1503 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | ||
1301 | 1504 | ||
1302 | if (!fb_find_mode(&default_var, &fb_info, | 1505 | if (default_par->image_blit) { |
1506 | info->flags |= FBINFO_HWACCEL_IMAGEBLIT; | ||
1507 | info->pixmap.scan_align = 4; | ||
1508 | } | ||
1509 | |||
1510 | if (noaccel) { | ||
1511 | printk(KERN_DEBUG "disabling acceleration\n"); | ||
1512 | info->flags |= FBINFO_HWACCEL_DISABLED; | ||
1513 | info->pixmap.scan_align = 1; | ||
1514 | } | ||
1515 | |||
1516 | if (!fb_find_mode(&info->var, info, | ||
1303 | mode_option, NULL, 0, NULL, bpp)) { | 1517 | mode_option, NULL, 0, NULL, bpp)) { |
1304 | err = -EINVAL; | 1518 | err = -EINVAL; |
1305 | goto out_unmap2; | 1519 | goto out_unmap2; |
1306 | } | 1520 | } |
1307 | err = fb_alloc_cmap(&fb_info.cmap, 256, 0); | 1521 | err = fb_alloc_cmap(&info->cmap, 256, 0); |
1308 | if (err < 0) | 1522 | if (err < 0) |
1309 | goto out_unmap2; | 1523 | goto out_unmap2; |
1310 | 1524 | ||
1311 | if (defaultaccel && acc) | 1525 | info->var.activate |= FB_ACTIVATE_NOW; |
1312 | default_var.accel_flags |= FB_ACCELF_TEXT; | 1526 | info->device = &dev->dev; |
1313 | else | 1527 | if (register_framebuffer(info) < 0) { |
1314 | default_var.accel_flags &= ~FB_ACCELF_TEXT; | 1528 | printk(KERN_ERR "tridentfb: could not register framebuffer\n"); |
1315 | default_var.activate |= FB_ACTIVATE_NOW; | 1529 | fb_dealloc_cmap(&info->cmap); |
1316 | fb_info.var = default_var; | ||
1317 | fb_info.device = &dev->dev; | ||
1318 | if (register_framebuffer(&fb_info) < 0) { | ||
1319 | printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n"); | ||
1320 | fb_dealloc_cmap(&fb_info.cmap); | ||
1321 | err = -EINVAL; | 1530 | err = -EINVAL; |
1322 | goto out_unmap2; | 1531 | goto out_unmap2; |
1323 | } | 1532 | } |
1324 | output("fb%d: %s frame buffer device %dx%d-%dbpp\n", | 1533 | output("fb%d: %s frame buffer device %dx%d-%dbpp\n", |
1325 | fb_info.node, fb_info.fix.id, default_var.xres, | 1534 | info->node, info->fix.id, info->var.xres, |
1326 | default_var.yres, default_var.bits_per_pixel); | 1535 | info->var.yres, info->var.bits_per_pixel); |
1536 | |||
1537 | pci_set_drvdata(dev, info); | ||
1327 | return 0; | 1538 | return 0; |
1328 | 1539 | ||
1329 | out_unmap2: | 1540 | out_unmap2: |
1330 | if (fb_info.screen_base) | 1541 | kfree(info->pixmap.addr); |
1331 | iounmap(fb_info.screen_base); | 1542 | if (info->screen_base) |
1543 | iounmap(info->screen_base); | ||
1332 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); | 1544 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
1333 | disable_mmio(); | 1545 | disable_mmio(info->par); |
1334 | out_unmap1: | 1546 | out_unmap1: |
1335 | if (default_par.io_virt) | 1547 | if (default_par->io_virt) |
1336 | iounmap(default_par.io_virt); | 1548 | iounmap(default_par->io_virt); |
1337 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); | 1549 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
1550 | framebuffer_release(info); | ||
1338 | return err; | 1551 | return err; |
1339 | } | 1552 | } |
1340 | 1553 | ||
1341 | static void __devexit trident_pci_remove(struct pci_dev *dev) | 1554 | static void __devexit trident_pci_remove(struct pci_dev *dev) |
1342 | { | 1555 | { |
1343 | struct tridentfb_par *par = (struct tridentfb_par*)fb_info.par; | 1556 | struct fb_info *info = pci_get_drvdata(dev); |
1344 | unregister_framebuffer(&fb_info); | 1557 | struct tridentfb_par *par = info->par; |
1558 | |||
1559 | unregister_framebuffer(info); | ||
1345 | iounmap(par->io_virt); | 1560 | iounmap(par->io_virt); |
1346 | iounmap(fb_info.screen_base); | 1561 | iounmap(info->screen_base); |
1347 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); | 1562 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
1348 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); | 1563 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
1564 | pci_set_drvdata(dev, NULL); | ||
1565 | kfree(info->pixmap.addr); | ||
1566 | framebuffer_release(info); | ||
1349 | } | 1567 | } |
1350 | 1568 | ||
1351 | /* List of boards that we are trying to support */ | 1569 | /* List of boards that we are trying to support */ |
@@ -1358,6 +1576,7 @@ static struct pci_device_id trident_devices[] = { | |||
1358 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | 1576 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1359 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | 1577 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1360 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | 1578 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1579 | {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | ||
1361 | {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | 1580 | {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1362 | {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | 1581 | {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1363 | {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | 1582 | {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
@@ -1399,9 +1618,9 @@ static int __init tridentfb_setup(char *options) | |||
1399 | if (!strncmp(opt, "noaccel", 7)) | 1618 | if (!strncmp(opt, "noaccel", 7)) |
1400 | noaccel = 1; | 1619 | noaccel = 1; |
1401 | else if (!strncmp(opt, "fp", 2)) | 1620 | else if (!strncmp(opt, "fp", 2)) |
1402 | displaytype = DISPLAY_FP; | 1621 | fp = 1; |
1403 | else if (!strncmp(opt, "crt", 3)) | 1622 | else if (!strncmp(opt, "crt", 3)) |
1404 | displaytype = DISPLAY_CRT; | 1623 | fp = 0; |
1405 | else if (!strncmp(opt, "bpp=", 4)) | 1624 | else if (!strncmp(opt, "bpp=", 4)) |
1406 | bpp = simple_strtoul(opt + 4, NULL, 0); | 1625 | bpp = simple_strtoul(opt + 4, NULL, 0); |
1407 | else if (!strncmp(opt, "center", 6)) | 1626 | else if (!strncmp(opt, "center", 6)) |
@@ -1430,7 +1649,6 @@ static int __init tridentfb_init(void) | |||
1430 | return -ENODEV; | 1649 | return -ENODEV; |
1431 | tridentfb_setup(option); | 1650 | tridentfb_setup(option); |
1432 | #endif | 1651 | #endif |
1433 | output("Trident framebuffer %s initializing\n", VERSION); | ||
1434 | return pci_register_driver(&tridentfb_pci_driver); | 1652 | return pci_register_driver(&tridentfb_pci_driver); |
1435 | } | 1653 | } |
1436 | 1654 | ||