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path: root/drivers/video/tridentfb.c
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Diffstat (limited to 'drivers/video/tridentfb.c')
-rw-r--r--drivers/video/tridentfb.c28
1 files changed, 17 insertions, 11 deletions
diff --git a/drivers/video/tridentfb.c b/drivers/video/tridentfb.c
index da8004e5d03d..698ca9232e73 100644
--- a/drivers/video/tridentfb.c
+++ b/drivers/video/tridentfb.c
@@ -454,13 +454,16 @@ static struct accel_switch accel_image = {
454static void tridentfb_fillrect(struct fb_info * info, const struct fb_fillrect *fr) 454static void tridentfb_fillrect(struct fb_info * info, const struct fb_fillrect *fr)
455{ 455{
456 int bpp = info->var.bits_per_pixel; 456 int bpp = info->var.bits_per_pixel;
457 int col; 457 int col = 0;
458 458
459 switch (bpp) { 459 switch (bpp) {
460 default: 460 default:
461 case 8: col = fr->color; 461 case 8: col |= fr->color;
462 col |= col << 8;
463 col |= col << 16;
462 break; 464 break;
463 case 16: col = ((u32 *)(info->pseudo_palette))[fr->color]; 465 case 16: col = ((u32 *)(info->pseudo_palette))[fr->color];
466
464 break; 467 break;
465 case 32: col = ((u32 *)(info->pseudo_palette))[fr->color]; 468 case 32: col = ((u32 *)(info->pseudo_palette))[fr->color];
466 break; 469 break;
@@ -882,8 +885,9 @@ static int tridentfb_set_par(struct fb_info *info)
882 885
883 write3X4(GraphEngReg, 0x80); //enable GE for text acceleration 886 write3X4(GraphEngReg, 0x80); //enable GE for text acceleration
884 887
885// if (info->var.accel_flags & FB_ACCELF_TEXT) 888#ifdef CONFIG_FB_TRIDENT_ACCEL
886//FIXME acc->init_accel(info->var.xres,bpp); 889 acc->init_accel(info->var.xres,bpp);
890#endif
887 891
888 switch (bpp) { 892 switch (bpp) {
889 case 8: tmp = 0x00; break; 893 case 8: tmp = 0x00; break;
@@ -900,7 +904,7 @@ static int tridentfb_set_par(struct fb_info *info)
900 write3X4(DRAMControl, tmp); //both IO,linear enable 904 write3X4(DRAMControl, tmp); //both IO,linear enable
901 905
902 write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40); 906 write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40);
903 write3X4(Performance,0x20); 907 write3X4(Performance,0x92);
904 write3X4(PCIReg,0x07); //MMIO & PCI read and write burst enable 908 write3X4(PCIReg,0x07); //MMIO & PCI read and write burst enable
905 909
906 /* convert from picoseconds to MHz */ 910 /* convert from picoseconds to MHz */
@@ -981,12 +985,14 @@ static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
981 t_outb(green>>10,0x3C9); 985 t_outb(green>>10,0x3C9);
982 t_outb(blue>>10,0x3C9); 986 t_outb(blue>>10,0x3C9);
983 987
984 } else 988 } else if (bpp == 16) { /* RGB 565 */
985 if (bpp == 16) /* RGB 565 */ 989 u32 col;
986 ((u32*)info->pseudo_palette)[regno] = (red & 0xF800) | 990
987 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); 991 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
988 else 992 ((blue & 0xF800) >> 11);
989 if (bpp == 32) /* ARGB 8888 */ 993 col |= col << 16;
994 ((u32 *)(info->pseudo_palette))[regno] = col;
995 } else if (bpp == 32) /* ARGB 8888 */
990 ((u32*)info->pseudo_palette)[regno] = 996 ((u32*)info->pseudo_palette)[regno] =
991 ((transp & 0xFF00) <<16) | 997 ((transp & 0xFF00) <<16) |
992 ((red & 0xFF00) << 8) | 998 ((red & 0xFF00) << 8) |