aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video/riva
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/video/riva')
-rw-r--r--drivers/video/riva/Makefile11
-rw-r--r--drivers/video/riva/fbdev.c2229
-rw-r--r--drivers/video/riva/nv4ref.h2445
-rw-r--r--drivers/video/riva/nv_driver.c425
-rw-r--r--drivers/video/riva/nv_type.h58
-rw-r--r--drivers/video/riva/nvreg.h188
-rw-r--r--drivers/video/riva/riva_hw.c2259
-rw-r--r--drivers/video/riva/riva_hw.h548
-rw-r--r--drivers/video/riva/riva_tbl.h1008
-rw-r--r--drivers/video/riva/rivafb-i2c.c214
-rw-r--r--drivers/video/riva/rivafb.h79
11 files changed, 9464 insertions, 0 deletions
diff --git a/drivers/video/riva/Makefile b/drivers/video/riva/Makefile
new file mode 100644
index 000000000000..8898c9915b02
--- /dev/null
+++ b/drivers/video/riva/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the Riva framebuffer driver
3#
4
5obj-$(CONFIG_FB_RIVA) += rivafb.o
6
7rivafb-objs := fbdev.o riva_hw.o nv_driver.o
8
9ifdef CONFIG_FB_RIVA_I2C
10 rivafb-objs += rivafb-i2c.o
11endif
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c
new file mode 100644
index 000000000000..b0c886de0404
--- /dev/null
+++ b/drivers/video/riva/fbdev.c
@@ -0,0 +1,2229 @@
1/*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
32#include <linux/config.h>
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/errno.h>
36#include <linux/string.h>
37#include <linux/mm.h>
38#include <linux/tty.h>
39#include <linux/slab.h>
40#include <linux/delay.h>
41#include <linux/fb.h>
42#include <linux/init.h>
43#include <linux/pci.h>
44#ifdef CONFIG_MTRR
45#include <asm/mtrr.h>
46#endif
47#ifdef CONFIG_PPC_OF
48#include <asm/prom.h>
49#include <asm/pci-bridge.h>
50#endif
51#ifdef CONFIG_PMAC_BACKLIGHT
52#include <asm/backlight.h>
53#endif
54
55#include "rivafb.h"
56#include "nvreg.h"
57
58#ifndef CONFIG_PCI /* sanity check */
59#error This driver requires PCI support.
60#endif
61
62/* version number of this driver */
63#define RIVAFB_VERSION "0.9.5b"
64
65/* ------------------------------------------------------------------------- *
66 *
67 * various helpful macros and constants
68 *
69 * ------------------------------------------------------------------------- */
70#ifdef CONFIG_FB_RIVA_DEBUG
71#define NVTRACE printk
72#else
73#define NVTRACE if(0) printk
74#endif
75
76#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
78
79#ifdef CONFIG_FB_RIVA_DEBUG
80#define assert(expr) \
81 if(!(expr)) { \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
84 BUG(); \
85 }
86#else
87#define assert(expr)
88#endif
89
90#define PFX "rivafb: "
91
92/* macro that allows you to set overflow bits */
93#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94#define SetBit(n) (1<<(n))
95#define Set8Bits(value) ((value)&0xff)
96
97/* HW cursor parameters */
98#define MAX_CURS 32
99
100/* ------------------------------------------------------------------------- *
101 *
102 * prototypes
103 *
104 * ------------------------------------------------------------------------- */
105
106static int rivafb_blank(int blank, struct fb_info *info);
107
108/* ------------------------------------------------------------------------- *
109 *
110 * card identification
111 *
112 * ------------------------------------------------------------------------- */
113
114static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 // NF2/IGP version, GeForce 4 MX, NV18
156 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
192 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
194 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
196 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
198 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
200 { 0, } /* terminate list */
201};
202MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
203
204/* ------------------------------------------------------------------------- *
205 *
206 * global variables
207 *
208 * ------------------------------------------------------------------------- */
209
210/* command line data, set in rivafb_setup() */
211static int flatpanel __devinitdata = -1; /* Autodetect later */
212static int forceCRTC __devinitdata = -1;
213static int noaccel __devinitdata = 0;
214#ifdef CONFIG_MTRR
215static int nomtrr __devinitdata = 0;
216#endif
217
218static char *mode_option __devinitdata = NULL;
219static int strictmode = 0;
220
221static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
222 .type = FB_TYPE_PACKED_PIXELS,
223 .xpanstep = 1,
224 .ypanstep = 1,
225};
226
227static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
228 .xres = 640,
229 .yres = 480,
230 .xres_virtual = 640,
231 .yres_virtual = 480,
232 .bits_per_pixel = 8,
233 .red = {0, 8, 0},
234 .green = {0, 8, 0},
235 .blue = {0, 8, 0},
236 .transp = {0, 0, 0},
237 .activate = FB_ACTIVATE_NOW,
238 .height = -1,
239 .width = -1,
240 .pixclock = 39721,
241 .left_margin = 40,
242 .right_margin = 24,
243 .upper_margin = 32,
244 .lower_margin = 11,
245 .hsync_len = 96,
246 .vsync_len = 2,
247 .vmode = FB_VMODE_NONINTERLACED
248};
249
250/* from GGI */
251static const struct riva_regs reg_template = {
252 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
253 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
254 0x41, 0x01, 0x0F, 0x00, 0x00},
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
256 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
258 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
260 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, /* 0x40 */
264 },
265 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
266 0xFF},
267 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
268 0xEB /* MISC */
269};
270
271/*
272 * Backlight control
273 */
274#ifdef CONFIG_PMAC_BACKLIGHT
275
276static int riva_backlight_levels[] = {
277 0x158,
278 0x192,
279 0x1c6,
280 0x200,
281 0x234,
282 0x268,
283 0x2a2,
284 0x2d6,
285 0x310,
286 0x344,
287 0x378,
288 0x3b2,
289 0x3e6,
290 0x41a,
291 0x454,
292 0x534,
293};
294
295static int riva_set_backlight_enable(int on, int level, void *data);
296static int riva_set_backlight_level(int level, void *data);
297static struct backlight_controller riva_backlight_controller = {
298 riva_set_backlight_enable,
299 riva_set_backlight_level
300};
301#endif /* CONFIG_PMAC_BACKLIGHT */
302
303/* ------------------------------------------------------------------------- *
304 *
305 * MMIO access macros
306 *
307 * ------------------------------------------------------------------------- */
308
309static inline void CRTCout(struct riva_par *par, unsigned char index,
310 unsigned char val)
311{
312 VGA_WR08(par->riva.PCIO, 0x3d4, index);
313 VGA_WR08(par->riva.PCIO, 0x3d5, val);
314}
315
316static inline unsigned char CRTCin(struct riva_par *par,
317 unsigned char index)
318{
319 VGA_WR08(par->riva.PCIO, 0x3d4, index);
320 return (VGA_RD08(par->riva.PCIO, 0x3d5));
321}
322
323static inline void GRAout(struct riva_par *par, unsigned char index,
324 unsigned char val)
325{
326 VGA_WR08(par->riva.PVIO, 0x3ce, index);
327 VGA_WR08(par->riva.PVIO, 0x3cf, val);
328}
329
330static inline unsigned char GRAin(struct riva_par *par,
331 unsigned char index)
332{
333 VGA_WR08(par->riva.PVIO, 0x3ce, index);
334 return (VGA_RD08(par->riva.PVIO, 0x3cf));
335}
336
337static inline void SEQout(struct riva_par *par, unsigned char index,
338 unsigned char val)
339{
340 VGA_WR08(par->riva.PVIO, 0x3c4, index);
341 VGA_WR08(par->riva.PVIO, 0x3c5, val);
342}
343
344static inline unsigned char SEQin(struct riva_par *par,
345 unsigned char index)
346{
347 VGA_WR08(par->riva.PVIO, 0x3c4, index);
348 return (VGA_RD08(par->riva.PVIO, 0x3c5));
349}
350
351static inline void ATTRout(struct riva_par *par, unsigned char index,
352 unsigned char val)
353{
354 VGA_WR08(par->riva.PCIO, 0x3c0, index);
355 VGA_WR08(par->riva.PCIO, 0x3c0, val);
356}
357
358static inline unsigned char ATTRin(struct riva_par *par,
359 unsigned char index)
360{
361 VGA_WR08(par->riva.PCIO, 0x3c0, index);
362 return (VGA_RD08(par->riva.PCIO, 0x3c1));
363}
364
365static inline void MISCout(struct riva_par *par, unsigned char val)
366{
367 VGA_WR08(par->riva.PVIO, 0x3c2, val);
368}
369
370static inline unsigned char MISCin(struct riva_par *par)
371{
372 return (VGA_RD08(par->riva.PVIO, 0x3cc));
373}
374
375static u8 byte_rev[256] = {
376 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
377 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
378 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
379 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
380 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
381 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
382 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
383 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
384 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
385 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
386 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
387 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
388 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
389 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
390 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
391 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
392 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
393 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
394 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
395 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
396 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
397 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
398 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
399 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
400 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
401 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
402 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
403 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
404 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
405 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
406 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
407 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
408};
409
410static inline void reverse_order(u32 *l)
411{
412 u8 *a = (u8 *)l;
413 *a = byte_rev[*a], a++;
414 *a = byte_rev[*a], a++;
415 *a = byte_rev[*a], a++;
416 *a = byte_rev[*a];
417}
418
419/* ------------------------------------------------------------------------- *
420 *
421 * cursor stuff
422 *
423 * ------------------------------------------------------------------------- */
424
425/**
426 * rivafb_load_cursor_image - load cursor image to hardware
427 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
428 * @par: pointer to private data
429 * @w: width of cursor image in pixels
430 * @h: height of cursor image in scanlines
431 * @bg: background color (ARGB1555) - alpha bit determines opacity
432 * @fg: foreground color (ARGB1555)
433 *
434 * DESCRIPTiON:
435 * Loads cursor image based on a monochrome source and mask bitmap. The
436 * image bits determines the color of the pixel, 0 for background, 1 for
437 * foreground. Only the affected region (as determined by @w and @h
438 * parameters) will be updated.
439 *
440 * CALLED FROM:
441 * rivafb_cursor()
442 */
443static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
444 u16 bg, u16 fg, u32 w, u32 h)
445{
446 int i, j, k = 0;
447 u32 b, tmp;
448 u32 *data = (u32 *)data8;
449 bg = le16_to_cpu(bg);
450 fg = le16_to_cpu(fg);
451
452 w = (w + 1) & ~1;
453
454 for (i = 0; i < h; i++) {
455 b = *data++;
456 reverse_order(&b);
457
458 for (j = 0; j < w/2; j++) {
459 tmp = 0;
460#if defined (__BIG_ENDIAN)
461 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
462 b <<= 1;
463 tmp |= (b & (1 << 31)) ? fg : bg;
464 b <<= 1;
465#else
466 tmp = (b & 1) ? fg : bg;
467 b >>= 1;
468 tmp |= (b & 1) ? fg << 16 : bg << 16;
469 b >>= 1;
470#endif
471 writel(tmp, &par->riva.CURSOR[k++]);
472 }
473 k += (MAX_CURS - w)/2;
474 }
475}
476
477/* ------------------------------------------------------------------------- *
478 *
479 * general utility functions
480 *
481 * ------------------------------------------------------------------------- */
482
483/**
484 * riva_wclut - set CLUT entry
485 * @chip: pointer to RIVA_HW_INST object
486 * @regnum: register number
487 * @red: red component
488 * @green: green component
489 * @blue: blue component
490 *
491 * DESCRIPTION:
492 * Sets color register @regnum.
493 *
494 * CALLED FROM:
495 * rivafb_setcolreg()
496 */
497static void riva_wclut(RIVA_HW_INST *chip,
498 unsigned char regnum, unsigned char red,
499 unsigned char green, unsigned char blue)
500{
501 VGA_WR08(chip->PDIO, 0x3c8, regnum);
502 VGA_WR08(chip->PDIO, 0x3c9, red);
503 VGA_WR08(chip->PDIO, 0x3c9, green);
504 VGA_WR08(chip->PDIO, 0x3c9, blue);
505}
506
507/**
508 * riva_rclut - read fromCLUT register
509 * @chip: pointer to RIVA_HW_INST object
510 * @regnum: register number
511 * @red: red component
512 * @green: green component
513 * @blue: blue component
514 *
515 * DESCRIPTION:
516 * Reads red, green, and blue from color register @regnum.
517 *
518 * CALLED FROM:
519 * rivafb_setcolreg()
520 */
521static void riva_rclut(RIVA_HW_INST *chip,
522 unsigned char regnum, unsigned char *red,
523 unsigned char *green, unsigned char *blue)
524{
525
526 VGA_WR08(chip->PDIO, 0x3c7, regnum);
527 *red = VGA_RD08(chip->PDIO, 0x3c9);
528 *green = VGA_RD08(chip->PDIO, 0x3c9);
529 *blue = VGA_RD08(chip->PDIO, 0x3c9);
530}
531
532/**
533 * riva_save_state - saves current chip state
534 * @par: pointer to riva_par object containing info for current riva board
535 * @regs: pointer to riva_regs object
536 *
537 * DESCRIPTION:
538 * Saves current chip state to @regs.
539 *
540 * CALLED FROM:
541 * rivafb_probe()
542 */
543/* from GGI */
544static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
545{
546 int i;
547
548 NVTRACE_ENTER();
549 par->riva.LockUnlock(&par->riva, 0);
550
551 par->riva.UnloadStateExt(&par->riva, &regs->ext);
552
553 regs->misc_output = MISCin(par);
554
555 for (i = 0; i < NUM_CRT_REGS; i++)
556 regs->crtc[i] = CRTCin(par, i);
557
558 for (i = 0; i < NUM_ATC_REGS; i++)
559 regs->attr[i] = ATTRin(par, i);
560
561 for (i = 0; i < NUM_GRC_REGS; i++)
562 regs->gra[i] = GRAin(par, i);
563
564 for (i = 0; i < NUM_SEQ_REGS; i++)
565 regs->seq[i] = SEQin(par, i);
566 NVTRACE_LEAVE();
567}
568
569/**
570 * riva_load_state - loads current chip state
571 * @par: pointer to riva_par object containing info for current riva board
572 * @regs: pointer to riva_regs object
573 *
574 * DESCRIPTION:
575 * Loads chip state from @regs.
576 *
577 * CALLED FROM:
578 * riva_load_video_mode()
579 * rivafb_probe()
580 * rivafb_remove()
581 */
582/* from GGI */
583static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
584{
585 RIVA_HW_STATE *state = &regs->ext;
586 int i;
587
588 NVTRACE_ENTER();
589 CRTCout(par, 0x11, 0x00);
590
591 par->riva.LockUnlock(&par->riva, 0);
592
593 par->riva.LoadStateExt(&par->riva, state);
594
595 MISCout(par, regs->misc_output);
596
597 for (i = 0; i < NUM_CRT_REGS; i++) {
598 switch (i) {
599 case 0x19:
600 case 0x20 ... 0x40:
601 break;
602 default:
603 CRTCout(par, i, regs->crtc[i]);
604 }
605 }
606
607 for (i = 0; i < NUM_ATC_REGS; i++)
608 ATTRout(par, i, regs->attr[i]);
609
610 for (i = 0; i < NUM_GRC_REGS; i++)
611 GRAout(par, i, regs->gra[i]);
612
613 for (i = 0; i < NUM_SEQ_REGS; i++)
614 SEQout(par, i, regs->seq[i]);
615 NVTRACE_LEAVE();
616}
617
618/**
619 * riva_load_video_mode - calculate timings
620 * @info: pointer to fb_info object containing info for current riva board
621 *
622 * DESCRIPTION:
623 * Calculate some timings and then send em off to riva_load_state().
624 *
625 * CALLED FROM:
626 * rivafb_set_par()
627 */
628static void riva_load_video_mode(struct fb_info *info)
629{
630 int bpp, width, hDisplaySize, hDisplay, hStart,
631 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
632 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
633 struct riva_par *par = (struct riva_par *) info->par;
634 struct riva_regs newmode;
635
636 NVTRACE_ENTER();
637 /* time to calculate */
638 rivafb_blank(1, info);
639
640 bpp = info->var.bits_per_pixel;
641 if (bpp == 16 && info->var.green.length == 5)
642 bpp = 15;
643 width = info->var.xres_virtual;
644 hDisplaySize = info->var.xres;
645 hDisplay = (hDisplaySize / 8) - 1;
646 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
647 hEnd = (hDisplaySize + info->var.right_margin +
648 info->var.hsync_len) / 8 - 1;
649 hTotal = (hDisplaySize + info->var.right_margin +
650 info->var.hsync_len + info->var.left_margin) / 8 - 5;
651 hBlankStart = hDisplay;
652 hBlankEnd = hTotal + 4;
653
654 height = info->var.yres_virtual;
655 vDisplay = info->var.yres - 1;
656 vStart = info->var.yres + info->var.lower_margin - 1;
657 vEnd = info->var.yres + info->var.lower_margin +
658 info->var.vsync_len - 1;
659 vTotal = info->var.yres + info->var.lower_margin +
660 info->var.vsync_len + info->var.upper_margin + 2;
661 vBlankStart = vDisplay;
662 vBlankEnd = vTotal + 1;
663 dotClock = 1000000000 / info->var.pixclock;
664
665 memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
666
667 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
668 vTotal |= 1;
669
670 if (par->FlatPanel) {
671 vStart = vTotal - 3;
672 vEnd = vTotal - 2;
673 vBlankStart = vStart;
674 hStart = hTotal - 3;
675 hEnd = hTotal - 2;
676 hBlankEnd = hTotal + 4;
677 }
678
679 newmode.crtc[0x0] = Set8Bits (hTotal);
680 newmode.crtc[0x1] = Set8Bits (hDisplay);
681 newmode.crtc[0x2] = Set8Bits (hBlankStart);
682 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
683 newmode.crtc[0x4] = Set8Bits (hStart);
684 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
685 | SetBitField (hEnd, 4: 0, 4:0);
686 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
687 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
688 | SetBitField (vDisplay, 8: 8, 1:1)
689 | SetBitField (vStart, 8: 8, 2:2)
690 | SetBitField (vBlankStart, 8: 8, 3:3)
691 | SetBit (4)
692 | SetBitField (vTotal, 9: 9, 5:5)
693 | SetBitField (vDisplay, 9: 9, 6:6)
694 | SetBitField (vStart, 9: 9, 7:7);
695 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
696 | SetBit (6);
697 newmode.crtc[0x10] = Set8Bits (vStart);
698 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
699 | SetBit (5);
700 newmode.crtc[0x12] = Set8Bits (vDisplay);
701 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
702 newmode.crtc[0x15] = Set8Bits (vBlankStart);
703 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
704
705 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
706 | SetBitField(vBlankStart,10:10,3:3)
707 | SetBitField(vStart,10:10,2:2)
708 | SetBitField(vDisplay,10:10,1:1)
709 | SetBitField(vTotal,10:10,0:0);
710 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
711 | SetBitField(hDisplay,8:8,1:1)
712 | SetBitField(hBlankStart,8:8,2:2)
713 | SetBitField(hStart,8:8,3:3);
714 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
715 | SetBitField(vDisplay,11:11,2:2)
716 | SetBitField(vStart,11:11,4:4)
717 | SetBitField(vBlankStart,11:11,6:6);
718
719 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
720 int tmp = (hTotal >> 1) & ~1;
721 newmode.ext.interlace = Set8Bits(tmp);
722 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
723 } else
724 newmode.ext.interlace = 0xff; /* interlace off */
725
726 if (par->riva.Architecture >= NV_ARCH_10)
727 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
728
729 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
730 newmode.misc_output &= ~0x40;
731 else
732 newmode.misc_output |= 0x40;
733 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
734 newmode.misc_output &= ~0x80;
735 else
736 newmode.misc_output |= 0x80;
737
738 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
739 hDisplaySize, height, dotClock);
740
741 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
742 0xfff000ff;
743 if (par->FlatPanel == 1) {
744 newmode.ext.pixel |= (1 << 7);
745 newmode.ext.scale |= (1 << 8);
746 }
747 if (par->SecondCRTC) {
748 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
749 ~0x00001000;
750 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
751 0x00001000;
752 newmode.ext.crtcOwner = 3;
753 newmode.ext.pllsel |= 0x20000800;
754 newmode.ext.vpll2 = newmode.ext.vpll;
755 } else if (par->riva.twoHeads) {
756 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
757 0x00001000;
758 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
759 ~0x00001000;
760 newmode.ext.crtcOwner = 0;
761 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
762 }
763 if (par->FlatPanel == 1) {
764 newmode.ext.pixel |= (1 << 7);
765 newmode.ext.scale |= (1 << 8);
766 }
767 newmode.ext.cursorConfig = 0x02000100;
768 par->current_state = newmode;
769 riva_load_state(par, &par->current_state);
770 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
771 rivafb_blank(0, info);
772 NVTRACE_LEAVE();
773}
774
775static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
776{
777 NVTRACE_ENTER();
778 var->xres = var->xres_virtual = modedb->xres;
779 var->yres = modedb->yres;
780 if (var->yres_virtual < var->yres)
781 var->yres_virtual = var->yres;
782 var->xoffset = var->yoffset = 0;
783 var->pixclock = modedb->pixclock;
784 var->left_margin = modedb->left_margin;
785 var->right_margin = modedb->right_margin;
786 var->upper_margin = modedb->upper_margin;
787 var->lower_margin = modedb->lower_margin;
788 var->hsync_len = modedb->hsync_len;
789 var->vsync_len = modedb->vsync_len;
790 var->sync = modedb->sync;
791 var->vmode = modedb->vmode;
792 NVTRACE_LEAVE();
793}
794
795/**
796 * rivafb_do_maximize -
797 * @info: pointer to fb_info object containing info for current riva board
798 * @var:
799 * @nom:
800 * @den:
801 *
802 * DESCRIPTION:
803 * .
804 *
805 * RETURNS:
806 * -EINVAL on failure, 0 on success
807 *
808 *
809 * CALLED FROM:
810 * rivafb_check_var()
811 */
812static int rivafb_do_maximize(struct fb_info *info,
813 struct fb_var_screeninfo *var,
814 int nom, int den)
815{
816 static struct {
817 int xres, yres;
818 } modes[] = {
819 {1600, 1280},
820 {1280, 1024},
821 {1024, 768},
822 {800, 600},
823 {640, 480},
824 {-1, -1}
825 };
826 int i;
827
828 NVTRACE_ENTER();
829 /* use highest possible virtual resolution */
830 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
831 printk(KERN_WARNING PFX
832 "using maximum available virtual resolution\n");
833 for (i = 0; modes[i].xres != -1; i++) {
834 if (modes[i].xres * nom / den * modes[i].yres <
835 info->fix.smem_len)
836 break;
837 }
838 if (modes[i].xres == -1) {
839 printk(KERN_ERR PFX
840 "could not find a virtual resolution that fits into video memory!!\n");
841 NVTRACE("EXIT - EINVAL error\n");
842 return -EINVAL;
843 }
844 var->xres_virtual = modes[i].xres;
845 var->yres_virtual = modes[i].yres;
846
847 printk(KERN_INFO PFX
848 "virtual resolution set to maximum of %dx%d\n",
849 var->xres_virtual, var->yres_virtual);
850 } else if (var->xres_virtual == -1) {
851 var->xres_virtual = (info->fix.smem_len * den /
852 (nom * var->yres_virtual)) & ~15;
853 printk(KERN_WARNING PFX
854 "setting virtual X resolution to %d\n", var->xres_virtual);
855 } else if (var->yres_virtual == -1) {
856 var->xres_virtual = (var->xres_virtual + 15) & ~15;
857 var->yres_virtual = info->fix.smem_len * den /
858 (nom * var->xres_virtual);
859 printk(KERN_WARNING PFX
860 "setting virtual Y resolution to %d\n", var->yres_virtual);
861 } else {
862 var->xres_virtual = (var->xres_virtual + 15) & ~15;
863 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
864 printk(KERN_ERR PFX
865 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
866 var->xres, var->yres, var->bits_per_pixel);
867 NVTRACE("EXIT - EINVAL error\n");
868 return -EINVAL;
869 }
870 }
871
872 if (var->xres_virtual * nom / den >= 8192) {
873 printk(KERN_WARNING PFX
874 "virtual X resolution (%d) is too high, lowering to %d\n",
875 var->xres_virtual, 8192 * den / nom - 16);
876 var->xres_virtual = 8192 * den / nom - 16;
877 }
878
879 if (var->xres_virtual < var->xres) {
880 printk(KERN_ERR PFX
881 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
882 return -EINVAL;
883 }
884
885 if (var->yres_virtual < var->yres) {
886 printk(KERN_ERR PFX
887 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
888 return -EINVAL;
889 }
890 if (var->yres_virtual > 0x7fff/nom)
891 var->yres_virtual = 0x7fff/nom;
892 if (var->xres_virtual > 0x7fff/nom)
893 var->xres_virtual = 0x7fff/nom;
894 NVTRACE_LEAVE();
895 return 0;
896}
897
898static void
899riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
900{
901 RIVA_FIFO_FREE(par->riva, Patt, 4);
902 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
903 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
904 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
905 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
906}
907
908/* acceleration routines */
909static inline void wait_for_idle(struct riva_par *par)
910{
911 while (par->riva.Busy(&par->riva));
912}
913
914/*
915 * Set ROP. Translate X rop into ROP3. Internal routine.
916 */
917static void
918riva_set_rop_solid(struct riva_par *par, int rop)
919{
920 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
921 RIVA_FIFO_FREE(par->riva, Rop, 1);
922 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
923
924}
925
926static void riva_setup_accel(struct fb_info *info)
927{
928 struct riva_par *par = (struct riva_par *) info->par;
929
930 RIVA_FIFO_FREE(par->riva, Clip, 2);
931 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
932 NV_WR32(&par->riva.Clip->WidthHeight, 0,
933 (info->var.xres_virtual & 0xffff) |
934 (info->var.yres_virtual << 16));
935 riva_set_rop_solid(par, 0xcc);
936 wait_for_idle(par);
937}
938
939/**
940 * riva_get_cmap_len - query current color map length
941 * @var: standard kernel fb changeable data
942 *
943 * DESCRIPTION:
944 * Get current color map length.
945 *
946 * RETURNS:
947 * Length of color map
948 *
949 * CALLED FROM:
950 * rivafb_setcolreg()
951 */
952static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
953{
954 int rc = 256; /* reasonable default */
955
956 switch (var->green.length) {
957 case 8:
958 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
959 break;
960 case 5:
961 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
962 break;
963 case 6:
964 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
965 break;
966 default:
967 /* should not occur */
968 break;
969 }
970 return rc;
971}
972
973/* ------------------------------------------------------------------------- *
974 *
975 * Backlight operations
976 *
977 * ------------------------------------------------------------------------- */
978
979#ifdef CONFIG_PMAC_BACKLIGHT
980static int riva_set_backlight_enable(int on, int level, void *data)
981{
982 struct riva_par *par = (struct riva_par *)data;
983 U032 tmp_pcrt, tmp_pmc;
984
985 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
986 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
987 if(on && (level > BACKLIGHT_OFF)) {
988 tmp_pcrt |= 0x1;
989 tmp_pmc |= (1 << 31); // backlight bit
990 tmp_pmc |= riva_backlight_levels[level-1] << 16; // level
991 }
992 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
993 par->riva.PMC[0x10F0/4] = tmp_pmc;
994 return 0;
995}
996
997static int riva_set_backlight_level(int level, void *data)
998{
999 return riva_set_backlight_enable(1, level, data);
1000}
1001#endif /* CONFIG_PMAC_BACKLIGHT */
1002
1003/* ------------------------------------------------------------------------- *
1004 *
1005 * framebuffer operations
1006 *
1007 * ------------------------------------------------------------------------- */
1008
1009static int rivafb_open(struct fb_info *info, int user)
1010{
1011 struct riva_par *par = (struct riva_par *) info->par;
1012 int cnt = atomic_read(&par->ref_count);
1013
1014 NVTRACE_ENTER();
1015 if (!cnt) {
1016#ifdef CONFIG_X86
1017 memset(&par->state, 0, sizeof(struct vgastate));
1018 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1019 /* save the DAC for Riva128 */
1020 if (par->riva.Architecture == NV_ARCH_03)
1021 par->state.flags |= VGA_SAVE_CMAP;
1022 save_vga(&par->state);
1023#endif
1024 /* vgaHWunlock() + riva unlock (0x7F) */
1025 CRTCout(par, 0x11, 0xFF);
1026 par->riva.LockUnlock(&par->riva, 0);
1027
1028 riva_save_state(par, &par->initial_state);
1029 }
1030 atomic_inc(&par->ref_count);
1031 NVTRACE_LEAVE();
1032 return 0;
1033}
1034
1035static int rivafb_release(struct fb_info *info, int user)
1036{
1037 struct riva_par *par = (struct riva_par *) info->par;
1038 int cnt = atomic_read(&par->ref_count);
1039
1040 NVTRACE_ENTER();
1041 if (!cnt)
1042 return -EINVAL;
1043 if (cnt == 1) {
1044 par->riva.LockUnlock(&par->riva, 0);
1045 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1046 riva_load_state(par, &par->initial_state);
1047#ifdef CONFIG_X86
1048 restore_vga(&par->state);
1049#endif
1050 par->riva.LockUnlock(&par->riva, 1);
1051 }
1052 atomic_dec(&par->ref_count);
1053 NVTRACE_LEAVE();
1054 return 0;
1055}
1056
1057static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1058{
1059 struct fb_videomode *mode;
1060 struct riva_par *par = (struct riva_par *) info->par;
1061 int nom, den; /* translating from pixels->bytes */
1062 int mode_valid = 0;
1063
1064 NVTRACE_ENTER();
1065 switch (var->bits_per_pixel) {
1066 case 1 ... 8:
1067 var->red.offset = var->green.offset = var->blue.offset = 0;
1068 var->red.length = var->green.length = var->blue.length = 8;
1069 var->bits_per_pixel = 8;
1070 nom = den = 1;
1071 break;
1072 case 9 ... 15:
1073 var->green.length = 5;
1074 /* fall through */
1075 case 16:
1076 var->bits_per_pixel = 16;
1077 /* The Riva128 supports RGB555 only */
1078 if (par->riva.Architecture == NV_ARCH_03)
1079 var->green.length = 5;
1080 if (var->green.length == 5) {
1081 /* 0rrrrrgg gggbbbbb */
1082 var->red.offset = 10;
1083 var->green.offset = 5;
1084 var->blue.offset = 0;
1085 var->red.length = 5;
1086 var->green.length = 5;
1087 var->blue.length = 5;
1088 } else {
1089 /* rrrrrggg gggbbbbb */
1090 var->red.offset = 11;
1091 var->green.offset = 5;
1092 var->blue.offset = 0;
1093 var->red.length = 5;
1094 var->green.length = 6;
1095 var->blue.length = 5;
1096 }
1097 nom = 2;
1098 den = 1;
1099 break;
1100 case 17 ... 32:
1101 var->red.length = var->green.length = var->blue.length = 8;
1102 var->bits_per_pixel = 32;
1103 var->red.offset = 16;
1104 var->green.offset = 8;
1105 var->blue.offset = 0;
1106 nom = 4;
1107 den = 1;
1108 break;
1109 default:
1110 printk(KERN_ERR PFX
1111 "mode %dx%dx%d rejected...color depth not supported.\n",
1112 var->xres, var->yres, var->bits_per_pixel);
1113 NVTRACE("EXIT, returning -EINVAL\n");
1114 return -EINVAL;
1115 }
1116
1117 if (!strictmode) {
1118 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1119 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1120 mode_valid = 1;
1121 }
1122
1123 /* calculate modeline if supported by monitor */
1124 if (!mode_valid && info->monspecs.gtf) {
1125 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1126 mode_valid = 1;
1127 }
1128
1129 if (!mode_valid) {
1130 mode = fb_find_best_mode(var, &info->modelist);
1131 if (mode) {
1132 riva_update_var(var, mode);
1133 mode_valid = 1;
1134 }
1135 }
1136
1137 if (!mode_valid && info->monspecs.modedb_len)
1138 return -EINVAL;
1139
1140 if (var->xres_virtual < var->xres)
1141 var->xres_virtual = var->xres;
1142 if (var->yres_virtual <= var->yres)
1143 var->yres_virtual = -1;
1144 if (rivafb_do_maximize(info, var, nom, den) < 0)
1145 return -EINVAL;
1146
1147 if (var->xoffset < 0)
1148 var->xoffset = 0;
1149 if (var->yoffset < 0)
1150 var->yoffset = 0;
1151
1152 /* truncate xoffset and yoffset to maximum if too high */
1153 if (var->xoffset > var->xres_virtual - var->xres)
1154 var->xoffset = var->xres_virtual - var->xres - 1;
1155
1156 if (var->yoffset > var->yres_virtual - var->yres)
1157 var->yoffset = var->yres_virtual - var->yres - 1;
1158
1159 var->red.msb_right =
1160 var->green.msb_right =
1161 var->blue.msb_right =
1162 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1163 NVTRACE_LEAVE();
1164 return 0;
1165}
1166
1167static int rivafb_set_par(struct fb_info *info)
1168{
1169 struct riva_par *par = (struct riva_par *) info->par;
1170
1171 NVTRACE_ENTER();
1172 /* vgaHWunlock() + riva unlock (0x7F) */
1173 CRTCout(par, 0x11, 0xFF);
1174 par->riva.LockUnlock(&par->riva, 0);
1175 riva_load_video_mode(info);
1176 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1177 riva_setup_accel(info);
1178
1179 par->cursor_reset = 1;
1180 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1181 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1182 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1183
1184 if (info->flags & FBINFO_HWACCEL_DISABLED)
1185 info->pixmap.scan_align = 1;
1186 else
1187 info->pixmap.scan_align = 4;
1188 NVTRACE_LEAVE();
1189 return 0;
1190}
1191
1192/**
1193 * rivafb_pan_display
1194 * @var: standard kernel fb changeable data
1195 * @con: TODO
1196 * @info: pointer to fb_info object containing info for current riva board
1197 *
1198 * DESCRIPTION:
1199 * Pan (or wrap, depending on the `vmode' field) the display using the
1200 * `xoffset' and `yoffset' fields of the `var' structure.
1201 * If the values don't fit, return -EINVAL.
1202 *
1203 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1204 */
1205static int rivafb_pan_display(struct fb_var_screeninfo *var,
1206 struct fb_info *info)
1207{
1208 struct riva_par *par = (struct riva_par *)info->par;
1209 unsigned int base;
1210
1211 NVTRACE_ENTER();
1212 if (var->xoffset > (var->xres_virtual - var->xres))
1213 return -EINVAL;
1214 if (var->yoffset > (var->yres_virtual - var->yres))
1215 return -EINVAL;
1216
1217 if (var->vmode & FB_VMODE_YWRAP) {
1218 if (var->yoffset < 0
1219 || var->yoffset >= info->var.yres_virtual
1220 || var->xoffset) return -EINVAL;
1221 } else {
1222 if (var->xoffset + info->var.xres > info->var.xres_virtual ||
1223 var->yoffset + info->var.yres > info->var.yres_virtual)
1224 return -EINVAL;
1225 }
1226
1227 base = var->yoffset * info->fix.line_length + var->xoffset;
1228
1229 par->riva.SetStartAddress(&par->riva, base);
1230
1231 info->var.xoffset = var->xoffset;
1232 info->var.yoffset = var->yoffset;
1233
1234 if (var->vmode & FB_VMODE_YWRAP)
1235 info->var.vmode |= FB_VMODE_YWRAP;
1236 else
1237 info->var.vmode &= ~FB_VMODE_YWRAP;
1238 NVTRACE_LEAVE();
1239 return 0;
1240}
1241
1242static int rivafb_blank(int blank, struct fb_info *info)
1243{
1244 struct riva_par *par= (struct riva_par *)info->par;
1245 unsigned char tmp, vesa;
1246
1247 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1248 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1249
1250 NVTRACE_ENTER();
1251
1252 if (blank)
1253 tmp |= 0x20;
1254
1255 switch (blank) {
1256 case FB_BLANK_UNBLANK:
1257 case FB_BLANK_NORMAL:
1258 break;
1259 case FB_BLANK_VSYNC_SUSPEND:
1260 vesa |= 0x80;
1261 break;
1262 case FB_BLANK_HSYNC_SUSPEND:
1263 vesa |= 0x40;
1264 break;
1265 case FB_BLANK_POWERDOWN:
1266 vesa |= 0xc0;
1267 break;
1268 }
1269
1270 SEQout(par, 0x01, tmp);
1271 CRTCout(par, 0x1a, vesa);
1272
1273#ifdef CONFIG_PMAC_BACKLIGHT
1274 if ( par->FlatPanel && _machine == _MACH_Pmac) {
1275 set_backlight_enable(!blank);
1276 }
1277#endif
1278
1279 NVTRACE_LEAVE();
1280
1281 return 0;
1282}
1283
1284/**
1285 * rivafb_setcolreg
1286 * @regno: register index
1287 * @red: red component
1288 * @green: green component
1289 * @blue: blue component
1290 * @transp: transparency
1291 * @info: pointer to fb_info object containing info for current riva board
1292 *
1293 * DESCRIPTION:
1294 * Set a single color register. The values supplied have a 16 bit
1295 * magnitude.
1296 *
1297 * RETURNS:
1298 * Return != 0 for invalid regno.
1299 *
1300 * CALLED FROM:
1301 * fbcmap.c:fb_set_cmap()
1302 */
1303static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1304 unsigned blue, unsigned transp,
1305 struct fb_info *info)
1306{
1307 struct riva_par *par = (struct riva_par *)info->par;
1308 RIVA_HW_INST *chip = &par->riva;
1309 int i;
1310
1311 if (regno >= riva_get_cmap_len(&info->var))
1312 return -EINVAL;
1313
1314 if (info->var.grayscale) {
1315 /* gray = 0.30*R + 0.59*G + 0.11*B */
1316 red = green = blue =
1317 (red * 77 + green * 151 + blue * 28) >> 8;
1318 }
1319
1320 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1321 ((u32 *) info->pseudo_palette)[regno] =
1322 (regno << info->var.red.offset) |
1323 (regno << info->var.green.offset) |
1324 (regno << info->var.blue.offset);
1325 /*
1326 * The Riva128 2D engine requires color information in
1327 * TrueColor format even if framebuffer is in DirectColor
1328 */
1329 if (par->riva.Architecture == NV_ARCH_03) {
1330 switch (info->var.bits_per_pixel) {
1331 case 16:
1332 par->palette[regno] = ((red & 0xf800) >> 1) |
1333 ((green & 0xf800) >> 6) |
1334 ((blue & 0xf800) >> 11);
1335 break;
1336 case 32:
1337 par->palette[regno] = ((red & 0xff00) << 8) |
1338 ((green & 0xff00)) |
1339 ((blue & 0xff00) >> 8);
1340 break;
1341 }
1342 }
1343 }
1344
1345 switch (info->var.bits_per_pixel) {
1346 case 8:
1347 /* "transparent" stuff is completely ignored. */
1348 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1349 break;
1350 case 16:
1351 if (info->var.green.length == 5) {
1352 for (i = 0; i < 8; i++) {
1353 riva_wclut(chip, regno*8+i, red >> 8,
1354 green >> 8, blue >> 8);
1355 }
1356 } else {
1357 u8 r, g, b;
1358
1359 if (regno < 32) {
1360 for (i = 0; i < 8; i++) {
1361 riva_wclut(chip, regno*8+i,
1362 red >> 8, green >> 8,
1363 blue >> 8);
1364 }
1365 }
1366 riva_rclut(chip, regno*4, &r, &g, &b);
1367 for (i = 0; i < 4; i++)
1368 riva_wclut(chip, regno*4+i, r,
1369 green >> 8, b);
1370 }
1371 break;
1372 case 32:
1373 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1374 break;
1375 default:
1376 /* do nothing */
1377 break;
1378 }
1379 return 0;
1380}
1381
1382/**
1383 * rivafb_fillrect - hardware accelerated color fill function
1384 * @info: pointer to fb_info structure
1385 * @rect: pointer to fb_fillrect structure
1386 *
1387 * DESCRIPTION:
1388 * This function fills up a region of framebuffer memory with a solid
1389 * color with a choice of two different ROP's, copy or invert.
1390 *
1391 * CALLED FROM:
1392 * framebuffer hook
1393 */
1394static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1395{
1396 struct riva_par *par = (struct riva_par *) info->par;
1397 u_int color, rop = 0;
1398
1399 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1400 cfb_fillrect(info, rect);
1401 return;
1402 }
1403
1404 if (info->var.bits_per_pixel == 8)
1405 color = rect->color;
1406 else {
1407 if (par->riva.Architecture != NV_ARCH_03)
1408 color = ((u32 *)info->pseudo_palette)[rect->color];
1409 else
1410 color = par->palette[rect->color];
1411 }
1412
1413 switch (rect->rop) {
1414 case ROP_XOR:
1415 rop = 0x66;
1416 break;
1417 case ROP_COPY:
1418 default:
1419 rop = 0xCC;
1420 break;
1421 }
1422
1423 riva_set_rop_solid(par, rop);
1424
1425 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1426 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1427
1428 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1429 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1430 (rect->dx << 16) | rect->dy);
1431 mb();
1432 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1433 (rect->width << 16) | rect->height);
1434 mb();
1435 riva_set_rop_solid(par, 0xcc);
1436
1437}
1438
1439/**
1440 * rivafb_copyarea - hardware accelerated blit function
1441 * @info: pointer to fb_info structure
1442 * @region: pointer to fb_copyarea structure
1443 *
1444 * DESCRIPTION:
1445 * This copies an area of pixels from one location to another
1446 *
1447 * CALLED FROM:
1448 * framebuffer hook
1449 */
1450static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1451{
1452 struct riva_par *par = (struct riva_par *) info->par;
1453
1454 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1455 cfb_copyarea(info, region);
1456 return;
1457 }
1458
1459 RIVA_FIFO_FREE(par->riva, Blt, 3);
1460 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1461 (region->sy << 16) | region->sx);
1462 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1463 (region->dy << 16) | region->dx);
1464 mb();
1465 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1466 (region->height << 16) | region->width);
1467 mb();
1468}
1469
1470static inline void convert_bgcolor_16(u32 *col)
1471{
1472 *col = ((*col & 0x0000F800) << 8)
1473 | ((*col & 0x00007E0) << 5)
1474 | ((*col & 0x0000001F) << 3)
1475 | 0xFF000000;
1476 mb();
1477}
1478
1479/**
1480 * rivafb_imageblit: hardware accelerated color expand function
1481 * @info: pointer to fb_info structure
1482 * @image: pointer to fb_image structure
1483 *
1484 * DESCRIPTION:
1485 * If the source is a monochrome bitmap, the function fills up a a region
1486 * of framebuffer memory with pixels whose color is determined by the bit
1487 * setting of the bitmap, 1 - foreground, 0 - background.
1488 *
1489 * If the source is not a monochrome bitmap, color expansion is not done.
1490 * In this case, it is channeled to a software function.
1491 *
1492 * CALLED FROM:
1493 * framebuffer hook
1494 */
1495static void rivafb_imageblit(struct fb_info *info,
1496 const struct fb_image *image)
1497{
1498 struct riva_par *par = (struct riva_par *) info->par;
1499 u32 fgx = 0, bgx = 0, width, tmp;
1500 u8 *cdat = (u8 *) image->data;
1501 volatile u32 __iomem *d;
1502 int i, size;
1503
1504 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1505 cfb_imageblit(info, image);
1506 return;
1507 }
1508
1509 switch (info->var.bits_per_pixel) {
1510 case 8:
1511 fgx = image->fg_color;
1512 bgx = image->bg_color;
1513 break;
1514 case 16:
1515 case 32:
1516 if (par->riva.Architecture != NV_ARCH_03) {
1517 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1518 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1519 } else {
1520 fgx = par->palette[image->fg_color];
1521 bgx = par->palette[image->bg_color];
1522 }
1523 if (info->var.green.length == 6)
1524 convert_bgcolor_16(&bgx);
1525 break;
1526 }
1527
1528 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1529 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1530 (image->dy << 16) | (image->dx & 0xFFFF));
1531 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1532 (((image->dy + image->height) << 16) |
1533 ((image->dx + image->width) & 0xffff)));
1534 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1535 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1536 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1537 (image->height << 16) | ((image->width + 31) & ~31));
1538 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1539 (image->height << 16) | ((image->width + 31) & ~31));
1540 NV_WR32(&par->riva.Bitmap->PointE, 0,
1541 (image->dy << 16) | (image->dx & 0xFFFF));
1542
1543 d = &par->riva.Bitmap->MonochromeData01E;
1544
1545 width = (image->width + 31)/32;
1546 size = width * image->height;
1547 while (size >= 16) {
1548 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1549 for (i = 0; i < 16; i++) {
1550 tmp = *((u32 *)cdat);
1551 cdat = (u8 *)((u32 *)cdat + 1);
1552 reverse_order(&tmp);
1553 NV_WR32(d, i*4, tmp);
1554 }
1555 size -= 16;
1556 }
1557 if (size) {
1558 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1559 for (i = 0; i < size; i++) {
1560 tmp = *((u32 *) cdat);
1561 cdat = (u8 *)((u32 *)cdat + 1);
1562 reverse_order(&tmp);
1563 NV_WR32(d, i*4, tmp);
1564 }
1565 }
1566}
1567
1568/**
1569 * rivafb_cursor - hardware cursor function
1570 * @info: pointer to info structure
1571 * @cursor: pointer to fbcursor structure
1572 *
1573 * DESCRIPTION:
1574 * A cursor function that supports displaying a cursor image via hardware.
1575 * Within the kernel, copy and invert rops are supported. If exported
1576 * to user space, only the copy rop will be supported.
1577 *
1578 * CALLED FROM
1579 * framebuffer hook
1580 */
1581static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1582{
1583 struct riva_par *par = (struct riva_par *) info->par;
1584 u8 data[MAX_CURS * MAX_CURS/8];
1585 u16 fg, bg;
1586 int i, set = cursor->set;
1587
1588 if (cursor->image.width > MAX_CURS ||
1589 cursor->image.height > MAX_CURS)
1590 return soft_cursor(info, cursor);
1591
1592 par->riva.ShowHideCursor(&par->riva, 0);
1593
1594 if (par->cursor_reset) {
1595 set = FB_CUR_SETALL;
1596 par->cursor_reset = 0;
1597 }
1598
1599 if (set & FB_CUR_SETSIZE)
1600 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1601
1602 if (set & FB_CUR_SETPOS) {
1603 u32 xx, yy, temp;
1604
1605 yy = cursor->image.dy - info->var.yoffset;
1606 xx = cursor->image.dx - info->var.xoffset;
1607 temp = xx & 0xFFFF;
1608 temp |= yy << 16;
1609
1610 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1611 }
1612
1613
1614 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1615 u32 bg_idx = cursor->image.bg_color;
1616 u32 fg_idx = cursor->image.fg_color;
1617 u32 s_pitch = (cursor->image.width+7) >> 3;
1618 u32 d_pitch = MAX_CURS/8;
1619 u8 *dat = (u8 *) cursor->image.data;
1620 u8 *msk = (u8 *) cursor->mask;
1621 u8 *src;
1622
1623 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1624
1625 if (src) {
1626 switch (cursor->rop) {
1627 case ROP_XOR:
1628 for (i = 0; i < s_pitch * cursor->image.height;
1629 i++)
1630 src[i] = dat[i] ^ msk[i];
1631 break;
1632 case ROP_COPY:
1633 default:
1634 for (i = 0; i < s_pitch * cursor->image.height;
1635 i++)
1636 src[i] = dat[i] & msk[i];
1637 break;
1638 }
1639
1640 fb_sysmove_buf_aligned(info, &info->pixmap, data,
1641 d_pitch, src, s_pitch,
1642 cursor->image.height);
1643
1644 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1645 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1646 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1647 1 << 15;
1648
1649 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1650 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1651 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1652 1 << 15;
1653
1654 par->riva.LockUnlock(&par->riva, 0);
1655
1656 rivafb_load_cursor_image(par, data, bg, fg,
1657 cursor->image.width,
1658 cursor->image.height);
1659 kfree(src);
1660 }
1661 }
1662
1663 if (cursor->enable)
1664 par->riva.ShowHideCursor(&par->riva, 1);
1665
1666 return 0;
1667}
1668
1669static int rivafb_sync(struct fb_info *info)
1670{
1671 struct riva_par *par = (struct riva_par *)info->par;
1672
1673 wait_for_idle(par);
1674 return 0;
1675}
1676
1677/* ------------------------------------------------------------------------- *
1678 *
1679 * initialization helper functions
1680 *
1681 * ------------------------------------------------------------------------- */
1682
1683/* kernel interface */
1684static struct fb_ops riva_fb_ops = {
1685 .owner = THIS_MODULE,
1686 .fb_open = rivafb_open,
1687 .fb_release = rivafb_release,
1688 .fb_check_var = rivafb_check_var,
1689 .fb_set_par = rivafb_set_par,
1690 .fb_setcolreg = rivafb_setcolreg,
1691 .fb_pan_display = rivafb_pan_display,
1692 .fb_blank = rivafb_blank,
1693 .fb_fillrect = rivafb_fillrect,
1694 .fb_copyarea = rivafb_copyarea,
1695 .fb_imageblit = rivafb_imageblit,
1696 .fb_cursor = rivafb_cursor,
1697 .fb_sync = rivafb_sync,
1698};
1699
1700static int __devinit riva_set_fbinfo(struct fb_info *info)
1701{
1702 unsigned int cmap_len;
1703 struct riva_par *par = (struct riva_par *) info->par;
1704
1705 NVTRACE_ENTER();
1706 info->flags = FBINFO_DEFAULT
1707 | FBINFO_HWACCEL_XPAN
1708 | FBINFO_HWACCEL_YPAN
1709 | FBINFO_HWACCEL_COPYAREA
1710 | FBINFO_HWACCEL_FILLRECT
1711 | FBINFO_HWACCEL_IMAGEBLIT;
1712
1713 /* Accel seems to not work properly on NV30 yet...*/
1714 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1715 printk(KERN_DEBUG PFX "disabling acceleration\n");
1716 info->flags |= FBINFO_HWACCEL_DISABLED;
1717 }
1718
1719 info->var = rivafb_default_var;
1720 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1721 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1722
1723 info->pseudo_palette = par->pseudo_palette;
1724
1725 cmap_len = riva_get_cmap_len(&info->var);
1726 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1727
1728 info->pixmap.size = 8 * 1024;
1729 info->pixmap.buf_align = 4;
1730 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1731 info->var.yres_virtual = -1;
1732 NVTRACE_LEAVE();
1733 return (rivafb_check_var(&info->var, info));
1734}
1735
1736#ifdef CONFIG_PPC_OF
1737static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1738{
1739 struct riva_par *par = (struct riva_par *) info->par;
1740 struct device_node *dp;
1741 unsigned char *pedid = NULL;
1742 unsigned char *disptype = NULL;
1743 static char *propnames[] = {
1744 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1745 int i;
1746
1747 NVTRACE_ENTER();
1748 dp = pci_device_to_OF_node(pd);
1749 for (; dp != NULL; dp = dp->child) {
1750 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1751 if (disptype == NULL)
1752 continue;
1753 if (strncmp(disptype, "LCD", 3) != 0)
1754 continue;
1755 for (i = 0; propnames[i] != NULL; ++i) {
1756 pedid = (unsigned char *)
1757 get_property(dp, propnames[i], NULL);
1758 if (pedid != NULL) {
1759 par->EDID = pedid;
1760 NVTRACE("LCD found.\n");
1761 return 1;
1762 }
1763 }
1764 }
1765 NVTRACE_LEAVE();
1766 return 0;
1767}
1768#endif /* CONFIG_PPC_OF */
1769
1770#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1771static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1772{
1773 struct riva_par *par = (struct riva_par *) info->par;
1774 struct fb_var_screeninfo var;
1775 int i;
1776
1777 NVTRACE_ENTER();
1778 riva_create_i2c_busses(par);
1779 for (i = 0; i < par->bus; i++) {
1780 riva_probe_i2c_connector(par, i+1, &par->EDID);
1781 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1782 printk(PFX "Found EDID Block from BUS %i\n", i);
1783 break;
1784 }
1785 }
1786
1787 NVTRACE_LEAVE();
1788 return (par->EDID) ? 1 : 0;
1789}
1790#endif /* CONFIG_FB_RIVA_I2C */
1791
1792static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1793 struct fb_info *info)
1794{
1795 struct fb_monspecs *specs = &info->monspecs;
1796 struct fb_videomode modedb;
1797
1798 NVTRACE_ENTER();
1799 /* respect mode options */
1800 if (mode_option) {
1801 fb_find_mode(var, info, mode_option,
1802 specs->modedb, specs->modedb_len,
1803 NULL, 8);
1804 } else if (specs->modedb != NULL) {
1805 /* get preferred timing */
1806 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1807 int i;
1808
1809 for (i = 0; i < specs->modedb_len; i++) {
1810 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1811 modedb = specs->modedb[i];
1812 break;
1813 }
1814 }
1815 } else {
1816 /* otherwise, get first mode in database */
1817 modedb = specs->modedb[0];
1818 }
1819 var->bits_per_pixel = 8;
1820 riva_update_var(var, &modedb);
1821 }
1822 NVTRACE_LEAVE();
1823}
1824
1825
1826static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1827{
1828 NVTRACE_ENTER();
1829#ifdef CONFIG_PPC_OF
1830 if (!riva_get_EDID_OF(info, pdev))
1831 printk(PFX "could not retrieve EDID from OF\n");
1832#elif CONFIG_FB_RIVA_I2C
1833 if (!riva_get_EDID_i2c(info))
1834 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1835#endif
1836 NVTRACE_LEAVE();
1837}
1838
1839
1840static void __devinit riva_get_edidinfo(struct fb_info *info)
1841{
1842 struct fb_var_screeninfo *var = &rivafb_default_var;
1843 struct riva_par *par = (struct riva_par *) info->par;
1844
1845 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1846 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1847 &info->modelist);
1848 riva_update_default_var(var, info);
1849
1850 /* if user specified flatpanel, we respect that */
1851 if (info->monspecs.input & FB_DISP_DDI)
1852 par->FlatPanel = 1;
1853}
1854
1855/* ------------------------------------------------------------------------- *
1856 *
1857 * PCI bus
1858 *
1859 * ------------------------------------------------------------------------- */
1860
1861static u32 __devinit riva_get_arch(struct pci_dev *pd)
1862{
1863 u32 arch = 0;
1864
1865 switch (pd->device & 0x0ff0) {
1866 case 0x0100: /* GeForce 256 */
1867 case 0x0110: /* GeForce2 MX */
1868 case 0x0150: /* GeForce2 */
1869 case 0x0170: /* GeForce4 MX */
1870 case 0x0180: /* GeForce4 MX (8x AGP) */
1871 case 0x01A0: /* nForce */
1872 case 0x01F0: /* nForce2 */
1873 arch = NV_ARCH_10;
1874 break;
1875 case 0x0200: /* GeForce3 */
1876 case 0x0250: /* GeForce4 Ti */
1877 case 0x0280: /* GeForce4 Ti (8x AGP) */
1878 arch = NV_ARCH_20;
1879 break;
1880 case 0x0300: /* GeForceFX 5800 */
1881 case 0x0310: /* GeForceFX 5600 */
1882 case 0x0320: /* GeForceFX 5200 */
1883 case 0x0330: /* GeForceFX 5900 */
1884 case 0x0340: /* GeForceFX 5700 */
1885 arch = NV_ARCH_30;
1886 break;
1887 case 0x0020: /* TNT, TNT2 */
1888 arch = NV_ARCH_04;
1889 break;
1890 case 0x0010: /* Riva128 */
1891 arch = NV_ARCH_03;
1892 break;
1893 default: /* unknown architecture */
1894 break;
1895 }
1896 return arch;
1897}
1898
1899static int __devinit rivafb_probe(struct pci_dev *pd,
1900 const struct pci_device_id *ent)
1901{
1902 struct riva_par *default_par;
1903 struct fb_info *info;
1904 int ret;
1905
1906 NVTRACE_ENTER();
1907 assert(pd != NULL);
1908
1909 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1910 if (!info) {
1911 printk (KERN_ERR PFX "could not allocate memory\n");
1912 ret = -ENOMEM;
1913 goto err_ret;
1914 }
1915 default_par = (struct riva_par *) info->par;
1916 default_par->pdev = pd;
1917
1918 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1919 if (info->pixmap.addr == NULL) {
1920 ret = -ENOMEM;
1921 goto err_framebuffer_release;
1922 }
1923 memset(info->pixmap.addr, 0, 8 * 1024);
1924
1925 ret = pci_enable_device(pd);
1926 if (ret < 0) {
1927 printk(KERN_ERR PFX "cannot enable PCI device\n");
1928 goto err_free_pixmap;
1929 }
1930
1931 ret = pci_request_regions(pd, "rivafb");
1932 if (ret < 0) {
1933 printk(KERN_ERR PFX "cannot request PCI regions\n");
1934 goto err_disable_device;
1935 }
1936
1937 default_par->riva.Architecture = riva_get_arch(pd);
1938
1939 default_par->Chipset = (pd->vendor << 16) | pd->device;
1940 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1941
1942#ifdef CONFIG_PCI_NAMES
1943 printk(KERN_INFO PFX "%s\n", pd->pretty_name);
1944#endif
1945
1946 if(default_par->riva.Architecture == 0) {
1947 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1948 ret=-ENODEV;
1949 goto err_release_region;
1950 }
1951 if(default_par->riva.Architecture == NV_ARCH_10 ||
1952 default_par->riva.Architecture == NV_ARCH_20 ||
1953 default_par->riva.Architecture == NV_ARCH_30) {
1954 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1955 } else {
1956 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1957 }
1958
1959 default_par->FlatPanel = flatpanel;
1960 if (flatpanel == 1)
1961 printk(KERN_INFO PFX "flatpanel support enabled\n");
1962 default_par->forceCRTC = forceCRTC;
1963
1964 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1965 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1966
1967 {
1968 /* enable IO and mem if not already done */
1969 unsigned short cmd;
1970
1971 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1972 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1973 pci_write_config_word(pd, PCI_COMMAND, cmd);
1974 }
1975
1976 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1977 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1978
1979 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1980 rivafb_fix.mmio_len);
1981 if (!default_par->ctrl_base) {
1982 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1983 ret = -EIO;
1984 goto err_release_region;
1985 }
1986
1987 switch (default_par->riva.Architecture) {
1988 case NV_ARCH_03:
1989 /* Riva128's PRAMIN is in the "framebuffer" space
1990 * Since these cards were never made with more than 8 megabytes
1991 * we can safely allocate this separately.
1992 */
1993 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1994 if (!default_par->riva.PRAMIN) {
1995 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1996 ret = -EIO;
1997 goto err_iounmap_ctrl_base;
1998 }
1999 break;
2000 case NV_ARCH_04:
2001 case NV_ARCH_10:
2002 case NV_ARCH_20:
2003 case NV_ARCH_30:
2004 default_par->riva.PCRTC0 =
2005 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2006 default_par->riva.PRAMIN =
2007 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2008 break;
2009 }
2010 riva_common_setup(default_par);
2011
2012 if (default_par->riva.Architecture == NV_ARCH_03) {
2013 default_par->riva.PCRTC = default_par->riva.PCRTC0
2014 = default_par->riva.PGRAPH;
2015 }
2016
2017 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2018 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2019 info->screen_base = ioremap(rivafb_fix.smem_start,
2020 rivafb_fix.smem_len);
2021 if (!info->screen_base) {
2022 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2023 ret = -EIO;
2024 goto err_iounmap_pramin;
2025 }
2026
2027#ifdef CONFIG_MTRR
2028 if (!nomtrr) {
2029 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2030 rivafb_fix.smem_len,
2031 MTRR_TYPE_WRCOMB, 1);
2032 if (default_par->mtrr.vram < 0) {
2033 printk(KERN_ERR PFX "unable to setup MTRR\n");
2034 } else {
2035 default_par->mtrr.vram_valid = 1;
2036 /* let there be speed */
2037 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2038 }
2039 }
2040#endif /* CONFIG_MTRR */
2041
2042 info->fbops = &riva_fb_ops;
2043 info->fix = rivafb_fix;
2044 riva_get_EDID(info, pd);
2045 riva_get_edidinfo(info);
2046
2047 ret=riva_set_fbinfo(info);
2048 if (ret < 0) {
2049 printk(KERN_ERR PFX "error setting initial video mode\n");
2050 goto err_iounmap_screen_base;
2051 }
2052
2053 fb_destroy_modedb(info->monspecs.modedb);
2054 info->monspecs.modedb = NULL;
2055 ret = register_framebuffer(info);
2056 if (ret < 0) {
2057 printk(KERN_ERR PFX
2058 "error registering riva framebuffer\n");
2059 goto err_iounmap_screen_base;
2060 }
2061
2062 pci_set_drvdata(pd, info);
2063
2064 printk(KERN_INFO PFX
2065 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2066 info->fix.id,
2067 RIVAFB_VERSION,
2068 info->fix.smem_len / (1024 * 1024),
2069 info->fix.smem_start);
2070#ifdef CONFIG_PMAC_BACKLIGHT
2071 if (default_par->FlatPanel && _machine == _MACH_Pmac)
2072 register_backlight_controller(&riva_backlight_controller,
2073 default_par, "mnca");
2074#endif
2075 NVTRACE_LEAVE();
2076 return 0;
2077
2078err_iounmap_screen_base:
2079#ifdef CONFIG_FB_RIVA_I2C
2080 riva_delete_i2c_busses((struct riva_par *) info->par);
2081#endif
2082 iounmap(info->screen_base);
2083err_iounmap_pramin:
2084 if (default_par->riva.Architecture == NV_ARCH_03)
2085 iounmap(default_par->riva.PRAMIN);
2086err_iounmap_ctrl_base:
2087 iounmap(default_par->ctrl_base);
2088err_release_region:
2089 pci_release_regions(pd);
2090err_disable_device:
2091 pci_disable_device(pd);
2092err_free_pixmap:
2093 kfree(info->pixmap.addr);
2094err_framebuffer_release:
2095 framebuffer_release(info);
2096err_ret:
2097 return ret;
2098}
2099
2100static void __exit rivafb_remove(struct pci_dev *pd)
2101{
2102 struct fb_info *info = pci_get_drvdata(pd);
2103 struct riva_par *par = (struct riva_par *) info->par;
2104
2105 NVTRACE_ENTER();
2106 if (!info)
2107 return;
2108
2109#ifdef CONFIG_FB_RIVA_I2C
2110 riva_delete_i2c_busses(par);
2111 kfree(par->EDID);
2112#endif
2113
2114 unregister_framebuffer(info);
2115#ifdef CONFIG_MTRR
2116 if (par->mtrr.vram_valid)
2117 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2118 info->fix.smem_len);
2119#endif /* CONFIG_MTRR */
2120
2121 iounmap(par->ctrl_base);
2122 iounmap(info->screen_base);
2123 if (par->riva.Architecture == NV_ARCH_03)
2124 iounmap(par->riva.PRAMIN);
2125 pci_release_regions(pd);
2126 pci_disable_device(pd);
2127 kfree(info->pixmap.addr);
2128 framebuffer_release(info);
2129 pci_set_drvdata(pd, NULL);
2130 NVTRACE_LEAVE();
2131}
2132
2133/* ------------------------------------------------------------------------- *
2134 *
2135 * initialization
2136 *
2137 * ------------------------------------------------------------------------- */
2138
2139#ifndef MODULE
2140static int __init rivafb_setup(char *options)
2141{
2142 char *this_opt;
2143
2144 NVTRACE_ENTER();
2145 if (!options || !*options)
2146 return 0;
2147
2148 while ((this_opt = strsep(&options, ",")) != NULL) {
2149 if (!strncmp(this_opt, "forceCRTC", 9)) {
2150 char *p;
2151
2152 p = this_opt + 9;
2153 if (!*p || !*(++p)) continue;
2154 forceCRTC = *p - '0';
2155 if (forceCRTC < 0 || forceCRTC > 1)
2156 forceCRTC = -1;
2157 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2158 flatpanel = 1;
2159#ifdef CONFIG_MTRR
2160 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2161 nomtrr = 1;
2162#endif
2163 } else if (!strncmp(this_opt, "strictmode", 10)) {
2164 strictmode = 1;
2165 } else if (!strncmp(this_opt, "noaccel", 7)) {
2166 noaccel = 1;
2167 } else
2168 mode_option = this_opt;
2169 }
2170 NVTRACE_LEAVE();
2171 return 0;
2172}
2173#endif /* !MODULE */
2174
2175static struct pci_driver rivafb_driver = {
2176 .name = "rivafb",
2177 .id_table = rivafb_pci_tbl,
2178 .probe = rivafb_probe,
2179 .remove = __exit_p(rivafb_remove),
2180};
2181
2182
2183
2184/* ------------------------------------------------------------------------- *
2185 *
2186 * modularization
2187 *
2188 * ------------------------------------------------------------------------- */
2189
2190static int __devinit rivafb_init(void)
2191{
2192#ifndef MODULE
2193 char *option = NULL;
2194
2195 if (fb_get_options("rivafb", &option))
2196 return -ENODEV;
2197 rivafb_setup(option);
2198#endif
2199 return pci_register_driver(&rivafb_driver);
2200}
2201
2202
2203module_init(rivafb_init);
2204
2205#ifdef MODULE
2206static void __exit rivafb_exit(void)
2207{
2208 pci_unregister_driver(&rivafb_driver);
2209}
2210
2211module_exit(rivafb_exit);
2212#endif /* MODULE */
2213
2214module_param(noaccel, bool, 0);
2215MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2216module_param(flatpanel, int, 0);
2217MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2218module_param(forceCRTC, int, 0);
2219MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2220#ifdef CONFIG_MTRR
2221module_param(nomtrr, bool, 0);
2222MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2223#endif
2224module_param(strictmode, bool, 0);
2225MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2226
2227MODULE_AUTHOR("Ani Joshi, maintainer");
2228MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2229MODULE_LICENSE("GPL");
diff --git a/drivers/video/riva/nv4ref.h b/drivers/video/riva/nv4ref.h
new file mode 100644
index 000000000000..3b5f9117c37d
--- /dev/null
+++ b/drivers/video/riva/nv4ref.h
@@ -0,0 +1,2445 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45 */
46
47 /***************************************************************************\
48|* Modified 1999 by Fredrik Reite (fredrik@reite.com) *|
49 \***************************************************************************/
50
51
52#ifndef __NV4REF_H__
53#define __NV4REF_H__
54
55/* Magic values to lock/unlock extended regs */
56#define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */
57#define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */
58#define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */
59#define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */
60
61#define UNLOCK_EXT_MAGIC 0x57
62#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */
63
64#define LOCK_EXT_INDEX 0x6
65
66#define NV_PCRTC_HORIZ_TOTAL 0x00
67#define NV_PCRTC_HORIZ_DISPLAY_END 0x01
68#define NV_PCRTC_HORIZ_BLANK_START 0x02
69
70#define NV_PCRTC_HORIZ_BLANK_END 0x03
71#define NV_PCRTC_HORIZ_BLANK_END_EVRA 7:7
72#define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW 6:5
73#define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END 4:0
74
75#define NV_PCRTC_HORIZ_RETRACE_START 0x04
76
77#define NV_PCRTC_HORIZ_RETRACE_END 0x05
78#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5 7:7
79#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW 6:5
80#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END 4:0
81
82#define NV_PCRTC_VERT_TOTAL 0x06
83
84#define NV_PCRTC_OVERFLOW 0x07
85#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9 7:7
86#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9 6:6
87#define NV_PCRTC_OVERFLOW_VERT_TOTAL_9 5:5
88#define NV_PCRTC_OVERFLOW_LINE_COMPARE_8 4:4
89#define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8 3:3
90#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8 2:2
91#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8 1:1
92#define NV_PCRTC_OVERFLOW_VERT_TOTAL_8 0:0
93
94#define NV_PCRTC_PRESET_ROW_SCAN 0x08
95
96#define NV_PCRTC_MAX_SCAN_LINE 0x09
97#define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN 7:7
98#define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9 6:6
99#define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9 5:5
100#define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE 4:0
101
102#define NV_PCRTC_CURSOR_START 0x0A
103#define NV_PCRTC_CURSOR_END 0x0B
104#define NV_PCRTC_START_ADDR_HIGH 0x0C
105#define NV_PCRTC_START_ADDR_LOW 0x0D
106#define NV_PCRTC_CURSOR_LOCATION_HIGH 0x0E
107#define NV_PCRTC_CURSOR_LOCATION_LOW 0x0F
108
109#define NV_PCRTC_VERT_RETRACE_START 0x10
110#define NV_PCRTC_VERT_RETRACE_END 0x11
111#define NV_PCRTC_VERT_DISPLAY_END 0x12
112#define NV_PCRTC_OFFSET 0x13
113#define NV_PCRTC_UNDERLINE_LOCATION 0x14
114#define NV_PCRTC_VERT_BLANK_START 0x15
115#define NV_PCRTC_VERT_BLANK_END 0x16
116#define NV_PCRTC_MODE_CONTROL 0x17
117#define NV_PCRTC_LINE_COMPARE 0x18
118
119/* Extended offset and start address */
120#define NV_PCRTC_REPAINT0 0x19
121#define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5
122#define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0
123
124/* Horizonal extended bits */
125#define NV_PCRTC_HORIZ_EXTRA 0x2d
126#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4
127#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3
128#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2
129#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1
130#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0
131
132/* Assorted extra bits */
133#define NV_PCRTC_EXTRA 0x25
134#define NV_PCRTC_EXTRA_OFFSET_11 5:5
135#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4
136#define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3
137#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2
138#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1
139#define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0
140
141/* Controls how much data the refresh fifo requests */
142#define NV_PCRTC_FIFO_CONTROL 0x1b
143#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7
144#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0
145#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0
146#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1
147#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2
148#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3
149#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4
150
151/* When the fifo occupancy falls below *twice* the watermark,
152 * the refresh fifo will start to be refilled. If this value is
153 * too low, you will get junk on the screen. Too high, and performance
154 * will suffer. Watermark in units of 8 bytes
155 */
156#define NV_PCRTC_FIFO 0x20
157#define NV_PCRTC_FIFO_RESET 7:7
158#define NV_PCRTC_FIFO_WATERMARK 5:0
159
160/* Various flags */
161#define NV_PCRTC_REPAINT1 0x1a
162#define NV_PCRTC_REPAINT1_HSYNC 7:7
163#define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01
164#define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00
165#define NV_PCRTC_REPAINT1_VSYNC 6:6
166#define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01
167#define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00
168#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4
169#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01
170#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00
171#define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2
172#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01
173#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */
174#define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1
175#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00
176#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01
177
178#define NV_PCRTC_GRCURSOR0 0x30
179#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0
180
181#define NV_PCRTC_GRCURSOR1 0x31
182#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3
183#define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1
184#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0
185#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1
186#define NV_PCRTC_GRCURSOR1_CURSOR 0:0
187#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0
188#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1
189
190/* Controls what the format of the framebuffer is */
191#define NV_PCRTC_PIXEL 0x28
192#define NV_PCRTC_PIXEL_MODE 7:7
193#define NV_PCRTC_PIXEL_MODE_TV 0x01
194#define NV_PCRTC_PIXEL_MODE_VGA 0x00
195#define NV_PCRTC_PIXEL_TV_MODE 6:6
196#define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00
197#define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01
198#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3
199#define NV_PCRTC_PIXEL_FORMAT 1:0
200#define NV_PCRTC_PIXEL_FORMAT_VGA 0x00
201#define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01
202#define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02
203#define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03
204
205/* RAMDAC registers and fields */
206#define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */
207#define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */
208#define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */
209#define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */
210#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */
211#define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */
212#define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */
213#define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */
214#define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */
215#define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */
216#define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */
217#define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */
218#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */
219#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */
220#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */
221#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */
222#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */
223#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */
224#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */
225#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */
226#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */
227#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */
228#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */
229#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */
230#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */
231#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */
232#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */
233#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */
234#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */
235#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */
236#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */
237#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */
238#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */
239#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */
240#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */
241#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */
242#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */
243#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */
244#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */
245#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */
246#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */
247#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */
248#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */
249#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */
250#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */
251#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */
252#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */
253#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */
254#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */
255#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */
256#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */
257#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */
258#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */
259#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */
260#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */
261#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */
262#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */
263#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */
264#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */
265#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */
266#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */
267#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */
268#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */
269#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */
270#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */
271#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */
272
273/* Master Control */
274#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */
275#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
276#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */
277#define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */
278#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */
279#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */
280#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */
281#define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */
282#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */
283#define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */
284#define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */
285#define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */
286#define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */
287#define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */
288#define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* C---V */
289#define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */
290#define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */
291#define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */
292#define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */
293#define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */
294#define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */
295#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */
296#define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */
297#define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */
298#define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */
299#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */
300#define NV_PMC_INTR_0 0x00000100 /* RW-4R */
301#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */
302#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */
303#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */
304#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */
305#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */
306#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */
307#define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */
308#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */
309#define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */
310#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */
311#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */
312#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */
313#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */
314#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */
315#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */
316#define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */
317#define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */
318#define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */
319#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */
320#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */
321#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */
322#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */
323#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */
324#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */
325#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */
326#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */
327#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */
328#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */
329#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */
330#define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */
331#define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */
332#define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */
333#define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */
334#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
335#define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */
336#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */
337#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */
338#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
339#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
340#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
341#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */
342#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */
343#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */
344#define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */
345#define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */
346#define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */
347#define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */
348#define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */
349#define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */
350#define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */
351#define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */
352#define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */
353#define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */
354#define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */
355#define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */
356
357/* dev_timer.ref */
358#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */
359#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */
360#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */
361#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */
362#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */
363#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */
364#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */
365#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */
366#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */
367#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */
368#define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */
369#define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */
370#define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */
371#define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */
372#define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */
373#define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */
374#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */
375#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
376#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */
377#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
378#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */
379#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */
380
381/* dev_fifo.ref */
382#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */
383#define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */
384#define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */
385#define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */
386#define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */
387#define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */
388#define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */
389#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */
390#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */
391#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */
392#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */
393#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */
394#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */
395#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */
396#define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */
397#define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */
398#define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */
399#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */
400#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */
401#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */
402#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */
403#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */
404#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */
405#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */
406#define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */
407#define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */
408#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */
409#define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */
410#define NV_PFIFO_NEXT_CHANNEL_CHID 3:0 /* RWXUF */
411#define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */
412#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */
413#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */
414#define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */
415#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */
416#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */
417#define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */
418#define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */
419#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */
420#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */
421#define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */
422#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */
423#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */
424#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */
425#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */
426#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */
427#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */
428#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */
429#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */
430#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */
431#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */
432#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */
433#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */
434#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */
435#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */
436#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */
437#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */
438#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */
439#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */
440#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */
441#define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */
442#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */
443#define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */
444#define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */
445#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */
446#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */
447#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */
448#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */
449#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */
450#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */
451#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */
452#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */
453#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */
454#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */
455#define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */
456#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */
457#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */
458#define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */
459#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */
460#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */
461#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */
462#define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */
463#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */
464#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */
465#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */
466#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */
467#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */
468#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */
469#define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */
470#define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */
471#define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */
472#define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */
473#define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */
474#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */
475#define NV_PFIFO_RAMFC_BASE_ADDRESS 8:1 /* RWIUF */
476#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000088 /* RWI-V */
477#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */
478#define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */
479#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RWI-V */
480#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */
481#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */
482#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */
483#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */
484#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */
485#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */
486#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */
487#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */
488#define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */
489#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */
490#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */
491#define NV_PFIFO_MODE 0x00002504 /* RW-4R */
492#define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */
493#define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */
494#define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */
495#define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */
496#define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */
497#define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */
498#define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */
499#define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */
500#define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */
501#define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */
502#define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */
503#define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */
504#define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */
505#define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */
506#define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */
507#define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */
508#define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */
509#define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */
510#define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */
511#define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */
512#define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */
513#define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */
514#define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */
515#define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */
516#define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */
517#define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */
518#define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */
519#define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */
520#define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */
521#define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */
522#define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */
523#define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */
524#define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */
525#define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */
526#define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */
527#define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */
528#define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */
529#define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */
530#define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */
531#define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */
532#define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */
533#define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */
534#define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */
535#define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */
536#define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */
537#define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */
538#define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */
539#define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */
540#define NV_PFIFO_DMA 0x00002508 /* RW-4R */
541#define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */
542#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */
543#define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */
544#define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */
545#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */
546#define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */
547#define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */
548#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */
549#define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */
550#define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */
551#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */
552#define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */
553#define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */
554#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */
555#define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */
556#define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */
557#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */
558#define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */
559#define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */
560#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */
561#define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */
562#define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */
563#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */
564#define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */
565#define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */
566#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */
567#define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */
568#define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */
569#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */
570#define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */
571#define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */
572#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */
573#define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */
574#define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */
575#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */
576#define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */
577#define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */
578#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */
579#define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */
580#define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */
581#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */
582#define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */
583#define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */
584#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */
585#define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */
586#define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */
587#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */
588#define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */
589#define NV_PFIFO_SIZE 0x0000250C /* RW-4R */
590#define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */
591#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */
592#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */
593#define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */
594#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */
595#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */
596#define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */
597#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */
598#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */
599#define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */
600#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */
601#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */
602#define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */
603#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */
604#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */
605#define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */
606#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */
607#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */
608#define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */
609#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */
610#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */
611#define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */
612#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */
613#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */
614#define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */
615#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */
616#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */
617#define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */
618#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */
619#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */
620#define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */
621#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */
622#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */
623#define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */
624#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */
625#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */
626#define NV_PFIFO_SIZE_CHANNEL_12 12:12 /* RWIVF */
627#define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES 0x00000000 /* RWI-V */
628#define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES 0x00000001 /* RW--V */
629#define NV_PFIFO_SIZE_CHANNEL_13 13:13 /* RWIVF */
630#define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES 0x00000000 /* RWI-V */
631#define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES 0x00000001 /* RW--V */
632#define NV_PFIFO_SIZE_CHANNEL_14 14:14 /* RWIVF */
633#define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES 0x00000000 /* RWI-V */
634#define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES 0x00000001 /* RW--V */
635#define NV_PFIFO_SIZE_CHANNEL_15 15:15 /* RWIVF */
636#define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES 0x00000000 /* RWI-V */
637#define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES 0x00000001 /* RW--V */
638#define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */
639#define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */
640#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */
641#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */
642#define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */
643#define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */
644#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */
645#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */
646#define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */
647#define NV_PFIFO_CACHE0_PUSH1_CHID 3:0 /* RWXUF */
648#define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */
649#define NV_PFIFO_CACHE1_PUSH1_CHID 3:0 /* RWXUF */
650#define NV_PFIFO_CACHE1_PUSH1_MODE 8:8 /* RWIVF */
651#define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 /* RWI-V */
652#define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000001 /* RW--V */
653#define NV_PFIFO_CACHE1_DMA_PUSH 0x00003220 /* RW-4R */
654#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS 0:0 /* RWIVF */
655#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 /* RWI-V */
656#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 /* RW--V */
657#define NV_PFIFO_CACHE1_DMA_PUSH_STATE 4:4 /* R--VF */
658#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 /* R---V */
659#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000001 /* R---V */
660#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER 8:8 /* R--VF */
661#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 /* R---V */
662#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000001 /* R---V */
663#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS 12:12 /* RWIVF */
664#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 /* RWI-V */
665#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00000001 /* RW--V */
666#define NV_PFIFO_CACHE1_DMA_FETCH 0x00003224 /* RW-4R */
667#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 /* RWIUF */
668#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 /* RW--V */
669#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000001 /* RW--V */
670#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000002 /* RW--V */
671#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000003 /* RW--V */
672#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000004 /* RW--V */
673#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000005 /* RW--V */
674#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000006 /* RW--V */
675#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000007 /* RW--V */
676#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000008 /* RW--V */
677#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000009 /* RW--V */
678#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000000A /* RW--V */
679#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000000B /* RW--V */
680#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000000C /* RW--V */
681#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000000D /* RW--V */
682#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000000E /* RW--V */
683#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000000F /* RWI-V */
684#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000010 /* RW--V */
685#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000011 /* RW--V */
686#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000012 /* RW--V */
687#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000013 /* RW--V */
688#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x00000014 /* RW--V */
689#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x00000015 /* RW--V */
690#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x00000016 /* RW--V */
691#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x00000017 /* RW--V */
692#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x00000018 /* RW--V */
693#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x00000019 /* RW--V */
694#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x0000001A /* RW--V */
695#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x0000001B /* RW--V */
696#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x0000001C /* RW--V */
697#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x0000001D /* RW--V */
698#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x0000001E /* RW--V */
699#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x0000001F /* RW--V */
700#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 15:13 /* RWIUF */
701#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 /* RW--V */
702#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00000001 /* RW--V */
703#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00000002 /* RW--V */
704#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00000003 /* RWI-V */
705#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00000004 /* RW--V */
706#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x00000005 /* RW--V */
707#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x00000006 /* RW--V */
708#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x00000007 /* RW--V */
709#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 19:16 /* RWIUF */
710#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 /* RWI-V */
711#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00000001 /* RW--V */
712#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00000002 /* RW--V */
713#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00000003 /* RW--V */
714#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00000004 /* RW--V */
715#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00000005 /* RW--V */
716#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00000006 /* RW--V */
717#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00000007 /* RW--V */
718#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00000008 /* RW--V */
719#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00000009 /* RW--V */
720#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x0000000A /* RW--V */
721#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x0000000B /* RW--V */
722#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x0000000C /* RW--V */
723#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x0000000D /* RW--V */
724#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x0000000E /* RW--V */
725#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x0000000F /* RW--V */
726#define NV_PFIFO_CACHE1_DMA_PUT 0x00003240 /* RW-4R */
727#define NV_PFIFO_CACHE1_DMA_PUT_OFFSET 28:2 /* RWXUF */
728#define NV_PFIFO_CACHE1_DMA_GET 0x00003244 /* RW-4R */
729#define NV_PFIFO_CACHE1_DMA_GET_OFFSET 28:2 /* RWXUF */
730#define NV_PFIFO_CACHE1_DMA_STATE 0x00003228 /* RW-4R */
731#define NV_PFIFO_CACHE1_DMA_STATE_METHOD 12:2 /* RWXUF */
732#define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 15:13 /* RWXUF */
733#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 28:18 /* RWIUF */
734#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x00000000 /* RWI-V */
735#define NV_PFIFO_CACHE1_DMA_STATE_ERROR 31:30 /* RWXUF */
736#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 /* RW--V */
737#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x00000001 /* RW--V */
738#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x00000002 /* RW--V */
739#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x00000003 /* RW--V */
740#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000322C /* RW-4R */
741#define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 15:0 /* RWXUF */
742#define NV_PFIFO_CACHE1_DMA_CTL 0x00003230 /* RW-4R */
743#define NV_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 /* RWXUF */
744#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12:12 /* RWXUF */
745#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */
746#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
747#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13:13 /* RWXUF */
748#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
749#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
750#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 17:16 /* RWXUF */
751#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00000002 /* RW--V */
752#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00000003 /* RW--V */
753#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO 31:31 /* RWIUF */
754#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 /* RW--V */
755#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x00000001 /* RWI-V */
756#define NV_PFIFO_CACHE1_DMA_LIMIT 0x00003234 /* RW-4R */
757#define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET 28:2 /* RWXUF */
758#define NV_PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 /* RW-4R */
759#define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 /* RWXUF */
760#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0:0 /* RWIUF */
761#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 /* RWI-V */
762#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 /* RW--V */
763#define NV_PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C /* RW-4R */
764#define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
765#define NV_PFIFO_CACHE0_PULL0 0x00003050 /* RW-4R */
766#define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */
767#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */
768#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */
769#define NV_PFIFO_CACHE0_PULL0_HASH 4:4 /* R-XVF */
770#define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */
771#define NV_PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000001 /* R---V */
772#define NV_PFIFO_CACHE0_PULL0_DEVICE 8:8 /* R-XVF */
773#define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */
774#define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */
775#define NV_PFIFO_CACHE0_PULL0_HASH_STATE 12:12 /* R-XVF */
776#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */
777#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */
778#define NV_PFIFO_CACHE1_PULL0 0x00003250 /* RW-4R */
779#define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */
780#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */
781#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */
782#define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */
783#define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */
784#define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */
785#define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */
786#define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */
787#define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */
788#define NV_PFIFO_CACHE1_PULL0_HASH_STATE 12:12 /* R-XVF */
789#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */
790#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */
791#define NV_PFIFO_CACHE0_PULL1 0x00003054 /* RW-4R */
792#define NV_PFIFO_CACHE0_PULL1_ENGINE 1:0 /* RWXUF */
793#define NV_PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 /* RW--V */
794#define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */
795#define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 /* RW--V */
796#define NV_PFIFO_CACHE1_PULL1 0x00003254 /* RW-4R */
797#define NV_PFIFO_CACHE1_PULL1_ENGINE 1:0 /* RWXUF */
798#define NV_PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 /* RW--V */
799#define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */
800#define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 /* RW--V */
801#define NV_PFIFO_CACHE0_HASH 0x00003058 /* RW-4R */
802#define NV_PFIFO_CACHE0_HASH_INSTANCE 15:0 /* RWXUF */
803#define NV_PFIFO_CACHE0_HASH_VALID 16:16 /* RWXVF */
804#define NV_PFIFO_CACHE1_HASH 0x00003258 /* RW-4R */
805#define NV_PFIFO_CACHE1_HASH_INSTANCE 15:0 /* RWXUF */
806#define NV_PFIFO_CACHE1_HASH_VALID 16:16 /* RWXVF */
807#define NV_PFIFO_CACHE0_STATUS 0x00003014 /* R--4R */
808#define NV_PFIFO_CACHE0_STATUS_LOW_MARK 4:4 /* R--VF */
809#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
810#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
811#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK 8:8 /* R--VF */
812#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
813#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
814#define NV_PFIFO_CACHE1_STATUS 0x00003214 /* R--4R */
815#define NV_PFIFO_CACHE1_STATUS_LOW_MARK 4:4 /* R--VF */
816#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
817#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
818#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK 8:8 /* R--VF */
819#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
820#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
821#define NV_PFIFO_CACHE1_STATUS1 0x00003218 /* R--4R */
822#define NV_PFIFO_CACHE1_STATUS1_RANOUT 0:0 /* R-XVF */
823#define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 /* R---V */
824#define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 /* R---V */
825#define NV_PFIFO_CACHE0_PUT 0x00003010 /* RW-4R */
826#define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */
827#define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */
828#define NV_PFIFO_CACHE1_PUT_ADDRESS 9:2 /* RWXUF */
829#define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */
830#define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */
831#define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */
832#define NV_PFIFO_CACHE1_GET_ADDRESS 9:2 /* RWXUF */
833#define NV_PFIFO_CACHE0_ENGINE 0x00003080 /* RW-4R */
834#define NV_PFIFO_CACHE0_ENGINE_0 1:0 /* RWXUF */
835#define NV_PFIFO_CACHE0_ENGINE_0_SW 0x00000000 /* RW--V */
836#define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */
837#define NV_PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 /* RW--V */
838#define NV_PFIFO_CACHE0_ENGINE_1 5:4 /* RWXUF */
839#define NV_PFIFO_CACHE0_ENGINE_1_SW 0x00000000 /* RW--V */
840#define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */
841#define NV_PFIFO_CACHE0_ENGINE_1_DVD 0x00000002 /* RW--V */
842#define NV_PFIFO_CACHE0_ENGINE_2 9:8 /* RWXUF */
843#define NV_PFIFO_CACHE0_ENGINE_2_SW 0x00000000 /* RW--V */
844#define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */
845#define NV_PFIFO_CACHE0_ENGINE_2_DVD 0x00000002 /* RW--V */
846#define NV_PFIFO_CACHE0_ENGINE_3 13:12 /* RWXUF */
847#define NV_PFIFO_CACHE0_ENGINE_3_SW 0x00000000 /* RW--V */
848#define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */
849#define NV_PFIFO_CACHE0_ENGINE_3_DVD 0x00000002 /* RW--V */
850#define NV_PFIFO_CACHE0_ENGINE_4 17:16 /* RWXUF */
851#define NV_PFIFO_CACHE0_ENGINE_4_SW 0x00000000 /* RW--V */
852#define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */
853#define NV_PFIFO_CACHE0_ENGINE_4_DVD 0x00000002 /* RW--V */
854#define NV_PFIFO_CACHE0_ENGINE_5 21:20 /* RWXUF */
855#define NV_PFIFO_CACHE0_ENGINE_5_SW 0x00000000 /* RW--V */
856#define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */
857#define NV_PFIFO_CACHE0_ENGINE_5_DVD 0x00000002 /* RW--V */
858#define NV_PFIFO_CACHE0_ENGINE_6 25:24 /* RWXUF */
859#define NV_PFIFO_CACHE0_ENGINE_6_SW 0x00000000 /* RW--V */
860#define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */
861#define NV_PFIFO_CACHE0_ENGINE_6_DVD 0x00000002 /* RW--V */
862#define NV_PFIFO_CACHE0_ENGINE_7 29:28 /* RWXUF */
863#define NV_PFIFO_CACHE0_ENGINE_7_SW 0x00000000 /* RW--V */
864#define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */
865#define NV_PFIFO_CACHE0_ENGINE_7_DVD 0x00000002 /* RW--V */
866#define NV_PFIFO_CACHE1_ENGINE 0x00003280 /* RW-4R */
867#define NV_PFIFO_CACHE1_ENGINE_0 1:0 /* RWXUF */
868#define NV_PFIFO_CACHE1_ENGINE_0_SW 0x00000000 /* RW--V */
869#define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */
870#define NV_PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 /* RW--V */
871#define NV_PFIFO_CACHE1_ENGINE_1 5:4 /* RWXUF */
872#define NV_PFIFO_CACHE1_ENGINE_1_SW 0x00000000 /* RW--V */
873#define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */
874#define NV_PFIFO_CACHE1_ENGINE_1_DVD 0x00000002 /* RW--V */
875#define NV_PFIFO_CACHE1_ENGINE_2 9:8 /* RWXUF */
876#define NV_PFIFO_CACHE1_ENGINE_2_SW 0x00000000 /* RW--V */
877#define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */
878#define NV_PFIFO_CACHE1_ENGINE_2_DVD 0x00000002 /* RW--V */
879#define NV_PFIFO_CACHE1_ENGINE_3 13:12 /* RWXUF */
880#define NV_PFIFO_CACHE1_ENGINE_3_SW 0x00000000 /* RW--V */
881#define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */
882#define NV_PFIFO_CACHE1_ENGINE_3_DVD 0x00000002 /* RW--V */
883#define NV_PFIFO_CACHE1_ENGINE_4 17:16 /* RWXUF */
884#define NV_PFIFO_CACHE1_ENGINE_4_SW 0x00000000 /* RW--V */
885#define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */
886#define NV_PFIFO_CACHE1_ENGINE_4_DVD 0x00000002 /* RW--V */
887#define NV_PFIFO_CACHE1_ENGINE_5 21:20 /* RWXUF */
888#define NV_PFIFO_CACHE1_ENGINE_5_SW 0x00000000 /* RW--V */
889#define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */
890#define NV_PFIFO_CACHE1_ENGINE_5_DVD 0x00000002 /* RW--V */
891#define NV_PFIFO_CACHE1_ENGINE_6 25:24 /* RWXUF */
892#define NV_PFIFO_CACHE1_ENGINE_6_SW 0x00000000 /* RW--V */
893#define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */
894#define NV_PFIFO_CACHE1_ENGINE_6_DVD 0x00000002 /* RW--V */
895#define NV_PFIFO_CACHE1_ENGINE_7 29:28 /* RWXUF */
896#define NV_PFIFO_CACHE1_ENGINE_7_SW 0x00000000 /* RW--V */
897#define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */
898#define NV_PFIFO_CACHE1_ENGINE_7_DVD 0x00000002 /* RW--V */
899#define NV_PFIFO_CACHE0_METHOD(i) (0x00003100+(i)*8) /* RW-4A */
900#define NV_PFIFO_CACHE0_METHOD__SIZE_1 1 /* */
901#define NV_PFIFO_CACHE0_METHOD_ADDRESS 12:2 /* RWXUF */
902#define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL 15:13 /* RWXUF */
903#define NV_PFIFO_CACHE1_METHOD(i) (0x00003800+(i)*8) /* RW-4A */
904#define NV_PFIFO_CACHE1_METHOD__SIZE_1 128 /* */
905#define NV_PFIFO_CACHE1_METHOD_ADDRESS 12:2 /* RWXUF */
906#define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 15:13 /* RWXUF */
907#define NV_PFIFO_CACHE1_METHOD_ALIAS(i) (0x00003C00+(i)*8) /* RW-4A */
908#define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1 128 /* */
909#define NV_PFIFO_CACHE0_DATA(i) (0x00003104+(i)*8) /* RW-4A */
910#define NV_PFIFO_CACHE0_DATA__SIZE_1 1 /* */
911#define NV_PFIFO_CACHE0_DATA_VALUE 31:0 /* RWXVF */
912#define NV_PFIFO_CACHE1_DATA(i) (0x00003804+(i)*8) /* RW-4A */
913#define NV_PFIFO_CACHE1_DATA__SIZE_1 128 /* */
914#define NV_PFIFO_CACHE1_DATA_VALUE 31:0 /* RWXVF */
915#define NV_PFIFO_CACHE1_DATA_ALIAS(i) (0x00003C04+(i)*8) /* RW-4A */
916#define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1 128 /* */
917#define NV_PFIFO_DEVICE(i) (0x00002800+(i)*4) /* R--4A */
918#define NV_PFIFO_DEVICE__SIZE_1 128 /* */
919#define NV_PFIFO_DEVICE_CHID 3:0 /* R--UF */
920#define NV_PFIFO_DEVICE_SWITCH 24:24 /* R--VF */
921#define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 /* R---V */
922#define NV_PFIFO_DEVICE_SWITCH_AVAILABLE 0x00000001 /* R---V */
923#define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */
924#define NV_PFIFO_RUNOUT_STATUS_RANOUT 0:0 /* R--VF */
925#define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 /* R---V */
926#define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 /* R---V */
927#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK 4:4 /* R--VF */
928#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
929#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
930#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK 8:8 /* R--VF */
931#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
932#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
933#define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */
934#define NV_PFIFO_RUNOUT_PUT_ADDRESS 12:3 /* RWXUF */
935#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0 8:3 /* RWXUF */
936#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1 12:3 /* RWXUF */
937#define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */
938#define NV_PFIFO_RUNOUT_GET_ADDRESS 13:3 /* RWXUF */
939/* dev_graphics.ref */
940#define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */
941#define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */
942#define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */
943#define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */
944#define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */
945#define NV_PGRAPH_INTR 0x00400100 /* RW-4R */
946#define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWIVF */
947#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
948#define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */
949#define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--C */
950#define NV_PGRAPH_INTR_MISSING_HW 4:4 /* RWIVF */
951#define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x00000000 /* R-I-V */
952#define NV_PGRAPH_INTR_MISSING_HW_PENDING 0x00000001 /* R---V */
953#define NV_PGRAPH_INTR_MISSING_HW_RESET 0x00000001 /* -W--C */
954#define NV_PGRAPH_INTR_TLB_PRESENT_A 8:8 /* RWIVF */
955#define NV_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x00000000 /* R-I-V */
956#define NV_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x00000001 /* R---V */
957#define NV_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x00000001 /* -W--C */
958#define NV_PGRAPH_INTR_TLB_PRESENT_B 9:9 /* RWIVF */
959#define NV_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x00000000 /* R-I-V */
960#define NV_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x00000001 /* R---V */
961#define NV_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x00000001 /* -W--C */
962#define NV_PGRAPH_INTR_CONTEXT_SWITCH 12:12 /* RWIVF */
963#define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */
964#define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */
965#define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x00000001 /* -W--C */
966#define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWIVF */
967#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
968#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */
969#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--C */
970#define NV_PGRAPH_NSTATUS 0x00400104 /* RW-4R */
971#define NV_PGRAPH_NSTATUS_STATE_IN_USE 11:11 /* RWIVF */
972#define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x00000000 /* RWI-V */
973#define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x00000001 /* RW--V */
974#define NV_PGRAPH_NSTATUS_INVALID_STATE 12:12 /* RWIVF */
975#define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x00000000 /* RWI-V */
976#define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x00000001 /* RW--V */
977#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT 13:13 /* RWIVF */
978#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x00000000 /* RWI-V */
979#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x00000001 /* RW--V */
980#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT 14:14 /* RWIVF */
981#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x00000000 /* RWI-V */
982#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x00000001 /* RW--V */
983#define NV_PGRAPH_NSOURCE 0x00400108 /* R--4R */
984#define NV_PGRAPH_NSOURCE_NOTIFICATION 0:0 /* R-IVF */
985#define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */
986#define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x00000001 /* R---V */
987#define NV_PGRAPH_NSOURCE_DATA_ERROR 1:1 /* R-IVF */
988#define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
989#define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x00000001 /* R---V */
990#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR 2:2 /* R-IVF */
991#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
992#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x00000001 /* R---V */
993#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION 3:3 /* R-IVF */
994#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
995#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x00000001 /* R---V */
996#define NV_PGRAPH_NSOURCE_LIMIT_COLOR 4:4 /* R-IVF */
997#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x00000000 /* R-I-V */
998#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x00000001 /* R---V */
999#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_ 5:5 /* R-IVF */
1000#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x00000000 /* R-I-V */
1001#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x00000001 /* R---V */
1002#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD 6:6 /* R-IVF */
1003#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */
1004#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */
1005#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION 7:7 /* R-IVF */
1006#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
1007#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x00000001 /* R---V */
1008#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION 8:8 /* R-IVF */
1009#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
1010#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x00000001 /* R---V */
1011#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9:9 /* R-IVF */
1012#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
1013#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x00000001 /* R---V */
1014#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION 10:10 /* R-IVF */
1015#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
1016#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x00000001 /* R---V */
1017#define NV_PGRAPH_NSOURCE_STATE_INVALID 11:11 /* R-IVF */
1018#define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x00000000 /* R-I-V */
1019#define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x00000001 /* R---V */
1020#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12:12 /* R-IVF */
1021#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
1022#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */
1023#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE 13:13 /* R-IVF */
1024#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x00000000 /* R-I-V */
1025#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x00000001 /* R---V */
1026#define NV_PGRAPH_NSOURCE_METHOD_CNT 14:14 /* R-IVF */
1027#define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x00000000 /* R-I-V */
1028#define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x00000001 /* R---V */
1029#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION 15:15 /* R-IVF */
1030#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */
1031#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x00000001 /* R---V */
1032#define NV_PGRAPH_INTR_EN 0x00400140 /* RW-4R */
1033#define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWIVF */
1034#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWI-V */
1035#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */
1036#define NV_PGRAPH_INTR_EN_MISSING_HW 4:4 /* RWIVF */
1037#define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED 0x00000000 /* RWI-V */
1038#define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x00000001 /* RW--V */
1039#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A 8:8 /* RWIVF */
1040#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_DISABLED 0x00000000 /* RWI-V */
1041#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x00000001 /* RW--V */
1042#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B 9:9 /* RWIVF */
1043#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_DISABLED 0x00000000 /* RWI-V */
1044#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x00000001 /* RW--V */
1045#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH 12:12 /* RWIVF */
1046#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */
1047#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */
1048#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWIVF */
1049#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWI-V */
1050#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */
1051#define NV_PGRAPH_CTX_SWITCH1 0x00400160 /* RW-4R */
1052#define NV_PGRAPH_CTX_SWITCH1_GRCLASS 7:0 /* RWXVF */
1053#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12:12 /* RWXUF */
1054#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x00000000 /* RW--V */
1055#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */
1056#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP 13:13 /* RWXUF */
1057#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x00000000 /* RW--V */
1058#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x00000001 /* RW--V */
1059#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE 14:14 /* RWXUF */
1060#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x00000000 /* RW--V */
1061#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x00000001 /* RW--V */
1062#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 /* RWXUF */
1063#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RW--V */
1064#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */
1065#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */
1066#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */
1067#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */
1068#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */
1069#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24:24 /* RWXUF */
1070#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x00000000 /* RW--V */
1071#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x00000001 /* RW--V */
1072#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25:25 /* RWXUF */
1073#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x00000000 /* RW--V */
1074#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x00000001 /* RW--V */
1075#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31:31 /* CWIVF */
1076#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x00000000 /* CWI-V */
1077#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x00000001 /* -W--T */
1078#define NV_PGRAPH_CTX_SWITCH2 0x00400164 /* RW-4R */
1079#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT 1:0 /* RWXUF */
1080#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 /* RW--V */
1081#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */
1082#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 /* RW--V */
1083#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 /* RWXUF */
1084#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 /* RW--V */
1085#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */
1086#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */
1087#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */
1088#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */
1089#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */
1090#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */
1091#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */
1092#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */
1093#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */
1094#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */
1095#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */
1096#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */
1097#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */
1098#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */
1099#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */
1100#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */
1101#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */
1102#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */
1103#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 31:16 /* RWXUF */
1104#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x0000 /* RW--V */
1105#define NV_PGRAPH_CTX_SWITCH3 0x00400168 /* RW-4R */
1106#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 15:0 /* RWXUF */
1107#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x0000 /* RW--V */
1108#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 31:16 /* RWXUF */
1109#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x0000 /* RW--V */
1110#define NV_PGRAPH_CTX_SWITCH4 0x0040016C /* RW-4R */
1111#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 15:0 /* RWXUF */
1112#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x0000 /* RW--V */
1113#define NV_PGRAPH_CTX_CACHE1(i) (0x00400180+(i)*4) /* RW-4A */
1114#define NV_PGRAPH_CTX_CACHE1__SIZE_1 8 /* */
1115#define NV_PGRAPH_CTX_CACHE1_GRCLASS 7:0 /* RWXVF */
1116#define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY 12:12 /* RWXVF */
1117#define NV_PGRAPH_CTX_CACHE1_USER_CLIP 13:13 /* RWXVF */
1118#define NV_PGRAPH_CTX_CACHE1_SWIZZLE 14:14 /* RWXVF */
1119#define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 /* RWXVF */
1120#define NV_PGRAPH_CTX_CACHE1_SPARE1 20:20 /* RWXVF */
1121#define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS 24:24 /* RWXVF */
1122#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25:25 /* RWXVF */
1123#define NV_PGRAPH_CTX_CACHE2(i) (0x004001a0+(i)*4) /* RW-4A */
1124#define NV_PGRAPH_CTX_CACHE2__SIZE_1 8 /* */
1125#define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT 1:0 /* RWXVF */
1126#define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 /* RWXVF */
1127#define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 31:16 /* RWXVF */
1128#define NV_PGRAPH_CTX_CACHE3(i) (0x004001c0+(i)*4) /* RW-4A */
1129#define NV_PGRAPH_CTX_CACHE3__SIZE_1 8 /* */
1130#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 15:0 /* RWXVF */
1131#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 31:16 /* RWXVF */
1132#define NV_PGRAPH_CTX_CACHE4(i) (0x004001e0+(i)*4) /* RW-4A */
1133#define NV_PGRAPH_CTX_CACHE4__SIZE_1 8 /* */
1134#define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE 15:0 /* RWXVF */
1135#define NV_PGRAPH_CTX_CONTROL 0x00400170 /* RW-4R */
1136#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */
1137#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */
1138#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */
1139#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */
1140#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */
1141#define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */
1142#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */
1143#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */
1144#define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */
1145#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */
1146#define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */
1147#define NV_PGRAPH_CTX_CONTROL_CHANGE 20:20 /* R--VF */
1148#define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x00000000 /* R---V */
1149#define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x00000001 /* R---V */
1150#define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */
1151#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */
1152#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */
1153#define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */
1154#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */
1155#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */
1156#define NV_PGRAPH_CTX_USER 0x00400174 /* RW-4R */
1157#define NV_PGRAPH_CTX_USER_SUBCH 15:13 /* RWIVF */
1158#define NV_PGRAPH_CTX_USER_SUBCH_0 0x00000000 /* RWI-V */
1159#define NV_PGRAPH_CTX_USER_CHID 27:24 /* RWIVF */
1160#define NV_PGRAPH_CTX_USER_CHID_0 0x00000000 /* RWI-V */
1161#define NV_PGRAPH_FIFO 0x00400720 /* RW-4R */
1162#define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */
1163#define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */
1164#define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */
1165#define NV_PGRAPH_FFINTFC_FIFO_0(i) (0x00400730+(i)*4) /* RW-4A */
1166#define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1 4 /* */
1167#define NV_PGRAPH_FFINTFC_FIFO_0_TAG 0:0 /* RWXVF */
1168#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x00000000 /* RW--V */
1169#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x00000001 /* RW--V */
1170#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH 3:1 /* RWXVF */
1171#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0 0x00000000 /* RW--V */
1172#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1 0x00000001 /* RW--V */
1173#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2 0x00000002 /* RW--V */
1174#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3 0x00000003 /* RW--V */
1175#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4 0x00000004 /* RW--V */
1176#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5 0x00000005 /* RW--V */
1177#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6 0x00000006 /* RW--V */
1178#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7 0x00000007 /* RW--V */
1179#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD 14:4 /* RWXVF */
1180#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x00000000 /* RW--V */
1181#define NV_PGRAPH_FFINTFC_FIFO_1(i) (0x00400740+(i)*4) /* RW-4A */
1182#define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1 4 /* */
1183#define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 31:0 /* RWXVF */
1184#define NV_PGRAPH_FFINTFC_FIFO_PTR 0x00400750 /* RW-4R */
1185#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE 2:0 /* RWIVF */
1186#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x00000000 /* RWI-V */
1187#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ 6:4 /* RWIVF */
1188#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x00000000 /* RWI-V */
1189#define NV_PGRAPH_FFINTFC_ST2 0x00400754 /* RW-4R */
1190#define NV_PGRAPH_FFINTFC_ST2_STATUS 0:0 /* RWIVF */
1191#define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x00000000 /* RWI-V */
1192#define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x00000001 /* RW--V */
1193#define NV_PGRAPH_FFINTFC_ST2_MTHD 11:1 /* RWIVF */
1194#define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x00000000 /* RWI-V */
1195#define NV_PGRAPH_FFINTFC_ST2_SUBCH 14:12 /* RWIVF */
1196#define NV_PGRAPH_FFINTFC_ST2_SUBCH_0 0x00000000 /* RWI-V */
1197#define NV_PGRAPH_FFINTFC_ST2_SUBCH_1 0x00000001 /* RW--V */
1198#define NV_PGRAPH_FFINTFC_ST2_SUBCH_2 0x00000002 /* RW--V */
1199#define NV_PGRAPH_FFINTFC_ST2_SUBCH_3 0x00000003 /* RW--V */
1200#define NV_PGRAPH_FFINTFC_ST2_SUBCH_4 0x00000004 /* RW--V */
1201#define NV_PGRAPH_FFINTFC_ST2_SUBCH_5 0x00000005 /* RW--V */
1202#define NV_PGRAPH_FFINTFC_ST2_SUBCH_6 0x00000006 /* RW--V */
1203#define NV_PGRAPH_FFINTFC_ST2_SUBCH_7 0x00000007 /* RW--V */
1204#define NV_PGRAPH_FFINTFC_ST2_CHID 18:15 /* RWIVF */
1205#define NV_PGRAPH_FFINTFC_ST2_CHID_0 0x00000000 /* RWI-V */
1206#define NV_PGRAPH_FFINTFC_ST2_CHID_1 0x00000001 /* RW--V */
1207#define NV_PGRAPH_FFINTFC_ST2_CHID_2 0x00000002 /* RW--V */
1208#define NV_PGRAPH_FFINTFC_ST2_CHID_3 0x00000003 /* RW--V */
1209#define NV_PGRAPH_FFINTFC_ST2_CHID_4 0x00000004 /* RW--V */
1210#define NV_PGRAPH_FFINTFC_ST2_CHID_5 0x00000005 /* RW--V */
1211#define NV_PGRAPH_FFINTFC_ST2_CHID_6 0x00000006 /* RW--V */
1212#define NV_PGRAPH_FFINTFC_ST2_CHID_7 0x00000007 /* RW--V */
1213#define NV_PGRAPH_FFINTFC_ST2_CHID_8 0x00000008 /* RW--V */
1214#define NV_PGRAPH_FFINTFC_ST2_CHID_9 0x00000009 /* RW--V */
1215#define NV_PGRAPH_FFINTFC_ST2_CHID_10 0x0000000A /* RW--V */
1216#define NV_PGRAPH_FFINTFC_ST2_CHID_11 0x0000000B /* RW--V */
1217#define NV_PGRAPH_FFINTFC_ST2_CHID_12 0x0000000C /* RW--V */
1218#define NV_PGRAPH_FFINTFC_ST2_CHID_13 0x0000000D /* RW--V */
1219#define NV_PGRAPH_FFINTFC_ST2_CHID_14 0x0000000E /* RW--V */
1220#define NV_PGRAPH_FFINTFC_ST2_CHID_15 0x0000000F /* RW--V */
1221#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS 19:19 /* RWIVF */
1222#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x00000000 /* RWI-V */
1223#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x00000001 /* RW--V */
1224#define NV_PGRAPH_FFINTFC_ST2_D 0x00400758 /* RW-4R */
1225#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT 31:0 /* RWIVF */
1226#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x00000000 /* RWI-V */
1227#define NV_PGRAPH_STATUS 0x00400700 /* R--4R */
1228#define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */
1229#define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */
1230#define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */
1231#define NV_PGRAPH_STATUS_XY_LOGIC 4:4 /* R-IVF */
1232#define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */
1233#define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */
1234#define NV_PGRAPH_STATUS_FE 5:5 /* R-IVF */
1235#define NV_PGRAPH_STATUS_FE_IDLE 0x00000000 /* R-I-V */
1236#define NV_PGRAPH_STATUS_FE_BUSY 0x00000001 /* R---V */
1237#define NV_PGRAPH_STATUS_RASTERIZER 6:6 /* R-IVF */
1238#define NV_PGRAPH_STATUS_RASTERIZER_IDLE 0x00000000 /* R-I-V */
1239#define NV_PGRAPH_STATUS_RASTERIZER_BUSY 0x00000001 /* R---V */
1240#define NV_PGRAPH_STATUS_PORT_NOTIFY 8:8 /* R-IVF */
1241#define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */
1242#define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */
1243#define NV_PGRAPH_STATUS_PORT_REGISTER 12:12 /* R-IVF */
1244#define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x00000000 /* R-I-V */
1245#define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x00000001 /* R---V */
1246#define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */
1247#define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */
1248#define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */
1249#define NV_PGRAPH_STATUS_DMA_ENGINE 17:17 /* R-IVF */
1250#define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 /* R-I-V */
1251#define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00000001 /* R---V */
1252#define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */
1253#define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */
1254#define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */
1255#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21:21 /* R-IVF */
1256#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 /* R-I-V */
1257#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00000001 /* R---V */
1258#define NV_PGRAPH_STATUS_D3D 24:24 /* R-IVF */
1259#define NV_PGRAPH_STATUS_D3D_IDLE 0x00000000 /* R-I-V */
1260#define NV_PGRAPH_STATUS_D3D_BUSY 0x00000001 /* R---V */
1261#define NV_PGRAPH_STATUS_CACHE 25:25 /* R-IVF */
1262#define NV_PGRAPH_STATUS_CACHE_IDLE 0x00000000 /* R-I-V */
1263#define NV_PGRAPH_STATUS_CACHE_BUSY 0x00000001 /* R---V */
1264#define NV_PGRAPH_STATUS_LIGHTING 26:26 /* R-IVF */
1265#define NV_PGRAPH_STATUS_LIGHTING_IDLE 0x00000000 /* R-I-V */
1266#define NV_PGRAPH_STATUS_LIGHTING_BUSY 0x00000001 /* R---V */
1267#define NV_PGRAPH_STATUS_PREROP 27:27 /* R-IVF */
1268#define NV_PGRAPH_STATUS_PREROP_IDLE 0x00000000 /* R-I-V */
1269#define NV_PGRAPH_STATUS_PREROP_BUSY 0x00000001 /* R---V */
1270#define NV_PGRAPH_STATUS_ROP 28:28 /* R-IVF */
1271#define NV_PGRAPH_STATUS_ROP_IDLE 0x00000000 /* R-I-V */
1272#define NV_PGRAPH_STATUS_ROP_BUSY 0x00000001 /* R---V */
1273#define NV_PGRAPH_STATUS_PORT_USER 29:29 /* R-IVF */
1274#define NV_PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 /* R-I-V */
1275#define NV_PGRAPH_STATUS_PORT_USER_BUSY 0x00000001 /* R---V */
1276#define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */
1277#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 /* R-XUF */
1278#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 15:13 /* R-XUF */
1279#define NV_PGRAPH_TRAPPED_ADDR_CHID 27:24 /* R-XUF */
1280#define NV_PGRAPH_TRAPPED_DATA 0x00400708 /* R--4R */
1281#define NV_PGRAPH_TRAPPED_DATA_VALUE 31:0 /* R-XVF */
1282#define NV_PGRAPH_SURFACE 0x0040070C /* RW-4R */
1283#define NV_PGRAPH_SURFACE_TYPE 1:0 /* RWIVF */
1284#define NV_PGRAPH_SURFACE_TYPE_INVALID 0x00000000 /* RWI-V */
1285#define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x00000001 /* RW--V */
1286#define NV_PGRAPH_SURFACE_TYPE_SWIZZLE 0x00000002 /* RW--V */
1287#define NV_PGRAPH_NOTIFY 0x00400714 /* RW-4R */
1288#define NV_PGRAPH_NOTIFY_BUFFER_REQ 0:0 /* RWIVF */
1289#define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x00000000 /* RWI-V */
1290#define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x00000001 /* RW--V */
1291#define NV_PGRAPH_NOTIFY_BUFFER_STYLE 8:8 /* RWIVF */
1292#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */
1293#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */
1294#define NV_PGRAPH_NOTIFY_REQ 16:16 /* RWIVF */
1295#define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x00000000 /* RWI-V */
1296#define NV_PGRAPH_NOTIFY_REQ_PENDING 0x00000001 /* RW--V */
1297#define NV_PGRAPH_NOTIFY_STYLE 20:20 /* RWIVF */
1298#define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */
1299#define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */
1300#define NV_PGRAPH_BOFFSET(i) (0x00400640+(i)*4) /* RW-4A */
1301#define NV_PGRAPH_BOFFSET__SIZE_1 6 /* */
1302#define NV_PGRAPH_BOFFSET_LINADRS 23:0 /* RWIUF */
1303#define NV_PGRAPH_BOFFSET_LINADRS_0 0x00000000 /* RWI-V */
1304#define NV_PGRAPH_BOFFSET0 0x00400640 /* RW-4R */
1305#define NV_PGRAPH_BOFFSET0__ALIAS_1 NV_PGRAPH_BOFFSET(0) /* */
1306#define NV_PGRAPH_BOFFSET0_LINADRS 23:0 /* RWIUF */
1307#define NV_PGRAPH_BOFFSET0_LINADRS_0 0x00000000 /* RWI-V */
1308#define NV_PGRAPH_BOFFSET1 0x00400644 /* RW-4R */
1309#define NV_PGRAPH_BOFFSET1__ALIAS_1 NV_PGRAPH_BOFFSET(1) /* */
1310#define NV_PGRAPH_BOFFSET1_LINADRS 23:0 /* RWIUF */
1311#define NV_PGRAPH_BOFFSET1_LINADRS_0 0x00000000 /* RWI-V */
1312#define NV_PGRAPH_BOFFSET2 0x00400648 /* RW-4R */
1313#define NV_PGRAPH_BOFFSET2__ALIAS_1 NV_PGRAPH_BOFFSET(2) /* */
1314#define NV_PGRAPH_BOFFSET2_LINADRS 23:0 /* RWIUF */
1315#define NV_PGRAPH_BOFFSET2_LINADRS_0 0x00000000 /* RWI-V */
1316#define NV_PGRAPH_BOFFSET3 0x0040064C /* RW-4R */
1317#define NV_PGRAPH_BOFFSET3__ALIAS_1 NV_PGRAPH_BOFFSET(3) /* */
1318#define NV_PGRAPH_BOFFSET3_LINADRS 23:0 /* RWIUF */
1319#define NV_PGRAPH_BOFFSET3_LINADRS_0 0x00000000 /* RWI-V */
1320#define NV_PGRAPH_BOFFSET4 0x00400650 /* RW-4R */
1321#define NV_PGRAPH_BOFFSET4__ALIAS_1 NV_PGRAPH_BOFFSET(4) /* */
1322#define NV_PGRAPH_BOFFSET4_LINADRS 23:0 /* RWIUF */
1323#define NV_PGRAPH_BOFFSET4_LINADRS_0 0x00000000 /* RWI-V */
1324#define NV_PGRAPH_BOFFSET5 0x00400654 /* RW-4R */
1325#define NV_PGRAPH_BOFFSET5__ALIAS_1 NV_PGRAPH_BOFFSET(5) /* */
1326#define NV_PGRAPH_BOFFSET5_LINADRS 23:0 /* RWIUF */
1327#define NV_PGRAPH_BOFFSET5_LINADRS_0 0x00000000 /* RWI-V */
1328#define NV_PGRAPH_BBASE(i) (0x00400658+(i)*4) /* RW-4A */
1329#define NV_PGRAPH_BBASE__SIZE_1 6 /* */
1330#define NV_PGRAPH_BBASE_LINADRS 23:0 /* RWIUF */
1331#define NV_PGRAPH_BBASE_LINADRS_0 0x00000000 /* RWI-V */
1332#define NV_PGRAPH_BBASE0 0x00400658 /* RW-4R */
1333#define NV_PGRAPH_BBASE0__ALIAS_1 NV_PGRAPH_BBASE(0) /* */
1334#define NV_PGRAPH_BBASE0_LINADRS 23:0 /* RWIUF */
1335#define NV_PGRAPH_BBASE0_LINADRS_0 0x00000000 /* RWI-V */
1336#define NV_PGRAPH_BBASE1 0x0040065c /* RW-4R */
1337#define NV_PGRAPH_BBASE1__ALIAS_1 NV_PGRAPH_BBASE(1) /* */
1338#define NV_PGRAPH_BBASE1_LINADRS 23:0 /* RWIUF */
1339#define NV_PGRAPH_BBASE1_LINADRS_0 0x00000000 /* RWI-V */
1340#define NV_PGRAPH_BBASE2 0x00400660 /* RW-4R */
1341#define NV_PGRAPH_BBASE2__ALIAS_1 NV_PGRAPH_BBASE(2) /* */
1342#define NV_PGRAPH_BBASE2_LINADRS 23:0 /* RWIUF */
1343#define NV_PGRAPH_BBASE2_LINADRS_0 0x00000000 /* RWI-V */
1344#define NV_PGRAPH_BBASE3 0x00400664 /* RW-4R */
1345#define NV_PGRAPH_BBASE3__ALIAS_1 NV_PGRAPH_BBASE(3) /* */
1346#define NV_PGRAPH_BBASE3_LINADRS 23:0 /* RWIUF */
1347#define NV_PGRAPH_BBASE3_LINADRS_0 0x00000000 /* RWI-V */
1348#define NV_PGRAPH_BBASE4 0x00400668 /* RW-4R */
1349#define NV_PGRAPH_BBASE4__ALIAS_1 NV_PGRAPH_BBASE(4) /* */
1350#define NV_PGRAPH_BBASE4_LINADRS 23:0 /* RWIUF */
1351#define NV_PGRAPH_BBASE4_LINADRS_0 0x00000000 /* RWI-V */
1352#define NV_PGRAPH_BBASE5 0x0040066C /* RW-4R */
1353#define NV_PGRAPH_BBASE5__ALIAS_1 NV_PGRAPH_BBASE(5) /* */
1354#define NV_PGRAPH_BBASE5_LINADRS 23:0 /* RWIUF */
1355#define NV_PGRAPH_BBASE5_LINADRS_0 0x00000000 /* RWI-V */
1356#define NV_PGRAPH_BPITCH(i) (0x00400670+(i)*4) /* RW-4A */
1357#define NV_PGRAPH_BPITCH__SIZE_1 5 /* */
1358#define NV_PGRAPH_BPITCH_VALUE 12:0 /* RWIUF */
1359#define NV_PGRAPH_BPITCH_VALUE_0 0x00000000 /* RWI-V */
1360#define NV_PGRAPH_BPITCH0 0x00400670 /* RW-4R */
1361#define NV_PGRAPH_BPITCH0__ALIAS_1 NV_PGRAPH_BPITCH(0) /* */
1362#define NV_PGRAPH_BPITCH0_VALUE 12:0 /* RWIUF */
1363#define NV_PGRAPH_BPITCH0_VALUE_0 0x00000000 /* RWI-V */
1364#define NV_PGRAPH_BPITCH1 0x00400674 /* RW-4R */
1365#define NV_PGRAPH_BPITCH1__ALIAS_1 NV_PGRAPH_BPITCH(1) /* */
1366#define NV_PGRAPH_BPITCH1_VALUE 12:0 /* RWIUF */
1367#define NV_PGRAPH_BPITCH1_VALUE_0 0x00000000 /* RWI-V */
1368#define NV_PGRAPH_BPITCH2 0x00400678 /* RW-4R */
1369#define NV_PGRAPH_BPITCH2__ALIAS_1 NV_PGRAPH_BPITCH(2) /* */
1370#define NV_PGRAPH_BPITCH2_VALUE 12:0 /* RWIUF */
1371#define NV_PGRAPH_BPITCH2_VALUE_0 0x00000000 /* RWI-V */
1372#define NV_PGRAPH_BPITCH3 0x0040067C /* RW-4R */
1373#define NV_PGRAPH_BPITCH3__ALIAS_1 NV_PGRAPH_BPITCH(3) /* */
1374#define NV_PGRAPH_BPITCH3_VALUE 12:0 /* RWIUF */
1375#define NV_PGRAPH_BPITCH3_VALUE_0 0x00000000 /* RWI-V */
1376#define NV_PGRAPH_BPITCH4 0x00400680 /* RW-4R */
1377#define NV_PGRAPH_BPITCH4__ALIAS_1 NV_PGRAPH_BPITCH(4) /* */
1378#define NV_PGRAPH_BPITCH4_VALUE 12:0 /* RWIUF */
1379#define NV_PGRAPH_BPITCH4_VALUE_0 0x00000000 /* RWI-V */
1380#define NV_PGRAPH_BLIMIT(i) (0x00400684+(i)*4) /* RW-4A */
1381#define NV_PGRAPH_BLIMIT__SIZE_1 6 /* */
1382#define NV_PGRAPH_BLIMIT_VALUE 23:0 /* RWXUF */
1383#define NV_PGRAPH_BLIMIT_TYPE 31:31 /* RWIVF */
1384#define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x00000000 /* RW--V */
1385#define NV_PGRAPH_BLIMIT_TYPE_NULL 0x00000001 /* RWI-V */
1386#define NV_PGRAPH_BLIMIT0 0x00400684 /* RW-4R */
1387#define NV_PGRAPH_BLIMIT0__ALIAS_1 NV_PGRAPH_BLIMIT(0) /* */
1388#define NV_PGRAPH_BLIMIT0_VALUE 23:0 /* RWXUF */
1389#define NV_PGRAPH_BLIMIT0_TYPE 31:31 /* RWIVF */
1390#define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY 0x00000000 /* RW--V */
1391#define NV_PGRAPH_BLIMIT0_TYPE_NULL 0x00000001 /* RWI-V */
1392#define NV_PGRAPH_BLIMIT1 0x00400688 /* RW-4R */
1393#define NV_PGRAPH_BLIMIT1__ALIAS_1 NV_PGRAPH_BLIMIT(1) /* */
1394#define NV_PGRAPH_BLIMIT1_VALUE 23:0 /* RWXUF */
1395#define NV_PGRAPH_BLIMIT1_TYPE 31:31 /* RWIVF */
1396#define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY 0x00000000 /* RW--V */
1397#define NV_PGRAPH_BLIMIT1_TYPE_NULL 0x00000001 /* RWI-V */
1398#define NV_PGRAPH_BLIMIT2 0x0040068c /* RW-4R */
1399#define NV_PGRAPH_BLIMIT2__ALIAS_1 NV_PGRAPH_BLIMIT(2) /* */
1400#define NV_PGRAPH_BLIMIT2_VALUE 23:0 /* RWXUF */
1401#define NV_PGRAPH_BLIMIT2_TYPE 31:31 /* RWIVF */
1402#define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY 0x00000000 /* RW--V */
1403#define NV_PGRAPH_BLIMIT2_TYPE_NULL 0x00000001 /* RWI-V */
1404#define NV_PGRAPH_BLIMIT3 0x00400690 /* RW-4R */
1405#define NV_PGRAPH_BLIMIT3__ALIAS_1 NV_PGRAPH_BLIMIT(3) /* */
1406#define NV_PGRAPH_BLIMIT3_VALUE 23:0 /* RWXUF */
1407#define NV_PGRAPH_BLIMIT3_TYPE 31:31 /* RWIVF */
1408#define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY 0x00000000 /* RW--V */
1409#define NV_PGRAPH_BLIMIT3_TYPE_NULL 0x00000001 /* RWI-V */
1410#define NV_PGRAPH_BLIMIT4 0x00400694 /* RW-4R */
1411#define NV_PGRAPH_BLIMIT4__ALIAS_1 NV_PGRAPH_BLIMIT(4) /* */
1412#define NV_PGRAPH_BLIMIT4_VALUE 23:0 /* RWXUF */
1413#define NV_PGRAPH_BLIMIT4_TYPE 31:31 /* RWIVF */
1414#define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY 0x00000000 /* RW--V */
1415#define NV_PGRAPH_BLIMIT4_TYPE_NULL 0x00000001 /* RWI-V */
1416#define NV_PGRAPH_BLIMIT5 0x00400698 /* RW-4R */
1417#define NV_PGRAPH_BLIMIT5__ALIAS_1 NV_PGRAPH_BLIMIT(5) /* */
1418#define NV_PGRAPH_BLIMIT5_VALUE 23:0 /* RWXUF */
1419#define NV_PGRAPH_BLIMIT5_TYPE 31:31 /* RWIVF */
1420#define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY 0x00000000 /* RW--V */
1421#define NV_PGRAPH_BLIMIT5_TYPE_NULL 0x00000001 /* RWI-V */
1422#define NV_PGRAPH_BSWIZZLE2 0x0040069c /* RW-4R */
1423#define NV_PGRAPH_BSWIZZLE2_WIDTH 19:16 /* RWIUF */
1424#define NV_PGRAPH_BSWIZZLE2_WIDTH_0 0x00000000 /* RWI-V */
1425#define NV_PGRAPH_BSWIZZLE2_HEIGHT 27:24 /* RWIUF */
1426#define NV_PGRAPH_BSWIZZLE2_HEIGHT_0 0x00000000 /* RWI-V */
1427#define NV_PGRAPH_BSWIZZLE5 0x004006a0 /* RW-4R */
1428#define NV_PGRAPH_BSWIZZLE5_WIDTH 19:16 /* RWIUF */
1429#define NV_PGRAPH_BSWIZZLE5_WIDTH_0 0x00000000 /* RWI-V */
1430#define NV_PGRAPH_BSWIZZLE5_HEIGHT 27:24 /* RWIUF */
1431#define NV_PGRAPH_BSWIZZLE5_HEIGHT_0 0x00000000 /* RWI-V */
1432#define NV_PGRAPH_BPIXEL 0x00400724 /* RW-4R */
1433#define NV_PGRAPH_BPIXEL_DEPTH0 3:0 /* RWIVF */
1434#define NV_PGRAPH_BPIXEL_DEPTH0_INVALID 0x00000000 /* RWI-V */
1435#define NV_PGRAPH_BPIXEL_DEPTH0_Y8 0x00000001 /* RW--V */
1436#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
1437#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
1438#define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5 0x00000004 /* RW--V */
1439#define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5 0x00000005 /* RW--V */
1440#define NV_PGRAPH_BPIXEL_DEPTH0_Y16 0x00000006 /* RW--V */
1441#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
1442#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
1443#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
1444#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
1445#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
1446#define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8 0x0000000c /* RW--V */
1447#define NV_PGRAPH_BPIXEL_DEPTH0_Y32 0x0000000d /* RW--V */
1448#define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8 0x0000000e /* RW--V */
1449#define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8 0x0000000f /* RW--V */
1450#define NV_PGRAPH_BPIXEL_DEPTH1 7:4 /* RWIVF */
1451#define NV_PGRAPH_BPIXEL_DEPTH1_INVALID 0x00000000 /* RWI-V */
1452#define NV_PGRAPH_BPIXEL_DEPTH1_Y8 0x00000001 /* RW--V */
1453#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
1454#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
1455#define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5 0x00000004 /* RW--V */
1456#define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5 0x00000005 /* RW--V */
1457#define NV_PGRAPH_BPIXEL_DEPTH1_Y16 0x00000006 /* RW--V */
1458#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
1459#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
1460#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
1461#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
1462#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
1463#define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8 0x0000000c /* RW--V */
1464#define NV_PGRAPH_BPIXEL_DEPTH1_Y32 0x0000000d /* RW--V */
1465#define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8 0x0000000e /* RW--V */
1466#define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8 0x0000000f /* RW--V */
1467#define NV_PGRAPH_BPIXEL_DEPTH2 11:8 /* RWIVF */
1468#define NV_PGRAPH_BPIXEL_DEPTH2_INVALID 0x00000000 /* RWI-V */
1469#define NV_PGRAPH_BPIXEL_DEPTH2_Y8 0x00000001 /* RW--V */
1470#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
1471#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
1472#define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5 0x00000004 /* RW--V */
1473#define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5 0x00000005 /* RW--V */
1474#define NV_PGRAPH_BPIXEL_DEPTH2_Y16 0x00000006 /* RW--V */
1475#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
1476#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
1477#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
1478#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
1479#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
1480#define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8 0x0000000c /* RW--V */
1481#define NV_PGRAPH_BPIXEL_DEPTH2_Y32 0x0000000d /* RW--V */
1482#define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8 0x0000000e /* RW--V */
1483#define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8 0x0000000f /* RW--V */
1484#define NV_PGRAPH_BPIXEL_DEPTH3 15:12 /* RWIVF */
1485#define NV_PGRAPH_BPIXEL_DEPTH3_INVALID 0x00000000 /* RWI-V */
1486#define NV_PGRAPH_BPIXEL_DEPTH3_Y8 0x00000001 /* RW--V */
1487#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
1488#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
1489#define NV_PGRAPH_BPIXEL_DEPTH3_A1R5G5B5 0x00000004 /* RW--V */
1490#define NV_PGRAPH_BPIXEL_DEPTH3_R5G6B5 0x00000005 /* RW--V */
1491#define NV_PGRAPH_BPIXEL_DEPTH3_Y16 0x00000006 /* RW--V */
1492#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
1493#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
1494#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
1495#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
1496#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
1497#define NV_PGRAPH_BPIXEL_DEPTH3_A8R8G8B8 0x0000000c /* RW--V */
1498#define NV_PGRAPH_BPIXEL_DEPTH3_Y32 0x0000000d /* RW--V */
1499#define NV_PGRAPH_BPIXEL_DEPTH3_V8YB8U8YA8 0x0000000e /* RW--V */
1500#define NV_PGRAPH_BPIXEL_DEPTH3_YB8V8YA8U8 0x0000000f /* RW--V */
1501#define NV_PGRAPH_BPIXEL_DEPTH4 19:16 /* RWIVF */
1502#define NV_PGRAPH_BPIXEL_DEPTH4_INVALID 0x00000000 /* RWI-V */
1503#define NV_PGRAPH_BPIXEL_DEPTH4_Y8 0x00000001 /* RW--V */
1504#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
1505#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
1506#define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5 0x00000004 /* RW--V */
1507#define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5 0x00000005 /* RW--V */
1508#define NV_PGRAPH_BPIXEL_DEPTH4_Y16 0x00000006 /* RW--V */
1509#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
1510#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
1511#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
1512#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
1513#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
1514#define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8 0x0000000c /* RW--V */
1515#define NV_PGRAPH_BPIXEL_DEPTH4_Y32 0x0000000d /* RW--V */
1516#define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8 0x0000000e /* RW--V */
1517#define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8 0x0000000f /* RW--V */
1518#define NV_PGRAPH_BPIXEL_DEPTH5 23:20 /* RWIVF */
1519#define NV_PGRAPH_BPIXEL_DEPTH5_INVALID 0x00000000 /* RWI-V */
1520#define NV_PGRAPH_BPIXEL_DEPTH5_Y8 0x00000001 /* RW--V */
1521#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
1522#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
1523#define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5 0x00000004 /* RW--V */
1524#define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5 0x00000005 /* RW--V */
1525#define NV_PGRAPH_BPIXEL_DEPTH5_Y16 0x00000006 /* RW--V */
1526#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
1527#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
1528#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
1529#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
1530#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
1531#define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8 0x0000000c /* RW--V */
1532#define NV_PGRAPH_BPIXEL_DEPTH5_Y32 0x0000000d /* RW--V */
1533#define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8 0x0000000e /* RW--V */
1534#define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8 0x0000000f /* RW--V */
1535#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 /* RW-4R */
1536#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS 23:0 /* RWIVF */
1537#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x00000000 /* RWI-V */
1538#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT 29:29 /* RWIVF */
1539#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x00000000 /* RWI-V */
1540#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x00000001 /* RW--V */
1541#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30:30 /* RWIVF */
1542#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x00000000 /* RWI-V */
1543#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x00000001 /* RW--V */
1544#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31:31 /* RWIVF */
1545#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */
1546#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x00000001 /* RW--V */
1547#define NV_PGRAPH_LIMIT_VIOL_Z 0x00400614 /* RW-4R */
1548#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS 23:0 /* RWIVF */
1549#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x00000000 /* RWI-V */
1550#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT 30:30 /* RWIVF */
1551#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x00000000 /* RWI-V */
1552#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x00000001 /* RW--V */
1553#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31:31 /* RWIVF */
1554#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */
1555#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x00000001 /* RW--V */
1556#define NV_PGRAPH_STATE 0x00400710 /* RW-4R */
1557#define NV_PGRAPH_STATE_BUFFER_0 0:0 /* RWIVF */
1558#define NV_PGRAPH_STATE_BUFFER_0_INVALID 0x00000000 /* RWI-V */
1559#define NV_PGRAPH_STATE_BUFFER_0_VALID 0x00000001 /* RW--V */
1560#define NV_PGRAPH_STATE_BUFFER_1 1:1 /* RWIVF */
1561#define NV_PGRAPH_STATE_BUFFER_1_INVALID 0x00000000 /* RWI-V */
1562#define NV_PGRAPH_STATE_BUFFER_1_VALID 0x00000001 /* RW--V */
1563#define NV_PGRAPH_STATE_BUFFER_2 2:2 /* RWIVF */
1564#define NV_PGRAPH_STATE_BUFFER_2_INVALID 0x00000000 /* RWI-V */
1565#define NV_PGRAPH_STATE_BUFFER_2_VALID 0x00000001 /* RW--V */
1566#define NV_PGRAPH_STATE_BUFFER_3 3:3 /* RWIVF */
1567#define NV_PGRAPH_STATE_BUFFER_3_INVALID 0x00000000 /* RWI-V */
1568#define NV_PGRAPH_STATE_BUFFER_3_VALID 0x00000001 /* RW--V */
1569#define NV_PGRAPH_STATE_BUFFER_4 4:4 /* RWIVF */
1570#define NV_PGRAPH_STATE_BUFFER_4_INVALID 0x00000000 /* RWI-V */
1571#define NV_PGRAPH_STATE_BUFFER_4_VALID 0x00000001 /* RW--V */
1572#define NV_PGRAPH_STATE_BUFFER_5 5:5 /* RWIVF */
1573#define NV_PGRAPH_STATE_BUFFER_5_INVALID 0x00000000 /* RWI-V */
1574#define NV_PGRAPH_STATE_BUFFER_5_VALID 0x00000001 /* RW--V */
1575#define NV_PGRAPH_STATE_PITCH_0 8:8 /* RWIVF */
1576#define NV_PGRAPH_STATE_PITCH_0_INVALID 0x00000000 /* RWI-V */
1577#define NV_PGRAPH_STATE_PITCH_0_VALID 0x00000001 /* RW--V */
1578#define NV_PGRAPH_STATE_PITCH_1 9:9 /* RWIVF */
1579#define NV_PGRAPH_STATE_PITCH_1_INVALID 0x00000000 /* RWI-V */
1580#define NV_PGRAPH_STATE_PITCH_1_VALID 0x00000001 /* RW--V */
1581#define NV_PGRAPH_STATE_PITCH_2 10:10 /* RWIVF */
1582#define NV_PGRAPH_STATE_PITCH_2_INVALID 0x00000000 /* RWI-V */
1583#define NV_PGRAPH_STATE_PITCH_2_VALID 0x00000001 /* RW--V */
1584#define NV_PGRAPH_STATE_PITCH_3 11:11 /* RWIVF */
1585#define NV_PGRAPH_STATE_PITCH_3_INVALID 0x00000000 /* RWI-V */
1586#define NV_PGRAPH_STATE_PITCH_3_VALID 0x00000001 /* RW--V */
1587#define NV_PGRAPH_STATE_PITCH_4 12:12 /* RWIVF */
1588#define NV_PGRAPH_STATE_PITCH_4_INVALID 0x00000000 /* RWI-V */
1589#define NV_PGRAPH_STATE_PITCH_4_VALID 0x00000001 /* RW--V */
1590#define NV_PGRAPH_STATE_CHROMA_COLOR 16:16 /* RWIVF */
1591#define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x00000000 /* RWI-V */
1592#define NV_PGRAPH_STATE_CHROMA_COLOR_VALID 0x00000001 /* RW--V */
1593#define NV_PGRAPH_STATE_CHROMA_COLORFMT 17:17 /* RWIVF */
1594#define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x00000000 /* RWI-V */
1595#define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x00000001 /* RW--V */
1596#define NV_PGRAPH_STATE_CPATTERN_COLORFMT 20:20 /* RWIVF */
1597#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x00000000 /* RWI-V */
1598#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x00000001 /* RW--V */
1599#define NV_PGRAPH_STATE_CPATTERN_MONOFMT 21:21 /* RWIVF */
1600#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x00000000 /* RWI-V */
1601#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x00000001 /* RW--V */
1602#define NV_PGRAPH_STATE_CPATTERN_SELECT 22:22 /* RWIVF */
1603#define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x00000000 /* RWI-V */
1604#define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x00000001 /* RW--V */
1605#define NV_PGRAPH_STATE_PATTERN_COLOR0 24:24 /* RWIVF */
1606#define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x00000000 /* RWI-V */
1607#define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x00000001 /* RW--V */
1608#define NV_PGRAPH_STATE_PATTERN_COLOR1 25:25 /* RWIVF */
1609#define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x00000000 /* RWI-V */
1610#define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x00000001 /* RW--V */
1611#define NV_PGRAPH_STATE_PATTERN_PATT0 26:26 /* RWIVF */
1612#define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x00000000 /* RWI-V */
1613#define NV_PGRAPH_STATE_PATTERN_PATT0_VALID 0x00000001 /* RW--V */
1614#define NV_PGRAPH_STATE_PATTERN_PATT1 27:27 /* RWIVF */
1615#define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x00000000 /* RWI-V */
1616#define NV_PGRAPH_STATE_PATTERN_PATT1_VALID 0x00000001 /* RW--V */
1617#define NV_PGRAPH_CACHE_INDEX 0x00400728 /* RW-4R */
1618#define NV_PGRAPH_CACHE_INDEX_BANK 2:2 /* RWXVF */
1619#define NV_PGRAPH_CACHE_INDEX_BANK_10 0x00000000 /* RW--V */
1620#define NV_PGRAPH_CACHE_INDEX_BANK_32 0x00000001 /* RW--V */
1621#define NV_PGRAPH_CACHE_INDEX_ADRS 12:3 /* RWXVF */
1622#define NV_PGRAPH_CACHE_INDEX_ADRS_0 0x00000000 /* RW--V */
1623#define NV_PGRAPH_CACHE_INDEX_ADRS_1024 0x00000400 /* RW--V */
1624#define NV_PGRAPH_CACHE_INDEX_OP 14:13 /* RWXVF */
1625#define NV_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x00000000 /* RW--V */
1626#define NV_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x00000001 /* RW--V */
1627#define NV_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x00000002 /* RW--V */
1628#define NV_PGRAPH_CACHE_RAM 0x0040072c /* RW-4R */
1629#define NV_PGRAPH_CACHE_RAM_VALUE 31:0 /* RWXVF */
1630#define NV_PGRAPH_DMA_PITCH 0x00400760 /* RW-4R */
1631#define NV_PGRAPH_DMA_PITCH_S0 15:0 /* RWXSF */
1632#define NV_PGRAPH_DMA_PITCH_S1 31:16 /* RWXSF */
1633#define NV_PGRAPH_DVD_COLORFMT 0x00400764 /* RW-4R */
1634#define NV_PGRAPH_DVD_COLORFMT_IMAGE 5:0 /* RWNVF */
1635#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 /* RWN-V */
1636#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */
1637#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */
1638#define NV_PGRAPH_DVD_COLORFMT_OVLY 9:8 /* RWNVF */
1639#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 /* RWN-V */
1640#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 /* RW--V */
1641#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 /* RW--V */
1642#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 /* RW--V */
1643#define NV_PGRAPH_SCALED_FORMAT 0x00400768 /* RW-4R */
1644#define NV_PGRAPH_SCALED_FORMAT_ORIGIN 17:16 /* RWIVF */
1645#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x00000000 /* RWI-V */
1646#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* RW--V */
1647#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* RW--V */
1648#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24:24 /* RWIVF */
1649#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* RWI-V */
1650#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* RW--V */
1651#define NV_PGRAPH_PATT_COLOR0 0x00400800 /* RW-4R */
1652#define NV_PGRAPH_PATT_COLOR0_VALUE 31:0 /* RWXUF */
1653#define NV_PGRAPH_PATT_COLOR1 0x00400804 /* RW-4R */
1654#define NV_PGRAPH_PATT_COLOR1_VALUE 31:0 /* RWXUF */
1655#define NV_PGRAPH_PATT_COLORRAM(i) (0x00400900+(i)*4) /* R--4A */
1656#define NV_PGRAPH_PATT_COLORRAM__SIZE_1 64 /* */
1657#define NV_PGRAPH_PATT_COLORRAM_VALUE 23:0 /* R--UF */
1658#define NV_PGRAPH_PATTERN(i) (0x00400808+(i)*4) /* RW-4A */
1659#define NV_PGRAPH_PATTERN__SIZE_1 2 /* */
1660#define NV_PGRAPH_PATTERN_BITMAP 31:0 /* RWXVF */
1661#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 /* RW-4R */
1662#define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */
1663#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x00000000 /* RW--V */
1664#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x00000001 /* RW--V */
1665#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x00000002 /* RW--V */
1666#define NV_PGRAPH_PATTERN_SHAPE_SELECT 4:4 /* RWXVF */
1667#define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x00000000 /* RW--V */
1668#define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x00000001 /* RW--V */
1669#define NV_PGRAPH_MONO_COLOR0 0x00400600 /* RW-4R */
1670#define NV_PGRAPH_MONO_COLOR0_VALUE 31:0 /* RWXUF */
1671#define NV_PGRAPH_ROP3 0x00400604 /* RW-4R */
1672#define NV_PGRAPH_ROP3_VALUE 7:0 /* RWXVF */
1673#define NV_PGRAPH_CHROMA 0x00400814 /* RW-4R */
1674#define NV_PGRAPH_CHROMA_VALUE 31:0 /* RWXUF */
1675#define NV_PGRAPH_BETA_AND 0x00400608 /* RW-4R */
1676#define NV_PGRAPH_BETA_AND_VALUE_FRACTION 30:23 /* RWXUF */
1677#define NV_PGRAPH_BETA_PREMULT 0x0040060c /* RW-4R */
1678#define NV_PGRAPH_BETA_PREMULT_VALUE 31:0 /* RWXUF */
1679#define NV_PGRAPH_CONTROL0 0x00400818 /* RW-4R */
1680#define NV_PGRAPH_CONTROL1 0x0040081c /* RW-4R */
1681#define NV_PGRAPH_CONTROL2 0x00400820 /* RW-4R */
1682#define NV_PGRAPH_BLEND 0x00400824 /* RW-4R */
1683#define NV_PGRAPH_DPRAM_INDEX 0x00400828 /* RW-4R */
1684#define NV_PGRAPH_DPRAM_INDEX_ADRS 6:0 /* RWIVF */
1685#define NV_PGRAPH_DPRAM_INDEX_ADRS_0 0x00000000 /* RWI-V */
1686#define NV_PGRAPH_DPRAM_INDEX_SELECT 10:8 /* RWIVF */
1687#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x00000000 /* RWI-V */
1688#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x00000001 /* RW--V */
1689#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x00000002 /* RW--V */
1690#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x00000003 /* RW--V */
1691#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x00000004 /* RW--V */
1692#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x00000005 /* RW--V */
1693#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x00000006 /* RW--V */
1694#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x00000007 /* RW--V */
1695#define NV_PGRAPH_DPRAM_DATA 0x0040082c /* RW-4R */
1696#define NV_PGRAPH_DPRAM_DATA_VALUE 31:0 /* RWXVF */
1697#define NV_PGRAPH_DPRAM_ADRS_0 0x0040082c /* RW-4R */
1698#define NV_PGRAPH_DPRAM_ADRS_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
1699#define NV_PGRAPH_DPRAM_ADRS_0_VALUE 19:0 /* RWXVF */
1700#define NV_PGRAPH_DPRAM_ADRS_1 0x0040082c /* RW-4R */
1701#define NV_PGRAPH_DPRAM_ADRS_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
1702#define NV_PGRAPH_DPRAM_ADRS_1_VALUE 19:0 /* RWXVF */
1703#define NV_PGRAPH_DPRAM_DATA_0 0x0040082c /* RW-4R */
1704#define NV_PGRAPH_DPRAM_DATA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
1705#define NV_PGRAPH_DPRAM_DATA_0_VALUE 31:0 /* RWXVF */
1706#define NV_PGRAPH_DPRAM_DATA_1 0x0040082c /* RW-4R */
1707#define NV_PGRAPH_DPRAM_DATA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
1708#define NV_PGRAPH_DPRAM_DATA_1_VALUE 31:0 /* RWXVF */
1709#define NV_PGRAPH_DPRAM_WE_0 0x0040082c /* RW-4R */
1710#define NV_PGRAPH_DPRAM_WE_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
1711#define NV_PGRAPH_DPRAM_WE_0_VALUE 23:0 /* RWXVF */
1712#define NV_PGRAPH_DPRAM_WE_1 0x0040082c /* RW-4R */
1713#define NV_PGRAPH_DPRAM_WE_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
1714#define NV_PGRAPH_DPRAM_WE_1_VALUE 23:0 /* RWXVF */
1715#define NV_PGRAPH_DPRAM_ALPHA_0 0x0040082c /* RW-4R */
1716#define NV_PGRAPH_DPRAM_ALPHA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
1717#define NV_PGRAPH_DPRAM_ALPHA_0_VALUE 31:0 /* RWXVF */
1718#define NV_PGRAPH_DPRAM_ALPHA_1 0x0040082c /* RW-4R */
1719#define NV_PGRAPH_DPRAM_ALPHA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
1720#define NV_PGRAPH_DPRAM_ALPHA_1_VALUE 31:0 /* RWXVF */
1721#define NV_PGRAPH_STORED_FMT 0x00400830 /* RW-4R */
1722#define NV_PGRAPH_STORED_FMT_MONO0 5:0 /* RWXVF */
1723#define NV_PGRAPH_STORED_FMT_PATT0 13:8 /* RWXVF */
1724#define NV_PGRAPH_STORED_FMT_PATT1 21:16 /* RWXVF */
1725#define NV_PGRAPH_STORED_FMT_CHROMA 29:24 /* RWXVF */
1726#define NV_PGRAPH_FORMATS 0x00400618 /* RW-4R */
1727#define NV_PGRAPH_FORMATS_ROP 2:0 /* R-XVF */
1728#define NV_PGRAPH_FORMATS_ROP_Y8 0x00000000 /* -W--V */
1729#define NV_PGRAPH_FORMATS_ROP_RGB15 0x00000001 /* -W--V */
1730#define NV_PGRAPH_FORMATS_ROP_RGB16 0x00000002 /* -W--V */
1731#define NV_PGRAPH_FORMATS_ROP_Y16 0x00000003 /* -W--V */
1732#define NV_PGRAPH_FORMATS_ROP_INVALID 0x00000004 /* -W--V */
1733#define NV_PGRAPH_FORMATS_ROP_RGB24 0x00000005 /* -W--V */
1734#define NV_PGRAPH_FORMATS_ROP_RGB30 0x00000006 /* -W--V */
1735#define NV_PGRAPH_FORMATS_ROP_Y32 0x00000007 /* -W--V */
1736#define NV_PGRAPH_FORMATS_SRC 9:4 /* R-XVF */
1737#define NV_PGRAPH_FORMATS_SRC_INVALID 0x00000000 /* RW--V */
1738#define NV_PGRAPH_FORMATS_SRC_LE_Y8 0x00000001 /* RW--V */
1739#define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x00000002 /* RW--V */
1740#define NV_PGRAPH_FORMATS_SRC_LE_X24Y8 0x00000003 /* RW--V */
1741#define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x00000006 /* RW--V */
1742#define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x00000007 /* RW--V */
1743#define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x00000008 /* RW--V */
1744#define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x00000009 /* RW--V */
1745#define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5 0x0000000A /* RW--V */
1746#define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0x0000000B /* RW--V */
1747#define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0x0000000C /* RW--V */
1748#define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0x0000000D /* RW--V */
1749#define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0x0000000E /* RW--V */
1750#define NV_PGRAPH_FORMATS_SRC_LE_Y16 0x0000000F /* RW--V */
1751#define NV_PGRAPH_FORMATS_SRC_LE_A16Y16 0x00000010 /* RW--V */
1752#define NV_PGRAPH_FORMATS_SRC_LE_X16Y16 0x00000011 /* RW--V */
1753#define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x00000012 /* RW--V */
1754#define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x00000013 /* RW--V */
1755#define NV_PGRAPH_FORMATS_SRC_LE_Y32 0x00000014 /* RW--V */
1756#define NV_PGRAPH_FORMATS_FB 15:12 /* R-XVF */
1757#define NV_PGRAPH_FORMATS_FB_INVALID 0x00000000 /* RWI-V */
1758#define NV_PGRAPH_FORMATS_FB_Y8 0x00000001 /* RW--V */
1759#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
1760#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
1761#define NV_PGRAPH_FORMATS_FB_A1R5G5B5 0x00000004 /* RW--V */
1762#define NV_PGRAPH_FORMATS_FB_R5G6B5 0x00000005 /* RW--V */
1763#define NV_PGRAPH_FORMATS_FB_Y16 0x00000006 /* RW--V */
1764#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
1765#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
1766#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
1767#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
1768#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
1769#define NV_PGRAPH_FORMATS_FB_A8R8G8B8 0x0000000c /* RW--V */
1770#define NV_PGRAPH_FORMATS_FB_Y32 0x0000000d /* RW--V */
1771#define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8 0x0000000e /* RW--V */
1772#define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8 0x0000000f /* RW--V */
1773#define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */
1774#define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */
1775#define NV_PGRAPH_ABS_X_RAM_VALUE 31:0 /* RWXUF */
1776#define NV_PGRAPH_X_RAM_BPORT(i) (0x00400c00+(i)*4) /* R--4A */
1777#define NV_PGRAPH_X_RAM_BPORT__SIZE_1 32 /* */
1778#define NV_PGRAPH_X_RAM_BPORT_VALUE 31:0 /* R--UF */
1779#define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */
1780#define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */
1781#define NV_PGRAPH_ABS_Y_RAM_VALUE 31:0 /* RWXUF */
1782#define NV_PGRAPH_Y_RAM_BPORT(i) (0x00400c80+(i)*4) /* R--4A */
1783#define NV_PGRAPH_Y_RAM_BPORT__SIZE_1 32 /* */
1784#define NV_PGRAPH_Y_RAM_BPORT_VALUE 31:0 /* R--UF */
1785#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */
1786#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER 17:0 /* RWBUF */
1787#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x00000000 /* RWB-V */
1788#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20:20 /* RWVVF */
1789#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x00000000 /* RWV-V */
1790#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x00000001 /* RW--V */
1791#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX 31:28 /* RWBUF */
1792#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x00000000 /* RWB-V */
1793#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */
1794#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL 0:0 /* RWNVF */
1795#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x00000000 /* RWN-V */
1796#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x00000001 /* RW--V */
1797#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4:4 /* RWIVF */
1798#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */
1799#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x00000001 /* RW--V */
1800#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5:5 /* RWIVF */
1801#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */
1802#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x00000001 /* RW--V */
1803#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12:12 /* RWIVF */
1804#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x00000000 /* RWI-V */
1805#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */
1806#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16:16 /* RWIVF */
1807#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x00000000 /* RWI-V */
1808#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */
1809#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20:20 /* RWIVF */
1810#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */
1811#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */
1812#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */
1813#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0:0 /* RWIVF */
1814#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x00000000 /* RWI-V */
1815#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x00000001 /* RW--V */
1816#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4:4 /* RWIVF */
1817#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */
1818#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x00000001 /* RW--V */
1819#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5:5 /* RWIVF */
1820#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */
1821#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x00000001 /* RW--V */
1822#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12:12 /* RWIVF */
1823#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x00000000 /* RWI-V */
1824#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */
1825#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16:16 /* RWIVF */
1826#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x00000000 /* RWI-V */
1827#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */
1828#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20:20 /* RWIVF */
1829#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */
1830#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */
1831#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */
1832#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0:0 /* RWXVF */
1833#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x00000000 /* RW--V */
1834#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x00000001 /* RW--V */
1835#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4:4 /* RWXVF */
1836#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x00000000 /* RW--V */
1837#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x00000001 /* RW--V */
1838#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8:8 /* RWIVF */
1839#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x00000000 /* RWI-V */
1840#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x00000001 /* RW--V */
1841#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12:12 /* RWIVF */
1842#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x00000000 /* RWI-V */
1843#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x00000001 /* RW--V */
1844#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 22:16 /* RWXUF */
1845#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x00000000 /* RW--V */
1846#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 30:24 /* RWXUF */
1847#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x00000000 /* RW--V */
1848#define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */
1849#define NV_PGRAPH_X_MISC_BIT33_0 0:0 /* RWNVF */
1850#define NV_PGRAPH_X_MISC_BIT33_0_0 0x00000000 /* RWN-V */
1851#define NV_PGRAPH_X_MISC_BIT33_1 1:1 /* RWNVF */
1852#define NV_PGRAPH_X_MISC_BIT33_1_0 0x00000000 /* RWN-V */
1853#define NV_PGRAPH_X_MISC_BIT33_2 2:2 /* RWNVF */
1854#define NV_PGRAPH_X_MISC_BIT33_2_0 0x00000000 /* RWN-V */
1855#define NV_PGRAPH_X_MISC_BIT33_3 3:3 /* RWNVF */
1856#define NV_PGRAPH_X_MISC_BIT33_3_0 0x00000000 /* RWN-V */
1857#define NV_PGRAPH_X_MISC_RANGE_0 4:4 /* RWNVF */
1858#define NV_PGRAPH_X_MISC_RANGE_0_0 0x00000000 /* RWN-V */
1859#define NV_PGRAPH_X_MISC_RANGE_1 5:5 /* RWNVF */
1860#define NV_PGRAPH_X_MISC_RANGE_1_0 0x00000000 /* RWN-V */
1861#define NV_PGRAPH_X_MISC_RANGE_2 6:6 /* RWNVF */
1862#define NV_PGRAPH_X_MISC_RANGE_2_0 0x00000000 /* RWN-V */
1863#define NV_PGRAPH_X_MISC_RANGE_3 7:7 /* RWNVF */
1864#define NV_PGRAPH_X_MISC_RANGE_3_0 0x00000000 /* RWN-V */
1865#define NV_PGRAPH_X_MISC_ADDER_OUTPUT 29:28 /* RWXVF */
1866#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */
1867#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */
1868#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */
1869#define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */
1870#define NV_PGRAPH_Y_MISC_BIT33_0 0:0 /* RWNVF */
1871#define NV_PGRAPH_Y_MISC_BIT33_0_0 0x00000000 /* RWN-V */
1872#define NV_PGRAPH_Y_MISC_BIT33_1 1:1 /* RWNVF */
1873#define NV_PGRAPH_Y_MISC_BIT33_1_0 0x00000000 /* RWN-V */
1874#define NV_PGRAPH_Y_MISC_BIT33_2 2:2 /* RWNVF */
1875#define NV_PGRAPH_Y_MISC_BIT33_2_0 0x00000000 /* RWN-V */
1876#define NV_PGRAPH_Y_MISC_BIT33_3 3:3 /* RWNVF */
1877#define NV_PGRAPH_Y_MISC_BIT33_3_0 0x00000000 /* RWN-V */
1878#define NV_PGRAPH_Y_MISC_RANGE_0 4:4 /* RWNVF */
1879#define NV_PGRAPH_Y_MISC_RANGE_0_0 0x00000000 /* RWN-V */
1880#define NV_PGRAPH_Y_MISC_RANGE_1 5:5 /* RWNVF */
1881#define NV_PGRAPH_Y_MISC_RANGE_1_0 0x00000000 /* RWN-V */
1882#define NV_PGRAPH_Y_MISC_RANGE_2 6:6 /* RWNVF */
1883#define NV_PGRAPH_Y_MISC_RANGE_2_0 0x00000000 /* RWN-V */
1884#define NV_PGRAPH_Y_MISC_RANGE_3 7:7 /* RWNVF */
1885#define NV_PGRAPH_Y_MISC_RANGE_3_0 0x00000000 /* RWN-V */
1886#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT 29:28 /* RWXVF */
1887#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */
1888#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */
1889#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */
1890#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */
1891#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE 15:0 /* RWXSF */
1892#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */
1893#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE 17:0 /* RWXSF */
1894#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */
1895#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE 15:0 /* RWXSF */
1896#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */
1897#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE 17:0 /* RWXSF */
1898#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */
1899#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE 15:0 /* RWXSF */
1900#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */
1901#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE 17:0 /* RWXSF */
1902#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */
1903#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE 15:0 /* RWXSF */
1904#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */
1905#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE 17:0 /* RWXSF */
1906#define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */
1907#define NV_PGRAPH_SOURCE_COLOR_VALUE 31:0 /* RWNVF */
1908#define NV_PGRAPH_SOURCE_COLOR_VALUE_0 0x00000000 /* RWN-V */
1909#define NV_PGRAPH_VALID1 0x00400508 /* RW-4R */
1910#define NV_PGRAPH_VALID1_VLD 22:0 /* RWNVF */
1911#define NV_PGRAPH_VALID1_VLD_0 0x00000000 /* RWN-V */
1912#define NV_PGRAPH_VALID1_CLIP_MIN 28:28 /* RWIVF */
1913#define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x00000000 /* RWI-V */
1914#define NV_PGRAPH_VALID1_CLIP_MIN_ONLY 0x00000001 /* RW--V */
1915#define NV_PGRAPH_VALID1_CLIPA_MIN 29:29 /* RWIVF */
1916#define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x00000000 /* RWI-V */
1917#define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x00000001 /* RW--V */
1918#define NV_PGRAPH_VALID1_CLIP_MAX 30:30 /* RWIVF */
1919#define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x00000000 /* RWI-V */
1920#define NV_PGRAPH_VALID1_CLIP_MAX_ONLY 0x00000001 /* RW--V */
1921#define NV_PGRAPH_VALID1_CLIPA_MAX 31:31 /* RWIVF */
1922#define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x00000000 /* RWI-V */
1923#define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x00000001 /* RW--V */
1924#define NV_PGRAPH_VALID2 0x00400578 /* RW-4R */
1925#define NV_PGRAPH_VALID2_VLD2 28:0 /* RWNVF */
1926#define NV_PGRAPH_VALID2_VLD2_0 0x00000000 /* RWN-V */
1927#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */
1928#define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE 17:0 /* RWXSF */
1929#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */
1930#define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE 17:0 /* RWXSF */
1931#define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */
1932#define NV_PGRAPH_CLIPX_0_CLIP0_MIN 1:0 /* RWNVF */
1933#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT 0x00000000 /* RW--V */
1934#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */
1935#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */
1936#define NV_PGRAPH_CLIPX_0_CLIP0_MAX 3:2 /* RWNVF */
1937#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT 0x00000000 /* RW--V */
1938#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */
1939#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */
1940#define NV_PGRAPH_CLIPX_0_CLIP1_MIN 5:4 /* RWNVF */
1941#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT 0x00000000 /* RW--V */
1942#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */
1943#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */
1944#define NV_PGRAPH_CLIPX_0_CLIP1_MAX 7:6 /* RWNVF */
1945#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT 0x00000000 /* RW--V */
1946#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */
1947#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */
1948#define NV_PGRAPH_CLIPX_0_CLIP2_MIN 9:8 /* RWNVF */
1949#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT 0x00000000 /* RW--V */
1950#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */
1951#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */
1952#define NV_PGRAPH_CLIPX_0_CLIP2_MAX 11:10 /* RWNVF */
1953#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT 0x00000000 /* RW--V */
1954#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */
1955#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */
1956#define NV_PGRAPH_CLIPX_0_CLIP3_MIN 13:12 /* RWNVF */
1957#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT 0x00000000 /* RW--V */
1958#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */
1959#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */
1960#define NV_PGRAPH_CLIPX_0_CLIP3_MAX 15:14 /* RWNVF */
1961#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT 0x00000000 /* RW--V */
1962#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */
1963#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */
1964#define NV_PGRAPH_CLIPX_0_CLIP4_MIN 17:16 /* RWNVF */
1965#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT 0x00000000 /* RW--V */
1966#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */
1967#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */
1968#define NV_PGRAPH_CLIPX_0_CLIP4_MAX 19:18 /* RWNVF */
1969#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT 0x00000000 /* RW--V */
1970#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */
1971#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */
1972#define NV_PGRAPH_CLIPX_0_CLIP5_MIN 21:20 /* RWNVF */
1973#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT 0x00000000 /* RW--V */
1974#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */
1975#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */
1976#define NV_PGRAPH_CLIPX_0_CLIP5_MAX 23:22 /* RWNVF */
1977#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT 0x00000000 /* RW--V */
1978#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */
1979#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */
1980#define NV_PGRAPH_CLIPX_0_CLIP6_MIN 25:24 /* RWNVF */
1981#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT 0x00000000 /* RW--V */
1982#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */
1983#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */
1984#define NV_PGRAPH_CLIPX_0_CLIP6_MAX 27:26 /* RWNVF */
1985#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT 0x00000000 /* RW--V */
1986#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */
1987#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */
1988#define NV_PGRAPH_CLIPX_0_CLIP7_MIN 29:28 /* RWNVF */
1989#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT 0x00000000 /* RW--V */
1990#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */
1991#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */
1992#define NV_PGRAPH_CLIPX_0_CLIP7_MAX 31:30 /* RWNVF */
1993#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT 0x00000000 /* RW--V */
1994#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */
1995#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */
1996#define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */
1997#define NV_PGRAPH_CLIPX_1_CLIP8_MIN 1:0 /* RWNVF */
1998#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT 0x00000000 /* RW--V */
1999#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */
2000#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */
2001#define NV_PGRAPH_CLIPX_1_CLIP8_MAX 3:2 /* RWNVF */
2002#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT 0x00000000 /* RW--V */
2003#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */
2004#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */
2005#define NV_PGRAPH_CLIPX_1_CLIP9_MIN 5:4 /* RWNVF */
2006#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT 0x00000000 /* RW--V */
2007#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */
2008#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */
2009#define NV_PGRAPH_CLIPX_1_CLIP9_MAX 7:6 /* RWNVF */
2010#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT 0x00000000 /* RW--V */
2011#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */
2012#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */
2013#define NV_PGRAPH_CLIPX_1_CLIP10_MIN 9:8 /* RWNVF */
2014#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT 0x00000000 /* RW--V */
2015#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */
2016#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */
2017#define NV_PGRAPH_CLIPX_1_CLIP10_MAX 11:10 /* RWNVF */
2018#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT 0x00000000 /* RW--V */
2019#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */
2020#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */
2021#define NV_PGRAPH_CLIPX_1_CLIP11_MIN 13:12 /* RWNVF */
2022#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT 0x00000000 /* RW--V */
2023#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */
2024#define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ 0x00000002 /* RW--V */
2025#define NV_PGRAPH_CLIPX_1_CLIP11_MAX 15:14 /* RWNVF */
2026#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT 0x00000000 /* RW--V */
2027#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */
2028#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */
2029#define NV_PGRAPH_CLIPX_1_CLIP12_MIN 17:16 /* RWNVF */
2030#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT 0x00000000 /* RW--V */
2031#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */
2032#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */
2033#define NV_PGRAPH_CLIPX_1_CLIP12_MAX 19:18 /* RWNVF */
2034#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT 0x00000000 /* RW--V */
2035#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */
2036#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */
2037#define NV_PGRAPH_CLIPX_1_CLIP13_MIN 21:20 /* RWNVF */
2038#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT 0x00000000 /* RW--V */
2039#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */
2040#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */
2041#define NV_PGRAPH_CLIPX_1_CLIP13_MAX 23:22 /* RWNVF */
2042#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT 0x00000000 /* RW--V */
2043#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */
2044#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */
2045#define NV_PGRAPH_CLIPX_1_CLIP14_MIN 25:24 /* RWNVF */
2046#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT 0x00000000 /* RW--V */
2047#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */
2048#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */
2049#define NV_PGRAPH_CLIPX_1_CLIP14_MAX 27:26 /* RWNVF */
2050#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT 0x00000000 /* RW--V */
2051#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */
2052#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */
2053#define NV_PGRAPH_CLIPX_1_CLIP15_MIN 29:28 /* RWNVF */
2054#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT 0x00000000 /* RW--V */
2055#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */
2056#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */
2057#define NV_PGRAPH_CLIPX_1_CLIP15_MAX 31:30 /* RWNVF */
2058#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT 0x00000000 /* RW--V */
2059#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */
2060#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */
2061#define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */
2062#define NV_PGRAPH_CLIPY_0_CLIP0_MIN 1:0 /* RWNVF */
2063#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT 0x00000000 /* RW--V */
2064#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */
2065#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */
2066#define NV_PGRAPH_CLIPY_0_CLIP0_MAX 3:2 /* RWNVF */
2067#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT 0x00000000 /* RW--V */
2068#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */
2069#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */
2070#define NV_PGRAPH_CLIPY_0_CLIP1_MIN 5:4 /* RWNVF */
2071#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT 0x00000000 /* RW--V */
2072#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */
2073#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */
2074#define NV_PGRAPH_CLIPY_0_CLIP1_MAX 7:6 /* RWNVF */
2075#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT 0x00000000 /* RW--V */
2076#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */
2077#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */
2078#define NV_PGRAPH_CLIPY_0_CLIP2_MIN 9:8 /* RWNVF */
2079#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT 0x00000000 /* RW--V */
2080#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */
2081#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */
2082#define NV_PGRAPH_CLIPY_0_CLIP2_MAX 11:10 /* RWNVF */
2083#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT 0x00000000 /* RW--V */
2084#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */
2085#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */
2086#define NV_PGRAPH_CLIPY_0_CLIP3_MIN 13:12 /* RWNVF */
2087#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT 0x00000000 /* RW--V */
2088#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */
2089#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */
2090#define NV_PGRAPH_CLIPY_0_CLIP3_MAX 15:14 /* RWNVF */
2091#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT 0x00000000 /* RW--V */
2092#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */
2093#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */
2094#define NV_PGRAPH_CLIPY_0_CLIP4_MIN 17:16 /* RWNVF */
2095#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT 0x00000000 /* RW--V */
2096#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */
2097#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */
2098#define NV_PGRAPH_CLIPY_0_CLIP4_MAX 19:18 /* RWNVF */
2099#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT 0x00000000 /* RW--V */
2100#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */
2101#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */
2102#define NV_PGRAPH_CLIPY_0_CLIP5_MIN 21:20 /* RWNVF */
2103#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT 0x00000000 /* RW--V */
2104#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */
2105#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */
2106#define NV_PGRAPH_CLIPY_0_CLIP5_MAX 23:22 /* RWNVF */
2107#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT 0x00000000 /* RW--V */
2108#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */
2109#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */
2110#define NV_PGRAPH_CLIPY_0_CLIP6_MIN 25:24 /* RWNVF */
2111#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT 0x00000000 /* RW--V */
2112#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */
2113#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */
2114#define NV_PGRAPH_CLIPY_0_CLIP6_MAX 27:26 /* RWNVF */
2115#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT 0x00000000 /* RW--V */
2116#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */
2117#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */
2118#define NV_PGRAPH_CLIPY_0_CLIP7_MIN 29:28 /* RWNVF */
2119#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT 0x00000000 /* RW--V */
2120#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */
2121#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */
2122#define NV_PGRAPH_CLIPY_0_CLIP7_MAX 31:30 /* RWNVF */
2123#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT 0x00000000 /* RW--V */
2124#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */
2125#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */
2126#define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */
2127#define NV_PGRAPH_CLIPY_1_CLIP8_MIN 1:0 /* RWNVF */
2128#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT 0x00000000 /* RW--V */
2129#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */
2130#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */
2131#define NV_PGRAPH_CLIPY_1_CLIP8_MAX 3:2 /* RWNVF */
2132#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT 0x00000000 /* RW--V */
2133#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */
2134#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */
2135#define NV_PGRAPH_CLIPY_1_CLIP9_MIN 5:4 /* RWNVF */
2136#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT 0x00000000 /* RW--V */
2137#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */
2138#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */
2139#define NV_PGRAPH_CLIPY_1_CLIP9_MAX 7:6 /* RWNVF */
2140#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT 0x00000000 /* RW--V */
2141#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */
2142#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */
2143#define NV_PGRAPH_CLIPY_1_CLIP10_MIN 9:8 /* RWNVF */
2144#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT 0x00000000 /* RW--V */
2145#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */
2146#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */
2147#define NV_PGRAPH_CLIPY_1_CLIP10_MAX 11:10 /* RWNVF */
2148#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT 0x00000000 /* RW--V */
2149#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */
2150#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */
2151#define NV_PGRAPH_CLIPY_1_CLIP11_MIN 13:12 /* RWNVF */
2152#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT 0x00000000 /* RW--V */
2153#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */
2154#define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ 0x00000002 /* RW--V */
2155#define NV_PGRAPH_CLIPY_1_CLIP11_MAX 15:14 /* RWNVF */
2156#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT 0x00000000 /* RW--V */
2157#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */
2158#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */
2159#define NV_PGRAPH_CLIPY_1_CLIP12_MIN 17:16 /* RWNVF */
2160#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT 0x00000000 /* RW--V */
2161#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */
2162#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */
2163#define NV_PGRAPH_CLIPY_1_CLIP12_MAX 19:18 /* RWNVF */
2164#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT 0x00000000 /* RW--V */
2165#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */
2166#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */
2167#define NV_PGRAPH_CLIPY_1_CLIP13_MIN 21:20 /* RWNVF */
2168#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT 0x00000000 /* RW--V */
2169#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */
2170#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */
2171#define NV_PGRAPH_CLIPY_1_CLIP13_MAX 23:22 /* RWNVF */
2172#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT 0x00000000 /* RW--V */
2173#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */
2174#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */
2175#define NV_PGRAPH_CLIPY_1_CLIP14_MIN 25:24 /* RWNVF */
2176#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT 0x00000000 /* RW--V */
2177#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */
2178#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */
2179#define NV_PGRAPH_CLIPY_1_CLIP14_MAX 27:26 /* RWNVF */
2180#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT 0x00000000 /* RW--V */
2181#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */
2182#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */
2183#define NV_PGRAPH_CLIPY_1_CLIP15_MIN 29:28 /* RWNVF */
2184#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT 0x00000000 /* RW--V */
2185#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */
2186#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */
2187#define NV_PGRAPH_CLIPY_1_CLIP15_MAX 31:30 /* RWNVF */
2188#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT 0x00000000 /* RW--V */
2189#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */
2190#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */
2191#define NV_PGRAPH_MISC24_0 0x00400510 /* RW-4R */
2192#define NV_PGRAPH_MISC24_0_VALUE 23:0 /* RWXUF */
2193#define NV_PGRAPH_MISC24_1 0x00400570 /* RW-4R */
2194#define NV_PGRAPH_MISC24_1_VALUE 23:0 /* RWXUF */
2195#define NV_PGRAPH_MISC24_2 0x00400574 /* RW-4R */
2196#define NV_PGRAPH_MISC24_2_VALUE 23:0 /* RWXUF */
2197#define NV_PGRAPH_PASSTHRU_0 0x0040057C /* RW-4R */
2198#define NV_PGRAPH_PASSTHRU_0_VALUE 31:0 /* RWXUF */
2199#define NV_PGRAPH_PASSTHRU_1 0x00400580 /* RW-4R */
2200#define NV_PGRAPH_PASSTHRU_1_VALUE 31:0 /* RWXUF */
2201#define NV_PGRAPH_PASSTHRU_2 0x00400584 /* RW-4R */
2202#define NV_PGRAPH_PASSTHRU_2_VALUE 31:0 /* RWXUF */
2203#define NV_PGRAPH_U_RAM(i) (0x00400d00+(i)*4) /* RW-4A */
2204#define NV_PGRAPH_U_RAM__SIZE_1 16 /* */
2205#define NV_PGRAPH_U_RAM_VALUE 31:6 /* RWXFF */
2206#define NV_PGRAPH_V_RAM(i) (0x00400d40+(i)*4) /* RW-4A */
2207#define NV_PGRAPH_V_RAM__SIZE_1 16 /* */
2208#define NV_PGRAPH_V_RAM_VALUE 31:6 /* RWXFF */
2209#define NV_PGRAPH_M_RAM(i) (0x00400d80+(i)*4) /* RW-4A */
2210#define NV_PGRAPH_M_RAM__SIZE_1 16 /* */
2211#define NV_PGRAPH_M_RAM_VALUE 31:6 /* RWXFF */
2212#define NV_PGRAPH_DMA_START_0 0x00401000 /* RW-4R */
2213#define NV_PGRAPH_DMA_START_0_VALUE 31:0 /* RWXUF */
2214#define NV_PGRAPH_DMA_START_1 0x00401004 /* RW-4R */
2215#define NV_PGRAPH_DMA_START_1_VALUE 31:0 /* RWXUF */
2216#define NV_PGRAPH_DMA_LENGTH 0x00401008 /* RW-4R */
2217#define NV_PGRAPH_DMA_LENGTH_VALUE 21:0 /* RWXUF */
2218#define NV_PGRAPH_DMA_MISC 0x0040100C /* RW-4R */
2219#define NV_PGRAPH_DMA_MISC_COUNT 15:0 /* RWXUF */
2220#define NV_PGRAPH_DMA_MISC_FMT_SRC 18:16 /* RWXVF */
2221#define NV_PGRAPH_DMA_MISC_FMT_DST 22:20 /* RWXVF */
2222#define NV_PGRAPH_DMA_DATA_0 0x00401020 /* RW-4R */
2223#define NV_PGRAPH_DMA_DATA_0_VALUE 31:0 /* RWXUF */
2224#define NV_PGRAPH_DMA_DATA_1 0x00401024 /* RW-4R */
2225#define NV_PGRAPH_DMA_DATA_1_VALUE 31:0 /* RWXUF */
2226#define NV_PGRAPH_DMA_RM 0x00401030 /* RW-4R */
2227#define NV_PGRAPH_DMA_RM_ASSIST_A 0:0 /* RWIVF */
2228#define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x00000000 /* R-I-V */
2229#define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x00000001 /* R---V */
2230#define NV_PGRAPH_DMA_RM_ASSIST_A_RESET 0x00000001 /* -W--C */
2231#define NV_PGRAPH_DMA_RM_ASSIST_B 1:1 /* RWIVF */
2232#define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x00000000 /* R-I-V */
2233#define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x00000001 /* R---V */
2234#define NV_PGRAPH_DMA_RM_ASSIST_B_RESET 0x00000001 /* -W--C */
2235#define NV_PGRAPH_DMA_RM_WRITE_REQ 4:4 /* CWIVF */
2236#define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x00000000 /* CWI-V */
2237#define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x00000001 /* -W--T */
2238#define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040 /* RW-4R */
2239#define NV_PGRAPH_DMA_A_XLATE_INST_VALUE 15:0 /* RWXUF */
2240#define NV_PGRAPH_DMA_A_CONTROL 0x00401044 /* RW-4R */
2241#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12:12 /* RWIVF */
2242#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */
2243#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
2244#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */
2245#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
2246#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
2247#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE 17:16 /* RWXUF */
2248#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */
2249#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */
2250#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */
2251#define NV_PGRAPH_DMA_A_CONTROL_ADJUST 31:20 /* RWXUF */
2252#define NV_PGRAPH_DMA_A_LIMIT 0x00401048 /* RW-4R */
2253#define NV_PGRAPH_DMA_A_LIMIT_OFFSET 31:0 /* RWXUF */
2254#define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C /* RW-4R */
2255#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS 1:1 /* RWXVF */
2256#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */
2257#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */
2258#define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
2259#define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050 /* RW-4R */
2260#define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS 31:12 /* RWXUF */
2261#define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 /* RW-4R */
2262#define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 31:0 /* RWXUF */
2263#define NV_PGRAPH_DMA_A_OFFSET 0x00401058 /* RW-4R */
2264#define NV_PGRAPH_DMA_A_OFFSET_VALUE 31:0 /* RWXUF */
2265#define NV_PGRAPH_DMA_A_SIZE 0x0040105C /* RW-4R */
2266#define NV_PGRAPH_DMA_A_SIZE_VALUE 24:0 /* RWXUF */
2267#define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060 /* RW-4R */
2268#define NV_PGRAPH_DMA_A_Y_SIZE_VALUE 10:0 /* RWXUF */
2269#define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080 /* RW-4R */
2270#define NV_PGRAPH_DMA_B_XLATE_INST_VALUE 15:0 /* RWXUF */
2271#define NV_PGRAPH_DMA_B_CONTROL 0x00401084 /* RW-4R */
2272#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12:12 /* RWIVF */
2273#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */
2274#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
2275#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */
2276#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
2277#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
2278#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE 17:16 /* RWXUF */
2279#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */
2280#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */
2281#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */
2282#define NV_PGRAPH_DMA_B_CONTROL_ADJUST 31:20 /* RWXUF */
2283#define NV_PGRAPH_DMA_B_LIMIT 0x00401088 /* RW-4R */
2284#define NV_PGRAPH_DMA_B_LIMIT_OFFSET 31:0 /* RWXUF */
2285#define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C /* RW-4R */
2286#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS 1:1 /* RWXVF */
2287#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */
2288#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */
2289#define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
2290#define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090 /* RW-4R */
2291#define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS 31:12 /* RWXUF */
2292#define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 /* RW-4R */
2293#define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 31:0 /* RWXUF */
2294#define NV_PGRAPH_DMA_B_OFFSET 0x00401098 /* RW-4R */
2295#define NV_PGRAPH_DMA_B_OFFSET_VALUE 31:0 /* RWXUF */
2296#define NV_PGRAPH_DMA_B_SIZE 0x0040109C /* RW-4R */
2297#define NV_PGRAPH_DMA_B_SIZE_VALUE 24:0 /* RWXUF */
2298#define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0 /* RW-4R */
2299#define NV_PGRAPH_DMA_B_Y_SIZE_VALUE 10:0 /* RWXUF */
2300
2301/* Framebuffer registers */
2302#define NV_PFB 0x00100FFF:0x00100000 /* RW--D */
2303#define NV_PFB_BOOT_0 0x00100000 /* RW-4R */
2304#define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RW-VF */
2305#define NV_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 /* RW--V */
2306#define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 /* RW--V */
2307#define NV_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 /* RW--V */
2308#define NV_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 /* RW--V */
2309#define NV_PFB_BOOT_0_RAM_WIDTH_128 2:2 /* RW-VF */
2310#define NV_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x00000000 /* RW--V */
2311#define NV_PFB_BOOT_0_RAM_WIDTH_128_ON 0x00000001 /* RW--V */
2312#define NV_PFB_BOOT_0_RAM_TYPE 4:3 /* RW-VF */
2313#define NV_PFB_BOOT_0_RAM_TYPE_256K 0x00000000 /* RW--V */
2314#define NV_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x00000001 /* RW--V */
2315#define NV_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x00000002 /* RW--V */
2316#define NV_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x00000003 /* RW--V */
2317#define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */
2318#define NV_PFB_CONFIG_0_TYPE 14:0 /* RWIVF */
2319#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x00000120 /* RW--V */
2320#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x00000220 /* RW--V */
2321#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x00000320 /* RW--V */
2322#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x00004120 /* RW--V */
2323#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x00004220 /* RW--V */
2324#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x00004320 /* RW--V */
2325#define NV_PFB_CONFIG_0_TYPE_TETRIS 0x00002000 /* RW--V */
2326#define NV_PFB_CONFIG_0_TYPE_NOTILING 0x00001114 /* RWI-V */
2327#define NV_PFB_CONFIG_0_TETRIS_MODE 17:15 /* RWI-F */
2328#define NV_PFB_CONFIG_0_TETRIS_MODE_PASS 0x00000000 /* RWI-V */
2329#define NV_PFB_CONFIG_0_TETRIS_MODE_1 0x00000001 /* RW--V */
2330#define NV_PFB_CONFIG_0_TETRIS_MODE_2 0x00000002 /* RW--V */
2331#define NV_PFB_CONFIG_0_TETRIS_MODE_3 0x00000003 /* RW--V */
2332#define NV_PFB_CONFIG_0_TETRIS_MODE_4 0x00000004 /* RW--V */
2333#define NV_PFB_CONFIG_0_TETRIS_MODE_5 0x00000005 /* RW--V */
2334#define NV_PFB_CONFIG_0_TETRIS_MODE_6 0x00000006 /* RW--V */
2335#define NV_PFB_CONFIG_0_TETRIS_MODE_7 0x00000007 /* RW--V */
2336#define NV_PFB_CONFIG_0_TETRIS_SHIFT 19:18 /* RWI-F */
2337#define NV_PFB_CONFIG_0_TETRIS_SHIFT_0 0x00000000 /* RWI-V */
2338#define NV_PFB_CONFIG_0_TETRIS_SHIFT_1 0x00000001 /* RW--V */
2339#define NV_PFB_CONFIG_0_TETRIS_SHIFT_2 0x00000002 /* RW--V */
2340#define NV_PFB_CONFIG_0_BANK_SWAP 22:20 /* RWI-F */
2341#define NV_PFB_CONFIG_0_BANK_SWAP_OFF 0x00000000 /* RWI-V */
2342#define NV_PFB_CONFIG_0_BANK_SWAP_1M 0x00000001 /* RW--V */
2343#define NV_PFB_CONFIG_0_BANK_SWAP_2M 0x00000005 /* RW--V */
2344#define NV_PFB_CONFIG_0_BANK_SWAP_4M 0x00000007 /* RW--V */
2345#define NV_PFB_CONFIG_0_UNUSED 23:23 /* RW-VF */
2346#define NV_PFB_CONFIG_0_SCRAMBLE_EN 29:29 /* RWIVF */
2347#define NV_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x00000000 /* RW--V */
2348#define NV_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x00000001 /* RW--V */
2349#define NV_PFB_CONFIG_0_PRAMIN_WR 28:28 /* RWIVF */
2350#define NV_PFB_CONFIG_0_PRAMIN_WR_INIT 0x00000000 /* RW--V */
2351#define NV_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x00000001 /* RW--V */
2352#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK 27:24 /* RWIVF */
2353#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x00000000 /* RWI-V */
2354#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0x0000000f /* RWI-V */
2355#define NV_PFB_CONFIG_1 0x00100204 /* RW-4R */
2356#define NV_PFB_RTL 0x00100300 /* RW-4R */
2357#define NV_PFB_RTL_H 0:0 /* RWIUF */
2358#define NV_PFB_RTL_H_DEFAULT 0x00000000 /* RWI-V */
2359#define NV_PFB_RTL_MC 1:1 /* RWIUF */
2360#define NV_PFB_RTL_MC_DEFAULT 0x00000000 /* RWI-V */
2361#define NV_PFB_RTL_V 2:2 /* RWIUF */
2362#define NV_PFB_RTL_V_DEFAULT 0x00000000 /* RWI-V */
2363#define NV_PFB_RTL_G 3:3 /* RWIUF */
2364#define NV_PFB_RTL_G_DEFAULT 0x00000000 /* RWI-V */
2365#define NV_PFB_RTL_GB 4:4 /* RWIUF */
2366#define NV_PFB_RTL_GB_DEFAULT 0x00000000 /* RWI-V */
2367#define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */
2368#define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */
2369#define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */
2370#define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */
2371#define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */
2372#define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */
2373#define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */
2374#define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */
2375#define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */
2376#define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */
2377#define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */
2378#define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */
2379#define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */
2380#define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */
2381#define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */
2382#define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */
2383#define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */
2384#define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */
2385#define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */
2386#define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */
2387#define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */
2388#define NV_PFB_CONFIG_1_SGRAM100 3:3 /* RWIVF */
2389#define NV_PFB_CONFIG_1_SGRAM100_ENABLED 0x00000000 /* RWI-V */
2390#define NV_PFB_CONFIG_1_SGRAM100_DISABLED 0x00000001 /* RW--V */
2391#define NV_PFB_DEBUG_0_CKE_ALWAYSON 29:29 /* RWIVF */
2392#define NV_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x00000000 /* RW--V */
2393#define NV_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x00000001 /* RWI-V */
2394
2395#define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */
2396#define NV_PEXTDEV_BOOT_0 0x00101000 /* R--4R */
2397#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0:0 /* R-XVF */
2398#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x00000000 /* R---V */
2399#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x00000001 /* R---V */
2400#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1:1 /* R-XVF */
2401#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x00000000 /* R---V */
2402#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x00000001 /* R---V */
2403#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 3:2 /* R-XVF */
2404#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x00000000 /* R---V */
2405#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x00000001 /* R---V */
2406#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x00000002 /* R---V */
2407#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x00000003 /* R---V */
2408#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4:4 /* R-XVF */
2409#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x00000000 /* R---V */
2410#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x00000001 /* R---V */
2411#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5:5 /* R-XVF */
2412#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x00000000 /* R---V */
2413#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x00000001 /* R---V */
2414#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* R-XVF */
2415#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x00000000 /* R---V */
2416#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x00000001 /* R---V */
2417#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 8:7 /* R-XVF */
2418#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x00000000 /* R---V */
2419#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x00000001 /* R---V */
2420#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x00000002 /* R---V */
2421#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x00000003 /* R---V */
2422#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11:11 /* RWIVF */
2423#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
2424#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */
2425
2426/* Extras */
2427#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
2428/*#define NV_PRAMIN 0x00FFFFFF:0x00C00000*/
2429#define NV_PNVM 0x01FFFFFF:0x01000000 /* RW--M */
2430/*#define NV_PNVM 0x00BFFFFF:0x00800000*/
2431#define NV_CHAN0 0x0080ffff:0x00800000
2432
2433/* FIFO subchannels */
2434#define NV_UROP 0x43
2435#define NV_UCHROMA 0x57
2436#define NV_UCLIP 0x19
2437#define NV_UPATT 0x18
2438#define NV_ULIN 0x5C
2439#define NV_UTRI 0x5D
2440#define NV_URECT 0x5E
2441#define NV_UBLIT 0x5F
2442#define NV_UGLYPH 0x4B
2443
2444#endif /*__NV4REF_H__*/
2445
diff --git a/drivers/video/riva/nv_driver.c b/drivers/video/riva/nv_driver.c
new file mode 100644
index 000000000000..be630a0ccfd4
--- /dev/null
+++ b/drivers/video/riva/nv_driver.c
@@ -0,0 +1,425 @@
1/* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */
2/*
3 * Copyright 1996-1997 David J. McKay
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24/*
25 * GPL licensing note -- nVidia is allowing a liberal interpretation of
26 * the documentation restriction above, to merely say that this nVidia's
27 * copyright and disclaimer should be included with all code derived
28 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
29 */
30
31/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
32 <jpaana@s2.org> */
33
34/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0
355 20:47:06 mvojkovi Exp $ */
36
37#include <linux/delay.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include "nv_type.h"
41#include "rivafb.h"
42#include "nvreg.h"
43
44
45#ifndef CONFIG_PCI /* sanity check */
46#error This driver requires PCI support.
47#endif
48
49#define PFX "rivafb: "
50
51static inline unsigned char MISCin(struct riva_par *par)
52{
53 return (VGA_RD08(par->riva.PVIO, 0x3cc));
54}
55
56static Bool
57riva_is_connected(struct riva_par *par, Bool second)
58{
59 volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0;
60 U032 reg52C, reg608;
61 Bool present;
62
63 if(second) PRAMDAC += 0x800;
64
65 reg52C = NV_RD32(PRAMDAC, 0x052C);
66 reg608 = NV_RD32(PRAMDAC, 0x0608);
67
68 NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
69
70 NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
71 mdelay(1);
72 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
73
74 NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140);
75 NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000);
76
77 mdelay(1);
78
79 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE;
80
81 NV_WR32(par->riva.PRAMDAC0, 0x0608,
82 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF);
83
84 NV_WR32(PRAMDAC, 0x052C, reg52C);
85 NV_WR32(PRAMDAC, 0x0608, reg608);
86
87 return present;
88}
89
90static void
91riva_override_CRTC(struct riva_par *par)
92{
93 printk(KERN_INFO PFX
94 "Detected CRTC controller %i being used\n",
95 par->SecondCRTC ? 1 : 0);
96
97 if(par->forceCRTC != -1) {
98 printk(KERN_INFO PFX
99 "Forcing usage of CRTC %i\n", par->forceCRTC);
100 par->SecondCRTC = par->forceCRTC;
101 }
102}
103
104static void
105riva_is_second(struct riva_par *par)
106{
107 if (par->FlatPanel == 1) {
108 switch(par->Chipset & 0xffff) {
109 case 0x0174:
110 case 0x0175:
111 case 0x0176:
112 case 0x0177:
113 case 0x0179:
114 case 0x017C:
115 case 0x017D:
116 case 0x0186:
117 case 0x0187:
118 /* this might not be a good default for the chips below */
119 case 0x0286:
120 case 0x028C:
121 case 0x0316:
122 case 0x0317:
123 case 0x031A:
124 case 0x031B:
125 case 0x031C:
126 case 0x031D:
127 case 0x031E:
128 case 0x031F:
129 case 0x0324:
130 case 0x0325:
131 case 0x0328:
132 case 0x0329:
133 case 0x032C:
134 case 0x032D:
135 par->SecondCRTC = TRUE;
136 break;
137 default:
138 par->SecondCRTC = FALSE;
139 break;
140 }
141 } else {
142 if(riva_is_connected(par, 0)) {
143
144 if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100)
145 par->SecondCRTC = TRUE;
146 else
147 par->SecondCRTC = FALSE;
148 } else
149 if (riva_is_connected(par, 1)) {
150 if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100)
151 par->SecondCRTC = TRUE;
152 else
153 par->SecondCRTC = FALSE;
154 } else /* default */
155 par->SecondCRTC = FALSE;
156 }
157 riva_override_CRTC(par);
158}
159
160unsigned long riva_get_memlen(struct riva_par *par)
161{
162 RIVA_HW_INST *chip = &par->riva;
163 unsigned long memlen = 0;
164 unsigned int chipset = par->Chipset;
165 struct pci_dev* dev;
166 int amt;
167
168 switch (chip->Architecture) {
169 case NV_ARCH_03:
170 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
171 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
172 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) {
173 /*
174 * SDRAM 128 ZX.
175 */
176 switch (NV_RD32(chip->PFB,0x00000000) & 0x03) {
177 case 2:
178 memlen = 1024 * 4;
179 break;
180 case 1:
181 memlen = 1024 * 2;
182 break;
183 default:
184 memlen = 1024 * 8;
185 break;
186 }
187 } else {
188 memlen = 1024 * 8;
189 }
190 } else {
191 /*
192 * SGRAM 128.
193 */
194 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
195 case 0:
196 memlen = 1024 * 8;
197 break;
198 case 2:
199 memlen = 1024 * 4;
200 break;
201 default:
202 memlen = 1024 * 2;
203 break;
204 }
205 }
206 break;
207 case NV_ARCH_04:
208 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) {
209 memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) *
210 1024 * 2 + 1024 * 2;
211 } else {
212 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
213 case 0:
214 memlen = 1024 * 32;
215 break;
216 case 1:
217 memlen = 1024 * 4;
218 break;
219 case 2:
220 memlen = 1024 * 8;
221 break;
222 case 3:
223 default:
224 memlen = 1024 * 16;
225 break;
226 }
227 }
228 break;
229 case NV_ARCH_10:
230 case NV_ARCH_20:
231 case NV_ARCH_30:
232 if(chipset == NV_CHIP_IGEFORCE2) {
233
234 dev = pci_find_slot(0, 1);
235 pci_read_config_dword(dev, 0x7C, &amt);
236 memlen = (((amt >> 6) & 31) + 1) * 1024;
237 } else if (chipset == NV_CHIP_0x01F0) {
238 dev = pci_find_slot(0, 1);
239 pci_read_config_dword(dev, 0x84, &amt);
240 memlen = (((amt >> 4) & 127) + 1) * 1024;
241 } else {
242 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) &
243 0x000000FF){
244 case 0x02:
245 memlen = 1024 * 2;
246 break;
247 case 0x04:
248 memlen = 1024 * 4;
249 break;
250 case 0x08:
251 memlen = 1024 * 8;
252 break;
253 case 0x10:
254 memlen = 1024 * 16;
255 break;
256 case 0x20:
257 memlen = 1024 * 32;
258 break;
259 case 0x40:
260 memlen = 1024 * 64;
261 break;
262 case 0x80:
263 memlen = 1024 * 128;
264 break;
265 default:
266 memlen = 1024 * 16;
267 break;
268 }
269 }
270 break;
271 }
272 return memlen;
273}
274
275unsigned long riva_get_maxdclk(struct riva_par *par)
276{
277 RIVA_HW_INST *chip = &par->riva;
278 unsigned long dclk = 0;
279
280 switch (chip->Architecture) {
281 case NV_ARCH_03:
282 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
283 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
284 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) {
285 /*
286 * SDRAM 128 ZX.
287 */
288 dclk = 800000;
289 } else {
290 dclk = 1000000;
291 }
292 } else {
293 /*
294 * SGRAM 128.
295 */
296 dclk = 1000000;
297 }
298 break;
299 case NV_ARCH_04:
300 case NV_ARCH_10:
301 case NV_ARCH_20:
302 case NV_ARCH_30:
303 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) {
304 case 3:
305 dclk = 800000;
306 break;
307 default:
308 dclk = 1000000;
309 break;
310 }
311 break;
312 }
313 return dclk;
314}
315
316void
317riva_common_setup(struct riva_par *par)
318{
319 par->riva.EnableIRQ = 0;
320 par->riva.PRAMDAC0 =
321 (volatile U032 __iomem *)(par->ctrl_base + 0x00680000);
322 par->riva.PFB =
323 (volatile U032 __iomem *)(par->ctrl_base + 0x00100000);
324 par->riva.PFIFO =
325 (volatile U032 __iomem *)(par->ctrl_base + 0x00002000);
326 par->riva.PGRAPH =
327 (volatile U032 __iomem *)(par->ctrl_base + 0x00400000);
328 par->riva.PEXTDEV =
329 (volatile U032 __iomem *)(par->ctrl_base + 0x00101000);
330 par->riva.PTIMER =
331 (volatile U032 __iomem *)(par->ctrl_base + 0x00009000);
332 par->riva.PMC =
333 (volatile U032 __iomem *)(par->ctrl_base + 0x00000000);
334 par->riva.FIFO =
335 (volatile U032 __iomem *)(par->ctrl_base + 0x00800000);
336 par->riva.PCIO0 = par->ctrl_base + 0x00601000;
337 par->riva.PDIO0 = par->ctrl_base + 0x00681000;
338 par->riva.PVIO = par->ctrl_base + 0x000C0000;
339
340 par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0;
341
342 if (par->FlatPanel == -1) {
343 switch (par->Chipset & 0xffff) {
344 case 0x0112: /* known laptop chips */
345 case 0x0174:
346 case 0x0175:
347 case 0x0176:
348 case 0x0177:
349 case 0x0179:
350 case 0x017C:
351 case 0x017D:
352 case 0x0186:
353 case 0x0187:
354 case 0x0286:
355 case 0x028C:
356 case 0x0316:
357 case 0x0317:
358 case 0x031A:
359 case 0x031B:
360 case 0x031C:
361 case 0x031D:
362 case 0x031E:
363 case 0x031F:
364 case 0x0324:
365 case 0x0325:
366 case 0x0328:
367 case 0x0329:
368 case 0x032C:
369 case 0x032D:
370 printk(KERN_INFO PFX
371 "On a laptop. Assuming Digital Flat Panel\n");
372 par->FlatPanel = 1;
373 break;
374 default:
375 break;
376 }
377 }
378
379 switch (par->Chipset & 0x0ff0) {
380 case 0x0110:
381 if (par->Chipset == NV_CHIP_GEFORCE2_GO)
382 par->SecondCRTC = TRUE;
383#if defined(__powerpc__)
384 if (par->FlatPanel == 1)
385 par->SecondCRTC = TRUE;
386#endif
387 riva_override_CRTC(par);
388 break;
389 case 0x0170:
390 case 0x0180:
391 case 0x01F0:
392 case 0x0250:
393 case 0x0280:
394 case 0x0300:
395 case 0x0310:
396 case 0x0320:
397 case 0x0330:
398 case 0x0340:
399 riva_is_second(par);
400 break;
401 default:
402 break;
403 }
404
405 if (par->SecondCRTC) {
406 par->riva.PCIO = par->riva.PCIO0 + 0x2000;
407 par->riva.PCRTC = par->riva.PCRTC0 + 0x800;
408 par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800;
409 par->riva.PDIO = par->riva.PDIO0 + 0x2000;
410 } else {
411 par->riva.PCIO = par->riva.PCIO0;
412 par->riva.PCRTC = par->riva.PCRTC0;
413 par->riva.PRAMDAC = par->riva.PRAMDAC0;
414 par->riva.PDIO = par->riva.PDIO0;
415 }
416
417 if (par->FlatPanel == -1) {
418 /* Fix me, need x86 DDC code */
419 par->FlatPanel = 0;
420 }
421 par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
422
423 RivaGetConfig(&par->riva, par->Chipset);
424}
425
diff --git a/drivers/video/riva/nv_type.h b/drivers/video/riva/nv_type.h
new file mode 100644
index 000000000000..a69480c9a67c
--- /dev/null
+++ b/drivers/video/riva/nv_type.h
@@ -0,0 +1,58 @@
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.35 2002/08/05 20:47:06 mvojkovi Exp $ */
2
3#ifndef __NV_STRUCT_H__
4#define __NV_STRUCT_H__
5
6#define NV_CHIP_RIVA_128 ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128)
7#define NV_CHIP_TNT ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT)
8#define NV_CHIP_TNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2)
9#define NV_CHIP_UTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2)
10#define NV_CHIP_VTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2)
11#define NV_CHIP_UVTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2)
12#define NV_CHIP_ITNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2)
13#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256)
14#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR)
15#define NV_CHIP_QUADRO ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_QUADRO)
16#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX)
17#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX_100)
18#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR)
19#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO)
20#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS)
21#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_TI)
22#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA)
23#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO)
24#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460)
25#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440)
26#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420)
27#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO)
28#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO)
29#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32)
30#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL)
31#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64)
32#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_200)
33#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL)
34#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL)
35#define NV_CHIP_0x0180 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0180)
36#define NV_CHIP_0x0181 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0181)
37#define NV_CHIP_0x0182 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0182)
38#define NV_CHIP_0x0188 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0188)
39#define NV_CHIP_0x018A ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018A)
40#define NV_CHIP_0x018B ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018B)
41#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_IGEFORCE2)
42#define NV_CHIP_0x01F0 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x01F0)
43#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3)
44#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_200)
45#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_500)
46#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO_DCC)
47#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600)
48#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400)
49#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200)
50#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL)
51#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL)
52#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL)
53#define NV_CHIP_0x0280 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0280)
54#define NV_CHIP_0x0281 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0281)
55#define NV_CHIP_0x0288 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0288)
56#define NV_CHIP_0x0289 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0289)
57
58#endif /* __NV_STRUCT_H__ */
diff --git a/drivers/video/riva/nvreg.h b/drivers/video/riva/nvreg.h
new file mode 100644
index 000000000000..abfc167ae8d8
--- /dev/null
+++ b/drivers/video/riva/nvreg.h
@@ -0,0 +1,188 @@
1/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
2/*
3 * Copyright 1996-1997 David J. McKay
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */
25
26#ifndef __NVREG_H_
27#define __NVREG_H_
28
29/* Little macro to construct bitmask for contiguous ranges of bits */
30#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
31#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
32
33/* Macro to set specific bitfields (mask has to be a macro x:y) ! */
34#define SetBF(mask,value) ((value) << (0?mask))
35#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
36
37#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
38 | SetBF(mask,value)))
39
40#define DEVICE_BASE(device) (0?NV##_##device)
41#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
42
43/* This is where we will have to have conditional compilation */
44#define DEVICE_ACCESS(device,reg) \
45 nvCONTROL[(NV_##device##_##reg)/4]
46
47#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
48#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg)
49#define DEVICE_PRINT(device,reg) \
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
51#define DEVICE_DEF(device,mask,value) \
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
54#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
55
56#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value)
57#define PDAC_Read(reg) DEVICE_READ(PDAC,reg)
58#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg)
59#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value)
60#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value)
61#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask)
62
63#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)
64#define PFB_Read(reg) DEVICE_READ(PFB,reg)
65#define PFB_Print(reg) DEVICE_PRINT(PFB,reg)
66#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)
67#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)
68#define PFB_Mask(mask) DEVICE_MASK(PFB,mask)
69
70#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value)
71#define PRM_Read(reg) DEVICE_READ(PRM,reg)
72#define PRM_Print(reg) DEVICE_PRINT(PRM,reg)
73#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value)
74#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value)
75#define PRM_Mask(mask) DEVICE_MASK(PRM,mask)
76
77#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value)
78#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg)
79#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg)
80#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value)
81#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value)
82#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask)
83
84#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
85#define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
86#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
87#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
88#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
89#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
90
91#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value)
92#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg)
93#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg)
94#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value)
95#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value)
96#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask)
97
98#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value)
99#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)
100#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg)
101#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value)
102#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value)
103#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)
104
105#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
106#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
107#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
108#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
109#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
110#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
111
112#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value)
113#define PRAM_Read(reg) DEVICE_READ(PRAM,reg)
114#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg)
115#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value)
116#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value)
117#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask)
118
119#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value)
120#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg)
121#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg)
122#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value)
123#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value)
124#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask)
125
126#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127#define PMC_Read(reg) DEVICE_READ(PMC,reg)
128#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
132
133#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134#define PMC_Read(reg) DEVICE_READ(PMC,reg)
135#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
137#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
138#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
139
140
141#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value)
142#define PBUS_Read(reg) DEVICE_READ(PBUS,reg)
143#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg)
144#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value)
145#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value)
146#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask)
147
148
149#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value)
150#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg)
151#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg)
152#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value)
153#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value)
154#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask)
155
156
157#define PDAC_ReadExt(reg) \
158 ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
159 (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
160 (PDAC_Read(INDEX_DATA)))
161
162#define PDAC_WriteExt(reg,value)\
163 ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
164 (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
165 (PDAC_Write(INDEX_DATA,(value))))
166
167#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5)
168#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5))
169
170#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)
171#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)
172
173#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
174#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
175#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
176
177#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)
178#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))
179
180extern volatile unsigned *nvCONTROL;
181
182typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType;
183
184NVChipType GetChipType(void);
185
186#endif
187
188
diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c
new file mode 100644
index 000000000000..b6f8690b96c9
--- /dev/null
+++ b/drivers/video/riva/riva_hw.c
@@ -0,0 +1,2259 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45 */
46
47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */
48
49#include <linux/kernel.h>
50#include <linux/pci.h>
51#include <linux/pci_ids.h>
52#include "riva_hw.h"
53#include "riva_tbl.h"
54#include "nv_type.h"
55
56/*
57 * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
58 * operate identically (except TNT has more memory and better 3D quality.
59 */
60static int nv3Busy
61(
62 RIVA_HW_INST *chip
63)
64{
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);
67}
68static int nv4Busy
69(
70 RIVA_HW_INST *chip
71)
72{
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
75}
76static int nv10Busy
77(
78 RIVA_HW_INST *chip
79)
80{
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
83}
84
85static void vgaLockUnlock
86(
87 RIVA_HW_INST *chip,
88 int Lock
89)
90{
91 U008 cr11;
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11);
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5);
94 if(Lock) cr11 |= 0x80;
95 else cr11 &= ~0x80;
96 VGA_WR08(chip->PCIO, 0x3D5, cr11);
97}
98static void nv3LockUnlock
99(
100 RIVA_HW_INST *chip,
101 int Lock
102)
103{
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06);
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
106 vgaLockUnlock(chip, Lock);
107}
108static void nv4LockUnlock
109(
110 RIVA_HW_INST *chip,
111 int Lock
112)
113{
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
116 vgaLockUnlock(chip, Lock);
117}
118
119static int ShowHideCursor
120(
121 RIVA_HW_INST *chip,
122 int ShowHide
123)
124{
125 int cursor;
126 cursor = chip->CurrentState->cursor1;
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
128 (ShowHide & 0x01);
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31);
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
131 return (cursor & 0x01);
132}
133
134/****************************************************************************\
135* *
136* The video arbitration routines calculate some "magic" numbers. Fixes *
137* the snow seen when accessing the framebuffer without it. *
138* It just works (I hope). *
139* *
140\****************************************************************************/
141
142#define DEFAULT_GR_LWM 100
143#define DEFAULT_VID_LWM 100
144#define DEFAULT_GR_BURST_SIZE 256
145#define DEFAULT_VID_BURST_SIZE 128
146#define VIDEO 0
147#define GRAPHICS 1
148#define MPORT 2
149#define ENGINE 3
150#define GFIFO_SIZE 320
151#define GFIFO_SIZE_128 256
152#define MFIFO_SIZE 120
153#define VFIFO_SIZE 256
154
155typedef struct {
156 int gdrain_rate;
157 int vdrain_rate;
158 int mdrain_rate;
159 int gburst_size;
160 int vburst_size;
161 char vid_en;
162 char gr_en;
163 int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
164 int by_gfacc;
165 char vid_only_once;
166 char gr_only_once;
167 char first_vacc;
168 char first_gacc;
169 char first_macc;
170 int vocc;
171 int gocc;
172 int mocc;
173 char cur;
174 char engine_en;
175 char converged;
176 int priority;
177} nv3_arb_info;
178typedef struct {
179 int graphics_lwm;
180 int video_lwm;
181 int graphics_burst_size;
182 int video_burst_size;
183 int graphics_hi_priority;
184 int media_hi_priority;
185 int rtl_values;
186 int valid;
187} nv3_fifo_info;
188typedef struct {
189 char pix_bpp;
190 char enable_video;
191 char gr_during_vid;
192 char enable_mp;
193 int memory_width;
194 int video_scale;
195 int pclk_khz;
196 int mclk_khz;
197 int mem_page_miss;
198 int mem_latency;
199 char mem_aligned;
200} nv3_sim_state;
201typedef struct {
202 int graphics_lwm;
203 int video_lwm;
204 int graphics_burst_size;
205 int video_burst_size;
206 int valid;
207} nv4_fifo_info;
208typedef struct {
209 int pclk_khz;
210 int mclk_khz;
211 int nvclk_khz;
212 char mem_page_miss;
213 char mem_latency;
214 int memory_width;
215 char enable_video;
216 char gr_during_vid;
217 char pix_bpp;
218 char mem_aligned;
219 char enable_mp;
220} nv4_sim_state;
221typedef struct {
222 int graphics_lwm;
223 int video_lwm;
224 int graphics_burst_size;
225 int video_burst_size;
226 int valid;
227} nv10_fifo_info;
228typedef struct {
229 int pclk_khz;
230 int mclk_khz;
231 int nvclk_khz;
232 char mem_page_miss;
233 char mem_latency;
234 int memory_type;
235 int memory_width;
236 char enable_video;
237 char gr_during_vid;
238 char pix_bpp;
239 char mem_aligned;
240 char enable_mp;
241} nv10_sim_state;
242static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
243{
244 int iter = 0;
245 int tmp;
246 int vfsize, mfsize, gfsize;
247 int mburst_size = 32;
248 int mmisses, gmisses, vmisses;
249 int misses;
250 int vlwm, glwm, mlwm;
251 int last, next, cur;
252 int max_gfsize ;
253 long ns;
254
255 vlwm = 0;
256 glwm = 0;
257 mlwm = 0;
258 vfsize = 0;
259 gfsize = 0;
260 cur = ainfo->cur;
261 mmisses = 2;
262 gmisses = 2;
263 vmisses = 2;
264 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
265 else max_gfsize = GFIFO_SIZE;
266 max_gfsize = GFIFO_SIZE;
267 while (1)
268 {
269 if (ainfo->vid_en)
270 {
271 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
272 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
273 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
274 vfsize = ns * ainfo->vdrain_rate / 1000000;
275 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize;
276 }
277 if (state->enable_mp)
278 {
279 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
280 }
281 if (ainfo->gr_en)
282 {
283 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
284 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
285 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
286 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;
287 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
288 }
289 mfsize = 0;
290 if (!state->gr_during_vid && ainfo->vid_en)
291 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
292 next = VIDEO;
293 else if (ainfo->mocc < 0)
294 next = MPORT;
295 else if (ainfo->gocc< ainfo->by_gfacc)
296 next = GRAPHICS;
297 else return (0);
298 else switch (ainfo->priority)
299 {
300 case VIDEO:
301 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
302 next = VIDEO;
303 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
304 next = GRAPHICS;
305 else if (ainfo->mocc<0)
306 next = MPORT;
307 else return (0);
308 break;
309 case GRAPHICS:
310 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
311 next = GRAPHICS;
312 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
313 next = VIDEO;
314 else if (ainfo->mocc<0)
315 next = MPORT;
316 else return (0);
317 break;
318 default:
319 if (ainfo->mocc<0)
320 next = MPORT;
321 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
322 next = GRAPHICS;
323 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
324 next = VIDEO;
325 else return (0);
326 break;
327 }
328 last = cur;
329 cur = next;
330 iter++;
331 switch (cur)
332 {
333 case VIDEO:
334 if (last==cur) misses = 0;
335 else if (ainfo->first_vacc) misses = vmisses;
336 else misses = 1;
337 ainfo->first_vacc = 0;
338 if (last!=cur)
339 {
340 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
341 vlwm = ns * ainfo->vdrain_rate/ 1000000;
342 vlwm = ainfo->vocc - vlwm;
343 }
344 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
345 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
346 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
347 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
348 break;
349 case GRAPHICS:
350 if (last==cur) misses = 0;
351 else if (ainfo->first_gacc) misses = gmisses;
352 else misses = 1;
353 ainfo->first_gacc = 0;
354 if (last!=cur)
355 {
356 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
357 glwm = ns * ainfo->gdrain_rate/1000000;
358 glwm = ainfo->gocc - glwm;
359 }
360 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
361 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
362 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
363 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
364 break;
365 default:
366 if (last==cur) misses = 0;
367 else if (ainfo->first_macc) misses = mmisses;
368 else misses = 1;
369 ainfo->first_macc = 0;
370 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
371 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
372 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
373 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
374 break;
375 }
376 if (iter>100)
377 {
378 ainfo->converged = 0;
379 return (1);
380 }
381 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
382 tmp = ns * ainfo->gdrain_rate/1000000;
383 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)
384 {
385 ainfo->converged = 0;
386 return (1);
387 }
388 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
389 tmp = ns * ainfo->vdrain_rate/1000000;
390 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE)
391 {
392 ainfo->converged = 0;
393 return (1);
394 }
395 if (abs(ainfo->gocc) > max_gfsize)
396 {
397 ainfo->converged = 0;
398 return (1);
399 }
400 if (abs(ainfo->vocc) > VFIFO_SIZE)
401 {
402 ainfo->converged = 0;
403 return (1);
404 }
405 if (abs(ainfo->mocc) > MFIFO_SIZE)
406 {
407 ainfo->converged = 0;
408 return (1);
409 }
410 if (abs(vfsize) > VFIFO_SIZE)
411 {
412 ainfo->converged = 0;
413 return (1);
414 }
415 if (abs(gfsize) > max_gfsize)
416 {
417 ainfo->converged = 0;
418 return (1);
419 }
420 if (abs(mfsize) > MFIFO_SIZE)
421 {
422 ainfo->converged = 0;
423 return (1);
424 }
425 }
426}
427static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
428{
429 long ens, vns, mns, gns;
430 int mmisses, gmisses, vmisses, eburst_size, mburst_size;
431 int refresh_cycle;
432
433 refresh_cycle = 0;
434 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
435 mmisses = 2;
436 if (state->mem_aligned) gmisses = 2;
437 else gmisses = 3;
438 vmisses = 2;
439 eburst_size = state->memory_width * 1;
440 mburst_size = 32;
441 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
442 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
443 ainfo->wcmocc = 0;
444 ainfo->wcgocc = 0;
445 ainfo->wcvocc = 0;
446 ainfo->wcvlwm = 0;
447 ainfo->wcglwm = 0;
448 ainfo->engine_en = 1;
449 ainfo->converged = 1;
450 if (ainfo->engine_en)
451 {
452 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
453 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
454 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
455 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
456 ainfo->cur = ENGINE;
457 ainfo->first_vacc = 1;
458 ainfo->first_gacc = 1;
459 ainfo->first_macc = 1;
460 nv3_iterate(res_info, state,ainfo);
461 }
462 if (state->enable_mp)
463 {
464 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
465 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
466 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
467 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
468 ainfo->cur = MPORT;
469 ainfo->first_vacc = 1;
470 ainfo->first_gacc = 1;
471 ainfo->first_macc = 0;
472 nv3_iterate(res_info, state,ainfo);
473 }
474 if (ainfo->gr_en)
475 {
476 ainfo->first_vacc = 1;
477 ainfo->first_gacc = 0;
478 ainfo->first_macc = 1;
479 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
480 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
481 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
482 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;
483 ainfo->cur = GRAPHICS;
484 nv3_iterate(res_info, state,ainfo);
485 }
486 if (ainfo->vid_en)
487 {
488 ainfo->first_vacc = 0;
489 ainfo->first_gacc = 1;
490 ainfo->first_macc = 1;
491 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
492 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
493 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
494 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
495 ainfo->cur = VIDEO;
496 nv3_iterate(res_info, state, ainfo);
497 }
498 if (ainfo->converged)
499 {
500 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16;
501 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32;
502 res_info->graphics_burst_size = ainfo->gburst_size;
503 res_info->video_burst_size = ainfo->vburst_size;
504 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
505 res_info->media_hi_priority = (ainfo->priority == MPORT);
506 if (res_info->video_lwm > 160)
507 {
508 res_info->graphics_lwm = 256;
509 res_info->video_lwm = 128;
510 res_info->graphics_burst_size = 64;
511 res_info->video_burst_size = 64;
512 res_info->graphics_hi_priority = 0;
513 res_info->media_hi_priority = 0;
514 ainfo->converged = 0;
515 return (0);
516 }
517 if (res_info->video_lwm > 128)
518 {
519 res_info->video_lwm = 128;
520 }
521 return (1);
522 }
523 else
524 {
525 res_info->graphics_lwm = 256;
526 res_info->video_lwm = 128;
527 res_info->graphics_burst_size = 64;
528 res_info->video_burst_size = 64;
529 res_info->graphics_hi_priority = 0;
530 res_info->media_hi_priority = 0;
531 return (0);
532 }
533}
534static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
535{
536 int done, g,v, p;
537
538 done = 0;
539 for (p=0; p < 2; p++)
540 {
541 for (g=128 ; g > 32; g= g>> 1)
542 {
543 for (v=128; v >=32; v = v>> 1)
544 {
545 ainfo->priority = p;
546 ainfo->gburst_size = g;
547 ainfo->vburst_size = v;
548 done = nv3_arb(res_info, state,ainfo);
549 if (done && (g==128))
550 if ((res_info->graphics_lwm + g) > 256)
551 done = 0;
552 if (done)
553 goto Done;
554 }
555 }
556 }
557
558 Done:
559 return done;
560}
561static void nv3CalcArbitration
562(
563 nv3_fifo_info * res_info,
564 nv3_sim_state * state
565)
566{
567 nv3_fifo_info save_info;
568 nv3_arb_info ainfo;
569 char res_gr, res_vid;
570
571 ainfo.gr_en = 1;
572 ainfo.vid_en = state->enable_video;
573 ainfo.vid_only_once = 0;
574 ainfo.gr_only_once = 0;
575 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
576 ainfo.vdrain_rate = (int) state->pclk_khz * 2;
577 if (state->video_scale != 0)
578 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
579 ainfo.mdrain_rate = 33000;
580 res_info->rtl_values = 0;
581 if (!state->gr_during_vid && state->enable_video)
582 {
583 ainfo.gr_only_once = 1;
584 ainfo.gr_en = 1;
585 ainfo.gdrain_rate = 0;
586 res_vid = nv3_get_param(res_info, state, &ainfo);
587 res_vid = ainfo.converged;
588 save_info.video_lwm = res_info->video_lwm;
589 save_info.video_burst_size = res_info->video_burst_size;
590 ainfo.vid_en = 1;
591 ainfo.vid_only_once = 1;
592 ainfo.gr_en = 1;
593 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
594 ainfo.vdrain_rate = 0;
595 res_gr = nv3_get_param(res_info, state, &ainfo);
596 res_gr = ainfo.converged;
597 res_info->video_lwm = save_info.video_lwm;
598 res_info->video_burst_size = save_info.video_burst_size;
599 res_info->valid = res_gr & res_vid;
600 }
601 else
602 {
603 if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
604 if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
605 res_gr = nv3_get_param(res_info, state, &ainfo);
606 res_info->valid = ainfo.converged;
607 }
608}
609static void nv3UpdateArbitrationSettings
610(
611 unsigned VClk,
612 unsigned pixelDepth,
613 unsigned *burst,
614 unsigned *lwm,
615 RIVA_HW_INST *chip
616)
617{
618 nv3_fifo_info fifo_data;
619 nv3_sim_state sim_data;
620 unsigned int M, N, P, pll, MClk;
621
622 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
623 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
624 MClk = (N * chip->CrystalFreqKHz / M) >> P;
625 sim_data.pix_bpp = (char)pixelDepth;
626 sim_data.enable_video = 0;
627 sim_data.enable_mp = 0;
628 sim_data.video_scale = 1;
629 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
630 128 : 64;
631 sim_data.memory_width = 128;
632
633 sim_data.mem_latency = 9;
634 sim_data.mem_aligned = 1;
635 sim_data.mem_page_miss = 11;
636 sim_data.gr_during_vid = 0;
637 sim_data.pclk_khz = VClk;
638 sim_data.mclk_khz = MClk;
639 nv3CalcArbitration(&fifo_data, &sim_data);
640 if (fifo_data.valid)
641 {
642 int b = fifo_data.graphics_burst_size >> 4;
643 *burst = 0;
644 while (b >>= 1)
645 (*burst)++;
646 *lwm = fifo_data.graphics_lwm >> 3;
647 }
648 else
649 {
650 *lwm = 0x24;
651 *burst = 0x2;
652 }
653}
654static void nv4CalcArbitration
655(
656 nv4_fifo_info *fifo,
657 nv4_sim_state *arb
658)
659{
660 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
661 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
662 int found, mclk_extra, mclk_loop, cbs, m1, p1;
663 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
664 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
665 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
666 int craw, vraw;
667
668 fifo->valid = 1;
669 pclk_freq = arb->pclk_khz;
670 mclk_freq = arb->mclk_khz;
671 nvclk_freq = arb->nvclk_khz;
672 pagemiss = arb->mem_page_miss;
673 cas = arb->mem_latency;
674 width = arb->memory_width >> 6;
675 video_enable = arb->enable_video;
676 color_key_enable = arb->gr_during_vid;
677 bpp = arb->pix_bpp;
678 align = arb->mem_aligned;
679 mp_enable = arb->enable_mp;
680 clwm = 0;
681 vlwm = 0;
682 cbs = 128;
683 pclks = 2;
684 nvclks = 2;
685 nvclks += 2;
686 nvclks += 1;
687 mclks = 5;
688 mclks += 3;
689 mclks += 1;
690 mclks += cas;
691 mclks += 1;
692 mclks += 1;
693 mclks += 1;
694 mclks += 1;
695 mclk_extra = 3;
696 nvclks += 2;
697 nvclks += 1;
698 nvclks += 1;
699 nvclks += 1;
700 if (mp_enable)
701 mclks+=4;
702 nvclks += 0;
703 pclks += 0;
704 found = 0;
705 vbs = 0;
706 while (found != 1)
707 {
708 fifo->valid = 1;
709 found = 1;
710 mclk_loop = mclks+mclk_extra;
711 us_m = mclk_loop *1000*1000 / mclk_freq;
712 us_n = nvclks*1000*1000 / nvclk_freq;
713 us_p = nvclks*1000*1000 / pclk_freq;
714 if (video_enable)
715 {
716 video_drain_rate = pclk_freq * 2;
717 crtc_drain_rate = pclk_freq * bpp/8;
718 vpagemiss = 2;
719 vpagemiss += 1;
720 crtpagemiss = 2;
721 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
722 if (nvclk_freq * 2 > mclk_freq * width)
723 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
724 else
725 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
726 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
727 vlwm = us_video * video_drain_rate/(1000*1000);
728 vlwm++;
729 vbs = 128;
730 if (vlwm > 128) vbs = 64;
731 if (vlwm > (256-64)) vbs = 32;
732 if (nvclk_freq * 2 > mclk_freq * width)
733 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
734 else
735 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
736 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
737 us_crt =
738 us_video
739 +video_fill_us
740 +cpm_us
741 +us_m + us_n +us_p
742 ;
743 clwm = us_crt * crtc_drain_rate/(1000*1000);
744 clwm++;
745 }
746 else
747 {
748 crtc_drain_rate = pclk_freq * bpp/8;
749 crtpagemiss = 2;
750 crtpagemiss += 1;
751 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
752 us_crt = cpm_us + us_m + us_n + us_p ;
753 clwm = us_crt * crtc_drain_rate/(1000*1000);
754 clwm++;
755 }
756 m1 = clwm + cbs - 512;
757 p1 = m1 * pclk_freq / mclk_freq;
758 p1 = p1 * bpp / 8;
759 if ((p1 < m1) && (m1 > 0))
760 {
761 fifo->valid = 0;
762 found = 0;
763 if (mclk_extra ==0) found = 1;
764 mclk_extra--;
765 }
766 else if (video_enable)
767 {
768 if ((clwm > 511) || (vlwm > 255))
769 {
770 fifo->valid = 0;
771 found = 0;
772 if (mclk_extra ==0) found = 1;
773 mclk_extra--;
774 }
775 }
776 else
777 {
778 if (clwm > 519)
779 {
780 fifo->valid = 0;
781 found = 0;
782 if (mclk_extra ==0) found = 1;
783 mclk_extra--;
784 }
785 }
786 craw = clwm;
787 vraw = vlwm;
788 if (clwm < 384) clwm = 384;
789 if (vlwm < 128) vlwm = 128;
790 data = (int)(clwm);
791 fifo->graphics_lwm = data;
792 fifo->graphics_burst_size = 128;
793 data = (int)((vlwm+15));
794 fifo->video_lwm = data;
795 fifo->video_burst_size = vbs;
796 }
797}
798static void nv4UpdateArbitrationSettings
799(
800 unsigned VClk,
801 unsigned pixelDepth,
802 unsigned *burst,
803 unsigned *lwm,
804 RIVA_HW_INST *chip
805)
806{
807 nv4_fifo_info fifo_data;
808 nv4_sim_state sim_data;
809 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
810
811 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
812 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
813 MClk = (N * chip->CrystalFreqKHz / M) >> P;
814 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
815 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
816 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
817 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
818 sim_data.pix_bpp = (char)pixelDepth;
819 sim_data.enable_video = 0;
820 sim_data.enable_mp = 0;
821 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
822 128 : 64;
823 sim_data.mem_latency = (char)cfg1 & 0x0F;
824 sim_data.mem_aligned = 1;
825 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
826 sim_data.gr_during_vid = 0;
827 sim_data.pclk_khz = VClk;
828 sim_data.mclk_khz = MClk;
829 sim_data.nvclk_khz = NVClk;
830 nv4CalcArbitration(&fifo_data, &sim_data);
831 if (fifo_data.valid)
832 {
833 int b = fifo_data.graphics_burst_size >> 4;
834 *burst = 0;
835 while (b >>= 1)
836 (*burst)++;
837 *lwm = fifo_data.graphics_lwm >> 3;
838 }
839}
840static void nv10CalcArbitration
841(
842 nv10_fifo_info *fifo,
843 nv10_sim_state *arb
844)
845{
846 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
847 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
848 int nvclk_fill, us_extra;
849 int found, mclk_extra, mclk_loop, cbs, m1;
850 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
851 int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate;
852 int vus_m, vus_n, vus_p;
853 int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm;
854 int clwm_rnd_down;
855 int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2;
856 int pclks_2_top_fifo, min_mclk_extra;
857 int us_min_mclk_extra;
858
859 fifo->valid = 1;
860 pclk_freq = arb->pclk_khz; /* freq in KHz */
861 mclk_freq = arb->mclk_khz;
862 nvclk_freq = arb->nvclk_khz;
863 pagemiss = arb->mem_page_miss;
864 cas = arb->mem_latency;
865 width = arb->memory_width/64;
866 video_enable = arb->enable_video;
867 color_key_enable = arb->gr_during_vid;
868 bpp = arb->pix_bpp;
869 align = arb->mem_aligned;
870 mp_enable = arb->enable_mp;
871 clwm = 0;
872 vlwm = 1024;
873
874 cbs = 512;
875 vbs = 512;
876
877 pclks = 4; /* lwm detect. */
878
879 nvclks = 3; /* lwm -> sync. */
880 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
881
882 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
883
884 mclks += 1; /* arb_hp_req */
885 mclks += 5; /* ap_hp_req tiling pipeline */
886
887 mclks += 2; /* tc_req latency fifo */
888 mclks += 2; /* fb_cas_n_ memory request to fbio block */
889 mclks += 7; /* sm_d_rdv data returned from fbio block */
890
891 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
892 if (arb->memory_type == 0)
893 if (arb->memory_width == 64) /* 64 bit bus */
894 mclks += 4;
895 else
896 mclks += 2;
897 else
898 if (arb->memory_width == 64) /* 64 bit bus */
899 mclks += 2;
900 else
901 mclks += 1;
902
903 if ((!video_enable) && (arb->memory_width == 128))
904 {
905 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
906 min_mclk_extra = 17;
907 }
908 else
909 {
910 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
911 /* mclk_extra = 4; */ /* Margin of error */
912 min_mclk_extra = 18;
913 }
914
915 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
916 nvclks += 1; /* fbi_d_rdv_n */
917 nvclks += 1; /* Fbi_d_rdata */
918 nvclks += 1; /* crtfifo load */
919
920 if(mp_enable)
921 mclks+=4; /* Mp can get in with a burst of 8. */
922 /* Extra clocks determined by heuristics */
923
924 nvclks += 0;
925 pclks += 0;
926 found = 0;
927 while(found != 1) {
928 fifo->valid = 1;
929 found = 1;
930 mclk_loop = mclks+mclk_extra;
931 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
932 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
933 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
934 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
935 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
936 us_pipe = us_m + us_n + us_p;
937 us_pipe_min = us_m_min + us_n + us_p;
938 us_extra = 0;
939
940 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
941 vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */
942 vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */
943 vus_pipe = vus_m + vus_n + vus_p;
944
945 if(video_enable) {
946 video_drain_rate = pclk_freq * 4; /* MB/s */
947 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
948
949 vpagemiss = 1; /* self generating page miss */
950 vpagemiss += 1; /* One higher priority before */
951
952 crtpagemiss = 2; /* self generating page miss */
953 if(mp_enable)
954 crtpagemiss += 1; /* if MA0 conflict */
955
956 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
957
958 us_video = vpm_us + vus_m; /* Video has separate read return path */
959
960 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
961 us_crt =
962 us_video /* Wait for video */
963 +cpm_us /* CRT Page miss */
964 +us_m + us_n +us_p /* other latency */
965 ;
966
967 clwm = us_crt * crtc_drain_rate/(1000*1000);
968 clwm++; /* fixed point <= float_point - 1. Fixes that */
969 } else {
970 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
971
972 crtpagemiss = 1; /* self generating page miss */
973 crtpagemiss += 1; /* MA0 page miss */
974 if(mp_enable)
975 crtpagemiss += 1; /* if MA0 conflict */
976 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
977 us_crt = cpm_us + us_m + us_n + us_p ;
978 clwm = us_crt * crtc_drain_rate/(1000*1000);
979 clwm++; /* fixed point <= float_point - 1. Fixes that */
980
981 /*
982 //
983 // Another concern, only for high pclks so don't do this
984 // with video:
985 // What happens if the latency to fetch the cbs is so large that
986 // fifo empties. In that case we need to have an alternate clwm value
987 // based off the total burst fetch
988 //
989 us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
990 us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq;
991 clwm_mt = us_crt * crtc_drain_rate/(1000*1000);
992 clwm_mt ++;
993 if(clwm_mt > clwm)
994 clwm = clwm_mt;
995 */
996 /* Finally, a heuristic check when width == 64 bits */
997 if(width == 1){
998 nvclk_fill = nvclk_freq * 8;
999 if(crtc_drain_rate * 100 >= nvclk_fill * 102)
1000 clwm = 0xfff; /*Large number to fail */
1001
1002 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
1003 clwm = 1024;
1004 cbs = 512;
1005 us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
1006 }
1007 }
1008 }
1009
1010
1011 /*
1012 Overfill check:
1013
1014 */
1015
1016 clwm_rnd_down = ((int)clwm/8)*8;
1017 if (clwm_rnd_down < clwm)
1018 clwm += 8;
1019
1020 m1 = clwm + cbs - 1024; /* Amount of overfill */
1021 m2us = us_pipe_min + us_min_mclk_extra;
1022 pclks_2_top_fifo = (1024-clwm)/(8*width);
1023
1024 /* pclk cycles to drain */
1025 p1clk = m2us * pclk_freq/(1000*1000);
1026 p2 = p1clk * bpp / 8; /* bytes drained. */
1027
1028 if((p2 < m1) && (m1 > 0)) {
1029 fifo->valid = 0;
1030 found = 0;
1031 if(min_mclk_extra == 0) {
1032 if(cbs <= 32) {
1033 found = 1; /* Can't adjust anymore! */
1034 } else {
1035 cbs = cbs/2; /* reduce the burst size */
1036 }
1037 } else {
1038 min_mclk_extra--;
1039 }
1040 } else {
1041 if (clwm > 1023){ /* Have some margin */
1042 fifo->valid = 0;
1043 found = 0;
1044 if(min_mclk_extra == 0)
1045 found = 1; /* Can't adjust anymore! */
1046 else
1047 min_mclk_extra--;
1048 }
1049 }
1050 craw = clwm;
1051
1052 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
1053 data = (int)(clwm);
1054 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
1055 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
1056
1057 /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */
1058 fifo->video_lwm = 1024; fifo->video_burst_size = 512;
1059 }
1060}
1061static void nv10UpdateArbitrationSettings
1062(
1063 unsigned VClk,
1064 unsigned pixelDepth,
1065 unsigned *burst,
1066 unsigned *lwm,
1067 RIVA_HW_INST *chip
1068)
1069{
1070 nv10_fifo_info fifo_data;
1071 nv10_sim_state sim_data;
1072 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
1073
1074 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
1075 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1076 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1077 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1078 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1079 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1080 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
1081 sim_data.pix_bpp = (char)pixelDepth;
1082 sim_data.enable_video = 0;
1083 sim_data.enable_mp = 0;
1084 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ?
1085 1 : 0;
1086 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1087 128 : 64;
1088 sim_data.mem_latency = (char)cfg1 & 0x0F;
1089 sim_data.mem_aligned = 1;
1090 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
1091 sim_data.gr_during_vid = 0;
1092 sim_data.pclk_khz = VClk;
1093 sim_data.mclk_khz = MClk;
1094 sim_data.nvclk_khz = NVClk;
1095 nv10CalcArbitration(&fifo_data, &sim_data);
1096 if (fifo_data.valid)
1097 {
1098 int b = fifo_data.graphics_burst_size >> 4;
1099 *burst = 0;
1100 while (b >>= 1)
1101 (*burst)++;
1102 *lwm = fifo_data.graphics_lwm >> 3;
1103 }
1104}
1105
1106static void nForceUpdateArbitrationSettings
1107(
1108 unsigned VClk,
1109 unsigned pixelDepth,
1110 unsigned *burst,
1111 unsigned *lwm,
1112 RIVA_HW_INST *chip
1113)
1114{
1115 nv10_fifo_info fifo_data;
1116 nv10_sim_state sim_data;
1117 unsigned int M, N, P, pll, MClk, NVClk;
1118 unsigned int uMClkPostDiv;
1119 struct pci_dev *dev;
1120
1121 dev = pci_find_slot(0, 3);
1122 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
1123 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
1124
1125 if(!uMClkPostDiv) uMClkPostDiv = 4;
1126 MClk = 400000 / uMClkPostDiv;
1127
1128 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1129 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1130 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1131 sim_data.pix_bpp = (char)pixelDepth;
1132 sim_data.enable_video = 0;
1133 sim_data.enable_mp = 0;
1134
1135 dev = pci_find_slot(0, 1);
1136 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
1137 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
1138
1139 sim_data.memory_width = 64;
1140 sim_data.mem_latency = 3;
1141 sim_data.mem_aligned = 1;
1142 sim_data.mem_page_miss = 10;
1143 sim_data.gr_during_vid = 0;
1144 sim_data.pclk_khz = VClk;
1145 sim_data.mclk_khz = MClk;
1146 sim_data.nvclk_khz = NVClk;
1147 nv10CalcArbitration(&fifo_data, &sim_data);
1148 if (fifo_data.valid)
1149 {
1150 int b = fifo_data.graphics_burst_size >> 4;
1151 *burst = 0;
1152 while (b >>= 1)
1153 (*burst)++;
1154 *lwm = fifo_data.graphics_lwm >> 3;
1155 }
1156}
1157
1158/****************************************************************************\
1159* *
1160* RIVA Mode State Routines *
1161* *
1162\****************************************************************************/
1163
1164/*
1165 * Calculate the Video Clock parameters for the PLL.
1166 */
1167static int CalcVClock
1168(
1169 int clockIn,
1170 int *clockOut,
1171 int *mOut,
1172 int *nOut,
1173 int *pOut,
1174 RIVA_HW_INST *chip
1175)
1176{
1177 unsigned lowM, highM, highP;
1178 unsigned DeltaNew, DeltaOld;
1179 unsigned VClk, Freq;
1180 unsigned M, N, P;
1181
1182 DeltaOld = 0xFFFFFFFF;
1183
1184 VClk = (unsigned)clockIn;
1185
1186 if (chip->CrystalFreqKHz == 13500)
1187 {
1188 lowM = 7;
1189 highM = 13 - (chip->Architecture == NV_ARCH_03);
1190 }
1191 else
1192 {
1193 lowM = 8;
1194 highM = 14 - (chip->Architecture == NV_ARCH_03);
1195 }
1196
1197 highP = 4 - (chip->Architecture == NV_ARCH_03);
1198 for (P = 0; P <= highP; P ++)
1199 {
1200 Freq = VClk << P;
1201 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
1202 {
1203 for (M = lowM; M <= highM; M++)
1204 {
1205 N = (VClk << P) * M / chip->CrystalFreqKHz;
1206 if(N <= 255) {
1207 Freq = (chip->CrystalFreqKHz * N / M) >> P;
1208 if (Freq > VClk)
1209 DeltaNew = Freq - VClk;
1210 else
1211 DeltaNew = VClk - Freq;
1212 if (DeltaNew < DeltaOld)
1213 {
1214 *mOut = M;
1215 *nOut = N;
1216 *pOut = P;
1217 *clockOut = Freq;
1218 DeltaOld = DeltaNew;
1219 }
1220 }
1221 }
1222 }
1223 }
1224 return (DeltaOld != 0xFFFFFFFF);
1225}
1226/*
1227 * Calculate extended mode parameters (SVGA) and save in a
1228 * mode state structure.
1229 */
1230static void CalcStateExt
1231(
1232 RIVA_HW_INST *chip,
1233 RIVA_HW_STATE *state,
1234 int bpp,
1235 int width,
1236 int hDisplaySize,
1237 int height,
1238 int dotClock
1239)
1240{
1241 int pixelDepth, VClk, m, n, p;
1242 /*
1243 * Save mode parameters.
1244 */
1245 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
1246 state->width = width;
1247 state->height = height;
1248 /*
1249 * Extended RIVA registers.
1250 */
1251 pixelDepth = (bpp + 1)/8;
1252 CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
1253
1254 switch (chip->Architecture)
1255 {
1256 case NV_ARCH_03:
1257 nv3UpdateArbitrationSettings(VClk,
1258 pixelDepth * 8,
1259 &(state->arbitration0),
1260 &(state->arbitration1),
1261 chip);
1262 state->cursor0 = 0x00;
1263 state->cursor1 = 0x78;
1264 state->cursor2 = 0x00000000;
1265 state->pllsel = 0x10010100;
1266 state->config = ((width + 31)/32)
1267 | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
1268 | 0x1000;
1269 state->general = 0x00100100;
1270 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
1271 break;
1272 case NV_ARCH_04:
1273 nv4UpdateArbitrationSettings(VClk,
1274 pixelDepth * 8,
1275 &(state->arbitration0),
1276 &(state->arbitration1),
1277 chip);
1278 state->cursor0 = 0x00;
1279 state->cursor1 = 0xFC;
1280 state->cursor2 = 0x00000000;
1281 state->pllsel = 0x10000700;
1282 state->config = 0x00001114;
1283 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1284 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1285 break;
1286 case NV_ARCH_10:
1287 case NV_ARCH_20:
1288 case NV_ARCH_30:
1289 if((chip->Chipset == NV_CHIP_IGEFORCE2) ||
1290 (chip->Chipset == NV_CHIP_0x01F0))
1291 {
1292 nForceUpdateArbitrationSettings(VClk,
1293 pixelDepth * 8,
1294 &(state->arbitration0),
1295 &(state->arbitration1),
1296 chip);
1297 } else {
1298 nv10UpdateArbitrationSettings(VClk,
1299 pixelDepth * 8,
1300 &(state->arbitration0),
1301 &(state->arbitration1),
1302 chip);
1303 }
1304 state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1305 state->cursor1 = (chip->CursorStart >> 11) << 2;
1306 state->cursor2 = chip->CursorStart >> 24;
1307 state->pllsel = 0x10000700;
1308 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0);
1309 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1310 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1311 break;
1312 }
1313
1314 /* Paul Richards: below if block borks things in kernel for some reason */
1315 /* Tony: Below is needed to set hardware in DirectColor */
1316 if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
1317 state->general |= 0x00000030;
1318
1319 state->vpll = (p << 16) | (n << 8) | m;
1320 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
1321 state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
1322 state->offset0 =
1323 state->offset1 =
1324 state->offset2 =
1325 state->offset3 = 0;
1326 state->pitch0 =
1327 state->pitch1 =
1328 state->pitch2 =
1329 state->pitch3 = pixelDepth * width;
1330}
1331/*
1332 * Load fixed function state and pre-calculated/stored state.
1333 */
1334#if 0
1335#define LOAD_FIXED_STATE(tbl,dev) \
1336 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1337 chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
1338#define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1339 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1340 chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
1341#define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1342 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1343 chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
1344#define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1345 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1346 chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
1347#define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1348 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1349 chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
1350#endif
1351
1352#define LOAD_FIXED_STATE(tbl,dev) \
1353 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1354 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1355#define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1356 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1357 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1358#define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1359 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1360 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1361#define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1362 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1363 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1364#define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1365 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1366 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1367
1368static void UpdateFifoState
1369(
1370 RIVA_HW_INST *chip
1371)
1372{
1373 int i;
1374
1375 switch (chip->Architecture)
1376 {
1377 case NV_ARCH_04:
1378 LOAD_FIXED_STATE(nv4,FIFO);
1379 chip->Tri03 = NULL;
1380 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1381 break;
1382 case NV_ARCH_10:
1383 case NV_ARCH_20:
1384 case NV_ARCH_30:
1385 /*
1386 * Initialize state for the RivaTriangle3D05 routines.
1387 */
1388 LOAD_FIXED_STATE(nv10tri05,PGRAPH);
1389 LOAD_FIXED_STATE(nv10,FIFO);
1390 chip->Tri03 = NULL;
1391 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1392 break;
1393 }
1394}
1395static void LoadStateExt
1396(
1397 RIVA_HW_INST *chip,
1398 RIVA_HW_STATE *state
1399)
1400{
1401 int i;
1402
1403 /*
1404 * Load HW fixed function state.
1405 */
1406 LOAD_FIXED_STATE(Riva,PMC);
1407 LOAD_FIXED_STATE(Riva,PTIMER);
1408 switch (chip->Architecture)
1409 {
1410 case NV_ARCH_03:
1411 /*
1412 * Make sure frame buffer config gets set before loading PRAMIN.
1413 */
1414 NV_WR32(chip->PFB, 0x00000200, state->config);
1415 LOAD_FIXED_STATE(nv3,PFIFO);
1416 LOAD_FIXED_STATE(nv3,PRAMIN);
1417 LOAD_FIXED_STATE(nv3,PGRAPH);
1418 switch (state->bpp)
1419 {
1420 case 15:
1421 case 16:
1422 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
1423 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
1424 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1425 break;
1426 case 24:
1427 case 32:
1428 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
1429 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
1430 chip->Tri03 = NULL;
1431 break;
1432 case 8:
1433 default:
1434 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
1435 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
1436 chip->Tri03 = NULL;
1437 break;
1438 }
1439 for (i = 0x00000; i < 0x00800; i++)
1440 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03);
1441 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);
1442 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);
1443 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);
1444 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);
1445 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);
1446 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);
1447 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);
1448 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);
1449 break;
1450 case NV_ARCH_04:
1451 /*
1452 * Make sure frame buffer config gets set before loading PRAMIN.
1453 */
1454 NV_WR32(chip->PFB, 0x00000200, state->config);
1455 LOAD_FIXED_STATE(nv4,PFIFO);
1456 LOAD_FIXED_STATE(nv4,PRAMIN);
1457 LOAD_FIXED_STATE(nv4,PGRAPH);
1458 switch (state->bpp)
1459 {
1460 case 15:
1461 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
1462 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
1463 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1464 break;
1465 case 16:
1466 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
1467 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
1468 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1469 break;
1470 case 24:
1471 case 32:
1472 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
1473 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
1474 chip->Tri03 = NULL;
1475 break;
1476 case 8:
1477 default:
1478 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
1479 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
1480 chip->Tri03 = NULL;
1481 break;
1482 }
1483 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1484 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1485 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1486 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1487 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1488 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1489 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1490 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1491 break;
1492 case NV_ARCH_10:
1493 case NV_ARCH_20:
1494 case NV_ARCH_30:
1495 if(chip->twoHeads) {
1496 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1497 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1498 chip->LockUnlock(chip, 0);
1499 }
1500
1501 LOAD_FIXED_STATE(nv10,PFIFO);
1502 LOAD_FIXED_STATE(nv10,PRAMIN);
1503 LOAD_FIXED_STATE(nv10,PGRAPH);
1504 switch (state->bpp)
1505 {
1506 case 15:
1507 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
1508 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
1509 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1510 break;
1511 case 16:
1512 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
1513 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
1514 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1515 break;
1516 case 24:
1517 case 32:
1518 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
1519 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
1520 chip->Tri03 = NULL;
1521 break;
1522 case 8:
1523 default:
1524 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
1525 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
1526 chip->Tri03 = NULL;
1527 break;
1528 }
1529
1530 if(chip->Architecture == NV_ARCH_10) {
1531 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1532 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1533 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1534 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1535 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1536 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1537 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1538 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1539 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);
1540 } else {
1541 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);
1542 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);
1543 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);
1544 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);
1545 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);
1546 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);
1547 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);
1548 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);
1549 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);
1550 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);
1551 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200));
1552 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204));
1553 }
1554 if(chip->twoHeads) {
1555 NV_WR32(chip->PCRTC0, 0x00000860, state->head);
1556 NV_WR32(chip->PCRTC0, 0x00002860, state->head2);
1557 }
1558 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25));
1559
1560 NV_WR32(chip->PMC, 0x00008704, 1);
1561 NV_WR32(chip->PMC, 0x00008140, 0);
1562 NV_WR32(chip->PMC, 0x00008920, 0);
1563 NV_WR32(chip->PMC, 0x00008924, 0);
1564 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);
1565 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);
1566 NV_WR32(chip->PMC, 0x00001588, 0);
1567
1568 NV_WR32(chip->PFB, 0x00000240, 0);
1569 NV_WR32(chip->PFB, 0x00000250, 0);
1570 NV_WR32(chip->PFB, 0x00000260, 0);
1571 NV_WR32(chip->PFB, 0x00000270, 0);
1572 NV_WR32(chip->PFB, 0x00000280, 0);
1573 NV_WR32(chip->PFB, 0x00000290, 0);
1574 NV_WR32(chip->PFB, 0x000002A0, 0);
1575 NV_WR32(chip->PFB, 0x000002B0, 0);
1576
1577 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240));
1578 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244));
1579 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248));
1580 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C));
1581 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250));
1582 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254));
1583 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258));
1584 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C));
1585 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260));
1586 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264));
1587 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268));
1588 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C));
1589 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270));
1590 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274));
1591 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278));
1592 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C));
1593 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280));
1594 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284));
1595 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288));
1596 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C));
1597 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290));
1598 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294));
1599 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298));
1600 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C));
1601 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0));
1602 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4));
1603 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8));
1604 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC));
1605 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0));
1606 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4));
1607 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8));
1608 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC));
1609 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000);
1610 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000);
1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1612 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008);
1613 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200);
1614 for (i = 0; i < (3*16); i++)
1615 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1616 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1617 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1618 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800);
1619 for (i = 0; i < (16*16); i++)
1620 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1621 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000);
1622 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004);
1623 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400);
1624 for (i = 0; i < (59*4); i++)
1625 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1626 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800);
1627 for (i = 0; i < (47*4); i++)
1628 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1629 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00);
1630 for (i = 0; i < (3*4); i++)
1631 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1632 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000);
1633 for (i = 0; i < (19*4); i++)
1634 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1635 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400);
1636 for (i = 0; i < (12*4); i++)
1637 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1638 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800);
1639 for (i = 0; i < (12*4); i++)
1640 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1641 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400);
1642 for (i = 0; i < (8*4); i++)
1643 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1644 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000);
1645 for (i = 0; i < 16; i++)
1646 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1647 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1648 for (i = 0; i < 4; i++)
1649 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1650
1651 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);
1652
1653 if(chip->flatPanel) {
1654 if((chip->Chipset & 0x0ff0) == 0x0110) {
1655 NV_WR32(chip->PRAMDAC, 0x0528, state->dither);
1656 } else
1657 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1658 NV_WR32(chip->PRAMDAC, 0x083C, state->dither);
1659 }
1660
1661 VGA_WR08(chip->PCIO, 0x03D4, 0x53);
1662 VGA_WR08(chip->PCIO, 0x03D5, 0);
1663 VGA_WR08(chip->PCIO, 0x03D4, 0x54);
1664 VGA_WR08(chip->PCIO, 0x03D5, 0);
1665 VGA_WR08(chip->PCIO, 0x03D4, 0x21);
1666 VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
1667 }
1668
1669 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1670 VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1671 }
1672 LOAD_FIXED_STATE(Riva,FIFO);
1673 UpdateFifoState(chip);
1674 /*
1675 * Load HW mode state.
1676 */
1677 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1678 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1679 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1680 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
1681 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1682 VGA_WR08(chip->PCIO, 0x03D5, state->screen);
1683 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1684 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
1685 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1686 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
1687 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1688 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
1689 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1690 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
1691 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1692 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1693 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1694 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1695 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1696 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1697 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1698 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1699
1700 if(!chip->flatPanel) {
1701 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
1702 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);
1703 if(chip->twoHeads)
1704 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);
1705 } else {
1706 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);
1707 }
1708 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);
1709
1710 /*
1711 * Turn off VBlank enable and reset.
1712 */
1713 NV_WR32(chip->PCRTC, 0x00000140, 0);
1714 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit);
1715 /*
1716 * Set interrupt enable.
1717 */
1718 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);
1719 /*
1720 * Set current state pointer.
1721 */
1722 chip->CurrentState = state;
1723 /*
1724 * Reset FIFO free and empty counts.
1725 */
1726 chip->FifoFreeCount = 0;
1727 /* Free count from first subchannel */
1728 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0);
1729}
1730static void UnloadStateExt
1731(
1732 RIVA_HW_INST *chip,
1733 RIVA_HW_STATE *state
1734)
1735{
1736 /*
1737 * Save current HW state.
1738 */
1739 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1740 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
1741 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1742 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
1743 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1744 state->screen = VGA_RD08(chip->PCIO, 0x03D5);
1745 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1746 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
1747 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1748 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
1749 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1750 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
1751 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1752 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
1753 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1754 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1755 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1756 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1757 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1758 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1759 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1760 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1761 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);
1762 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520);
1763 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C);
1764 state->general = NV_RD32(chip->PRAMDAC, 0x00000600);
1765 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848);
1766 state->config = NV_RD32(chip->PFB, 0x00000200);
1767 switch (chip->Architecture)
1768 {
1769 case NV_ARCH_03:
1770 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630);
1771 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634);
1772 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638);
1773 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C);
1774 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650);
1775 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654);
1776 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658);
1777 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C);
1778 break;
1779 case NV_ARCH_04:
1780 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1781 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1782 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1783 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1784 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1785 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1786 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1787 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1788 break;
1789 case NV_ARCH_10:
1790 case NV_ARCH_20:
1791 case NV_ARCH_30:
1792 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1793 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1794 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1795 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1796 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1797 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1798 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1799 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1800 if(chip->twoHeads) {
1801 state->head = NV_RD32(chip->PCRTC0, 0x00000860);
1802 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860);
1803 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1804 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1805 }
1806 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1807 state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1808 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810);
1809
1810 if((chip->Chipset & 0x0ff0) == 0x0110) {
1811 state->dither = NV_RD32(chip->PRAMDAC, 0x0528);
1812 } else
1813 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1814 state->dither = NV_RD32(chip->PRAMDAC, 0x083C);
1815 }
1816 break;
1817 }
1818}
1819static void SetStartAddress
1820(
1821 RIVA_HW_INST *chip,
1822 unsigned start
1823)
1824{
1825 NV_WR32(chip->PCRTC, 0x800, start);
1826}
1827
1828static void SetStartAddress3
1829(
1830 RIVA_HW_INST *chip,
1831 unsigned start
1832)
1833{
1834 int offset = start >> 2;
1835 int pan = (start & 3) << 1;
1836 unsigned char tmp;
1837
1838 /*
1839 * Unlock extended registers.
1840 */
1841 chip->LockUnlock(chip, 0);
1842 /*
1843 * Set start address.
1844 */
1845 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
1846 offset >>= 8;
1847 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
1848 offset >>= 8;
1849 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1850 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
1851 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1852 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
1853 /*
1854 * 4 pixel pan register.
1855 */
1856 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
1857 VGA_WR08(chip->PCIO, 0x3C0, 0x13);
1858 VGA_WR08(chip->PCIO, 0x3C0, pan);
1859}
1860static void nv3SetSurfaces2D
1861(
1862 RIVA_HW_INST *chip,
1863 unsigned surf0,
1864 unsigned surf1
1865)
1866{
1867 RivaSurface __iomem *Surface =
1868 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1869
1870 RIVA_FIFO_FREE(*chip,Tri03,5);
1871 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1872 NV_WR32(&Surface->Offset, 0, surf0);
1873 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1874 NV_WR32(&Surface->Offset, 0, surf1);
1875 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1876}
1877static void nv4SetSurfaces2D
1878(
1879 RIVA_HW_INST *chip,
1880 unsigned surf0,
1881 unsigned surf1
1882)
1883{
1884 RivaSurface __iomem *Surface =
1885 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1886
1887 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1888 NV_WR32(&Surface->Offset, 0, surf0);
1889 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1890 NV_WR32(&Surface->Offset, 0, surf1);
1891 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1892}
1893static void nv10SetSurfaces2D
1894(
1895 RIVA_HW_INST *chip,
1896 unsigned surf0,
1897 unsigned surf1
1898)
1899{
1900 RivaSurface __iomem *Surface =
1901 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1902
1903 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1904 NV_WR32(&Surface->Offset, 0, surf0);
1905 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1906 NV_WR32(&Surface->Offset, 0, surf1);
1907 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1908}
1909static void nv3SetSurfaces3D
1910(
1911 RIVA_HW_INST *chip,
1912 unsigned surf0,
1913 unsigned surf1
1914)
1915{
1916 RivaSurface __iomem *Surface =
1917 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1918
1919 RIVA_FIFO_FREE(*chip,Tri03,5);
1920 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1921 NV_WR32(&Surface->Offset, 0, surf0);
1922 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1923 NV_WR32(&Surface->Offset, 0, surf1);
1924 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1925}
1926static void nv4SetSurfaces3D
1927(
1928 RIVA_HW_INST *chip,
1929 unsigned surf0,
1930 unsigned surf1
1931)
1932{
1933 RivaSurface __iomem *Surface =
1934 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1935
1936 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1937 NV_WR32(&Surface->Offset, 0, surf0);
1938 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1939 NV_WR32(&Surface->Offset, 0, surf1);
1940 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1941}
1942static void nv10SetSurfaces3D
1943(
1944 RIVA_HW_INST *chip,
1945 unsigned surf0,
1946 unsigned surf1
1947)
1948{
1949 RivaSurface3D __iomem *Surfaces3D =
1950 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]);
1951
1952 RIVA_FIFO_FREE(*chip,Tri03,4);
1953 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007);
1954 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0);
1955 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1);
1956 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1957}
1958
1959/****************************************************************************\
1960* *
1961* Probe RIVA Chip Configuration *
1962* *
1963\****************************************************************************/
1964
1965static void nv3GetConfig
1966(
1967 RIVA_HW_INST *chip
1968)
1969{
1970 /*
1971 * Fill in chip configuration.
1972 */
1973 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020)
1974 {
1975 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
1976 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02))
1977 {
1978 /*
1979 * SDRAM 128 ZX.
1980 */
1981 chip->RamBandwidthKBytesPerSec = 800000;
1982 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03)
1983 {
1984 case 2:
1985 chip->RamAmountKBytes = 1024 * 4;
1986 break;
1987 case 1:
1988 chip->RamAmountKBytes = 1024 * 2;
1989 break;
1990 default:
1991 chip->RamAmountKBytes = 1024 * 8;
1992 break;
1993 }
1994 }
1995 else
1996 {
1997 chip->RamBandwidthKBytesPerSec = 1000000;
1998 chip->RamAmountKBytes = 1024 * 8;
1999 }
2000 }
2001 else
2002 {
2003 /*
2004 * SGRAM 128.
2005 */
2006 chip->RamBandwidthKBytesPerSec = 1000000;
2007 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2008 {
2009 case 0:
2010 chip->RamAmountKBytes = 1024 * 8;
2011 break;
2012 case 2:
2013 chip->RamAmountKBytes = 1024 * 4;
2014 break;
2015 default:
2016 chip->RamAmountKBytes = 1024 * 2;
2017 break;
2018 }
2019 }
2020 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2021 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
2022 chip->VBlankBit = 0x00000100;
2023 chip->MaxVClockFreqKHz = 256000;
2024 /*
2025 * Set chip functions.
2026 */
2027 chip->Busy = nv3Busy;
2028 chip->ShowHideCursor = ShowHideCursor;
2029 chip->CalcStateExt = CalcStateExt;
2030 chip->LoadStateExt = LoadStateExt;
2031 chip->UnloadStateExt = UnloadStateExt;
2032 chip->SetStartAddress = SetStartAddress3;
2033 chip->SetSurfaces2D = nv3SetSurfaces2D;
2034 chip->SetSurfaces3D = nv3SetSurfaces3D;
2035 chip->LockUnlock = nv3LockUnlock;
2036}
2037static void nv4GetConfig
2038(
2039 RIVA_HW_INST *chip
2040)
2041{
2042 /*
2043 * Fill in chip configuration.
2044 */
2045 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100)
2046 {
2047 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2
2048 + 1024 * 2;
2049 }
2050 else
2051 {
2052 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2053 {
2054 case 0:
2055 chip->RamAmountKBytes = 1024 * 32;
2056 break;
2057 case 1:
2058 chip->RamAmountKBytes = 1024 * 4;
2059 break;
2060 case 2:
2061 chip->RamAmountKBytes = 1024 * 8;
2062 break;
2063 case 3:
2064 default:
2065 chip->RamAmountKBytes = 1024 * 16;
2066 break;
2067 }
2068 }
2069 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2070 {
2071 case 3:
2072 chip->RamBandwidthKBytesPerSec = 800000;
2073 break;
2074 default:
2075 chip->RamBandwidthKBytesPerSec = 1000000;
2076 break;
2077 }
2078 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2079 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
2080 chip->VBlankBit = 0x00000001;
2081 chip->MaxVClockFreqKHz = 350000;
2082 /*
2083 * Set chip functions.
2084 */
2085 chip->Busy = nv4Busy;
2086 chip->ShowHideCursor = ShowHideCursor;
2087 chip->CalcStateExt = CalcStateExt;
2088 chip->LoadStateExt = LoadStateExt;
2089 chip->UnloadStateExt = UnloadStateExt;
2090 chip->SetStartAddress = SetStartAddress;
2091 chip->SetSurfaces2D = nv4SetSurfaces2D;
2092 chip->SetSurfaces3D = nv4SetSurfaces3D;
2093 chip->LockUnlock = nv4LockUnlock;
2094}
2095static void nv10GetConfig
2096(
2097 RIVA_HW_INST *chip,
2098 unsigned int chipset
2099)
2100{
2101 struct pci_dev* dev;
2102 int amt;
2103
2104#ifdef __BIG_ENDIAN
2105 /* turn on big endian register access */
2106 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001))
2107 NV_WR32(chip->PMC, 0x00000004, 0x01000001);
2108#endif
2109
2110 /*
2111 * Fill in chip configuration.
2112 */
2113 if(chipset == NV_CHIP_IGEFORCE2) {
2114 dev = pci_find_slot(0, 1);
2115 pci_read_config_dword(dev, 0x7C, &amt);
2116 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
2117 } else if(chipset == NV_CHIP_0x01F0) {
2118 dev = pci_find_slot(0, 1);
2119 pci_read_config_dword(dev, 0x84, &amt);
2120 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
2121 } else {
2122 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)
2123 {
2124 case 0x02:
2125 chip->RamAmountKBytes = 1024 * 2;
2126 break;
2127 case 0x04:
2128 chip->RamAmountKBytes = 1024 * 4;
2129 break;
2130 case 0x08:
2131 chip->RamAmountKBytes = 1024 * 8;
2132 break;
2133 case 0x10:
2134 chip->RamAmountKBytes = 1024 * 16;
2135 break;
2136 case 0x20:
2137 chip->RamAmountKBytes = 1024 * 32;
2138 break;
2139 case 0x40:
2140 chip->RamAmountKBytes = 1024 * 64;
2141 break;
2142 case 0x80:
2143 chip->RamAmountKBytes = 1024 * 128;
2144 break;
2145 default:
2146 chip->RamAmountKBytes = 1024 * 16;
2147 break;
2148 }
2149 }
2150 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2151 {
2152 case 3:
2153 chip->RamBandwidthKBytesPerSec = 800000;
2154 break;
2155 default:
2156 chip->RamBandwidthKBytesPerSec = 1000000;
2157 break;
2158 }
2159 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ?
2160 14318 : 13500;
2161
2162 switch (chipset & 0x0ff0) {
2163 case 0x0170:
2164 case 0x0180:
2165 case 0x01F0:
2166 case 0x0250:
2167 case 0x0280:
2168 case 0x0300:
2169 case 0x0310:
2170 case 0x0320:
2171 case 0x0330:
2172 case 0x0340:
2173 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22))
2174 chip->CrystalFreqKHz = 27000;
2175 break;
2176 default:
2177 break;
2178 }
2179
2180 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
2181 chip->CURSOR = NULL; /* can't set this here */
2182 chip->VBlankBit = 0x00000001;
2183 chip->MaxVClockFreqKHz = 350000;
2184 /*
2185 * Set chip functions.
2186 */
2187 chip->Busy = nv10Busy;
2188 chip->ShowHideCursor = ShowHideCursor;
2189 chip->CalcStateExt = CalcStateExt;
2190 chip->LoadStateExt = LoadStateExt;
2191 chip->UnloadStateExt = UnloadStateExt;
2192 chip->SetStartAddress = SetStartAddress;
2193 chip->SetSurfaces2D = nv10SetSurfaces2D;
2194 chip->SetSurfaces3D = nv10SetSurfaces3D;
2195 chip->LockUnlock = nv4LockUnlock;
2196
2197 switch(chipset & 0x0ff0) {
2198 case 0x0110:
2199 case 0x0170:
2200 case 0x0180:
2201 case 0x01F0:
2202 case 0x0250:
2203 case 0x0280:
2204 case 0x0300:
2205 case 0x0310:
2206 case 0x0320:
2207 case 0x0330:
2208 case 0x0340:
2209 chip->twoHeads = TRUE;
2210 break;
2211 default:
2212 chip->twoHeads = FALSE;
2213 break;
2214 }
2215}
2216int RivaGetConfig
2217(
2218 RIVA_HW_INST *chip,
2219 unsigned int chipset
2220)
2221{
2222 /*
2223 * Save this so future SW know whats it's dealing with.
2224 */
2225 chip->Version = RIVA_SW_VERSION;
2226 /*
2227 * Chip specific configuration.
2228 */
2229 switch (chip->Architecture)
2230 {
2231 case NV_ARCH_03:
2232 nv3GetConfig(chip);
2233 break;
2234 case NV_ARCH_04:
2235 nv4GetConfig(chip);
2236 break;
2237 case NV_ARCH_10:
2238 case NV_ARCH_20:
2239 case NV_ARCH_30:
2240 nv10GetConfig(chip, chipset);
2241 break;
2242 default:
2243 return (-1);
2244 }
2245 chip->Chipset = chipset;
2246 /*
2247 * Fill in FIFO pointers.
2248 */
2249 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]);
2250 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]);
2251 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]);
2252 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]);
2253 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]);
2254 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]);
2255 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]);
2256 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
2257 return (0);
2258}
2259
diff --git a/drivers/video/riva/riva_hw.h b/drivers/video/riva/riva_hw.h
new file mode 100644
index 000000000000..a1e71a626df2
--- /dev/null
+++ b/drivers/video/riva/riva_hw.h
@@ -0,0 +1,548 @@
1/***************************************************************************\
2|* *|
3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38\***************************************************************************/
39
40/*
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45 */
46
47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
48#ifndef __RIVA_HW_H__
49#define __RIVA_HW_H__
50#define RIVA_SW_VERSION 0x00010003
51
52#ifndef Bool
53typedef int Bool;
54#endif
55
56#ifndef TRUE
57#define TRUE 1
58#endif
59#ifndef FALSE
60#define FALSE 0
61#endif
62#ifndef NULL
63#define NULL 0
64#endif
65
66/*
67 * Typedefs to force certain sized values.
68 */
69typedef unsigned char U008;
70typedef unsigned short U016;
71typedef unsigned int U032;
72
73/*
74 * HW access macros.
75 */
76#include <asm/io.h>
77
78#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
79#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
80#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
81#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
82#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
83#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
84
85#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
86#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
87
88/*
89 * Define different architectures.
90 */
91#define NV_ARCH_03 0x03
92#define NV_ARCH_04 0x04
93#define NV_ARCH_10 0x10
94#define NV_ARCH_20 0x20
95#define NV_ARCH_30 0x30
96#define NV_ARCH_40 0x40
97
98/***************************************************************************\
99* *
100* FIFO registers. *
101* *
102\***************************************************************************/
103
104/*
105 * Raster OPeration. Windows style ROP3.
106 */
107typedef volatile struct
108{
109 U032 reserved00[4];
110#ifdef __BIG_ENDIAN
111 U032 FifoFree;
112#else
113 U016 FifoFree;
114 U016 Nop;
115#endif
116 U032 reserved01[0x0BB];
117 U032 Rop3;
118} RivaRop;
119/*
120 * 8X8 Monochrome pattern.
121 */
122typedef volatile struct
123{
124 U032 reserved00[4];
125#ifdef __BIG_ENDIAN
126 U032 FifoFree;
127#else
128 U016 FifoFree;
129 U016 Nop;
130#endif
131 U032 reserved01[0x0BD];
132 U032 Shape;
133 U032 reserved03[0x001];
134 U032 Color0;
135 U032 Color1;
136 U032 Monochrome[2];
137} RivaPattern;
138/*
139 * Scissor clip rectangle.
140 */
141typedef volatile struct
142{
143 U032 reserved00[4];
144#ifdef __BIG_ENDIAN
145 U032 FifoFree;
146#else
147 U016 FifoFree;
148 U016 Nop;
149#endif
150 U032 reserved01[0x0BB];
151 U032 TopLeft;
152 U032 WidthHeight;
153} RivaClip;
154/*
155 * 2D filled rectangle.
156 */
157typedef volatile struct
158{
159 U032 reserved00[4];
160#ifdef __BIG_ENDIAN
161 U032 FifoFree;
162#else
163 U016 FifoFree;
164 U016 Nop[1];
165#endif
166 U032 reserved01[0x0BC];
167 U032 Color;
168 U032 reserved03[0x03E];
169 U032 TopLeft;
170 U032 WidthHeight;
171} RivaRectangle;
172/*
173 * 2D screen-screen BLT.
174 */
175typedef volatile struct
176{
177 U032 reserved00[4];
178#ifdef __BIG_ENDIAN
179 U032 FifoFree;
180#else
181 U016 FifoFree;
182 U016 Nop;
183#endif
184 U032 reserved01[0x0BB];
185 U032 TopLeftSrc;
186 U032 TopLeftDst;
187 U032 WidthHeight;
188} RivaScreenBlt;
189/*
190 * 2D pixel BLT.
191 */
192typedef volatile struct
193{
194 U032 reserved00[4];
195#ifdef __BIG_ENDIAN
196 U032 FifoFree;
197#else
198 U016 FifoFree;
199 U016 Nop[1];
200#endif
201 U032 reserved01[0x0BC];
202 U032 TopLeft;
203 U032 WidthHeight;
204 U032 WidthHeightIn;
205 U032 reserved02[0x03C];
206 U032 Pixels;
207} RivaPixmap;
208/*
209 * Filled rectangle combined with monochrome expand. Useful for glyphs.
210 */
211typedef volatile struct
212{
213 U032 reserved00[4];
214#ifdef __BIG_ENDIAN
215 U032 FifoFree;
216#else
217 U016 FifoFree;
218 U016 Nop;
219#endif
220 U032 reserved01[0x0BB];
221 U032 reserved03[(0x040)-1];
222 U032 Color1A;
223 struct
224 {
225 U032 TopLeft;
226 U032 WidthHeight;
227 } UnclippedRectangle[64];
228 U032 reserved04[(0x080)-3];
229 struct
230 {
231 U032 TopLeft;
232 U032 BottomRight;
233 } ClipB;
234 U032 Color1B;
235 struct
236 {
237 U032 TopLeft;
238 U032 BottomRight;
239 } ClippedRectangle[64];
240 U032 reserved05[(0x080)-5];
241 struct
242 {
243 U032 TopLeft;
244 U032 BottomRight;
245 } ClipC;
246 U032 Color1C;
247 U032 WidthHeightC;
248 U032 PointC;
249 U032 MonochromeData1C;
250 U032 reserved06[(0x080)+121];
251 struct
252 {
253 U032 TopLeft;
254 U032 BottomRight;
255 } ClipD;
256 U032 Color1D;
257 U032 WidthHeightInD;
258 U032 WidthHeightOutD;
259 U032 PointD;
260 U032 MonochromeData1D;
261 U032 reserved07[(0x080)+120];
262 struct
263 {
264 U032 TopLeft;
265 U032 BottomRight;
266 } ClipE;
267 U032 Color0E;
268 U032 Color1E;
269 U032 WidthHeightInE;
270 U032 WidthHeightOutE;
271 U032 PointE;
272 U032 MonochromeData01E;
273} RivaBitmap;
274/*
275 * 3D textured, Z buffered triangle.
276 */
277typedef volatile struct
278{
279 U032 reserved00[4];
280#ifdef __BIG_ENDIAN
281 U032 FifoFree;
282#else
283 U016 FifoFree;
284 U016 Nop;
285#endif
286 U032 reserved01[0x0BC];
287 U032 TextureOffset;
288 U032 TextureFormat;
289 U032 TextureFilter;
290 U032 FogColor;
291/* This is a problem on LynxOS */
292#ifdef Control
293#undef Control
294#endif
295 U032 Control;
296 U032 AlphaTest;
297 U032 reserved02[0x339];
298 U032 FogAndIndex;
299 U032 Color;
300 float ScreenX;
301 float ScreenY;
302 float ScreenZ;
303 float EyeM;
304 float TextureS;
305 float TextureT;
306} RivaTexturedTriangle03;
307typedef volatile struct
308{
309 U032 reserved00[4];
310#ifdef __BIG_ENDIAN
311 U032 FifoFree;
312#else
313 U016 FifoFree;
314 U016 Nop;
315#endif
316 U032 reserved01[0x0BB];
317 U032 ColorKey;
318 U032 TextureOffset;
319 U032 TextureFormat;
320 U032 TextureFilter;
321 U032 Blend;
322/* This is a problem on LynxOS */
323#ifdef Control
324#undef Control
325#endif
326 U032 Control;
327 U032 FogColor;
328 U032 reserved02[0x39];
329 struct
330 {
331 float ScreenX;
332 float ScreenY;
333 float ScreenZ;
334 float EyeM;
335 U032 Color;
336 U032 Specular;
337 float TextureS;
338 float TextureT;
339 } Vertex[16];
340 U032 DrawTriangle3D;
341} RivaTexturedTriangle05;
342/*
343 * 2D line.
344 */
345typedef volatile struct
346{
347 U032 reserved00[4];
348#ifdef __BIG_ENDIAN
349 U032 FifoFree;
350#else
351 U016 FifoFree;
352 U016 Nop[1];
353#endif
354 U032 reserved01[0x0BC];
355 U032 Color; /* source color 0304-0307*/
356 U032 Reserved02[0x03e];
357 struct { /* start aliased methods in array 0400- */
358 U032 point0; /* y_x S16_S16 in pixels 0- 3*/
359 U032 point1; /* y_x S16_S16 in pixels 4- 7*/
360 } Lin[16]; /* end of aliased methods in array -047f*/
361 struct { /* start aliased methods in array 0480- */
362 U032 point0X; /* in pixels, 0 at left 0- 3*/
363 U032 point0Y; /* in pixels, 0 at top 4- 7*/
364 U032 point1X; /* in pixels, 0 at left 8- b*/
365 U032 point1Y; /* in pixels, 0 at top c- f*/
366 } Lin32[8]; /* end of aliased methods in array -04ff*/
367 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
368 struct { /* start aliased methods in array 0580- */
369 U032 x; /* in pixels, 0 at left 0- 3*/
370 U032 y; /* in pixels, 0 at top 4- 7*/
371 } PolyLin32[16]; /* end of aliased methods in array -05ff*/
372 struct { /* start aliased methods in array 0600- */
373 U032 color; /* source color 0- 3*/
374 U032 point; /* y_x S16_S16 in pixels 4- 7*/
375 } ColorPolyLin[16]; /* end of aliased methods in array -067f*/
376} RivaLine;
377/*
378 * 2D/3D surfaces
379 */
380typedef volatile struct
381{
382 U032 reserved00[4];
383#ifdef __BIG_ENDIAN
384 U032 FifoFree;
385#else
386 U016 FifoFree;
387 U016 Nop;
388#endif
389 U032 reserved01[0x0BE];
390 U032 Offset;
391} RivaSurface;
392typedef volatile struct
393{
394 U032 reserved00[4];
395#ifdef __BIG_ENDIAN
396 U032 FifoFree;
397#else
398 U016 FifoFree;
399 U016 Nop;
400#endif
401 U032 reserved01[0x0BD];
402 U032 Pitch;
403 U032 RenderBufferOffset;
404 U032 ZBufferOffset;
405} RivaSurface3D;
406
407/***************************************************************************\
408* *
409* Virtualized RIVA H/W interface. *
410* *
411\***************************************************************************/
412
413#define FP_ENABLE 1
414#define FP_DITHER 2
415
416struct _riva_hw_inst;
417struct _riva_hw_state;
418/*
419 * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
420 */
421typedef struct _riva_hw_inst
422{
423 /*
424 * Chip specific settings.
425 */
426 U032 Architecture;
427 U032 Version;
428 U032 Chipset;
429 U032 CrystalFreqKHz;
430 U032 RamAmountKBytes;
431 U032 MaxVClockFreqKHz;
432 U032 RamBandwidthKBytesPerSec;
433 U032 EnableIRQ;
434 U032 IO;
435 U032 VBlankBit;
436 U032 FifoFreeCount;
437 U032 FifoEmptyCount;
438 U032 CursorStart;
439 U032 flatPanel;
440 Bool twoHeads;
441 /*
442 * Non-FIFO registers.
443 */
444 volatile U032 __iomem *PCRTC0;
445 volatile U032 __iomem *PCRTC;
446 volatile U032 __iomem *PRAMDAC0;
447 volatile U032 __iomem *PFB;
448 volatile U032 __iomem *PFIFO;
449 volatile U032 __iomem *PGRAPH;
450 volatile U032 __iomem *PEXTDEV;
451 volatile U032 __iomem *PTIMER;
452 volatile U032 __iomem *PMC;
453 volatile U032 __iomem *PRAMIN;
454 volatile U032 __iomem *FIFO;
455 volatile U032 __iomem *CURSOR;
456 volatile U008 __iomem *PCIO0;
457 volatile U008 __iomem *PCIO;
458 volatile U008 __iomem *PVIO;
459 volatile U008 __iomem *PDIO0;
460 volatile U008 __iomem *PDIO;
461 volatile U032 __iomem *PRAMDAC;
462 /*
463 * Common chip functions.
464 */
465 int (*Busy)(struct _riva_hw_inst *);
466 void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int);
467 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
468 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
469 void (*SetStartAddress)(struct _riva_hw_inst *,U032);
470 void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
471 void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
472 int (*ShowHideCursor)(struct _riva_hw_inst *,int);
473 void (*LockUnlock)(struct _riva_hw_inst *, int);
474 /*
475 * Current extended mode settings.
476 */
477 struct _riva_hw_state *CurrentState;
478 /*
479 * FIFO registers.
480 */
481 RivaRop __iomem *Rop;
482 RivaPattern __iomem *Patt;
483 RivaClip __iomem *Clip;
484 RivaPixmap __iomem *Pixmap;
485 RivaScreenBlt __iomem *Blt;
486 RivaBitmap __iomem *Bitmap;
487 RivaLine __iomem *Line;
488 RivaTexturedTriangle03 __iomem *Tri03;
489 RivaTexturedTriangle05 __iomem *Tri05;
490} RIVA_HW_INST;
491/*
492 * Extended mode state information.
493 */
494typedef struct _riva_hw_state
495{
496 U032 bpp;
497 U032 width;
498 U032 height;
499 U032 interlace;
500 U032 repaint0;
501 U032 repaint1;
502 U032 screen;
503 U032 scale;
504 U032 dither;
505 U032 extra;
506 U032 pixel;
507 U032 horiz;
508 U032 arbitration0;
509 U032 arbitration1;
510 U032 vpll;
511 U032 vpll2;
512 U032 pllsel;
513 U032 general;
514 U032 crtcOwner;
515 U032 head;
516 U032 head2;
517 U032 config;
518 U032 cursorConfig;
519 U032 cursor0;
520 U032 cursor1;
521 U032 cursor2;
522 U032 offset0;
523 U032 offset1;
524 U032 offset2;
525 U032 offset3;
526 U032 pitch0;
527 U032 pitch1;
528 U032 pitch2;
529 U032 pitch3;
530} RIVA_HW_STATE;
531/*
532 * External routines.
533 */
534int RivaGetConfig(RIVA_HW_INST *, unsigned int);
535/*
536 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
537 */
538
539#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \
540{ \
541 while ((hwinst).FifoFreeCount < (cnt)) { \
542 mb();mb(); \
543 (hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \
544 } \
545 (hwinst).FifoFreeCount -= (cnt); \
546}
547#endif /* __RIVA_HW_H__ */
548
diff --git a/drivers/video/riva/riva_tbl.h b/drivers/video/riva/riva_tbl.h
new file mode 100644
index 000000000000..7ee7d72932d4
--- /dev/null
+++ b/drivers/video/riva/riva_tbl.h
@@ -0,0 +1,1008 @@
1 /***************************************************************************\
2|* *|
3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45 */
46
47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.9 2002/01/30 01:35:03 mvojkovi Exp $ */
48
49
50/*
51 * RIVA Fixed Functionality Init Tables.
52 */
53static unsigned RivaTablePMC[][2] =
54{
55 {0x00000050, 0x00000000},
56 {0x00000080, 0xFFFF00FF},
57 {0x00000080, 0xFFFFFFFF}
58};
59static unsigned RivaTablePTIMER[][2] =
60{
61 {0x00000080, 0x00000008},
62 {0x00000084, 0x00000003},
63 {0x00000050, 0x00000000},
64 {0x00000040, 0xFFFFFFFF}
65};
66static unsigned RivaTableFIFO[][2] =
67{
68 {0x00000000, 0x80000000},
69 {0x00000800, 0x80000001},
70 {0x00001000, 0x80000002},
71 {0x00001800, 0x80000010},
72 {0x00002000, 0x80000011},
73 {0x00002800, 0x80000012},
74 {0x00003000, 0x80000016},
75 {0x00003800, 0x80000013}
76};
77static unsigned nv3TablePFIFO[][2] =
78{
79 {0x00000140, 0x00000000},
80 {0x00000480, 0x00000000},
81 {0x00000490, 0x00000000},
82 {0x00000494, 0x00000000},
83 {0x00000481, 0x00000000},
84 {0x00000084, 0x00000000},
85 {0x00000086, 0x00002000},
86 {0x00000085, 0x00002200},
87 {0x00000484, 0x00000000},
88 {0x0000049C, 0x00000000},
89 {0x00000104, 0x00000000},
90 {0x00000108, 0x00000000},
91 {0x00000100, 0x00000000},
92 {0x000004A0, 0x00000000},
93 {0x000004A4, 0x00000000},
94 {0x000004A8, 0x00000000},
95 {0x000004AC, 0x00000000},
96 {0x000004B0, 0x00000000},
97 {0x000004B4, 0x00000000},
98 {0x000004B8, 0x00000000},
99 {0x000004BC, 0x00000000},
100 {0x00000050, 0x00000000},
101 {0x00000040, 0xFFFFFFFF},
102 {0x00000480, 0x00000001},
103 {0x00000490, 0x00000001},
104 {0x00000140, 0x00000001}
105};
106static unsigned nv3TablePGRAPH[][2] =
107{
108 {0x00000020, 0x1230001F},
109 {0x00000021, 0x10113000},
110 {0x00000022, 0x1131F101},
111 {0x00000023, 0x0100F531},
112 {0x00000060, 0x00000000},
113 {0x00000065, 0x00000000},
114 {0x00000068, 0x00000000},
115 {0x00000069, 0x00000000},
116 {0x0000006A, 0x00000000},
117 {0x0000006B, 0x00000000},
118 {0x0000006C, 0x00000000},
119 {0x0000006D, 0x00000000},
120 {0x0000006E, 0x00000000},
121 {0x0000006F, 0x00000000},
122 {0x000001A8, 0x00000000},
123 {0x00000440, 0xFFFFFFFF},
124 {0x00000480, 0x00000001},
125 {0x000001A0, 0x00000000},
126 {0x000001A2, 0x00000000},
127 {0x0000018A, 0xFFFFFFFF},
128 {0x00000190, 0x00000000},
129 {0x00000142, 0x00000000},
130 {0x00000154, 0x00000000},
131 {0x00000155, 0xFFFFFFFF},
132 {0x00000156, 0x00000000},
133 {0x00000157, 0xFFFFFFFF},
134 {0x00000064, 0x10010002},
135 {0x00000050, 0x00000000},
136 {0x00000051, 0x00000000},
137 {0x00000040, 0xFFFFFFFF},
138 {0x00000041, 0xFFFFFFFF},
139 {0x00000440, 0xFFFFFFFF},
140 {0x000001A9, 0x00000001}
141};
142static unsigned nv3TablePGRAPH_8BPP[][2] =
143{
144 {0x000001AA, 0x00001111}
145};
146static unsigned nv3TablePGRAPH_15BPP[][2] =
147{
148 {0x000001AA, 0x00002222}
149};
150static unsigned nv3TablePGRAPH_32BPP[][2] =
151{
152 {0x000001AA, 0x00003333}
153};
154static unsigned nv3TablePRAMIN[][2] =
155{
156 {0x00000500, 0x00010000},
157 {0x00000501, 0x007FFFFF},
158 {0x00000200, 0x80000000},
159 {0x00000201, 0x00C20341},
160 {0x00000204, 0x80000001},
161 {0x00000205, 0x00C50342},
162 {0x00000208, 0x80000002},
163 {0x00000209, 0x00C60343},
164 {0x0000020C, 0x80000003},
165 {0x0000020D, 0x00DC0348},
166 {0x00000210, 0x80000004},
167 {0x00000211, 0x00DC0349},
168 {0x00000214, 0x80000005},
169 {0x00000215, 0x00DC034A},
170 {0x00000218, 0x80000006},
171 {0x00000219, 0x00DC034B},
172 {0x00000240, 0x80000010},
173 {0x00000241, 0x00D10344},
174 {0x00000244, 0x80000011},
175 {0x00000245, 0x00D00345},
176 {0x00000248, 0x80000012},
177 {0x00000249, 0x00CC0346},
178 {0x0000024C, 0x80000013},
179 {0x0000024D, 0x00D70347},
180 {0x00000258, 0x80000016},
181 {0x00000259, 0x00CA034C},
182 {0x00000D05, 0x00000000},
183 {0x00000D06, 0x00000000},
184 {0x00000D07, 0x00000000},
185 {0x00000D09, 0x00000000},
186 {0x00000D0A, 0x00000000},
187 {0x00000D0B, 0x00000000},
188 {0x00000D0D, 0x00000000},
189 {0x00000D0E, 0x00000000},
190 {0x00000D0F, 0x00000000},
191 {0x00000D11, 0x00000000},
192 {0x00000D12, 0x00000000},
193 {0x00000D13, 0x00000000},
194 {0x00000D15, 0x00000000},
195 {0x00000D16, 0x00000000},
196 {0x00000D17, 0x00000000},
197 {0x00000D19, 0x00000000},
198 {0x00000D1A, 0x00000000},
199 {0x00000D1B, 0x00000000},
200 {0x00000D1D, 0x00000140},
201 {0x00000D1E, 0x00000000},
202 {0x00000D1F, 0x00000000},
203 {0x00000D20, 0x10100200},
204 {0x00000D21, 0x00000000},
205 {0x00000D22, 0x00000000},
206 {0x00000D23, 0x00000000},
207 {0x00000D24, 0x10210200},
208 {0x00000D25, 0x00000000},
209 {0x00000D26, 0x00000000},
210 {0x00000D27, 0x00000000},
211 {0x00000D28, 0x10420200},
212 {0x00000D29, 0x00000000},
213 {0x00000D2A, 0x00000000},
214 {0x00000D2B, 0x00000000},
215 {0x00000D2C, 0x10830200},
216 {0x00000D2D, 0x00000000},
217 {0x00000D2E, 0x00000000},
218 {0x00000D2F, 0x00000000},
219 {0x00000D31, 0x00000000},
220 {0x00000D32, 0x00000000},
221 {0x00000D33, 0x00000000}
222};
223static unsigned nv3TablePRAMIN_8BPP[][2] =
224{
225 /* 0xXXXXX3XX For MSB mono format */
226 /* 0xXXXXX2XX For LSB mono format */
227 {0x00000D04, 0x10110203},
228 {0x00000D08, 0x10110203},
229 {0x00000D0C, 0x1011020B},
230 {0x00000D10, 0x10118203},
231 {0x00000D14, 0x10110203},
232 {0x00000D18, 0x10110203},
233 {0x00000D1C, 0x10419208},
234 {0x00000D30, 0x10118203}
235};
236static unsigned nv3TablePRAMIN_15BPP[][2] =
237{
238 /* 0xXXXXX2XX For MSB mono format */
239 /* 0xXXXXX3XX For LSB mono format */
240 {0x00000D04, 0x10110200},
241 {0x00000D08, 0x10110200},
242 {0x00000D0C, 0x10110208},
243 {0x00000D10, 0x10118200},
244 {0x00000D14, 0x10110200},
245 {0x00000D18, 0x10110200},
246 {0x00000D1C, 0x10419208},
247 {0x00000D30, 0x10118200}
248};
249static unsigned nv3TablePRAMIN_32BPP[][2] =
250{
251 /* 0xXXXXX3XX For MSB mono format */
252 /* 0xXXXXX2XX For LSB mono format */
253 {0x00000D04, 0x10110201},
254 {0x00000D08, 0x10110201},
255 {0x00000D0C, 0x10110209},
256 {0x00000D10, 0x10118201},
257 {0x00000D14, 0x10110201},
258 {0x00000D18, 0x10110201},
259 {0x00000D1C, 0x10419208},
260 {0x00000D30, 0x10118201}
261};
262static unsigned nv4TableFIFO[][2] =
263{
264 {0x00003800, 0x80000014}
265};
266static unsigned nv4TablePFIFO[][2] =
267{
268 {0x00000140, 0x00000000},
269 {0x00000480, 0x00000000},
270 {0x00000494, 0x00000000},
271 {0x00000481, 0x00000000},
272 {0x0000048B, 0x00000000},
273 {0x00000400, 0x00000000},
274 {0x00000414, 0x00000000},
275 {0x00000084, 0x03000100},
276 {0x00000085, 0x00000110},
277 {0x00000086, 0x00000112},
278 {0x00000143, 0x0000FFFF},
279 {0x00000496, 0x0000FFFF},
280 {0x00000050, 0x00000000},
281 {0x00000040, 0xFFFFFFFF},
282 {0x00000415, 0x00000001},
283 {0x00000480, 0x00000001},
284 {0x00000494, 0x00000001},
285 {0x00000495, 0x00000001},
286 {0x00000140, 0x00000001}
287};
288static unsigned nv4TablePGRAPH[][2] =
289{
290 {0x00000020, 0x1231C001},
291 {0x00000021, 0x72111101},
292 {0x00000022, 0x11D5F071},
293 {0x00000023, 0x10D4FF31},
294 {0x00000060, 0x00000000},
295 {0x00000068, 0x00000000},
296 {0x00000070, 0x00000000},
297 {0x00000078, 0x00000000},
298 {0x00000061, 0x00000000},
299 {0x00000069, 0x00000000},
300 {0x00000071, 0x00000000},
301 {0x00000079, 0x00000000},
302 {0x00000062, 0x00000000},
303 {0x0000006A, 0x00000000},
304 {0x00000072, 0x00000000},
305 {0x0000007A, 0x00000000},
306 {0x00000063, 0x00000000},
307 {0x0000006B, 0x00000000},
308 {0x00000073, 0x00000000},
309 {0x0000007B, 0x00000000},
310 {0x00000064, 0x00000000},
311 {0x0000006C, 0x00000000},
312 {0x00000074, 0x00000000},
313 {0x0000007C, 0x00000000},
314 {0x00000065, 0x00000000},
315 {0x0000006D, 0x00000000},
316 {0x00000075, 0x00000000},
317 {0x0000007D, 0x00000000},
318 {0x00000066, 0x00000000},
319 {0x0000006E, 0x00000000},
320 {0x00000076, 0x00000000},
321 {0x0000007E, 0x00000000},
322 {0x00000067, 0x00000000},
323 {0x0000006F, 0x00000000},
324 {0x00000077, 0x00000000},
325 {0x0000007F, 0x00000000},
326 {0x00000058, 0x00000000},
327 {0x00000059, 0x00000000},
328 {0x0000005A, 0x00000000},
329 {0x0000005B, 0x00000000},
330 {0x00000196, 0x00000000},
331 {0x000001A1, 0x01FFFFFF},
332 {0x00000197, 0x00000000},
333 {0x000001A2, 0x01FFFFFF},
334 {0x00000198, 0x00000000},
335 {0x000001A3, 0x01FFFFFF},
336 {0x00000199, 0x00000000},
337 {0x000001A4, 0x01FFFFFF},
338 {0x00000050, 0x00000000},
339 {0x00000040, 0xFFFFFFFF},
340 {0x0000005C, 0x10010100},
341 {0x000001C4, 0xFFFFFFFF},
342 {0x000001C8, 0x00000001},
343 {0x00000204, 0x00000000},
344 {0x000001C3, 0x00000001}
345};
346static unsigned nv4TablePGRAPH_8BPP[][2] =
347{
348 {0x000001C9, 0x00111111},
349 {0x00000186, 0x00001010},
350 {0x0000020C, 0x03020202}
351};
352static unsigned nv4TablePGRAPH_15BPP[][2] =
353{
354 {0x000001C9, 0x00226222},
355 {0x00000186, 0x00002071},
356 {0x0000020C, 0x09080808}
357};
358static unsigned nv4TablePGRAPH_16BPP[][2] =
359{
360 {0x000001C9, 0x00556555},
361 {0x00000186, 0x000050C2},
362 {0x0000020C, 0x0C0B0B0B}
363};
364static unsigned nv4TablePGRAPH_32BPP[][2] =
365{
366 {0x000001C9, 0x0077D777},
367 {0x00000186, 0x000070E5},
368 {0x0000020C, 0x0E0D0D0D}
369};
370static unsigned nv4TablePRAMIN[][2] =
371{
372 {0x00000000, 0x80000010},
373 {0x00000001, 0x80011145},
374 {0x00000002, 0x80000011},
375 {0x00000003, 0x80011146},
376 {0x00000004, 0x80000012},
377 {0x00000005, 0x80011147},
378 {0x00000006, 0x80000013},
379 {0x00000007, 0x80011148},
380 {0x00000008, 0x80000014},
381 {0x00000009, 0x80011149},
382 {0x0000000A, 0x80000015},
383 {0x0000000B, 0x8001114A},
384 {0x0000000C, 0x80000016},
385 {0x0000000D, 0x8001114F},
386 {0x00000020, 0x80000000},
387 {0x00000021, 0x80011142},
388 {0x00000022, 0x80000001},
389 {0x00000023, 0x80011143},
390 {0x00000024, 0x80000002},
391 {0x00000025, 0x80011144},
392 {0x00000026, 0x80000003},
393 {0x00000027, 0x8001114B},
394 {0x00000028, 0x80000004},
395 {0x00000029, 0x8001114C},
396 {0x0000002A, 0x80000005},
397 {0x0000002B, 0x8001114D},
398 {0x0000002C, 0x80000006},
399 {0x0000002D, 0x8001114E},
400 {0x00000500, 0x00003000},
401 {0x00000501, 0x01FFFFFF},
402 {0x00000502, 0x00000002},
403 {0x00000503, 0x00000002},
404 {0x00000508, 0x01008043},
405 {0x0000050A, 0x00000000},
406 {0x0000050B, 0x00000000},
407 {0x0000050C, 0x01008019},
408 {0x0000050E, 0x00000000},
409 {0x0000050F, 0x00000000},
410#if 1
411 {0x00000510, 0x01008018},
412#else
413 {0x00000510, 0x01008044},
414#endif
415 {0x00000512, 0x00000000},
416 {0x00000513, 0x00000000},
417 {0x00000514, 0x01008021},
418 {0x00000516, 0x00000000},
419 {0x00000517, 0x00000000},
420 {0x00000518, 0x0100805F},
421 {0x0000051A, 0x00000000},
422 {0x0000051B, 0x00000000},
423#if 1
424 {0x0000051C, 0x0100804B},
425#else
426 {0x0000051C, 0x0100804A},
427#endif
428 {0x0000051E, 0x00000000},
429 {0x0000051F, 0x00000000},
430 {0x00000520, 0x0100A048},
431 {0x00000521, 0x00000D01},
432 {0x00000522, 0x11401140},
433 {0x00000523, 0x00000000},
434 {0x00000524, 0x0300A054},
435 {0x00000525, 0x00000D01},
436 {0x00000526, 0x11401140},
437 {0x00000527, 0x00000000},
438 {0x00000528, 0x0300A055},
439 {0x00000529, 0x00000D01},
440 {0x0000052A, 0x11401140},
441 {0x0000052B, 0x00000000},
442 {0x0000052C, 0x00000058},
443 {0x0000052E, 0x11401140},
444 {0x0000052F, 0x00000000},
445 {0x00000530, 0x00000059},
446 {0x00000532, 0x11401140},
447 {0x00000533, 0x00000000},
448 {0x00000534, 0x0000005A},
449 {0x00000536, 0x11401140},
450 {0x00000537, 0x00000000},
451 {0x00000538, 0x0000005B},
452 {0x0000053A, 0x11401140},
453 {0x0000053B, 0x00000000},
454 {0x0000053C, 0x0300A01C},
455 {0x0000053E, 0x11401140},
456 {0x0000053F, 0x00000000}
457};
458static unsigned nv4TablePRAMIN_8BPP[][2] =
459{
460 /* 0xXXXXXX01 For MSB mono format */
461 /* 0xXXXXXX02 For LSB mono format */
462 {0x00000509, 0x00000302},
463 {0x0000050D, 0x00000302},
464 {0x00000511, 0x00000202},
465 {0x00000515, 0x00000302},
466 {0x00000519, 0x00000302},
467 {0x0000051D, 0x00000302},
468 {0x0000052D, 0x00000302},
469 {0x0000052E, 0x00000302},
470 {0x00000535, 0x00000000},
471 {0x00000539, 0x00000000},
472 {0x0000053D, 0x00000302}
473};
474static unsigned nv4TablePRAMIN_15BPP[][2] =
475{
476 /* 0xXXXXXX01 For MSB mono format */
477 /* 0xXXXXXX02 For LSB mono format */
478 {0x00000509, 0x00000902},
479 {0x0000050D, 0x00000902},
480 {0x00000511, 0x00000802},
481 {0x00000515, 0x00000902},
482 {0x00000519, 0x00000902},
483 {0x0000051D, 0x00000902},
484 {0x0000052D, 0x00000902},
485 {0x0000052E, 0x00000902},
486 {0x00000535, 0x00000702},
487 {0x00000539, 0x00000702},
488 {0x0000053D, 0x00000902}
489};
490static unsigned nv4TablePRAMIN_16BPP[][2] =
491{
492 /* 0xXXXXXX01 For MSB mono format */
493 /* 0xXXXXXX02 For LSB mono format */
494 {0x00000509, 0x00000C02},
495 {0x0000050D, 0x00000C02},
496 {0x00000511, 0x00000B02},
497 {0x00000515, 0x00000C02},
498 {0x00000519, 0x00000C02},
499 {0x0000051D, 0x00000C02},
500 {0x0000052D, 0x00000C02},
501 {0x0000052E, 0x00000C02},
502 {0x00000535, 0x00000702},
503 {0x00000539, 0x00000702},
504 {0x0000053D, 0x00000C02}
505};
506static unsigned nv4TablePRAMIN_32BPP[][2] =
507{
508 /* 0xXXXXXX01 For MSB mono format */
509 /* 0xXXXXXX02 For LSB mono format */
510 {0x00000509, 0x00000E02},
511 {0x0000050D, 0x00000E02},
512 {0x00000511, 0x00000D02},
513 {0x00000515, 0x00000E02},
514 {0x00000519, 0x00000E02},
515 {0x0000051D, 0x00000E02},
516 {0x0000052D, 0x00000E02},
517 {0x0000052E, 0x00000E02},
518 {0x00000535, 0x00000E02},
519 {0x00000539, 0x00000E02},
520 {0x0000053D, 0x00000E02}
521};
522static unsigned nv10TableFIFO[][2] =
523{
524 {0x00003800, 0x80000014}
525};
526static unsigned nv10TablePFIFO[][2] =
527{
528 {0x00000140, 0x00000000},
529 {0x00000480, 0x00000000},
530 {0x00000494, 0x00000000},
531 {0x00000481, 0x00000000},
532 {0x0000048B, 0x00000000},
533 {0x00000400, 0x00000000},
534 {0x00000414, 0x00000000},
535 {0x00000084, 0x03000100},
536 {0x00000085, 0x00000110},
537 {0x00000086, 0x00000112},
538 {0x00000143, 0x0000FFFF},
539 {0x00000496, 0x0000FFFF},
540 {0x00000050, 0x00000000},
541 {0x00000040, 0xFFFFFFFF},
542 {0x00000415, 0x00000001},
543 {0x00000480, 0x00000001},
544 {0x00000494, 0x00000001},
545 {0x00000495, 0x00000001},
546 {0x00000140, 0x00000001}
547};
548static unsigned nv10TablePGRAPH[][2] =
549{
550 {0x00000020, 0x0003FFFF},
551 {0x00000021, 0x00118701},
552 {0x00000022, 0x24F82AD9},
553 {0x00000023, 0x55DE0030},
554 {0x00000020, 0x00000000},
555 {0x00000024, 0x00000000},
556 {0x00000058, 0x00000000},
557 {0x00000060, 0x00000000},
558 {0x00000068, 0x00000000},
559 {0x00000070, 0x00000000},
560 {0x00000078, 0x00000000},
561 {0x00000059, 0x00000000},
562 {0x00000061, 0x00000000},
563 {0x00000069, 0x00000000},
564 {0x00000071, 0x00000000},
565 {0x00000079, 0x00000000},
566 {0x0000005A, 0x00000000},
567 {0x00000062, 0x00000000},
568 {0x0000006A, 0x00000000},
569 {0x00000072, 0x00000000},
570 {0x0000007A, 0x00000000},
571 {0x0000005B, 0x00000000},
572 {0x00000063, 0x00000000},
573 {0x0000006B, 0x00000000},
574 {0x00000073, 0x00000000},
575 {0x0000007B, 0x00000000},
576 {0x0000005C, 0x00000000},
577 {0x00000064, 0x00000000},
578 {0x0000006C, 0x00000000},
579 {0x00000074, 0x00000000},
580 {0x0000007C, 0x00000000},
581 {0x0000005D, 0x00000000},
582 {0x00000065, 0x00000000},
583 {0x0000006D, 0x00000000},
584 {0x00000075, 0x00000000},
585 {0x0000007D, 0x00000000},
586 {0x0000005E, 0x00000000},
587 {0x00000066, 0x00000000},
588 {0x0000006E, 0x00000000},
589 {0x00000076, 0x00000000},
590 {0x0000007E, 0x00000000},
591 {0x0000005F, 0x00000000},
592 {0x00000067, 0x00000000},
593 {0x0000006F, 0x00000000},
594 {0x00000077, 0x00000000},
595 {0x0000007F, 0x00000000},
596 {0x00000053, 0x00000000},
597 {0x00000054, 0x00000000},
598 {0x00000055, 0x00000000},
599 {0x00000056, 0x00000000},
600 {0x00000057, 0x00000000},
601 {0x00000196, 0x00000000},
602 {0x000001A1, 0x01FFFFFF},
603 {0x00000197, 0x00000000},
604 {0x000001A2, 0x01FFFFFF},
605 {0x00000198, 0x00000000},
606 {0x000001A3, 0x01FFFFFF},
607 {0x00000199, 0x00000000},
608 {0x000001A4, 0x01FFFFFF},
609 {0x0000019A, 0x00000000},
610 {0x000001A5, 0x01FFFFFF},
611 {0x0000019B, 0x00000000},
612 {0x000001A6, 0x01FFFFFF},
613 {0x00000050, 0x01111111},
614 {0x00000040, 0xFFFFFFFF},
615 {0x00000051, 0x10010100},
616 {0x000001C5, 0xFFFFFFFF},
617 {0x000001C8, 0x00000001},
618 {0x00000204, 0x00000000},
619 {0x000001C4, 0x00000001}
620};
621static unsigned nv10TablePGRAPH_8BPP[][2] =
622{
623 {0x000001C9, 0x00111111},
624 {0x00000186, 0x00001010},
625 {0x0000020C, 0x03020202}
626};
627static unsigned nv10TablePGRAPH_15BPP[][2] =
628{
629 {0x000001C9, 0x00226222},
630 {0x00000186, 0x00002071},
631 {0x0000020C, 0x09080808}
632};
633static unsigned nv10TablePGRAPH_16BPP[][2] =
634{
635 {0x000001C9, 0x00556555},
636 {0x00000186, 0x000050C2},
637 {0x0000020C, 0x000B0B0C}
638};
639static unsigned nv10TablePGRAPH_32BPP[][2] =
640{
641 {0x000001C9, 0x0077D777},
642 {0x00000186, 0x000070E5},
643 {0x0000020C, 0x0E0D0D0D}
644};
645static unsigned nv10tri05TablePGRAPH[][2] =
646{
647 {(0x00000E00/4), 0x00000000},
648 {(0x00000E04/4), 0x00000000},
649 {(0x00000E08/4), 0x00000000},
650 {(0x00000E0C/4), 0x00000000},
651 {(0x00000E10/4), 0x00001000},
652 {(0x00000E14/4), 0x00001000},
653 {(0x00000E18/4), 0x4003ff80},
654 {(0x00000E1C/4), 0x00000000},
655 {(0x00000E20/4), 0x00000000},
656 {(0x00000E24/4), 0x00000000},
657 {(0x00000E28/4), 0x00000000},
658 {(0x00000E2C/4), 0x00000000},
659 {(0x00000E30/4), 0x00080008},
660 {(0x00000E34/4), 0x00080008},
661 {(0x00000E38/4), 0x00000000},
662 {(0x00000E3C/4), 0x00000000},
663 {(0x00000E40/4), 0x00000000},
664 {(0x00000E44/4), 0x00000000},
665 {(0x00000E48/4), 0x00000000},
666 {(0x00000E4C/4), 0x00000000},
667 {(0x00000E50/4), 0x00000000},
668 {(0x00000E54/4), 0x00000000},
669 {(0x00000E58/4), 0x00000000},
670 {(0x00000E5C/4), 0x00000000},
671 {(0x00000E60/4), 0x00000000},
672 {(0x00000E64/4), 0x10000000},
673 {(0x00000E68/4), 0x00000000},
674 {(0x00000E6C/4), 0x00000000},
675 {(0x00000E70/4), 0x00000000},
676 {(0x00000E74/4), 0x00000000},
677 {(0x00000E78/4), 0x00000000},
678 {(0x00000E7C/4), 0x00000000},
679 {(0x00000E80/4), 0x00000000},
680 {(0x00000E84/4), 0x00000000},
681 {(0x00000E88/4), 0x08000000},
682 {(0x00000E8C/4), 0x00000000},
683 {(0x00000E90/4), 0x00000000},
684 {(0x00000E94/4), 0x00000000},
685 {(0x00000E98/4), 0x00000000},
686 {(0x00000E9C/4), 0x4B7FFFFF},
687 {(0x00000EA0/4), 0x00000000},
688 {(0x00000EA4/4), 0x00000000},
689 {(0x00000EA8/4), 0x00000000},
690 {(0x00000F00/4), 0x07FF0800},
691 {(0x00000F04/4), 0x07FF0800},
692 {(0x00000F08/4), 0x07FF0800},
693 {(0x00000F0C/4), 0x07FF0800},
694 {(0x00000F10/4), 0x07FF0800},
695 {(0x00000F14/4), 0x07FF0800},
696 {(0x00000F18/4), 0x07FF0800},
697 {(0x00000F1C/4), 0x07FF0800},
698 {(0x00000F20/4), 0x07FF0800},
699 {(0x00000F24/4), 0x07FF0800},
700 {(0x00000F28/4), 0x07FF0800},
701 {(0x00000F2C/4), 0x07FF0800},
702 {(0x00000F30/4), 0x07FF0800},
703 {(0x00000F34/4), 0x07FF0800},
704 {(0x00000F38/4), 0x07FF0800},
705 {(0x00000F3C/4), 0x07FF0800},
706 {(0x00000F40/4), 0x10000000},
707 {(0x00000F44/4), 0x00000000},
708 {(0x00000F50/4), 0x00006740},
709 {(0x00000F54/4), 0x00000000},
710 {(0x00000F54/4), 0x00000000},
711 {(0x00000F54/4), 0x00000000},
712 {(0x00000F54/4), 0x3F800000},
713 {(0x00000F50/4), 0x00006750},
714 {(0x00000F54/4), 0x40000000},
715 {(0x00000F54/4), 0x40000000},
716 {(0x00000F54/4), 0x40000000},
717 {(0x00000F54/4), 0x40000000},
718 {(0x00000F50/4), 0x00006760},
719 {(0x00000F54/4), 0x00000000},
720 {(0x00000F54/4), 0x00000000},
721 {(0x00000F54/4), 0x3F800000},
722 {(0x00000F54/4), 0x00000000},
723 {(0x00000F50/4), 0x00006770},
724 {(0x00000F54/4), 0xC5000000},
725 {(0x00000F54/4), 0xC5000000},
726 {(0x00000F54/4), 0x00000000},
727 {(0x00000F54/4), 0x00000000},
728 {(0x00000F50/4), 0x00006780},
729 {(0x00000F54/4), 0x00000000},
730 {(0x00000F54/4), 0x00000000},
731 {(0x00000F54/4), 0x3F800000},
732 {(0x00000F54/4), 0x00000000},
733 {(0x00000F50/4), 0x000067A0},
734 {(0x00000F54/4), 0x3F800000},
735 {(0x00000F54/4), 0x3F800000},
736 {(0x00000F54/4), 0x3F800000},
737 {(0x00000F54/4), 0x3F800000},
738 {(0x00000F50/4), 0x00006AB0},
739 {(0x00000F54/4), 0x3F800000},
740 {(0x00000F54/4), 0x3F800000},
741 {(0x00000F54/4), 0x3F800000},
742 {(0x00000F50/4), 0x00006AC0},
743 {(0x00000F54/4), 0x00000000},
744 {(0x00000F54/4), 0x00000000},
745 {(0x00000F54/4), 0x00000000},
746 {(0x00000F50/4), 0x00006C10},
747 {(0x00000F54/4), 0xBF800000},
748 {(0x00000F50/4), 0x00007030},
749 {(0x00000F54/4), 0x7149F2CA},
750 {(0x00000F50/4), 0x00007040},
751 {(0x00000F54/4), 0x7149F2CA},
752 {(0x00000F50/4), 0x00007050},
753 {(0x00000F54/4), 0x7149F2CA},
754 {(0x00000F50/4), 0x00007060},
755 {(0x00000F54/4), 0x7149F2CA},
756 {(0x00000F50/4), 0x00007070},
757 {(0x00000F54/4), 0x7149F2CA},
758 {(0x00000F50/4), 0x00007080},
759 {(0x00000F54/4), 0x7149F2CA},
760 {(0x00000F50/4), 0x00007090},
761 {(0x00000F54/4), 0x7149F2CA},
762 {(0x00000F50/4), 0x000070A0},
763 {(0x00000F54/4), 0x7149F2CA},
764 {(0x00000F50/4), 0x00006A80},
765 {(0x00000F54/4), 0x00000000},
766 {(0x00000F54/4), 0x00000000},
767 {(0x00000F54/4), 0x3F800000},
768 {(0x00000F50/4), 0x00006AA0},
769 {(0x00000F54/4), 0x00000000},
770 {(0x00000F54/4), 0x00000000},
771 {(0x00000F54/4), 0x00000000},
772 {(0x00000F50/4), 0x00000040},
773 {(0x00000F54/4), 0x00000005},
774 {(0x00000F50/4), 0x00006400},
775 {(0x00000F54/4), 0x3F800000},
776 {(0x00000F54/4), 0x3F800000},
777 {(0x00000F54/4), 0x4B7FFFFF},
778 {(0x00000F54/4), 0x00000000},
779 {(0x00000F50/4), 0x00006410},
780 {(0x00000F54/4), 0xC5000000},
781 {(0x00000F54/4), 0xC5000000},
782 {(0x00000F54/4), 0x00000000},
783 {(0x00000F54/4), 0x00000000},
784 {(0x00000F50/4), 0x00006420},
785 {(0x00000F54/4), 0x00000000},
786 {(0x00000F54/4), 0x00000000},
787 {(0x00000F54/4), 0x00000000},
788 {(0x00000F54/4), 0x00000000},
789 {(0x00000F50/4), 0x00006430},
790 {(0x00000F54/4), 0x00000000},
791 {(0x00000F54/4), 0x00000000},
792 {(0x00000F54/4), 0x00000000},
793 {(0x00000F54/4), 0x00000000},
794 {(0x00000F50/4), 0x000064C0},
795 {(0x00000F54/4), 0x3F800000},
796 {(0x00000F54/4), 0x3F800000},
797 {(0x00000F54/4), 0x477FFFFF},
798 {(0x00000F54/4), 0x3F800000},
799 {(0x00000F50/4), 0x000064D0},
800 {(0x00000F54/4), 0xC5000000},
801 {(0x00000F54/4), 0xC5000000},
802 {(0x00000F54/4), 0x00000000},
803 {(0x00000F54/4), 0x00000000},
804 {(0x00000F50/4), 0x000064E0},
805 {(0x00000F54/4), 0xC4FFF000},
806 {(0x00000F54/4), 0xC4FFF000},
807 {(0x00000F54/4), 0x00000000},
808 {(0x00000F54/4), 0x00000000},
809 {(0x00000F50/4), 0x000064F0},
810 {(0x00000F54/4), 0x00000000},
811 {(0x00000F54/4), 0x00000000},
812 {(0x00000F54/4), 0x00000000},
813 {(0x00000F54/4), 0x00000000},
814 {(0x00000F40/4), 0x30000000},
815 {(0x00000F44/4), 0x00000004},
816 {(0x00000F48/4), 0x10000000},
817 {(0x00000F4C/4), 0x00000000}
818};
819static unsigned nv10TablePRAMIN[][2] =
820{
821 {0x00000000, 0x80000010},
822 {0x00000001, 0x80011145},
823 {0x00000002, 0x80000011},
824 {0x00000003, 0x80011146},
825 {0x00000004, 0x80000012},
826 {0x00000005, 0x80011147},
827 {0x00000006, 0x80000013},
828 {0x00000007, 0x80011148},
829 {0x00000008, 0x80000014},
830 {0x00000009, 0x80011149},
831 {0x0000000A, 0x80000015},
832 {0x0000000B, 0x8001114A},
833 {0x0000000C, 0x80000016},
834 {0x0000000D, 0x80011150},
835 {0x00000020, 0x80000000},
836 {0x00000021, 0x80011142},
837 {0x00000022, 0x80000001},
838 {0x00000023, 0x80011143},
839 {0x00000024, 0x80000002},
840 {0x00000025, 0x80011144},
841 {0x00000026, 0x80000003},
842 {0x00000027, 0x8001114B},
843 {0x00000028, 0x80000004},
844 {0x00000029, 0x8001114C},
845 {0x0000002A, 0x80000005},
846 {0x0000002B, 0x8001114D},
847 {0x0000002C, 0x80000006},
848 {0x0000002D, 0x8001114E},
849 {0x0000002E, 0x80000007},
850 {0x0000002F, 0x8001114F},
851 {0x00000500, 0x00003000},
852 {0x00000501, 0x01FFFFFF},
853 {0x00000502, 0x00000002},
854 {0x00000503, 0x00000002},
855#ifdef __BIG_ENDIAN
856 {0x00000508, 0x01088043},
857#else
858 {0x00000508, 0x01008043},
859#endif
860 {0x0000050A, 0x00000000},
861 {0x0000050B, 0x00000000},
862#ifdef __BIG_ENDIAN
863 {0x0000050C, 0x01088019},
864#else
865 {0x0000050C, 0x01008019},
866#endif
867 {0x0000050E, 0x00000000},
868 {0x0000050F, 0x00000000},
869#ifdef __BIG_ENDIAN
870 {0x00000510, 0x01088018},
871#else
872 {0x00000510, 0x01008018},
873#endif
874 {0x00000512, 0x00000000},
875 {0x00000513, 0x00000000},
876#ifdef __BIG_ENDIAN
877 {0x00000514, 0x01088021},
878#else
879 {0x00000514, 0x01008021},
880#endif
881 {0x00000516, 0x00000000},
882 {0x00000517, 0x00000000},
883#ifdef __BIG_ENDIAN
884 {0x00000518, 0x0108805F},
885#else
886 {0x00000518, 0x0100805F},
887#endif
888 {0x0000051A, 0x00000000},
889 {0x0000051B, 0x00000000},
890#ifdef __BIG_ENDIAN
891 {0x0000051C, 0x0108804B},
892#else
893 {0x0000051C, 0x0100804B},
894#endif
895 {0x0000051E, 0x00000000},
896 {0x0000051F, 0x00000000},
897 {0x00000520, 0x0100A048},
898 {0x00000521, 0x00000D01},
899 {0x00000522, 0x11401140},
900 {0x00000523, 0x00000000},
901 {0x00000524, 0x0300A094},
902 {0x00000525, 0x00000D01},
903 {0x00000526, 0x11401140},
904 {0x00000527, 0x00000000},
905 {0x00000528, 0x0300A095},
906 {0x00000529, 0x00000D01},
907 {0x0000052A, 0x11401140},
908 {0x0000052B, 0x00000000},
909#ifdef __BIG_ENDIAN
910 {0x0000052C, 0x00080058},
911#else
912 {0x0000052C, 0x00000058},
913#endif
914 {0x0000052E, 0x11401140},
915 {0x0000052F, 0x00000000},
916#ifdef __BIG_ENDIAN
917 {0x00000530, 0x00080059},
918#else
919 {0x00000530, 0x00000059},
920#endif
921 {0x00000532, 0x11401140},
922 {0x00000533, 0x00000000},
923 {0x00000534, 0x0000005A},
924 {0x00000536, 0x11401140},
925 {0x00000537, 0x00000000},
926 {0x00000538, 0x0000005B},
927 {0x0000053A, 0x11401140},
928 {0x0000053B, 0x00000000},
929 {0x0000053C, 0x00000093},
930 {0x0000053E, 0x11401140},
931 {0x0000053F, 0x00000000},
932#ifdef __BIG_ENDIAN
933 {0x00000540, 0x0308A01C},
934#else
935 {0x00000540, 0x0300A01C},
936#endif
937 {0x00000542, 0x11401140},
938 {0x00000543, 0x00000000}
939};
940static unsigned nv10TablePRAMIN_8BPP[][2] =
941{
942 /* 0xXXXXXX01 For MSB mono format */
943 /* 0xXXXXXX02 For LSB mono format */
944 {0x00000509, 0x00000302},
945 {0x0000050D, 0x00000302},
946 {0x00000511, 0x00000202},
947 {0x00000515, 0x00000302},
948 {0x00000519, 0x00000302},
949 {0x0000051D, 0x00000302},
950 {0x0000052D, 0x00000302},
951 {0x0000052E, 0x00000302},
952 {0x00000535, 0x00000000},
953 {0x00000539, 0x00000000},
954 {0x0000053D, 0x00000000},
955 {0x00000541, 0x00000302}
956};
957static unsigned nv10TablePRAMIN_15BPP[][2] =
958{
959 /* 0xXXXXXX01 For MSB mono format */
960 /* 0xXXXXXX02 For LSB mono format */
961 {0x00000509, 0x00000902},
962 {0x0000050D, 0x00000902},
963 {0x00000511, 0x00000802},
964 {0x00000515, 0x00000902},
965 {0x00000519, 0x00000902},
966 {0x0000051D, 0x00000902},
967 {0x0000052D, 0x00000902},
968 {0x0000052E, 0x00000902},
969 {0x00000535, 0x00000902},
970 {0x00000539, 0x00000902},
971 {0x0000053D, 0x00000902},
972 {0x00000541, 0x00000902}
973};
974static unsigned nv10TablePRAMIN_16BPP[][2] =
975{
976 /* 0xXXXXXX01 For MSB mono format */
977 /* 0xXXXXXX02 For LSB mono format */
978 {0x00000509, 0x00000C02},
979 {0x0000050D, 0x00000C02},
980 {0x00000511, 0x00000B02},
981 {0x00000515, 0x00000C02},
982 {0x00000519, 0x00000C02},
983 {0x0000051D, 0x00000C02},
984 {0x0000052D, 0x00000C02},
985 {0x0000052E, 0x00000C02},
986 {0x00000535, 0x00000C02},
987 {0x00000539, 0x00000C02},
988 {0x0000053D, 0x00000C02},
989 {0x00000541, 0x00000C02}
990};
991static unsigned nv10TablePRAMIN_32BPP[][2] =
992{
993 /* 0xXXXXXX01 For MSB mono format */
994 /* 0xXXXXXX02 For LSB mono format */
995 {0x00000509, 0x00000E02},
996 {0x0000050D, 0x00000E02},
997 {0x00000511, 0x00000D02},
998 {0x00000515, 0x00000E02},
999 {0x00000519, 0x00000E02},
1000 {0x0000051D, 0x00000E02},
1001 {0x0000052D, 0x00000E02},
1002 {0x0000052E, 0x00000E02},
1003 {0x00000535, 0x00000E02},
1004 {0x00000539, 0x00000E02},
1005 {0x0000053D, 0x00000E02},
1006 {0x00000541, 0x00000E02}
1007};
1008
diff --git a/drivers/video/riva/rivafb-i2c.c b/drivers/video/riva/rivafb-i2c.c
new file mode 100644
index 000000000000..da1334dfd51d
--- /dev/null
+++ b/drivers/video/riva/rivafb-i2c.c
@@ -0,0 +1,214 @@
1/*
2 * linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
7 *
8 * Based on radeonfb-i2c.c
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15#include <linux/config.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/sched.h>
19#include <linux/delay.h>
20#include <linux/pci.h>
21#include <linux/fb.h>
22#include <linux/jiffies.h>
23
24#include <asm/io.h>
25
26#include "rivafb.h"
27#include "../edid.h"
28
29#define RIVA_DDC 0x50
30
31static void riva_gpio_setscl(void* data, int state)
32{
33 struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
34 struct riva_par *par = chan->par;
35 u32 val;
36
37 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
38 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
39
40 if (state)
41 val |= 0x20;
42 else
43 val &= ~0x20;
44
45 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
46 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
47}
48
49static void riva_gpio_setsda(void* data, int state)
50{
51 struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
52 struct riva_par *par = chan->par;
53 u32 val;
54
55 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
56 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
57
58 if (state)
59 val |= 0x10;
60 else
61 val &= ~0x10;
62
63 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
64 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
65}
66
67static int riva_gpio_getscl(void* data)
68{
69 struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
70 struct riva_par *par = chan->par;
71 u32 val = 0;
72
73 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
74 if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04)
75 val = 1;
76
77 val = VGA_RD08(par->riva.PCIO, 0x3d5);
78
79 return val;
80}
81
82static int riva_gpio_getsda(void* data)
83{
84 struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
85 struct riva_par *par = chan->par;
86 u32 val = 0;
87
88 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
89 if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08)
90 val = 1;
91
92 return val;
93}
94
95#define I2C_ALGO_RIVA 0x0e0000
96static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name)
97{
98 int rc;
99
100 strcpy(chan->adapter.name, name);
101 chan->adapter.owner = THIS_MODULE;
102 chan->adapter.id = I2C_ALGO_RIVA;
103 chan->adapter.algo_data = &chan->algo;
104 chan->adapter.dev.parent = &chan->par->pdev->dev;
105 chan->algo.setsda = riva_gpio_setsda;
106 chan->algo.setscl = riva_gpio_setscl;
107 chan->algo.getsda = riva_gpio_getsda;
108 chan->algo.getscl = riva_gpio_getscl;
109 chan->algo.udelay = 40;
110 chan->algo.timeout = msecs_to_jiffies(2);
111 chan->algo.data = chan;
112
113 i2c_set_adapdata(&chan->adapter, chan);
114
115 /* Raise SCL and SDA */
116 riva_gpio_setsda(chan, 1);
117 riva_gpio_setscl(chan, 1);
118 udelay(20);
119
120 rc = i2c_bit_add_bus(&chan->adapter);
121 if (rc == 0)
122 dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name);
123 else {
124 dev_warn(&chan->par->pdev->dev,
125 "Failed to register I2C bus %s.\n", name);
126 chan->par = NULL;
127 }
128
129 return rc;
130}
131
132void riva_create_i2c_busses(struct riva_par *par)
133{
134 par->bus = 3;
135
136 par->chan[0].par = par;
137 par->chan[1].par = par;
138 par->chan[2].par = par;
139
140 par->chan[0].ddc_base = 0x3e;
141 par->chan[1].ddc_base = 0x36;
142 par->chan[2].ddc_base = 0x50;
143 riva_setup_i2c_bus(&par->chan[0], "BUS1");
144 riva_setup_i2c_bus(&par->chan[1], "BUS2");
145 riva_setup_i2c_bus(&par->chan[2], "BUS3");
146}
147
148void riva_delete_i2c_busses(struct riva_par *par)
149{
150 if (par->chan[0].par)
151 i2c_bit_del_bus(&par->chan[0].adapter);
152 par->chan[0].par = NULL;
153
154 if (par->chan[1].par)
155 i2c_bit_del_bus(&par->chan[1].adapter);
156 par->chan[1].par = NULL;
157
158 if (par->chan[2].par)
159 i2c_bit_del_bus(&par->chan[2].adapter);
160 par->chan[2].par = NULL;
161}
162
163static u8 *riva_do_probe_i2c_edid(struct riva_i2c_chan *chan)
164{
165 u8 start = 0x0;
166 struct i2c_msg msgs[] = {
167 {
168 .addr = RIVA_DDC,
169 .len = 1,
170 .buf = &start,
171 }, {
172 .addr = RIVA_DDC,
173 .flags = I2C_M_RD,
174 .len = EDID_LENGTH,
175 },
176 };
177 u8 *buf;
178
179 if (!chan->par)
180 return NULL;
181
182 buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
183 if (!buf) {
184 dev_warn(&chan->par->pdev->dev, "Out of memory!\n");
185 return NULL;
186 }
187 msgs[1].buf = buf;
188
189 if (i2c_transfer(&chan->adapter, msgs, 2) == 2)
190 return buf;
191 dev_dbg(&chan->par->pdev->dev, "Unable to read EDID block.\n");
192 kfree(buf);
193 return NULL;
194}
195
196int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid)
197{
198 u8 *edid = NULL;
199 int i;
200
201 for (i = 0; i < 3; i++) {
202 /* Do the real work */
203 edid = riva_do_probe_i2c_edid(&par->chan[conn-1]);
204 if (edid)
205 break;
206 }
207 if (out_edid)
208 *out_edid = edid;
209 if (!edid)
210 return 1;
211
212 return 0;
213}
214
diff --git a/drivers/video/riva/rivafb.h b/drivers/video/riva/rivafb.h
new file mode 100644
index 000000000000..440ff445689b
--- /dev/null
+++ b/drivers/video/riva/rivafb.h
@@ -0,0 +1,79 @@
1#ifndef __RIVAFB_H
2#define __RIVAFB_H
3
4#include <linux/config.h>
5#include <linux/fb.h>
6#include <video/vga.h>
7#include <linux/i2c.h>
8#include <linux/i2c-id.h>
9#include <linux/i2c-algo-bit.h>
10
11#include "riva_hw.h"
12
13/* GGI compatibility macros */
14#define NUM_SEQ_REGS 0x05
15#define NUM_CRT_REGS 0x41
16#define NUM_GRC_REGS 0x09
17#define NUM_ATC_REGS 0x15
18
19/* I2C */
20#define DDC_SCL_READ_MASK (1 << 2)
21#define DDC_SCL_WRITE_MASK (1 << 5)
22#define DDC_SDA_READ_MASK (1 << 3)
23#define DDC_SDA_WRITE_MASK (1 << 4)
24
25/* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
26 * From KGI originally. */
27struct riva_regs {
28 u8 attr[NUM_ATC_REGS];
29 u8 crtc[NUM_CRT_REGS];
30 u8 gra[NUM_GRC_REGS];
31 u8 seq[NUM_SEQ_REGS];
32 u8 misc_output;
33 RIVA_HW_STATE ext;
34};
35
36struct riva_par;
37
38struct riva_i2c_chan {
39 struct riva_par *par;
40 unsigned long ddc_base;
41 struct i2c_adapter adapter;
42 struct i2c_algo_bit_data algo;
43};
44
45struct riva_par {
46 RIVA_HW_INST riva; /* interface to riva_hw.c */
47 u32 pseudo_palette[16]; /* default palette */
48 u32 palette[16]; /* for Riva128 */
49 u8 __iomem *ctrl_base; /* virtual control register base addr */
50 unsigned dclk_max; /* max DCLK */
51
52 struct riva_regs initial_state; /* initial startup video mode */
53 struct riva_regs current_state;
54#ifdef CONFIG_X86
55 struct vgastate state;
56#endif
57 atomic_t ref_count;
58 unsigned char *EDID;
59 unsigned int Chipset;
60 int forceCRTC;
61 Bool SecondCRTC;
62 int FlatPanel;
63 struct pci_dev *pdev;
64 int bus;
65 int cursor_reset;
66#ifdef CONFIG_MTRR
67 struct { int vram; int vram_valid; } mtrr;
68#endif
69 struct riva_i2c_chan chan[3];
70};
71
72void riva_common_setup(struct riva_par *);
73unsigned long riva_get_memlen(struct riva_par *);
74unsigned long riva_get_maxdclk(struct riva_par *);
75void riva_delete_i2c_busses(struct riva_par *par);
76void riva_create_i2c_busses(struct riva_par *par);
77int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid);
78
79#endif /* __RIVAFB_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 05:50:15 -0500