1 files changed, 129 insertions, 0 deletions
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
new file mode 100644
index 000000000000..de15fec5f82f
--- /dev/null
+++ b/drivers/video/pxafb.h
@@ -0,0 +1,129 @@
+#ifndef __PXAFB_H__
+#define __PXAFB_H__
+/*
+ * linux/drivers/video/pxafb.h
+ *    -- Intel PXA250/210 LCD Controller Frame Buffer Device
+ *
+ *  Copyright (C) 1999 Eric A. Thomas.
+ *  Copyright (C) 2004 Jean-Frederic Clere.
+ *  Copyright (C) 2004 Ian Campbell.
+ *  Copyright (C) 2004 Jeff Lackey.
+ *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
+ *  which in turn is
+ *   Based on acornfb.c Copyright (C) Russell King.
+ *
+ *  2001-08-03: Cliff Brake <cbrake@acclent.com>
+ *       - ported SA1100 code to PXA
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+/* Shadows for LCD controller registers */
+struct pxafb_lcd_reg {
+        unsigned int lccr0;
+        unsigned int lccr1;
+        unsigned int lccr2;
+        unsigned int lccr3;
+};
+/* PXA LCD DMA descriptor */
+struct pxafb_dma_descriptor {
+        unsigned int fdadr;
+        unsigned int fsadr;
+        unsigned int fidr;
+        unsigned int ldcmd;
+};
+struct pxafb_info {
+        struct fb_info          fb;
+        struct device           *dev;
+        u_int                   max_bpp;
+        u_int                   max_xres;
+        u_int                   max_yres;
+        /*
+         * These are the addresses we mapped
+         * the framebuffer memory region to.
+         */
+        /* raw memory addresses */
+        dma_addr_t              map_dma;        /* physical */
+        u_char *                map_cpu;        /* virtual */
+        u_int                   map_size;
+        /* addresses of pieces placed in raw buffer */
+        u_char *                screen_cpu;     /* virtual address of frame buffer */
+        dma_addr_t              screen_dma;     /* physical address of frame buffer */
+        u16 *                   palette_cpu;    /* virtual address of palette memory */
+        dma_addr_t              palette_dma;    /* physical address of palette memory */
+        u_int                   palette_size;
+        /* DMA descriptors */
+        struct pxafb_dma_descriptor *   dmadesc_fblow_cpu;
+        dma_addr_t              dmadesc_fblow_dma;
+        struct pxafb_dma_descriptor *   dmadesc_fbhigh_cpu;
+        dma_addr_t              dmadesc_fbhigh_dma;
+        struct pxafb_dma_descriptor *   dmadesc_palette_cpu;
+        dma_addr_t              dmadesc_palette_dma;
+        dma_addr_t              fdadr0;
+        dma_addr_t              fdadr1;
+        u_int                   lccr0;
+        u_int                   lccr3;
+        u_int                   cmap_inverse:1,
+                                cmap_static:1,
+                                unused:30;
+        u_int                   reg_lccr0;
+        u_int                   reg_lccr1;
+        u_int                   reg_lccr2;
+        u_int                   reg_lccr3;
+        volatile u_char         state;
+        volatile u_char         task_state;
+        struct semaphore        ctrlr_sem;
+        wait_queue_head_t       ctrlr_wait;
+        struct work_struct      task;
+#ifdef CONFIG_CPU_FREQ
+        struct notifier_block   freq_transition;
+        struct notifier_block   freq_policy;
+#endif
+};
+#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
+/*
+ * These are the actions for set_ctrlr_state
+ */
+#define C_DISABLE               (0)
+#define C_ENABLE                (1)
+#define C_DISABLE_CLKCHANGE     (2)
+#define C_ENABLE_CLKCHANGE      (3)
+#define C_REENABLE              (4)
+#define C_DISABLE_PM            (5)
+#define C_ENABLE_PM             (6)
+#define C_STARTUP               (7)
+#define PXA_NAME        "PXA"
+/*
+ *  Debug macros
+ */
+#if DEBUG
+#  define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#  define DPRINTK(fmt, args...)
+#endif
+/*
+ * Minimum X and Y resolutions
+ */
+#define MIN_XRES        64
+#define MIN_YRES        64
+#endif /* __PXAFB_H__ */

diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h new file mode 100644 index 000000000000..de15fec5f82f --- /dev/null +++ b/drivers/video/pxafb.h
@@ -0,0 +1,129 @@
	1	#ifndef __PXAFB_H__
	2	#define __PXAFB_H__
	3
	4	/*
	5	* linux/drivers/video/pxafb.h
	6	* -- Intel PXA250/210 LCD Controller Frame Buffer Device
	7	*
	8	* Copyright (C) 1999 Eric A. Thomas.
	9	* Copyright (C) 2004 Jean-Frederic Clere.
	10	* Copyright (C) 2004 Ian Campbell.
	11	* Copyright (C) 2004 Jeff Lackey.
	12	* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
	13	* which in turn is
	14	* Based on acornfb.c Copyright (C) Russell King.
	15	*
	16	* 2001-08-03: Cliff Brake <cbrake@acclent.com>
	17	* - ported SA1100 code to PXA
	18	*
	19	* This file is subject to the terms and conditions of the GNU General Public
	20	* License. See the file COPYING in the main directory of this archive
	21	* for more details.
	22	*/
	23
	24	/* Shadows for LCD controller registers */
	25	struct pxafb_lcd_reg {
	26	unsigned int lccr0;
	27	unsigned int lccr1;
	28	unsigned int lccr2;
	29	unsigned int lccr3;
	30	};
	31
	32	/* PXA LCD DMA descriptor */
	33	struct pxafb_dma_descriptor {
	34	unsigned int fdadr;
	35	unsigned int fsadr;
	36	unsigned int fidr;
	37	unsigned int ldcmd;
	38	};
	39
	40	struct pxafb_info {
	41	struct fb_info fb;
	42	struct device *dev;
	43
	44	u_int max_bpp;
	45	u_int max_xres;
	46	u_int max_yres;
	47
	48	/*
	49	* These are the addresses we mapped
	50	* the framebuffer memory region to.
	51	*/
	52	/* raw memory addresses */
	53	dma_addr_t map_dma; /* physical */
	54	u_char * map_cpu; /* virtual */
	55	u_int map_size;
	56
	57	/* addresses of pieces placed in raw buffer */
	58	u_char * screen_cpu; /* virtual address of frame buffer */
	59	dma_addr_t screen_dma; /* physical address of frame buffer */
	60	u16 * palette_cpu; /* virtual address of palette memory */
	61	dma_addr_t palette_dma; /* physical address of palette memory */
	62	u_int palette_size;
	63
	64	/* DMA descriptors */
	65	struct pxafb_dma_descriptor * dmadesc_fblow_cpu;
	66	dma_addr_t dmadesc_fblow_dma;
	67	struct pxafb_dma_descriptor * dmadesc_fbhigh_cpu;
	68	dma_addr_t dmadesc_fbhigh_dma;
	69	struct pxafb_dma_descriptor * dmadesc_palette_cpu;
	70	dma_addr_t dmadesc_palette_dma;
	71
	72	dma_addr_t fdadr0;
	73	dma_addr_t fdadr1;
	74
	75	u_int lccr0;
	76	u_int lccr3;
	77	u_int cmap_inverse:1,
	78	cmap_static:1,
	79	unused:30;
	80
	81	u_int reg_lccr0;
	82	u_int reg_lccr1;
	83	u_int reg_lccr2;
	84	u_int reg_lccr3;
	85
	86	volatile u_char state;
	87	volatile u_char task_state;
	88	struct semaphore ctrlr_sem;
	89	wait_queue_head_t ctrlr_wait;
	90	struct work_struct task;
	91
	92	#ifdef CONFIG_CPU_FREQ
	93	struct notifier_block freq_transition;
	94	struct notifier_block freq_policy;
	95	#endif
	96	};
	97
	98	#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
	99
	100	/*
	101	* These are the actions for set_ctrlr_state
	102	*/
	103	#define C_DISABLE (0)
	104	#define C_ENABLE (1)
	105	#define C_DISABLE_CLKCHANGE (2)
	106	#define C_ENABLE_CLKCHANGE (3)
	107	#define C_REENABLE (4)
	108	#define C_DISABLE_PM (5)
	109	#define C_ENABLE_PM (6)
	110	#define C_STARTUP (7)
	111
	112	#define PXA_NAME "PXA"
	113
	114	/*
	115	* Debug macros
	116	*/
	117	#if DEBUG
	118	# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
	119	#else
	120	# define DPRINTK(fmt, args...)
	121	#endif
	122
	123	/*
	124	* Minimum X and Y resolutions
	125	*/
	126	#define MIN_XRES 64
	127	#define MIN_YRES 64
	128
	129	#endif /* __PXAFB_H__ */