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-rw-r--r--drivers/video/pxafb.c1390
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diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
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1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
25#include <linux/config.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/kernel.h>
29#include <linux/sched.h>
30#include <linux/errno.h>
31#include <linux/string.h>
32#include <linux/interrupt.h>
33#include <linux/slab.h>
34#include <linux/fb.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/ioport.h>
38#include <linux/cpufreq.h>
39#include <linux/device.h>
40#include <linux/dma-mapping.h>
41
42#include <asm/hardware.h>
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/uaccess.h>
46#include <asm/arch/pxa-regs.h>
47#include <asm/arch/bitfield.h>
48#include <asm/arch/pxafb.h>
49
50/*
51 * Complain if VAR is out of range.
52 */
53#define DEBUG_VAR 1
54
55#include "pxafb.h"
56
57/* Bits which should not be set in machine configuration structures */
58#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
59#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
60
61static void (*pxafb_backlight_power)(int);
62static void (*pxafb_lcd_power)(int);
63
64static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
65static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
66
67#ifdef CONFIG_FB_PXA_PARAMETERS
68#define PXAFB_OPTIONS_SIZE 256
69static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
70#endif
71
72static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
73{
74 unsigned long flags;
75
76 local_irq_save(flags);
77 /*
78 * We need to handle two requests being made at the same time.
79 * There are two important cases:
80 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
81 * We must perform the unblanking, which will do our REENABLE for us.
82 * 2. When we are blanking, but immediately unblank before we have
83 * blanked. We do the "REENABLE" thing here as well, just to be sure.
84 */
85 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
86 state = (u_int) -1;
87 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
88 state = C_REENABLE;
89
90 if (state != (u_int)-1) {
91 fbi->task_state = state;
92 schedule_work(&fbi->task);
93 }
94 local_irq_restore(flags);
95}
96
97static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
98{
99 chan &= 0xffff;
100 chan >>= 16 - bf->length;
101 return chan << bf->offset;
102}
103
104static int
105pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
106 u_int trans, struct fb_info *info)
107{
108 struct pxafb_info *fbi = (struct pxafb_info *)info;
109 u_int val, ret = 1;
110
111 if (regno < fbi->palette_size) {
112 if (fbi->fb.var.grayscale) {
113 val = ((blue >> 8) & 0x00ff);
114 } else {
115 val = ((red >> 0) & 0xf800);
116 val |= ((green >> 5) & 0x07e0);
117 val |= ((blue >> 11) & 0x001f);
118 }
119 fbi->palette_cpu[regno] = val;
120 ret = 0;
121 }
122 return ret;
123}
124
125static int
126pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
127 u_int trans, struct fb_info *info)
128{
129 struct pxafb_info *fbi = (struct pxafb_info *)info;
130 unsigned int val;
131 int ret = 1;
132
133 /*
134 * If inverse mode was selected, invert all the colours
135 * rather than the register number. The register number
136 * is what you poke into the framebuffer to produce the
137 * colour you requested.
138 */
139 if (fbi->cmap_inverse) {
140 red = 0xffff - red;
141 green = 0xffff - green;
142 blue = 0xffff - blue;
143 }
144
145 /*
146 * If greyscale is true, then we convert the RGB value
147 * to greyscale no matter what visual we are using.
148 */
149 if (fbi->fb.var.grayscale)
150 red = green = blue = (19595 * red + 38470 * green +
151 7471 * blue) >> 16;
152
153 switch (fbi->fb.fix.visual) {
154 case FB_VISUAL_TRUECOLOR:
155 /*
156 * 16-bit True Colour. We encode the RGB value
157 * according to the RGB bitfield information.
158 */
159 if (regno < 16) {
160 u32 *pal = fbi->fb.pseudo_palette;
161
162 val = chan_to_field(red, &fbi->fb.var.red);
163 val |= chan_to_field(green, &fbi->fb.var.green);
164 val |= chan_to_field(blue, &fbi->fb.var.blue);
165
166 pal[regno] = val;
167 ret = 0;
168 }
169 break;
170
171 case FB_VISUAL_STATIC_PSEUDOCOLOR:
172 case FB_VISUAL_PSEUDOCOLOR:
173 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
174 break;
175 }
176
177 return ret;
178}
179
180/*
181 * pxafb_bpp_to_lccr3():
182 * Convert a bits per pixel value to the correct bit pattern for LCCR3
183 */
184static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
185{
186 int ret = 0;
187 switch (var->bits_per_pixel) {
188 case 1: ret = LCCR3_1BPP; break;
189 case 2: ret = LCCR3_2BPP; break;
190 case 4: ret = LCCR3_4BPP; break;
191 case 8: ret = LCCR3_8BPP; break;
192 case 16: ret = LCCR3_16BPP; break;
193 }
194 return ret;
195}
196
197#ifdef CONFIG_CPU_FREQ
198/*
199 * pxafb_display_dma_period()
200 * Calculate the minimum period (in picoseconds) between two DMA
201 * requests for the LCD controller. If we hit this, it means we're
202 * doing nothing but LCD DMA.
203 */
204static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
205{
206 /*
207 * Period = pixclock * bits_per_byte * bytes_per_transfer
208 * / memory_bits_per_pixel;
209 */
210 return var->pixclock * 8 * 16 / var->bits_per_pixel;
211}
212
213extern unsigned int get_clk_frequency_khz(int info);
214#endif
215
216/*
217 * pxafb_check_var():
218 * Get the video params out of 'var'. If a value doesn't fit, round it up,
219 * if it's too big, return -EINVAL.
220 *
221 * Round up in the following order: bits_per_pixel, xres,
222 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
223 * bitfields, horizontal timing, vertical timing.
224 */
225static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
226{
227 struct pxafb_info *fbi = (struct pxafb_info *)info;
228
229 if (var->xres < MIN_XRES)
230 var->xres = MIN_XRES;
231 if (var->yres < MIN_YRES)
232 var->yres = MIN_YRES;
233 if (var->xres > fbi->max_xres)
234 var->xres = fbi->max_xres;
235 if (var->yres > fbi->max_yres)
236 var->yres = fbi->max_yres;
237 var->xres_virtual =
238 max(var->xres_virtual, var->xres);
239 var->yres_virtual =
240 max(var->yres_virtual, var->yres);
241
242 /*
243 * Setup the RGB parameters for this display.
244 *
245 * The pixel packing format is described on page 7-11 of the
246 * PXA2XX Developer's Manual.
247 */
248 if (var->bits_per_pixel == 16) {
249 var->red.offset = 11; var->red.length = 5;
250 var->green.offset = 5; var->green.length = 6;
251 var->blue.offset = 0; var->blue.length = 5;
252 var->transp.offset = var->transp.length = 0;
253 } else {
254 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
255 var->red.length = 8;
256 var->green.length = 8;
257 var->blue.length = 8;
258 var->transp.length = 0;
259 }
260
261#ifdef CONFIG_CPU_FREQ
262 DPRINTK("dma period = %d ps, clock = %d kHz\n",
263 pxafb_display_dma_period(var),
264 get_clk_frequency_khz(0));
265#endif
266
267 return 0;
268}
269
270static inline void pxafb_set_truecolor(u_int is_true_color)
271{
272 DPRINTK("true_color = %d\n", is_true_color);
273 // do your machine-specific setup if needed
274}
275
276/*
277 * pxafb_set_par():
278 * Set the user defined part of the display for the specified console
279 */
280static int pxafb_set_par(struct fb_info *info)
281{
282 struct pxafb_info *fbi = (struct pxafb_info *)info;
283 struct fb_var_screeninfo *var = &info->var;
284 unsigned long palette_mem_size;
285
286 DPRINTK("set_par\n");
287
288 if (var->bits_per_pixel == 16)
289 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
290 else if (!fbi->cmap_static)
291 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
292 else {
293 /*
294 * Some people have weird ideas about wanting static
295 * pseudocolor maps. I suspect their user space
296 * applications are broken.
297 */
298 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
299 }
300
301 fbi->fb.fix.line_length = var->xres_virtual *
302 var->bits_per_pixel / 8;
303 if (var->bits_per_pixel == 16)
304 fbi->palette_size = 0;
305 else
306 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
307
308 palette_mem_size = fbi->palette_size * sizeof(u16);
309
310 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
311
312 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
313 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
314
315 /*
316 * Set (any) board control register to handle new color depth
317 */
318 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
319
320 if (fbi->fb.var.bits_per_pixel == 16)
321 fb_dealloc_cmap(&fbi->fb.cmap);
322 else
323 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
324
325 pxafb_activate_var(var, fbi);
326
327 return 0;
328}
329
330/*
331 * Formal definition of the VESA spec:
332 * On
333 * This refers to the state of the display when it is in full operation
334 * Stand-By
335 * This defines an optional operating state of minimal power reduction with
336 * the shortest recovery time
337 * Suspend
338 * This refers to a level of power management in which substantial power
339 * reduction is achieved by the display. The display can have a longer
340 * recovery time from this state than from the Stand-by state
341 * Off
342 * This indicates that the display is consuming the lowest level of power
343 * and is non-operational. Recovery from this state may optionally require
344 * the user to manually power on the monitor
345 *
346 * Now, the fbdev driver adds an additional state, (blank), where they
347 * turn off the video (maybe by colormap tricks), but don't mess with the
348 * video itself: think of it semantically between on and Stand-By.
349 *
350 * So here's what we should do in our fbdev blank routine:
351 *
352 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
353 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
354 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
355 * VESA_POWERDOWN (mode 3) Video off, front/back light off
356 *
357 * This will match the matrox implementation.
358 */
359
360/*
361 * pxafb_blank():
362 * Blank the display by setting all palette values to zero. Note, the
363 * 16 bpp mode does not really use the palette, so this will not
364 * blank the display in all modes.
365 */
366static int pxafb_blank(int blank, struct fb_info *info)
367{
368 struct pxafb_info *fbi = (struct pxafb_info *)info;
369 int i;
370
371 DPRINTK("pxafb_blank: blank=%d\n", blank);
372
373 switch (blank) {
374 case FB_BLANK_POWERDOWN:
375 case FB_BLANK_VSYNC_SUSPEND:
376 case FB_BLANK_HSYNC_SUSPEND:
377 case FB_BLANK_NORMAL:
378 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
379 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
380 for (i = 0; i < fbi->palette_size; i++)
381 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
382
383 pxafb_schedule_work(fbi, C_DISABLE);
384 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
385 break;
386
387 case FB_BLANK_UNBLANK:
388 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
389 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
390 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
391 fb_set_cmap(&fbi->fb.cmap, info);
392 pxafb_schedule_work(fbi, C_ENABLE);
393 }
394 return 0;
395}
396
397static int pxafb_mmap(struct fb_info *info, struct file *file,
398 struct vm_area_struct *vma)
399{
400 struct pxafb_info *fbi = (struct pxafb_info *)info;
401 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
402
403 if (off < info->fix.smem_len) {
404 vma->vm_pgoff += 1;
405 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
406 fbi->map_dma, fbi->map_size);
407 }
408 return -EINVAL;
409}
410
411static struct fb_ops pxafb_ops = {
412 .owner = THIS_MODULE,
413 .fb_check_var = pxafb_check_var,
414 .fb_set_par = pxafb_set_par,
415 .fb_setcolreg = pxafb_setcolreg,
416 .fb_fillrect = cfb_fillrect,
417 .fb_copyarea = cfb_copyarea,
418 .fb_imageblit = cfb_imageblit,
419 .fb_blank = pxafb_blank,
420 .fb_cursor = soft_cursor,
421 .fb_mmap = pxafb_mmap,
422};
423
424/*
425 * Calculate the PCD value from the clock rate (in picoseconds).
426 * We take account of the PPCR clock setting.
427 * From PXA Developer's Manual:
428 *
429 * PixelClock = LCLK
430 * -------------
431 * 2 ( PCD + 1 )
432 *
433 * PCD = LCLK
434 * ------------- - 1
435 * 2(PixelClock)
436 *
437 * Where:
438 * LCLK = LCD/Memory Clock
439 * PCD = LCCR3[7:0]
440 *
441 * PixelClock here is in Hz while the pixclock argument given is the
442 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
443 *
444 * The function get_lclk_frequency_10khz returns LCLK in units of
445 * 10khz. Calling the result of this function lclk gives us the
446 * following
447 *
448 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
449 * -------------------------------------- - 1
450 * 2
451 *
452 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
453 */
454static inline unsigned int get_pcd(unsigned int pixclock)
455{
456 unsigned long long pcd;
457
458 /* FIXME: Need to take into account Double Pixel Clock mode
459 * (DPC) bit? or perhaps set it based on the various clock
460 * speeds */
461
462 pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
463 pcd /= 100000000 * 2;
464 /* no need for this, since we should subtract 1 anyway. they cancel */
465 /* pcd += 1; */ /* make up for integer math truncations */
466 return (unsigned int)pcd;
467}
468
469/*
470 * pxafb_activate_var():
471 * Configures LCD Controller based on entries in var parameter. Settings are
472 * only written to the controller if changes were made.
473 */
474static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
475{
476 struct pxafb_lcd_reg new_regs;
477 u_long flags;
478 u_int lines_per_panel, pcd = get_pcd(var->pixclock);
479
480 DPRINTK("Configuring PXA LCD\n");
481
482 DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
483 var->xres, var->hsync_len,
484 var->left_margin, var->right_margin);
485 DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
486 var->yres, var->vsync_len,
487 var->upper_margin, var->lower_margin);
488 DPRINTK("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
489
490#if DEBUG_VAR
491 if (var->xres < 16 || var->xres > 1024)
492 printk(KERN_ERR "%s: invalid xres %d\n",
493 fbi->fb.fix.id, var->xres);
494 switch(var->bits_per_pixel) {
495 case 1:
496 case 2:
497 case 4:
498 case 8:
499 case 16:
500 break;
501 default:
502 printk(KERN_ERR "%s: invalid bit depth %d\n",
503 fbi->fb.fix.id, var->bits_per_pixel);
504 break;
505 }
506 if (var->hsync_len < 1 || var->hsync_len > 64)
507 printk(KERN_ERR "%s: invalid hsync_len %d\n",
508 fbi->fb.fix.id, var->hsync_len);
509 if (var->left_margin < 1 || var->left_margin > 255)
510 printk(KERN_ERR "%s: invalid left_margin %d\n",
511 fbi->fb.fix.id, var->left_margin);
512 if (var->right_margin < 1 || var->right_margin > 255)
513 printk(KERN_ERR "%s: invalid right_margin %d\n",
514 fbi->fb.fix.id, var->right_margin);
515 if (var->yres < 1 || var->yres > 1024)
516 printk(KERN_ERR "%s: invalid yres %d\n",
517 fbi->fb.fix.id, var->yres);
518 if (var->vsync_len < 1 || var->vsync_len > 64)
519 printk(KERN_ERR "%s: invalid vsync_len %d\n",
520 fbi->fb.fix.id, var->vsync_len);
521 if (var->upper_margin < 0 || var->upper_margin > 255)
522 printk(KERN_ERR "%s: invalid upper_margin %d\n",
523 fbi->fb.fix.id, var->upper_margin);
524 if (var->lower_margin < 0 || var->lower_margin > 255)
525 printk(KERN_ERR "%s: invalid lower_margin %d\n",
526 fbi->fb.fix.id, var->lower_margin);
527#endif
528
529 new_regs.lccr0 = fbi->lccr0 |
530 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
531 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
532
533 new_regs.lccr1 =
534 LCCR1_DisWdth(var->xres) +
535 LCCR1_HorSnchWdth(var->hsync_len) +
536 LCCR1_BegLnDel(var->left_margin) +
537 LCCR1_EndLnDel(var->right_margin);
538
539 /*
540 * If we have a dual scan LCD, we need to halve
541 * the YRES parameter.
542 */
543 lines_per_panel = var->yres;
544 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
545 lines_per_panel /= 2;
546
547 new_regs.lccr2 =
548 LCCR2_DisHght(lines_per_panel) +
549 LCCR2_VrtSnchWdth(var->vsync_len) +
550 LCCR2_BegFrmDel(var->upper_margin) +
551 LCCR2_EndFrmDel(var->lower_margin);
552
553 new_regs.lccr3 = fbi->lccr3 |
554 pxafb_bpp_to_lccr3(var) |
555 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
556 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
557
558 if (pcd)
559 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
560
561 DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0);
562 DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1);
563 DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2);
564 DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3);
565
566 /* Update shadow copy atomically */
567 local_irq_save(flags);
568
569 /* setup dma descriptors */
570 fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
571 fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
572 fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
573
574 fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
575 fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
576 fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
577
578#define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
579
580 /* populate descriptors */
581 fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
582 fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
583 fbi->dmadesc_fblow_cpu->fidr = 0;
584 fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
585
586 fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
587
588 fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
589 fbi->dmadesc_fbhigh_cpu->fidr = 0;
590 fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
591
592 fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
593 fbi->dmadesc_palette_cpu->fidr = 0;
594 fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
595
596 if (var->bits_per_pixel == 16) {
597 /* palette shouldn't be loaded in true-color mode */
598 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
599 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
600 /* init it to something, even though we won't be using it */
601 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
602 } else {
603 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
604 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
605 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
606 }
607
608#if 0
609 DPRINTK("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
610 DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
611 DPRINTK("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
612 DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
613 DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
614 DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
615
616 DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
617 DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
618 DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
619
620 DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
621 DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
622 DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
623
624 DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
625 DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
626 DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
627#endif
628
629 fbi->reg_lccr0 = new_regs.lccr0;
630 fbi->reg_lccr1 = new_regs.lccr1;
631 fbi->reg_lccr2 = new_regs.lccr2;
632 fbi->reg_lccr3 = new_regs.lccr3;
633 local_irq_restore(flags);
634
635 /*
636 * Only update the registers if the controller is enabled
637 * and something has changed.
638 */
639 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
640 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
641 (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
642 pxafb_schedule_work(fbi, C_REENABLE);
643
644 return 0;
645}
646
647/*
648 * NOTE! The following functions are purely helpers for set_ctrlr_state.
649 * Do not call them directly; set_ctrlr_state does the correct serialisation
650 * to ensure that things happen in the right way 100% of time time.
651 * -- rmk
652 */
653static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
654{
655 DPRINTK("backlight o%s\n", on ? "n" : "ff");
656
657 if (pxafb_backlight_power)
658 pxafb_backlight_power(on);
659}
660
661static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
662{
663 DPRINTK("LCD power o%s\n", on ? "n" : "ff");
664
665 if (pxafb_lcd_power)
666 pxafb_lcd_power(on);
667}
668
669static void pxafb_setup_gpio(struct pxafb_info *fbi)
670{
671 int gpio, ldd_bits;
672 unsigned int lccr0 = fbi->lccr0;
673
674 /*
675 * setup is based on type of panel supported
676 */
677
678 /* 4 bit interface */
679 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
680 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
681 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
682 ldd_bits = 4;
683
684 /* 8 bit interface */
685 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
686 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
687 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
688 (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
689 ldd_bits = 8;
690
691 /* 16 bit interface */
692 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
693 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
694 ldd_bits = 16;
695
696 else {
697 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
698 return;
699 }
700
701 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
702 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
703 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
704 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
705 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
706 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
707}
708
709static void pxafb_enable_controller(struct pxafb_info *fbi)
710{
711 DPRINTK("Enabling LCD controller\n");
712 DPRINTK("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
713 DPRINTK("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
714 DPRINTK("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
715 DPRINTK("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
716 DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
717 DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
718
719 /* Sequence from 11.7.10 */
720 LCCR3 = fbi->reg_lccr3;
721 LCCR2 = fbi->reg_lccr2;
722 LCCR1 = fbi->reg_lccr1;
723 LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
724
725 FDADR0 = fbi->fdadr0;
726 FDADR1 = fbi->fdadr1;
727 LCCR0 |= LCCR0_ENB;
728
729 DPRINTK("FDADR0 0x%08x\n", (unsigned int) FDADR0);
730 DPRINTK("FDADR1 0x%08x\n", (unsigned int) FDADR1);
731 DPRINTK("LCCR0 0x%08x\n", (unsigned int) LCCR0);
732 DPRINTK("LCCR1 0x%08x\n", (unsigned int) LCCR1);
733 DPRINTK("LCCR2 0x%08x\n", (unsigned int) LCCR2);
734 DPRINTK("LCCR3 0x%08x\n", (unsigned int) LCCR3);
735}
736
737static void pxafb_disable_controller(struct pxafb_info *fbi)
738{
739 DECLARE_WAITQUEUE(wait, current);
740
741 DPRINTK("Disabling LCD controller\n");
742
743 set_current_state(TASK_UNINTERRUPTIBLE);
744 add_wait_queue(&fbi->ctrlr_wait, &wait);
745
746 LCSR = 0xffffffff; /* Clear LCD Status Register */
747 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
748 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
749
750 schedule_timeout(20 * HZ / 1000);
751 remove_wait_queue(&fbi->ctrlr_wait, &wait);
752}
753
754/*
755 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
756 */
757static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
758{
759 struct pxafb_info *fbi = dev_id;
760 unsigned int lcsr = LCSR;
761
762 if (lcsr & LCSR_LDD) {
763 LCCR0 |= LCCR0_LDM;
764 wake_up(&fbi->ctrlr_wait);
765 }
766
767 LCSR = lcsr;
768 return IRQ_HANDLED;
769}
770
771/*
772 * This function must be called from task context only, since it will
773 * sleep when disabling the LCD controller, or if we get two contending
774 * processes trying to alter state.
775 */
776static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
777{
778 u_int old_state;
779
780 down(&fbi->ctrlr_sem);
781
782 old_state = fbi->state;
783
784 /*
785 * Hack around fbcon initialisation.
786 */
787 if (old_state == C_STARTUP && state == C_REENABLE)
788 state = C_ENABLE;
789
790 switch (state) {
791 case C_DISABLE_CLKCHANGE:
792 /*
793 * Disable controller for clock change. If the
794 * controller is already disabled, then do nothing.
795 */
796 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
797 fbi->state = state;
798 //TODO __pxafb_lcd_power(fbi, 0);
799 pxafb_disable_controller(fbi);
800 }
801 break;
802
803 case C_DISABLE_PM:
804 case C_DISABLE:
805 /*
806 * Disable controller
807 */
808 if (old_state != C_DISABLE) {
809 fbi->state = state;
810 __pxafb_backlight_power(fbi, 0);
811 __pxafb_lcd_power(fbi, 0);
812 if (old_state != C_DISABLE_CLKCHANGE)
813 pxafb_disable_controller(fbi);
814 }
815 break;
816
817 case C_ENABLE_CLKCHANGE:
818 /*
819 * Enable the controller after clock change. Only
820 * do this if we were disabled for the clock change.
821 */
822 if (old_state == C_DISABLE_CLKCHANGE) {
823 fbi->state = C_ENABLE;
824 pxafb_enable_controller(fbi);
825 //TODO __pxafb_lcd_power(fbi, 1);
826 }
827 break;
828
829 case C_REENABLE:
830 /*
831 * Re-enable the controller only if it was already
832 * enabled. This is so we reprogram the control
833 * registers.
834 */
835 if (old_state == C_ENABLE) {
836 pxafb_disable_controller(fbi);
837 pxafb_setup_gpio(fbi);
838 pxafb_enable_controller(fbi);
839 }
840 break;
841
842 case C_ENABLE_PM:
843 /*
844 * Re-enable the controller after PM. This is not
845 * perfect - think about the case where we were doing
846 * a clock change, and we suspended half-way through.
847 */
848 if (old_state != C_DISABLE_PM)
849 break;
850 /* fall through */
851
852 case C_ENABLE:
853 /*
854 * Power up the LCD screen, enable controller, and
855 * turn on the backlight.
856 */
857 if (old_state != C_ENABLE) {
858 fbi->state = C_ENABLE;
859 pxafb_setup_gpio(fbi);
860 pxafb_enable_controller(fbi);
861 __pxafb_lcd_power(fbi, 1);
862 __pxafb_backlight_power(fbi, 1);
863 }
864 break;
865 }
866 up(&fbi->ctrlr_sem);
867}
868
869/*
870 * Our LCD controller task (which is called when we blank or unblank)
871 * via keventd.
872 */
873static void pxafb_task(void *dummy)
874{
875 struct pxafb_info *fbi = dummy;
876 u_int state = xchg(&fbi->task_state, -1);
877
878 set_ctrlr_state(fbi, state);
879}
880
881#ifdef CONFIG_CPU_FREQ
882/*
883 * CPU clock speed change handler. We need to adjust the LCD timing
884 * parameters when the CPU clock is adjusted by the power management
885 * subsystem.
886 *
887 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
888 */
889static int
890pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
891{
892 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
893 //TODO struct cpufreq_freqs *f = data;
894 u_int pcd;
895
896 switch (val) {
897 case CPUFREQ_PRECHANGE:
898 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
899 break;
900
901 case CPUFREQ_POSTCHANGE:
902 pcd = get_pcd(fbi->fb.var.pixclock);
903 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
904 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
905 break;
906 }
907 return 0;
908}
909
910static int
911pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
912{
913 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
914 struct fb_var_screeninfo *var = &fbi->fb.var;
915 struct cpufreq_policy *policy = data;
916
917 switch (val) {
918 case CPUFREQ_ADJUST:
919 case CPUFREQ_INCOMPATIBLE:
920 printk(KERN_DEBUG "min dma period: %d ps, "
921 "new clock %d kHz\n", pxafb_display_dma_period(var),
922 policy->max);
923 // TODO: fill in min/max values
924 break;
925#if 0
926 case CPUFREQ_NOTIFY:
927 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
928 do {} while(0);
929 /* todo: panic if min/max values aren't fulfilled
930 * [can't really happen unless there's a bug in the
931 * CPU policy verification process *
932 */
933 break;
934#endif
935 }
936 return 0;
937}
938#endif
939
940#ifdef CONFIG_PM
941/*
942 * Power management hooks. Note that we won't be called from IRQ context,
943 * unlike the blank functions above, so we may sleep.
944 */
945static int pxafb_suspend(struct device *dev, u32 state, u32 level)
946{
947 struct pxafb_info *fbi = dev_get_drvdata(dev);
948
949 if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
950 set_ctrlr_state(fbi, C_DISABLE_PM);
951 return 0;
952}
953
954static int pxafb_resume(struct device *dev, u32 level)
955{
956 struct pxafb_info *fbi = dev_get_drvdata(dev);
957
958 if (level == RESUME_ENABLE)
959 set_ctrlr_state(fbi, C_ENABLE_PM);
960 return 0;
961}
962#else
963#define pxafb_suspend NULL
964#define pxafb_resume NULL
965#endif
966
967/*
968 * pxafb_map_video_memory():
969 * Allocates the DRAM memory for the frame buffer. This buffer is
970 * remapped into a non-cached, non-buffered, memory region to
971 * allow palette and pixel writes to occur without flushing the
972 * cache. Once this area is remapped, all virtual memory
973 * access to the video memory should occur at the new region.
974 */
975static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
976{
977 u_long palette_mem_size;
978
979 /*
980 * We reserve one page for the palette, plus the size
981 * of the framebuffer.
982 */
983 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
984 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
985 &fbi->map_dma, GFP_KERNEL);
986
987 if (fbi->map_cpu) {
988 /* prevent initial garbage on screen */
989 memset(fbi->map_cpu, 0, fbi->map_size);
990 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
991 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
992 /*
993 * FIXME: this is actually the wrong thing to place in
994 * smem_start. But fbdev suffers from the problem that
995 * it needs an API which doesn't exist (in this case,
996 * dma_writecombine_mmap)
997 */
998 fbi->fb.fix.smem_start = fbi->screen_dma;
999
1000 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1001
1002 palette_mem_size = fbi->palette_size * sizeof(u16);
1003 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
1004
1005 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1006 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1007 }
1008
1009 return fbi->map_cpu ? 0 : -ENOMEM;
1010}
1011
1012static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1013{
1014 struct pxafb_info *fbi;
1015 void *addr;
1016 struct pxafb_mach_info *inf = dev->platform_data;
1017
1018 /* Alloc the pxafb_info and pseudo_palette in one step */
1019 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1020 if (!fbi)
1021 return NULL;
1022
1023 memset(fbi, 0, sizeof(struct pxafb_info));
1024 fbi->dev = dev;
1025
1026 strcpy(fbi->fb.fix.id, PXA_NAME);
1027
1028 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1029 fbi->fb.fix.type_aux = 0;
1030 fbi->fb.fix.xpanstep = 0;
1031 fbi->fb.fix.ypanstep = 0;
1032 fbi->fb.fix.ywrapstep = 0;
1033 fbi->fb.fix.accel = FB_ACCEL_NONE;
1034
1035 fbi->fb.var.nonstd = 0;
1036 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1037 fbi->fb.var.height = -1;
1038 fbi->fb.var.width = -1;
1039 fbi->fb.var.accel_flags = 0;
1040 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1041
1042 fbi->fb.fbops = &pxafb_ops;
1043 fbi->fb.flags = FBINFO_DEFAULT;
1044 fbi->fb.node = -1;
1045
1046 addr = fbi;
1047 addr = addr + sizeof(struct pxafb_info);
1048 fbi->fb.pseudo_palette = addr;
1049
1050 fbi->max_xres = inf->xres;
1051 fbi->fb.var.xres = inf->xres;
1052 fbi->fb.var.xres_virtual = inf->xres;
1053 fbi->max_yres = inf->yres;
1054 fbi->fb.var.yres = inf->yres;
1055 fbi->fb.var.yres_virtual = inf->yres;
1056 fbi->max_bpp = inf->bpp;
1057 fbi->fb.var.bits_per_pixel = inf->bpp;
1058 fbi->fb.var.pixclock = inf->pixclock;
1059 fbi->fb.var.hsync_len = inf->hsync_len;
1060 fbi->fb.var.left_margin = inf->left_margin;
1061 fbi->fb.var.right_margin = inf->right_margin;
1062 fbi->fb.var.vsync_len = inf->vsync_len;
1063 fbi->fb.var.upper_margin = inf->upper_margin;
1064 fbi->fb.var.lower_margin = inf->lower_margin;
1065 fbi->fb.var.sync = inf->sync;
1066 fbi->fb.var.grayscale = inf->cmap_greyscale;
1067 fbi->cmap_inverse = inf->cmap_inverse;
1068 fbi->cmap_static = inf->cmap_static;
1069 fbi->lccr0 = inf->lccr0;
1070 fbi->lccr3 = inf->lccr3;
1071 fbi->state = C_STARTUP;
1072 fbi->task_state = (u_char)-1;
1073 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1074 fbi->max_bpp / 8;
1075
1076 init_waitqueue_head(&fbi->ctrlr_wait);
1077 INIT_WORK(&fbi->task, pxafb_task, fbi);
1078 init_MUTEX(&fbi->ctrlr_sem);
1079
1080 return fbi;
1081}
1082
1083#ifdef CONFIG_FB_PXA_PARAMETERS
1084static int __init pxafb_parse_options(struct device *dev, char *options)
1085{
1086 struct pxafb_mach_info *inf = dev->platform_data;
1087 char *this_opt;
1088
1089 if (!options || !*options)
1090 return 0;
1091
1092 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1093
1094 /* could be made table driven or similar?... */
1095 while ((this_opt = strsep(&options, ",")) != NULL) {
1096 if (!strncmp(this_opt, "mode:", 5)) {
1097 const char *name = this_opt+5;
1098 unsigned int namelen = strlen(name);
1099 int res_specified = 0, bpp_specified = 0;
1100 unsigned int xres = 0, yres = 0, bpp = 0;
1101 int yres_specified = 0;
1102 int i;
1103 for (i = namelen-1; i >= 0; i--) {
1104 switch (name[i]) {
1105 case '-':
1106 namelen = i;
1107 if (!bpp_specified && !yres_specified) {
1108 bpp = simple_strtoul(&name[i+1], NULL, 0);
1109 bpp_specified = 1;
1110 } else
1111 goto done;
1112 break;
1113 case 'x':
1114 if (!yres_specified) {
1115 yres = simple_strtoul(&name[i+1], NULL, 0);
1116 yres_specified = 1;
1117 } else
1118 goto done;
1119 break;
1120 case '0'...'9':
1121 break;
1122 default:
1123 goto done;
1124 }
1125 }
1126 if (i < 0 && yres_specified) {
1127 xres = simple_strtoul(name, NULL, 0);
1128 res_specified = 1;
1129 }
1130 done:
1131 if (res_specified) {
1132 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1133 inf->xres = xres; inf->yres = yres;
1134 }
1135 if (bpp_specified)
1136 switch (bpp) {
1137 case 1:
1138 case 2:
1139 case 4:
1140 case 8:
1141 case 16:
1142 inf->bpp = bpp;
1143 dev_info(dev, "overriding bit depth: %d\n", bpp);
1144 break;
1145 default:
1146 dev_err(dev, "Depth %d is not valid\n", bpp);
1147 }
1148 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1149 inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1150 dev_info(dev, "override pixclock: %ld\n", inf->pixclock);
1151 } else if (!strncmp(this_opt, "left:", 5)) {
1152 inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1153 dev_info(dev, "override left: %u\n", inf->left_margin);
1154 } else if (!strncmp(this_opt, "right:", 6)) {
1155 inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1156 dev_info(dev, "override right: %u\n", inf->right_margin);
1157 } else if (!strncmp(this_opt, "upper:", 6)) {
1158 inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1159 dev_info(dev, "override upper: %u\n", inf->upper_margin);
1160 } else if (!strncmp(this_opt, "lower:", 6)) {
1161 inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1162 dev_info(dev, "override lower: %u\n", inf->lower_margin);
1163 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1164 inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1165 dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1166 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1167 inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1168 dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1169 } else if (!strncmp(this_opt, "hsync:", 6)) {
1170 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1171 dev_info(dev, "override hsync: Active Low\n");
1172 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1173 } else {
1174 dev_info(dev, "override hsync: Active High\n");
1175 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1176 }
1177 } else if (!strncmp(this_opt, "vsync:", 6)) {
1178 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1179 dev_info(dev, "override vsync: Active Low\n");
1180 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1181 } else {
1182 dev_info(dev, "override vsync: Active High\n");
1183 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1184 }
1185 } else if (!strncmp(this_opt, "dpc:", 4)) {
1186 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1187 dev_info(dev, "override double pixel clock: false\n");
1188 inf->lccr3 &= ~LCCR3_DPC;
1189 } else {
1190 dev_info(dev, "override double pixel clock: true\n");
1191 inf->lccr3 |= LCCR3_DPC;
1192 }
1193 } else if (!strncmp(this_opt, "outputen:", 9)) {
1194 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1195 dev_info(dev, "override output enable: active low\n");
1196 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1197 } else {
1198 dev_info(dev, "override output enable: active high\n");
1199 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1200 }
1201 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1202 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1203 dev_info(dev, "override pixel clock polarity: falling edge\n");
1204 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1205 } else {
1206 dev_info(dev, "override pixel clock polarity: rising edge\n");
1207 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1208 }
1209 } else if (!strncmp(this_opt, "color", 5)) {
1210 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1211 } else if (!strncmp(this_opt, "mono", 4)) {
1212 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1213 } else if (!strncmp(this_opt, "active", 6)) {
1214 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1215 } else if (!strncmp(this_opt, "passive", 7)) {
1216 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1217 } else if (!strncmp(this_opt, "single", 6)) {
1218 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1219 } else if (!strncmp(this_opt, "dual", 4)) {
1220 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1221 } else if (!strncmp(this_opt, "4pix", 4)) {
1222 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1223 } else if (!strncmp(this_opt, "8pix", 4)) {
1224 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1225 } else {
1226 dev_err(dev, "unknown option: %s\n", this_opt);
1227 return -EINVAL;
1228 }
1229 }
1230 return 0;
1231
1232}
1233#endif
1234
1235int __init pxafb_probe(struct device *dev)
1236{
1237 struct pxafb_info *fbi;
1238 struct pxafb_mach_info *inf;
1239 int ret;
1240
1241 dev_dbg(dev, "pxafb_probe\n");
1242
1243 inf = dev->platform_data;
1244 ret = -ENOMEM;
1245 fbi = NULL;
1246 if (!inf)
1247 goto failed;
1248
1249#ifdef CONFIG_FB_PXA_PARAMETERS
1250 ret = pxafb_parse_options(dev, g_options);
1251 if (ret < 0)
1252 goto failed;
1253#endif
1254
1255#ifdef DEBUG_VAR
1256 /* Check for various illegal bit-combinations. Currently only
1257 * a warning is given. */
1258
1259 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1260 dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1261 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1262 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1263 dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1264 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1265 if (inf->lccr0 & LCCR0_DPD &&
1266 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1267 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1268 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1269 dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1270 " single panel mode\n");
1271 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1272 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1273 dev_warn(dev, "Dual panel only valid in passive mode\n");
1274 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1275 (inf->upper_margin || inf->lower_margin))
1276 dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n");
1277#endif
1278
1279 dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1280 if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
1281 dev_err(dev, "Invalid resolution or bit depth\n");
1282 ret = -EINVAL;
1283 goto failed;
1284 }
1285 pxafb_backlight_power = inf->pxafb_backlight_power;
1286 pxafb_lcd_power = inf->pxafb_lcd_power;
1287 fbi = pxafb_init_fbinfo(dev);
1288 if (!fbi) {
1289 dev_err(dev, "Failed to initialize framebuffer device\n");
1290 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1291 goto failed;
1292 }
1293
1294 /* Initialize video memory */
1295 ret = pxafb_map_video_memory(fbi);
1296 if (ret) {
1297 dev_err(dev, "Failed to allocate video RAM: %d\n", ret);
1298 ret = -ENOMEM;
1299 goto failed;
1300 }
1301 /* enable LCD controller clock */
1302 pxa_set_cken(CKEN16_LCD, 1);
1303
1304 ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1305 if (ret) {
1306 dev_err(dev, "request_irq failed: %d\n", ret);
1307 ret = -EBUSY;
1308 goto failed;
1309 }
1310
1311 /*
1312 * This makes sure that our colour bitfield
1313 * descriptors are correctly initialised.
1314 */
1315 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1316 pxafb_set_par(&fbi->fb);
1317
1318 dev_set_drvdata(dev, fbi);
1319
1320 ret = register_framebuffer(&fbi->fb);
1321 if (ret < 0) {
1322 dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
1323 goto failed;
1324 }
1325
1326#ifdef CONFIG_PM
1327 // TODO
1328#endif
1329
1330#ifdef CONFIG_CPU_FREQ
1331 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1332 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1333 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1334 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1335#endif
1336
1337 /*
1338 * Ok, now enable the LCD controller
1339 */
1340 set_ctrlr_state(fbi, C_ENABLE);
1341
1342 return 0;
1343
1344failed:
1345 dev_set_drvdata(dev, NULL);
1346 kfree(fbi);
1347 return ret;
1348}
1349
1350static struct device_driver pxafb_driver = {
1351 .name = "pxa2xx-fb",
1352 .bus = &platform_bus_type,
1353 .probe = pxafb_probe,
1354#ifdef CONFIG_PM
1355 .suspend = pxafb_suspend,
1356 .resume = pxafb_resume,
1357#endif
1358};
1359
1360#ifndef MODULE
1361int __devinit pxafb_setup(char *options)
1362{
1363# ifdef CONFIG_FB_PXA_PARAMETERS
1364 strlcpy(g_options, options, sizeof(g_options));
1365# endif
1366 return 0;
1367}
1368#else
1369# ifdef CONFIG_FB_PXA_PARAMETERS
1370module_param_string(options, g_options, sizeof(g_options), 0);
1371MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1372# endif
1373#endif
1374
1375int __devinit pxafb_init(void)
1376{
1377#ifndef MODULE
1378 char *option = NULL;
1379
1380 if (fb_get_options("pxafb", &option))
1381 return -ENODEV;
1382 pxafb_setup(option);
1383#endif
1384 return driver_register(&pxafb_driver);
1385}
1386
1387module_init(pxafb_init);
1388
1389MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1390MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 02:35:31 -0500