aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video/pm2fb.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/video/pm2fb.c')
-rw-r--r--drivers/video/pm2fb.c1314
1 files changed, 1314 insertions, 0 deletions
diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c
new file mode 100644
index 000000000000..5dceddedf507
--- /dev/null
+++ b/drivers/video/pm2fb.c
@@ -0,0 +1,1314 @@
1/*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
30#include <linux/config.h>
31#include <linux/module.h>
32#include <linux/moduleparam.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/string.h>
36#include <linux/mm.h>
37#include <linux/tty.h>
38#include <linux/slab.h>
39#include <linux/delay.h>
40#include <linux/fb.h>
41#include <linux/init.h>
42#include <linux/pci.h>
43
44#include <video/permedia2.h>
45#include <video/cvisionppc.h>
46
47#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
48#error "The endianness of the target host has not been defined."
49#endif
50
51#if !defined(CONFIG_PCI)
52#error "Only generic PCI cards supported."
53#endif
54
55#undef PM2FB_MASTER_DEBUG
56#ifdef PM2FB_MASTER_DEBUG
57#define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
58#else
59#define DPRINTK(a,b...)
60#endif
61
62/*
63 * Driver data
64 */
65static char *mode __devinitdata = NULL;
66
67/*
68 * The XFree GLINT driver will (I think to implement hardware cursor
69 * support on TVP4010 and similar where there is no RAMDAC - see
70 * comment in set_video) always request +ve sync regardless of what
71 * the mode requires. This screws me because I have a Sun
72 * fixed-frequency monitor which absolutely has to have -ve sync. So
73 * these flags allow the user to specify that requests for +ve sync
74 * should be silently turned in -ve sync.
75 */
76static int lowhsync __devinitdata = 0;
77static int lowvsync __devinitdata = 0;
78
79/*
80 * The hardware state of the graphics card that isn't part of the
81 * screeninfo.
82 */
83struct pm2fb_par
84{
85 pm2type_t type; /* Board type */
86 u32 fb_size; /* framebuffer memory size */
87 unsigned char __iomem *v_fb; /* virtual address of frame buffer */
88 unsigned char __iomem *v_regs;/* virtual address of p_regs */
89 u32 memclock; /* memclock */
90 u32 video; /* video flags before blanking */
91 u32 mem_config; /* MemConfig reg at probe */
92 u32 mem_control; /* MemControl reg at probe */
93 u32 boot_address; /* BootAddress reg at probe */
94};
95
96/*
97 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
98 * if we don't use modedb.
99 */
100static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
101 .id = "",
102 .type = FB_TYPE_PACKED_PIXELS,
103 .visual = FB_VISUAL_PSEUDOCOLOR,
104 .xpanstep = 1,
105 .ypanstep = 1,
106 .ywrapstep = 0,
107 .accel = FB_ACCEL_NONE,
108};
109
110/*
111 * Default video mode. In case the modedb doesn't work.
112 */
113static struct fb_var_screeninfo pm2fb_var __devinitdata = {
114 /* "640x480, 8 bpp @ 60 Hz */
115 .xres = 640,
116 .yres = 480,
117 .xres_virtual = 640,
118 .yres_virtual = 480,
119 .bits_per_pixel =8,
120 .red = {0, 8, 0},
121 .blue = {0, 8, 0},
122 .green = {0, 8, 0},
123 .activate = FB_ACTIVATE_NOW,
124 .height = -1,
125 .width = -1,
126 .accel_flags = 0,
127 .pixclock = 39721,
128 .left_margin = 40,
129 .right_margin = 24,
130 .upper_margin = 32,
131 .lower_margin = 11,
132 .hsync_len = 96,
133 .vsync_len = 2,
134 .vmode = FB_VMODE_NONINTERLACED
135};
136
137/*
138 * Utility functions
139 */
140
141inline static u32 RD32(unsigned char __iomem *base, s32 off)
142{
143 return fb_readl(base + off);
144}
145
146inline static void WR32(unsigned char __iomem *base, s32 off, u32 v)
147{
148 fb_writel(v, base + off);
149}
150
151inline static u32 pm2_RD(struct pm2fb_par* p, s32 off)
152{
153 return RD32(p->v_regs, off);
154}
155
156inline static void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
157{
158 WR32(p->v_regs, off, v);
159}
160
161inline static u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
162{
163 int index = PM2R_RD_INDEXED_DATA;
164 switch (p->type) {
165 case PM2_TYPE_PERMEDIA2:
166 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
167 break;
168 case PM2_TYPE_PERMEDIA2V:
169 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
170 index = PM2VR_RD_INDEXED_DATA;
171 break;
172 }
173 mb();
174 return pm2_RD(p, index);
175}
176
177inline static void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
178{
179 int index = PM2R_RD_INDEXED_DATA;
180 switch (p->type) {
181 case PM2_TYPE_PERMEDIA2:
182 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
183 break;
184 case PM2_TYPE_PERMEDIA2V:
185 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
186 index = PM2VR_RD_INDEXED_DATA;
187 break;
188 }
189 mb();
190 pm2_WR(p, index, v);
191}
192
193inline static void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
194{
195 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
196 mb();
197 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
198}
199
200#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
201#define WAIT_FIFO(p,a)
202#else
203inline static void WAIT_FIFO(struct pm2fb_par* p, u32 a)
204{
205 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
206 mb();
207}
208#endif
209
210/*
211 * partial products for the supported horizontal resolutions.
212 */
213#define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
214static const struct {
215 u16 width;
216 u16 pp;
217} pp_table[] = {
218 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
219 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
220 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
221 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
222 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
223 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
224 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
225 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
226 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
227 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
228 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
229 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
230 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
231 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
232 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
233 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
234 { 0, 0 } };
235
236static u32 partprod(u32 xres)
237{
238 int i;
239
240 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
241 ;
242 if ( pp_table[i].width == 0 )
243 DPRINTK("invalid width %u\n", xres);
244 return pp_table[i].pp;
245}
246
247static u32 to3264(u32 timing, int bpp, int is64)
248{
249 switch (bpp) {
250 case 8:
251 timing >>= 2 + is64;
252 break;
253 case 16:
254 timing >>= 1 + is64;
255 break;
256 case 24:
257 timing = (timing * 3) >> (2 + is64);
258 break;
259 case 32:
260 if (is64)
261 timing >>= 1;
262 break;
263 }
264 return timing;
265}
266
267static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
268 unsigned char* pp)
269{
270 unsigned char m;
271 unsigned char n;
272 unsigned char p;
273 u32 f;
274 s32 curr;
275 s32 delta = 100000;
276
277 *mm = *nn = *pp = 0;
278 for (n = 2; n < 15; n++) {
279 for (m = 2; m; m++) {
280 f = PM2_REFERENCE_CLOCK * m / n;
281 if (f >= 150000 && f <= 300000) {
282 for ( p = 0; p < 5; p++, f >>= 1) {
283 curr = ( clk > f ) ? clk - f : f - clk;
284 if ( curr < delta ) {
285 delta=curr;
286 *mm=m;
287 *nn=n;
288 *pp=p;
289 }
290 }
291 }
292 }
293 }
294}
295
296static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
297 unsigned char* pp)
298{
299 unsigned char m;
300 unsigned char n;
301 unsigned char p;
302 u32 f;
303 s32 delta = 1000;
304
305 *mm = *nn = *pp = 0;
306 for (n = 1; n; n++) {
307 for ( m = 1; m; m++) {
308 for ( p = 0; p < 2; p++) {
309 f = PM2_REFERENCE_CLOCK * n / (m * (1 << (p + 1)));
310 if ( clk > f - delta && clk < f + delta ) {
311 delta = ( clk > f ) ? clk - f : f - clk;
312 *mm=m;
313 *nn=n;
314 *pp=p;
315 }
316 }
317 }
318 }
319}
320
321static void clear_palette(struct pm2fb_par* p) {
322 int i=256;
323
324 WAIT_FIFO(p, 1);
325 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
326 wmb();
327 while (i--) {
328 WAIT_FIFO(p, 3);
329 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
330 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
331 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
332 }
333}
334
335static void reset_card(struct pm2fb_par* p)
336{
337 if (p->type == PM2_TYPE_PERMEDIA2V)
338 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
339 pm2_WR(p, PM2R_RESET_STATUS, 0);
340 mb();
341 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
342 ;
343 mb();
344#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
345 DPRINTK("FIFO disconnect enabled\n");
346 pm2_WR(p, PM2R_FIFO_DISCON, 1);
347 mb();
348#endif
349
350 /* Restore stashed memory config information from probe */
351 WAIT_FIFO(p, 3);
352 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
353 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
354 wmb();
355 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
356}
357
358static void reset_config(struct pm2fb_par* p)
359{
360 WAIT_FIFO(p, 52);
361 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&
362 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
363 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
364 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
365 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
366 pm2_WR(p, PM2R_APERTURE_ONE, 0);
367 pm2_WR(p, PM2R_APERTURE_TWO, 0);
368 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
369 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
370 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
371 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
372 pm2_WR(p, PM2R_LB_READ_MODE, 0);
373 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
374 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
375 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
376 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
377 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
378 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
379 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
380 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
381 pm2_WR(p, PM2R_DITHER_MODE, 0);
382 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
383 pm2_WR(p, PM2R_DEPTH_MODE, 0);
384 pm2_WR(p, PM2R_STENCIL_MODE, 0);
385 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
386 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
387 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
388 pm2_WR(p, PM2R_YUV_MODE, 0);
389 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
390 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
391 pm2_WR(p, PM2R_FOG_MODE, 0);
392 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
393 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
394 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
395 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
396 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
397 switch (p->type) {
398 case PM2_TYPE_PERMEDIA2:
399 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
400 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
401 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
402 break;
403 case PM2_TYPE_PERMEDIA2V:
404 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
405 break;
406 }
407 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
408 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
409 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
410 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
411 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
412}
413
414static void set_aperture(struct pm2fb_par* p, u32 depth)
415{
416 /*
417 * The hardware is little-endian. When used in big-endian
418 * hosts, the on-chip aperture settings are used where
419 * possible to translate from host to card byte order.
420 */
421 WAIT_FIFO(p, 4);
422#ifdef __LITTLE_ENDIAN
423 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
424#else
425 switch (depth) {
426 case 24: /* RGB->BGR */
427 /*
428 * We can't use the aperture to translate host to
429 * card byte order here, so we switch to BGR mode
430 * in pm2fb_set_par().
431 */
432 case 8: /* B->B */
433 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
434 break;
435 case 16: /* HL->LH */
436 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
437 break;
438 case 32: /* RGBA->ABGR */
439 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
440 break;
441 }
442#endif
443
444 // We don't use aperture two, so this may be superflous
445 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
446}
447
448static void set_color(struct pm2fb_par* p, unsigned char regno,
449 unsigned char r, unsigned char g, unsigned char b)
450{
451 WAIT_FIFO(p, 4);
452 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
453 wmb();
454 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
455 wmb();
456 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
457 wmb();
458 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
459}
460
461static void set_memclock(struct pm2fb_par* par, u32 clk)
462{
463 int i;
464 unsigned char m, n, p;
465
466 pm2_mnp(clk, &m, &n, &p);
467 WAIT_FIFO(par, 10);
468 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
469 wmb();
470 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
471 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
472 wmb();
473 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
474 wmb();
475 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
476 rmb();
477 for (i = 256;
478 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
479 i--)
480 ;
481}
482
483static void set_pixclock(struct pm2fb_par* par, u32 clk)
484{
485 int i;
486 unsigned char m, n, p;
487
488 switch (par->type) {
489 case PM2_TYPE_PERMEDIA2:
490 pm2_mnp(clk, &m, &n, &p);
491 WAIT_FIFO(par, 8);
492 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
493 wmb();
494 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
495 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
496 wmb();
497 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
498 wmb();
499 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
500 rmb();
501 for (i = 256;
502 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
503 i--)
504 ;
505 break;
506 case PM2_TYPE_PERMEDIA2V:
507 pm2v_mnp(clk/2, &m, &n, &p);
508 WAIT_FIFO(par, 8);
509 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
510 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
511 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
512 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
513 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
514 break;
515 }
516}
517
518static void set_video(struct pm2fb_par* p, u32 video) {
519 u32 tmp;
520 u32 vsync;
521
522 vsync = video;
523
524 DPRINTK("video = 0x%x\n", video);
525
526 /*
527 * The hardware cursor needs +vsync to recognise vert retrace.
528 * We may not be using the hardware cursor, but the X Glint
529 * driver may well. So always set +hsync/+vsync and then set
530 * the RAMDAC to invert the sync if necessary.
531 */
532 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
533 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
534
535 WAIT_FIFO(p, 5);
536 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
537
538 switch (p->type) {
539 case PM2_TYPE_PERMEDIA2:
540 tmp = PM2F_RD_PALETTE_WIDTH_8;
541 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
542 tmp |= 4; /* invert hsync */
543 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
544 tmp |= 8; /* invert vsync */
545 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
546 break;
547 case PM2_TYPE_PERMEDIA2V:
548 tmp = 0;
549 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
550 tmp |= 1; /* invert hsync */
551 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
552 tmp |= 4; /* invert vsync */
553 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
554 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
555 break;
556 }
557}
558
559/*
560 *
561 */
562
563/**
564 * pm2fb_check_var - Optional function. Validates a var passed in.
565 * @var: frame buffer variable screen structure
566 * @info: frame buffer structure that represents a single frame buffer
567 *
568 * Checks to see if the hardware supports the state requested by
569 * var passed in.
570 *
571 * Returns negative errno on error, or zero on success.
572 */
573static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
574{
575 u32 lpitch;
576
577 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
578 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
579 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
580 return -EINVAL;
581 }
582
583 if (var->xres != var->xres_virtual) {
584 DPRINTK("virtual x resolution != physical x resolution not supported\n");
585 return -EINVAL;
586 }
587
588 if (var->yres > var->yres_virtual) {
589 DPRINTK("virtual y resolution < physical y resolution not possible\n");
590 return -EINVAL;
591 }
592
593 if (var->xoffset) {
594 DPRINTK("xoffset not supported\n");
595 return -EINVAL;
596 }
597
598 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
599 DPRINTK("interlace not supported\n");
600 return -EINVAL;
601 }
602
603 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
604 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
605
606 if (var->xres < 320 || var->xres > 1600) {
607 DPRINTK("width not supported: %u\n", var->xres);
608 return -EINVAL;
609 }
610
611 if (var->yres < 200 || var->yres > 1200) {
612 DPRINTK("height not supported: %u\n", var->yres);
613 return -EINVAL;
614 }
615
616 if (lpitch * var->yres_virtual > info->fix.smem_len) {
617 DPRINTK("no memory for screen (%ux%ux%u)\n",
618 var->xres, var->yres_virtual, var->bits_per_pixel);
619 return -EINVAL;
620 }
621
622 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
623 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
624 return -EINVAL;
625 }
626
627 switch(var->bits_per_pixel) {
628 case 8:
629 var->red.length = var->green.length = var->blue.length = 8;
630 break;
631 case 16:
632 var->red.offset = 11;
633 var->red.length = 5;
634 var->green.offset = 5;
635 var->green.length = 6;
636 var->blue.offset = 0;
637 var->blue.length = 5;
638 break;
639 case 32:
640 var->transp.offset = 24;
641 var->transp.length = 8;
642 var->red.offset = 16;
643 var->green.offset = 8;
644 var->blue.offset = 0;
645 var->red.length = var->green.length = var->blue.length = 8;
646 break;
647 case 24:
648#ifdef __BIG_ENDIAN
649 var->red.offset = 0;
650 var->blue.offset = 16;
651#else
652 var->red.offset = 16;
653 var->blue.offset = 0;
654#endif
655 var->green.offset = 8;
656 var->red.length = var->green.length = var->blue.length = 8;
657 break;
658 }
659 var->height = var->width = -1;
660
661 var->accel_flags = 0; /* Can't mmap if this is on */
662
663 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
664 var->xres, var->yres, var->bits_per_pixel);
665 return 0;
666}
667
668/**
669 * pm2fb_set_par - Alters the hardware state.
670 * @info: frame buffer structure that represents a single frame buffer
671 *
672 * Using the fb_var_screeninfo in fb_info we set the resolution of the
673 * this particular framebuffer.
674 */
675static int pm2fb_set_par(struct fb_info *info)
676{
677 struct pm2fb_par *par = (struct pm2fb_par *) info->par;
678 u32 pixclock;
679 u32 width, height, depth;
680 u32 hsstart, hsend, hbend, htotal;
681 u32 vsstart, vsend, vbend, vtotal;
682 u32 stride;
683 u32 base;
684 u32 video = 0;
685 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
686 u32 txtmap = 0;
687 u32 pixsize = 0;
688 u32 clrformat = 0;
689 u32 xres;
690 int data64;
691
692 reset_card(par);
693 reset_config(par);
694 clear_palette(par);
695 if ( par->memclock )
696 set_memclock(par, par->memclock);
697
698 width = (info->var.xres_virtual + 7) & ~7;
699 height = info->var.yres_virtual;
700 depth = (info->var.bits_per_pixel + 7) & ~7;
701 depth = (depth > 32) ? 32 : depth;
702 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
703
704 xres = (info->var.xres + 31) & ~31;
705 pixclock = PICOS2KHZ(info->var.pixclock);
706 if (pixclock > PM2_MAX_PIXCLOCK) {
707 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
708 return -EINVAL;
709 }
710
711 hsstart = to3264(info->var.right_margin, depth, data64);
712 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
713 hbend = hsend + to3264(info->var.left_margin, depth, data64);
714 htotal = to3264(xres, depth, data64) + hbend - 1;
715 vsstart = (info->var.lower_margin)
716 ? info->var.lower_margin - 1
717 : 0; /* FIXME! */
718 vsend = info->var.lower_margin + info->var.vsync_len - 1;
719 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
720 vtotal = info->var.yres + vbend - 1;
721 stride = to3264(width, depth, 1);
722 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
723 if (data64)
724 video |= PM2F_DATA_64_ENABLE;
725
726 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
727 if (lowhsync) {
728 DPRINTK("ignoring +hsync, using -hsync.\n");
729 video |= PM2F_HSYNC_ACT_LOW;
730 } else
731 video |= PM2F_HSYNC_ACT_HIGH;
732 }
733 else
734 video |= PM2F_HSYNC_ACT_LOW;
735 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
736 if (lowvsync) {
737 DPRINTK("ignoring +vsync, using -vsync.\n");
738 video |= PM2F_VSYNC_ACT_LOW;
739 } else
740 video |= PM2F_VSYNC_ACT_HIGH;
741 }
742 else
743 video |= PM2F_VSYNC_ACT_LOW;
744 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
745 DPRINTK("interlaced not supported\n");
746 return -EINVAL;
747 }
748 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
749 video |= PM2F_LINE_DOUBLE;
750 if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
751 video |= PM2F_VIDEO_ENABLE;
752 par->video = video;
753
754 info->fix.visual =
755 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
756 info->fix.line_length = info->var.xres * depth / 8;
757 info->cmap.len = 256;
758
759 /*
760 * Settings calculated. Now write them out.
761 */
762 if (par->type == PM2_TYPE_PERMEDIA2V) {
763 WAIT_FIFO(par, 1);
764 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
765 }
766
767 set_aperture(par, depth);
768
769 mb();
770 WAIT_FIFO(par, 19);
771 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
772 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
773 switch (depth) {
774 case 8:
775 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
776 clrformat = 0x0e;
777 break;
778 case 16:
779 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
780 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
781 txtmap = PM2F_TEXTEL_SIZE_16;
782 pixsize = 1;
783 clrformat = 0x70;
784 break;
785 case 32:
786 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
787 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
788 txtmap = PM2F_TEXTEL_SIZE_32;
789 pixsize = 2;
790 clrformat = 0x20;
791 break;
792 case 24:
793 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
794 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
795 txtmap = PM2F_TEXTEL_SIZE_24;
796 pixsize = 4;
797 clrformat = 0x20;
798 break;
799 }
800 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
801 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
802 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
803 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
804 pm2_WR(par, PM2R_H_TOTAL, htotal);
805 pm2_WR(par, PM2R_HS_START, hsstart);
806 pm2_WR(par, PM2R_HS_END, hsend);
807 pm2_WR(par, PM2R_HG_END, hbend);
808 pm2_WR(par, PM2R_HB_END, hbend);
809 pm2_WR(par, PM2R_V_TOTAL, vtotal);
810 pm2_WR(par, PM2R_VS_START, vsstart);
811 pm2_WR(par, PM2R_VS_END, vsend);
812 pm2_WR(par, PM2R_VB_END, vbend);
813 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
814 wmb();
815 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
816 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
817 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
818 wmb();
819 pm2_WR(par, PM2R_SCREEN_BASE, base);
820 wmb();
821 set_video(par, video);
822 WAIT_FIFO(par, 4);
823 switch (par->type) {
824 case PM2_TYPE_PERMEDIA2:
825 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
826 break;
827 case PM2_TYPE_PERMEDIA2V:
828 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
829 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
830 break;
831 }
832 set_pixclock(par, pixclock);
833 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
834 info->var.xres, info->var.yres, info->var.bits_per_pixel);
835 return 0;
836}
837
838/**
839 * pm2fb_setcolreg - Sets a color register.
840 * @regno: boolean, 0 copy local, 1 get_user() function
841 * @red: frame buffer colormap structure
842 * @green: The green value which can be up to 16 bits wide
843 * @blue: The blue value which can be up to 16 bits wide.
844 * @transp: If supported the alpha value which can be up to 16 bits wide.
845 * @info: frame buffer info structure
846 *
847 * Set a single color register. The values supplied have a 16 bit
848 * magnitude which needs to be scaled in this function for the hardware.
849 * Pretty much a direct lift from tdfxfb.c.
850 *
851 * Returns negative errno on error, or zero on success.
852 */
853static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
854 unsigned blue, unsigned transp,
855 struct fb_info *info)
856{
857 struct pm2fb_par *par = (struct pm2fb_par *) info->par;
858
859 if (regno >= info->cmap.len) /* no. of hw registers */
860 return 1;
861 /*
862 * Program hardware... do anything you want with transp
863 */
864
865 /* grayscale works only partially under directcolor */
866 if (info->var.grayscale) {
867 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
868 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
869 }
870
871 /* Directcolor:
872 * var->{color}.offset contains start of bitfield
873 * var->{color}.length contains length of bitfield
874 * {hardwarespecific} contains width of DAC
875 * cmap[X] is programmed to
876 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
877 * RAMDAC[X] is programmed to (red, green, blue)
878 *
879 * Pseudocolor:
880 * uses offset = 0 && length = DAC register width.
881 * var->{color}.offset is 0
882 * var->{color}.length contains widht of DAC
883 * cmap is not used
884 * DAC[X] is programmed to (red, green, blue)
885 * Truecolor:
886 * does not use RAMDAC (usually has 3 of them).
887 * var->{color}.offset contains start of bitfield
888 * var->{color}.length contains length of bitfield
889 * cmap is programmed to
890 * (red << red.offset) | (green << green.offset) |
891 * (blue << blue.offset) | (transp << transp.offset)
892 * RAMDAC does not exist
893 */
894#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
895 switch (info->fix.visual) {
896 case FB_VISUAL_TRUECOLOR:
897 case FB_VISUAL_PSEUDOCOLOR:
898 red = CNVT_TOHW(red, info->var.red.length);
899 green = CNVT_TOHW(green, info->var.green.length);
900 blue = CNVT_TOHW(blue, info->var.blue.length);
901 transp = CNVT_TOHW(transp, info->var.transp.length);
902 break;
903 case FB_VISUAL_DIRECTCOLOR:
904 /* example here assumes 8 bit DAC. Might be different
905 * for your hardware */
906 red = CNVT_TOHW(red, 8);
907 green = CNVT_TOHW(green, 8);
908 blue = CNVT_TOHW(blue, 8);
909 /* hey, there is bug in transp handling... */
910 transp = CNVT_TOHW(transp, 8);
911 break;
912 }
913#undef CNVT_TOHW
914 /* Truecolor has hardware independent palette */
915 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
916 u32 v;
917
918 if (regno >= 16)
919 return 1;
920
921 v = (red << info->var.red.offset) |
922 (green << info->var.green.offset) |
923 (blue << info->var.blue.offset) |
924 (transp << info->var.transp.offset);
925
926 switch (info->var.bits_per_pixel) {
927 case 8:
928 break;
929 case 16:
930 case 24:
931 case 32:
932 ((u32*)(info->pseudo_palette))[regno] = v;
933 break;
934 }
935 return 0;
936 }
937 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
938 set_color(par, regno, red, green, blue);
939
940 return 0;
941}
942
943/**
944 * pm2fb_pan_display - Pans the display.
945 * @var: frame buffer variable screen structure
946 * @info: frame buffer structure that represents a single frame buffer
947 *
948 * Pan (or wrap, depending on the `vmode' field) the display using the
949 * `xoffset' and `yoffset' fields of the `var' structure.
950 * If the values don't fit, return -EINVAL.
951 *
952 * Returns negative errno on error, or zero on success.
953 *
954 */
955static int pm2fb_pan_display(struct fb_var_screeninfo *var,
956 struct fb_info *info)
957{
958 struct pm2fb_par *p = (struct pm2fb_par *) info->par;
959 u32 base;
960 u32 depth;
961 u32 xres;
962
963 xres = (var->xres + 31) & ~31;
964 depth = (var->bits_per_pixel + 7) & ~7;
965 depth = (depth > 32) ? 32 : depth;
966 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
967 WAIT_FIFO(p, 1);
968 pm2_WR(p, PM2R_SCREEN_BASE, base);
969 return 0;
970}
971
972/**
973 * pm2fb_blank - Blanks the display.
974 * @blank_mode: the blank mode we want.
975 * @info: frame buffer structure that represents a single frame buffer
976 *
977 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
978 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
979 * video mode which doesn't support it. Implements VESA suspend
980 * and powerdown modes on hardware that supports disabling hsync/vsync:
981 * blank_mode == 2: suspend vsync
982 * blank_mode == 3: suspend hsync
983 * blank_mode == 4: powerdown
984 *
985 * Returns negative errno on error, or zero on success.
986 *
987 */
988static int pm2fb_blank(int blank_mode, struct fb_info *info)
989{
990 struct pm2fb_par *par = (struct pm2fb_par *) info->par;
991 u32 video = par->video;
992
993 DPRINTK("blank_mode %d\n", blank_mode);
994
995 switch (blank_mode) {
996 case FB_BLANK_UNBLANK:
997 /* Screen: On */
998 video |= PM2F_VIDEO_ENABLE;
999 break;
1000 case FB_BLANK_NORMAL:
1001 /* Screen: Off */
1002 video &= ~PM2F_VIDEO_ENABLE;
1003 break;
1004 case FB_BLANK_VSYNC_SUSPEND:
1005 /* VSync: Off */
1006 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
1007 break;
1008 case FB_BLANK_HSYNC_SUSPEND:
1009 /* HSync: Off */
1010 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
1011 break;
1012 case FB_BLANK_POWERDOWN:
1013 /* HSync: Off, VSync: Off */
1014 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1015 break;
1016 }
1017 set_video(par, video);
1018 return 0;
1019}
1020
1021/* ------------ Hardware Independent Functions ------------ */
1022
1023/*
1024 * Frame buffer operations
1025 */
1026
1027static struct fb_ops pm2fb_ops = {
1028 .owner = THIS_MODULE,
1029 .fb_check_var = pm2fb_check_var,
1030 .fb_set_par = pm2fb_set_par,
1031 .fb_setcolreg = pm2fb_setcolreg,
1032 .fb_blank = pm2fb_blank,
1033 .fb_pan_display = pm2fb_pan_display,
1034 .fb_fillrect = cfb_fillrect,
1035 .fb_copyarea = cfb_copyarea,
1036 .fb_imageblit = cfb_imageblit,
1037 .fb_cursor = soft_cursor,
1038};
1039
1040/*
1041 * PCI stuff
1042 */
1043
1044
1045/**
1046 * Device initialisation
1047 *
1048 * Initialise and allocate resource for PCI device.
1049 *
1050 * @param pdev PCI device.
1051 * @param id PCI device ID.
1052 */
1053static int __devinit pm2fb_probe(struct pci_dev *pdev,
1054 const struct pci_device_id *id)
1055{
1056 struct pm2fb_par *default_par;
1057 struct fb_info *info;
1058 int size, err;
1059 int err_retval = -ENXIO;
1060
1061 err = pci_enable_device(pdev);
1062 if ( err ) {
1063 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1064 return err;
1065 }
1066
1067 size = sizeof(struct pm2fb_par) + 256 * sizeof(u32);
1068 info = framebuffer_alloc(size, &pdev->dev);
1069 if ( !info )
1070 return -ENOMEM;
1071 default_par = (struct pm2fb_par *) info->par;
1072
1073 switch (pdev->device) {
1074 case PCI_DEVICE_ID_TI_TVP4020:
1075 strcpy(pm2fb_fix.id, "TVP4020");
1076 default_par->type = PM2_TYPE_PERMEDIA2;
1077 break;
1078 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1079 strcpy(pm2fb_fix.id, "Permedia2");
1080 default_par->type = PM2_TYPE_PERMEDIA2;
1081 break;
1082 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1083 strcpy(pm2fb_fix.id, "Permedia2v");
1084 default_par->type = PM2_TYPE_PERMEDIA2V;
1085 break;
1086 }
1087
1088 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1089 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1090
1091#if defined(__BIG_ENDIAN)
1092 /*
1093 * PM2 has a 64k register file, mapped twice in 128k. Lower
1094 * map is little-endian, upper map is big-endian.
1095 */
1096 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1097 DPRINTK("Adjusting register base for big-endian.\n");
1098#endif
1099 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1100
1101 /* Registers - request region and map it. */
1102 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1103 "pm2fb regbase") ) {
1104 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1105 goto err_exit_neither;
1106 }
1107 default_par->v_regs =
1108 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1109 if ( !default_par->v_regs ) {
1110 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1111 pm2fb_fix.id);
1112 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1113 goto err_exit_neither;
1114 }
1115
1116 /* Stash away memory register info for use when we reset the board */
1117 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1118 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1119 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1120 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1121 default_par->mem_control, default_par->boot_address,
1122 default_par->mem_config);
1123
1124 /* Now work out how big lfb is going to be. */
1125 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1126 case PM2F_MEM_BANKS_1:
1127 default_par->fb_size=0x200000;
1128 break;
1129 case PM2F_MEM_BANKS_2:
1130 default_par->fb_size=0x400000;
1131 break;
1132 case PM2F_MEM_BANKS_3:
1133 default_par->fb_size=0x600000;
1134 break;
1135 case PM2F_MEM_BANKS_4:
1136 default_par->fb_size=0x800000;
1137 break;
1138 }
1139 default_par->memclock = CVPPC_MEMCLOCK;
1140 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1141 pm2fb_fix.smem_len = default_par->fb_size;
1142
1143 /* Linear frame buffer - request region and map it. */
1144 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1145 "pm2fb smem") ) {
1146 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1147 goto err_exit_mmio;
1148 }
1149 info->screen_base = default_par->v_fb =
1150 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1151 if ( !default_par->v_fb ) {
1152 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1153 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1154 goto err_exit_mmio;
1155 }
1156
1157 info->fbops = &pm2fb_ops;
1158 info->fix = pm2fb_fix;
1159 info->pseudo_palette = (void *)(default_par + 1);
1160 info->flags = FBINFO_DEFAULT |
1161 FBINFO_HWACCEL_YPAN;
1162
1163 if (!mode)
1164 mode = "640x480@60";
1165
1166 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1167 if (!err || err == 4)
1168 info->var = pm2fb_var;
1169
1170 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1171 goto err_exit_all;
1172
1173 if (register_framebuffer(info) < 0)
1174 goto err_exit_both;
1175
1176 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
1177 info->node, info->fix.id, default_par->fb_size / 1024);
1178
1179 /*
1180 * Our driver data
1181 */
1182 pci_set_drvdata(pdev, info);
1183
1184 return 0;
1185
1186 err_exit_all:
1187 fb_dealloc_cmap(&info->cmap);
1188 err_exit_both:
1189 iounmap(info->screen_base);
1190 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1191 err_exit_mmio:
1192 iounmap(default_par->v_regs);
1193 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1194 err_exit_neither:
1195 framebuffer_release(info);
1196 return err_retval;
1197}
1198
1199/**
1200 * Device removal.
1201 *
1202 * Release all device resources.
1203 *
1204 * @param pdev PCI device to clean up.
1205 */
1206static void __devexit pm2fb_remove(struct pci_dev *pdev)
1207{
1208 struct fb_info* info = pci_get_drvdata(pdev);
1209 struct fb_fix_screeninfo* fix = &info->fix;
1210 struct pm2fb_par *par = info->par;
1211
1212 unregister_framebuffer(info);
1213
1214 iounmap(info->screen_base);
1215 release_mem_region(fix->smem_start, fix->smem_len);
1216 iounmap(par->v_regs);
1217 release_mem_region(fix->mmio_start, fix->mmio_len);
1218
1219 pci_set_drvdata(pdev, NULL);
1220 kfree(info);
1221}
1222
1223static struct pci_device_id pm2fb_id_table[] = {
1224 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1225 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1226 0xff0000, 0 },
1227 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1228 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1229 0xff0000, 0 },
1230 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1231 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1232 0xff0000, 0 },
1233 { 0, }
1234};
1235
1236static struct pci_driver pm2fb_driver = {
1237 .name = "pm2fb",
1238 .id_table = pm2fb_id_table,
1239 .probe = pm2fb_probe,
1240 .remove = __devexit_p(pm2fb_remove),
1241};
1242
1243MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1244
1245
1246#ifndef MODULE
1247/**
1248 * Parse user speficied options.
1249 *
1250 * This is, comma-separated options following `video=pm2fb:'.
1251 */
1252static int __init pm2fb_setup(char *options)
1253{
1254 char* this_opt;
1255
1256 if (!options || !*options)
1257 return 0;
1258
1259 while ((this_opt = strsep(&options, ",")) != NULL) {
1260 if (!*this_opt)
1261 continue;
1262 if(!strcmp(this_opt, "lowhsync")) {
1263 lowhsync = 1;
1264 } else if(!strcmp(this_opt, "lowvsync")) {
1265 lowvsync = 1;
1266 } else {
1267 mode = this_opt;
1268 }
1269 }
1270 return 0;
1271}
1272#endif
1273
1274
1275static int __init pm2fb_init(void)
1276{
1277#ifndef MODULE
1278 char *option = NULL;
1279
1280 if (fb_get_options("pm2fb", &option))
1281 return -ENODEV;
1282 pm2fb_setup(option);
1283#endif
1284
1285 return pci_register_driver(&pm2fb_driver);
1286}
1287
1288module_init(pm2fb_init);
1289
1290#ifdef MODULE
1291/*
1292 * Cleanup
1293 */
1294
1295static void __exit pm2fb_exit(void)
1296{
1297 pci_unregister_driver(&pm2fb_driver);
1298}
1299#endif
1300
1301#ifdef MODULE
1302module_exit(pm2fb_exit);
1303
1304module_param(mode, charp, 0);
1305MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1306module_param(lowhsync, bool, 0);
1307MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1308module_param(lowvsync, bool, 0);
1309MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1310
1311MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1312MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1313MODULE_LICENSE("GPL");
1314#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 00:22:21 -0500