diff options
Diffstat (limited to 'drivers/video/omap/dispc.c')
-rw-r--r-- | drivers/video/omap/dispc.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c index 6efcf89e7fbe..dfb72f5e4c96 100644 --- a/drivers/video/omap/dispc.c +++ b/drivers/video/omap/dispc.c | |||
@@ -156,7 +156,7 @@ struct resmap { | |||
156 | }; | 156 | }; |
157 | 157 | ||
158 | static struct { | 158 | static struct { |
159 | u32 base; | 159 | void __iomem *base; |
160 | 160 | ||
161 | struct omapfb_mem_desc mem_desc; | 161 | struct omapfb_mem_desc mem_desc; |
162 | struct resmap *res_map[DISPC_MEMTYPE_NUM]; | 162 | struct resmap *res_map[DISPC_MEMTYPE_NUM]; |
@@ -212,9 +212,9 @@ static void enable_rfbi_mode(int enable) | |||
212 | dispc_write_reg(DISPC_CONTROL, l); | 212 | dispc_write_reg(DISPC_CONTROL, l); |
213 | 213 | ||
214 | /* Set bypass mode in RFBI module */ | 214 | /* Set bypass mode in RFBI module */ |
215 | l = __raw_readl(io_p2v(RFBI_CONTROL)); | 215 | l = __raw_readl(IO_ADDRESS(RFBI_CONTROL)); |
216 | l |= enable ? 0 : (1 << 1); | 216 | l |= enable ? 0 : (1 << 1); |
217 | __raw_writel(l, io_p2v(RFBI_CONTROL)); | 217 | __raw_writel(l, IO_ADDRESS(RFBI_CONTROL)); |
218 | } | 218 | } |
219 | 219 | ||
220 | static void set_lcd_data_lines(int data_lines) | 220 | static void set_lcd_data_lines(int data_lines) |
@@ -1349,14 +1349,19 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode, | |||
1349 | 1349 | ||
1350 | memset(&dispc, 0, sizeof(dispc)); | 1350 | memset(&dispc, 0, sizeof(dispc)); |
1351 | 1351 | ||
1352 | dispc.base = io_p2v(DISPC_BASE); | 1352 | dispc.base = ioremap(DISPC_BASE, SZ_1K); |
1353 | if (!dispc.base) { | ||
1354 | dev_err(fbdev->dev, "can't ioremap DISPC\n"); | ||
1355 | return -ENOMEM; | ||
1356 | } | ||
1357 | |||
1353 | dispc.fbdev = fbdev; | 1358 | dispc.fbdev = fbdev; |
1354 | dispc.ext_mode = ext_mode; | 1359 | dispc.ext_mode = ext_mode; |
1355 | 1360 | ||
1356 | init_completion(&dispc.frame_done); | 1361 | init_completion(&dispc.frame_done); |
1357 | 1362 | ||
1358 | if ((r = get_dss_clocks()) < 0) | 1363 | if ((r = get_dss_clocks()) < 0) |
1359 | return r; | 1364 | goto fail0; |
1360 | 1365 | ||
1361 | enable_interface_clocks(1); | 1366 | enable_interface_clocks(1); |
1362 | enable_lcd_clocks(1); | 1367 | enable_lcd_clocks(1); |
@@ -1414,7 +1419,7 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode, | |||
1414 | } | 1419 | } |
1415 | 1420 | ||
1416 | /* L3 firewall setting: enable access to OCM RAM */ | 1421 | /* L3 firewall setting: enable access to OCM RAM */ |
1417 | __raw_writel(0x402000b0, io_p2v(0x680050a0)); | 1422 | __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0)); |
1418 | 1423 | ||
1419 | if ((r = alloc_palette_ram()) < 0) | 1424 | if ((r = alloc_palette_ram()) < 0) |
1420 | goto fail2; | 1425 | goto fail2; |
@@ -1464,7 +1469,8 @@ fail1: | |||
1464 | enable_lcd_clocks(0); | 1469 | enable_lcd_clocks(0); |
1465 | enable_interface_clocks(0); | 1470 | enable_interface_clocks(0); |
1466 | put_dss_clocks(); | 1471 | put_dss_clocks(); |
1467 | 1472 | fail0: | |
1473 | iounmap(dispc.base); | ||
1468 | return r; | 1474 | return r; |
1469 | } | 1475 | } |
1470 | 1476 | ||
@@ -1481,6 +1487,7 @@ static void omap_dispc_cleanup(void) | |||
1481 | free_irq(INT_24XX_DSS_IRQ, dispc.fbdev); | 1487 | free_irq(INT_24XX_DSS_IRQ, dispc.fbdev); |
1482 | enable_interface_clocks(0); | 1488 | enable_interface_clocks(0); |
1483 | put_dss_clocks(); | 1489 | put_dss_clocks(); |
1490 | iounmap(dispc.base); | ||
1484 | } | 1491 | } |
1485 | 1492 | ||
1486 | const struct lcd_ctrl omap2_int_ctrl = { | 1493 | const struct lcd_ctrl omap2_int_ctrl = { |