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path: root/drivers/video/nvidia/nv_hw.c
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Diffstat (limited to 'drivers/video/nvidia/nv_hw.c')
-rw-r--r--drivers/video/nvidia/nv_hw.c81
1 files changed, 65 insertions, 16 deletions
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c
index b989358437b3..454283f9bdac 100644
--- a/drivers/video/nvidia/nv_hw.c
+++ b/drivers/video/nvidia/nv_hw.c
@@ -848,7 +848,7 @@ void NVCalcStateExt(struct nvidia_par *par,
848 int width, 848 int width,
849 int hDisplaySize, int height, int dotClock, int flags) 849 int hDisplaySize, int height, int dotClock, int flags)
850{ 850{
851 int pixelDepth, VClk; 851 int pixelDepth, VClk = 0;
852 /* 852 /*
853 * Save mode parameters. 853 * Save mode parameters.
854 */ 854 */
@@ -938,15 +938,24 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
938 938
939 if (par->Architecture == NV_ARCH_04) { 939 if (par->Architecture == NV_ARCH_04) {
940 NV_WR32(par->PFB, 0x0200, state->config); 940 NV_WR32(par->PFB, 0x0200, state->config);
941 } else if ((par->Chipset & 0xfff0) == 0x0090) { 941 } else if ((par->Architecture < NV_ARCH_40) ||
942 for (i = 0; i < 15; i++) { 942 (par->Chipset & 0xfff0) == 0x0040) {
943 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
944 NV_WR32(par->PFB, 0x0604 + (i * 0x10), par->FbMapSize - 1);
945 }
946 } else {
947 for (i = 0; i < 8; i++) { 943 for (i = 0; i < 8; i++) {
948 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0); 944 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
949 NV_WR32(par->PFB, 0x0244 + (i * 0x10), par->FbMapSize - 1); 945 NV_WR32(par->PFB, 0x0244 + (i * 0x10),
946 par->FbMapSize - 1);
947 }
948 } else {
949 int regions = 12;
950
951 if (((par->Chipset & 0xfff0) == 0x0090) ||
952 ((par->Chipset & 0xfff0) == 0x01D0) ||
953 ((par->Chipset & 0xfff0) == 0x0290))
954 regions = 15;
955 for(i = 0; i < regions; i++) {
956 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
957 NV_WR32(par->PFB, 0x0604 + (i * 0x10),
958 par->FbMapSize - 1);
950 } 959 }
951 } 960 }
952 961
@@ -1182,11 +1191,17 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1182 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF); 1191 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1183 } else { 1192 } else {
1184 if (par->Architecture >= NV_ARCH_40) { 1193 if (par->Architecture >= NV_ARCH_40) {
1194 u32 tmp;
1195
1185 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0); 1196 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1186 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051); 1197 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1187 NV_WR32(par->PGRAPH, 0x0090, 0x00008000); 1198 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1188 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f); 1199 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1189 1200
1201 tmp = NV_RD32(par->REGS, 0x1540) & 0xff;
1202 for(i = 0; tmp && !(tmp & 1); tmp >>= 1, i++);
1203 NV_WR32(par->PGRAPH, 0x5000, i);
1204
1190 if ((par->Chipset & 0xfff0) == 0x0040) { 1205 if ((par->Chipset & 0xfff0) == 0x0040) {
1191 NV_WR32(par->PGRAPH, 0x09b0, 1206 NV_WR32(par->PGRAPH, 0x09b0,
1192 0x83280fff); 1207 0x83280fff);
@@ -1211,6 +1226,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1211 0xffff7fff); 1226 0xffff7fff);
1212 break; 1227 break;
1213 case 0x00C0: 1228 case 0x00C0:
1229 case 0x0120:
1214 NV_WR32(par->PGRAPH, 0x0828, 1230 NV_WR32(par->PGRAPH, 0x0828,
1215 0x007596ff); 1231 0x007596ff);
1216 NV_WR32(par->PGRAPH, 0x082C, 1232 NV_WR32(par->PGRAPH, 0x082C,
@@ -1245,6 +1261,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1245 0x00100000); 1261 0x00100000);
1246 break; 1262 break;
1247 case 0x0090: 1263 case 0x0090:
1264 case 0x0290:
1248 NV_WR32(par->PRAMDAC, 0x0608, 1265 NV_WR32(par->PRAMDAC, 0x0608,
1249 NV_RD32(par->PRAMDAC, 0x0608) | 1266 NV_RD32(par->PRAMDAC, 0x0608) |
1250 0x00100000); 1267 0x00100000);
@@ -1310,14 +1327,44 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1310 } 1327 }
1311 } 1328 }
1312 1329
1313 if ((par->Chipset & 0xfff0) == 0x0090) { 1330 if ((par->Architecture < NV_ARCH_40) ||
1314 for (i = 0; i < 60; i++) 1331 ((par->Chipset & 0xfff0) == 0x0040)) {
1315 NV_WR32(par->PGRAPH, 0x0D00 + i, 1332 for (i = 0; i < 32; i++) {
1316 NV_RD32(par->PFB, 0x0600 + i)); 1333 NV_WR32(par->PGRAPH, 0x0900 + i*4,
1334 NV_RD32(par->PFB, 0x0240 +i*4));
1335 NV_WR32(par->PGRAPH, 0x6900 + i*4,
1336 NV_RD32(par->PFB, 0x0240 +i*4));
1337 }
1317 } else { 1338 } else {
1318 for (i = 0; i < 32; i++) 1339 if (((par->Chipset & 0xfff0) == 0x0090) ||
1319 NV_WR32(par->PGRAPH, 0x0900 + i, 1340 ((par->Chipset & 0xfff0) == 0x01D0) ||
1320 NV_RD32(par->PFB, 0x0240 + i)); 1341 ((par->Chipset & 0xfff0) == 0x0290)) {
1342 for (i = 0; i < 60; i++) {
1343 NV_WR32(par->PGRAPH,
1344 0x0D00 + i*4,
1345 NV_RD32(par->PFB,
1346 0x0600 + i*4));
1347 NV_WR32(par->PGRAPH,
1348 0x6900 + i*4,
1349 NV_RD32(par->PFB,
1350 0x0600 + i*4));
1351 }
1352 } else {
1353 for (i = 0; i < 48; i++) {
1354 NV_WR32(par->PGRAPH,
1355 0x0900 + i*4,
1356 NV_RD32(par->PFB,
1357 0x0600 + i*4));
1358 if(((par->Chipset & 0xfff0)
1359 != 0x0160) &&
1360 ((par->Chipset & 0xfff0)
1361 != 0x0220))
1362 NV_WR32(par->PGRAPH,
1363 0x6900 + i*4,
1364 NV_RD32(par->PFB,
1365 0x0600 + i*4));
1366 }
1367 }
1321 } 1368 }
1322 1369
1323 if (par->Architecture >= NV_ARCH_40) { 1370 if (par->Architecture >= NV_ARCH_40) {
@@ -1338,7 +1385,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1338 NV_WR32(par->PGRAPH, 0x0868, 1385 NV_WR32(par->PGRAPH, 0x0868,
1339 par->FbMapSize - 1); 1386 par->FbMapSize - 1);
1340 } else { 1387 } else {
1341 if((par->Chipset & 0xfff0) == 0x0090) { 1388 if ((par->Chipset & 0xfff0) == 0x0090 ||
1389 (par->Chipset & 0xfff0) == 0x01D0 ||
1390 (par->Chipset & 0xfff0) == 0x0290) {
1342 NV_WR32(par->PGRAPH, 0x0DF0, 1391 NV_WR32(par->PGRAPH, 0x0DF0,
1343 NV_RD32(par->PFB, 0x0200)); 1392 NV_RD32(par->PFB, 0x0200));
1344 NV_WR32(par->PGRAPH, 0x0DF4, 1393 NV_WR32(par->PGRAPH, 0x0DF4,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 21:01:57 -0500