diff options
Diffstat (limited to 'drivers/video/nvidia/nv_hw.c')
| -rw-r--r-- | drivers/video/nvidia/nv_hw.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c index f297c7b14a41..c627955aa124 100644 --- a/drivers/video/nvidia/nv_hw.c +++ b/drivers/video/nvidia/nv_hw.c | |||
| @@ -149,8 +149,7 @@ static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk, | |||
| 149 | pll = NV_RD32(par->PMC, 0x4024); | 149 | pll = NV_RD32(par->PMC, 0x4024); |
| 150 | M = pll & 0xFF; | 150 | M = pll & 0xFF; |
| 151 | N = (pll >> 8) & 0xFF; | 151 | N = (pll >> 8) & 0xFF; |
| 152 | if (((par->Chipset & 0xfff0) == 0x0290) || | 152 | if (((par->Chipset & 0xfff0) == 0x0290) || ((par->Chipset & 0xfff0) == 0x0390) || ((par->Chipset & 0xfff0) == 0x02E0)) { |
| 153 | ((par->Chipset & 0xfff0) == 0x0390)) { | ||
| 154 | MB = 1; | 153 | MB = 1; |
| 155 | NB = 1; | 154 | NB = 1; |
| 156 | } else { | 155 | } else { |
| @@ -963,6 +962,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
| 963 | 962 | ||
| 964 | if (((par->Chipset & 0xfff0) == 0x0090) || | 963 | if (((par->Chipset & 0xfff0) == 0x0090) || |
| 965 | ((par->Chipset & 0xfff0) == 0x01D0) || | 964 | ((par->Chipset & 0xfff0) == 0x01D0) || |
| 965 | ((par->Chipset & 0xfff0) == 0x02E0) || | ||
| 966 | ((par->Chipset & 0xfff0) == 0x0290)) | 966 | ((par->Chipset & 0xfff0) == 0x0290)) |
| 967 | regions = 15; | 967 | regions = 15; |
| 968 | for(i = 0; i < regions; i++) { | 968 | for(i = 0; i < regions; i++) { |
| @@ -1275,6 +1275,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
| 1275 | 0x00100000); | 1275 | 0x00100000); |
| 1276 | break; | 1276 | break; |
| 1277 | case 0x0090: | 1277 | case 0x0090: |
| 1278 | case 0x02E0: | ||
| 1278 | case 0x0290: | 1279 | case 0x0290: |
| 1279 | NV_WR32(par->PRAMDAC, 0x0608, | 1280 | NV_WR32(par->PRAMDAC, 0x0608, |
| 1280 | NV_RD32(par->PRAMDAC, 0x0608) | | 1281 | NV_RD32(par->PRAMDAC, 0x0608) | |
| @@ -1352,6 +1353,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
| 1352 | } else { | 1353 | } else { |
| 1353 | if (((par->Chipset & 0xfff0) == 0x0090) || | 1354 | if (((par->Chipset & 0xfff0) == 0x0090) || |
| 1354 | ((par->Chipset & 0xfff0) == 0x01D0) || | 1355 | ((par->Chipset & 0xfff0) == 0x01D0) || |
| 1356 | ((par->Chipset & 0xfff0) == 0x02E0) || | ||
| 1355 | ((par->Chipset & 0xfff0) == 0x0290)) { | 1357 | ((par->Chipset & 0xfff0) == 0x0290)) { |
| 1356 | for (i = 0; i < 60; i++) { | 1358 | for (i = 0; i < 60; i++) { |
| 1357 | NV_WR32(par->PGRAPH, | 1359 | NV_WR32(par->PGRAPH, |
| @@ -1403,6 +1405,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
| 1403 | } else { | 1405 | } else { |
| 1404 | if ((par->Chipset & 0xfff0) == 0x0090 || | 1406 | if ((par->Chipset & 0xfff0) == 0x0090 || |
| 1405 | (par->Chipset & 0xfff0) == 0x01D0 || | 1407 | (par->Chipset & 0xfff0) == 0x01D0 || |
| 1408 | (par->Chipset & 0xfff0) == 0x02E0 || | ||
| 1406 | (par->Chipset & 0xfff0) == 0x0290) { | 1409 | (par->Chipset & 0xfff0) == 0x0290) { |
| 1407 | NV_WR32(par->PGRAPH, 0x0DF0, | 1410 | NV_WR32(par->PGRAPH, 0x0DF0, |
| 1408 | NV_RD32(par->PFB, 0x0200)); | 1411 | NV_RD32(par->PFB, 0x0200)); |