aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video/nvidia/nv_hw.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/video/nvidia/nv_hw.c')
-rw-r--r--drivers/video/nvidia/nv_hw.c82
1 files changed, 66 insertions, 16 deletions
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c
index b989358437b3..99c3a8e6a237 100644
--- a/drivers/video/nvidia/nv_hw.c
+++ b/drivers/video/nvidia/nv_hw.c
@@ -52,6 +52,7 @@
52#include <linux/pci.h> 52#include <linux/pci.h>
53#include "nv_type.h" 53#include "nv_type.h"
54#include "nv_local.h" 54#include "nv_local.h"
55#include "nv_proto.h"
55 56
56void NVLockUnlock(struct nvidia_par *par, int Lock) 57void NVLockUnlock(struct nvidia_par *par, int Lock)
57{ 58{
@@ -848,7 +849,7 @@ void NVCalcStateExt(struct nvidia_par *par,
848 int width, 849 int width,
849 int hDisplaySize, int height, int dotClock, int flags) 850 int hDisplaySize, int height, int dotClock, int flags)
850{ 851{
851 int pixelDepth, VClk; 852 int pixelDepth, VClk = 0;
852 /* 853 /*
853 * Save mode parameters. 854 * Save mode parameters.
854 */ 855 */
@@ -938,15 +939,24 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
938 939
939 if (par->Architecture == NV_ARCH_04) { 940 if (par->Architecture == NV_ARCH_04) {
940 NV_WR32(par->PFB, 0x0200, state->config); 941 NV_WR32(par->PFB, 0x0200, state->config);
941 } else if ((par->Chipset & 0xfff0) == 0x0090) { 942 } else if ((par->Architecture < NV_ARCH_40) ||
942 for (i = 0; i < 15; i++) { 943 (par->Chipset & 0xfff0) == 0x0040) {
943 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
944 NV_WR32(par->PFB, 0x0604 + (i * 0x10), par->FbMapSize - 1);
945 }
946 } else {
947 for (i = 0; i < 8; i++) { 944 for (i = 0; i < 8; i++) {
948 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0); 945 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
949 NV_WR32(par->PFB, 0x0244 + (i * 0x10), par->FbMapSize - 1); 946 NV_WR32(par->PFB, 0x0244 + (i * 0x10),
947 par->FbMapSize - 1);
948 }
949 } else {
950 int regions = 12;
951
952 if (((par->Chipset & 0xfff0) == 0x0090) ||
953 ((par->Chipset & 0xfff0) == 0x01D0) ||
954 ((par->Chipset & 0xfff0) == 0x0290))
955 regions = 15;
956 for(i = 0; i < regions; i++) {
957 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
958 NV_WR32(par->PFB, 0x0604 + (i * 0x10),
959 par->FbMapSize - 1);
950 } 960 }
951 } 961 }
952 962
@@ -1182,11 +1192,17 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1182 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF); 1192 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1183 } else { 1193 } else {
1184 if (par->Architecture >= NV_ARCH_40) { 1194 if (par->Architecture >= NV_ARCH_40) {
1195 u32 tmp;
1196
1185 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0); 1197 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1186 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051); 1198 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1187 NV_WR32(par->PGRAPH, 0x0090, 0x00008000); 1199 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1188 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f); 1200 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1189 1201
1202 tmp = NV_RD32(par->REGS, 0x1540) & 0xff;
1203 for(i = 0; tmp && !(tmp & 1); tmp >>= 1, i++);
1204 NV_WR32(par->PGRAPH, 0x5000, i);
1205
1190 if ((par->Chipset & 0xfff0) == 0x0040) { 1206 if ((par->Chipset & 0xfff0) == 0x0040) {
1191 NV_WR32(par->PGRAPH, 0x09b0, 1207 NV_WR32(par->PGRAPH, 0x09b0,
1192 0x83280fff); 1208 0x83280fff);
@@ -1211,6 +1227,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1211 0xffff7fff); 1227 0xffff7fff);
1212 break; 1228 break;
1213 case 0x00C0: 1229 case 0x00C0:
1230 case 0x0120:
1214 NV_WR32(par->PGRAPH, 0x0828, 1231 NV_WR32(par->PGRAPH, 0x0828,
1215 0x007596ff); 1232 0x007596ff);
1216 NV_WR32(par->PGRAPH, 0x082C, 1233 NV_WR32(par->PGRAPH, 0x082C,
@@ -1245,6 +1262,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1245 0x00100000); 1262 0x00100000);
1246 break; 1263 break;
1247 case 0x0090: 1264 case 0x0090:
1265 case 0x0290:
1248 NV_WR32(par->PRAMDAC, 0x0608, 1266 NV_WR32(par->PRAMDAC, 0x0608,
1249 NV_RD32(par->PRAMDAC, 0x0608) | 1267 NV_RD32(par->PRAMDAC, 0x0608) |
1250 0x00100000); 1268 0x00100000);
@@ -1310,14 +1328,44 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1310 } 1328 }
1311 } 1329 }
1312 1330
1313 if ((par->Chipset & 0xfff0) == 0x0090) { 1331 if ((par->Architecture < NV_ARCH_40) ||
1314 for (i = 0; i < 60; i++) 1332 ((par->Chipset & 0xfff0) == 0x0040)) {
1315 NV_WR32(par->PGRAPH, 0x0D00 + i, 1333 for (i = 0; i < 32; i++) {
1316 NV_RD32(par->PFB, 0x0600 + i)); 1334 NV_WR32(par->PGRAPH, 0x0900 + i*4,
1335 NV_RD32(par->PFB, 0x0240 +i*4));
1336 NV_WR32(par->PGRAPH, 0x6900 + i*4,
1337 NV_RD32(par->PFB, 0x0240 +i*4));
1338 }
1317 } else { 1339 } else {
1318 for (i = 0; i < 32; i++) 1340 if (((par->Chipset & 0xfff0) == 0x0090) ||
1319 NV_WR32(par->PGRAPH, 0x0900 + i, 1341 ((par->Chipset & 0xfff0) == 0x01D0) ||
1320 NV_RD32(par->PFB, 0x0240 + i)); 1342 ((par->Chipset & 0xfff0) == 0x0290)) {
1343 for (i = 0; i < 60; i++) {
1344 NV_WR32(par->PGRAPH,
1345 0x0D00 + i*4,
1346 NV_RD32(par->PFB,
1347 0x0600 + i*4));
1348 NV_WR32(par->PGRAPH,
1349 0x6900 + i*4,
1350 NV_RD32(par->PFB,
1351 0x0600 + i*4));
1352 }
1353 } else {
1354 for (i = 0; i < 48; i++) {
1355 NV_WR32(par->PGRAPH,
1356 0x0900 + i*4,
1357 NV_RD32(par->PFB,
1358 0x0600 + i*4));
1359 if(((par->Chipset & 0xfff0)
1360 != 0x0160) &&
1361 ((par->Chipset & 0xfff0)
1362 != 0x0220))
1363 NV_WR32(par->PGRAPH,
1364 0x6900 + i*4,
1365 NV_RD32(par->PFB,
1366 0x0600 + i*4));
1367 }
1368 }
1321 } 1369 }
1322 1370
1323 if (par->Architecture >= NV_ARCH_40) { 1371 if (par->Architecture >= NV_ARCH_40) {
@@ -1338,7 +1386,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
1338 NV_WR32(par->PGRAPH, 0x0868, 1386 NV_WR32(par->PGRAPH, 0x0868,
1339 par->FbMapSize - 1); 1387 par->FbMapSize - 1);
1340 } else { 1388 } else {
1341 if((par->Chipset & 0xfff0) == 0x0090) { 1389 if ((par->Chipset & 0xfff0) == 0x0090 ||
1390 (par->Chipset & 0xfff0) == 0x01D0 ||
1391 (par->Chipset & 0xfff0) == 0x0290) {
1342 NV_WR32(par->PGRAPH, 0x0DF0, 1392 NV_WR32(par->PGRAPH, 0x0DF0,
1343 NV_RD32(par->PFB, 0x0200)); 1393 NV_RD32(par->PFB, 0x0200));
1344 NV_WR32(par->PGRAPH, 0x0DF4, 1394 NV_WR32(par->PGRAPH, 0x0DF4,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 18:03:05 -0500