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-rw-r--r--drivers/video/mbx/Makefile4
-rw-r--r--drivers/video/mbx/mbxdebugfs.c188
-rw-r--r--drivers/video/mbx/mbxfb.c683
-rw-r--r--drivers/video/mbx/reg_bits.h418
-rw-r--r--drivers/video/mbx/regs.h195
5 files changed, 1488 insertions, 0 deletions
diff --git a/drivers/video/mbx/Makefile b/drivers/video/mbx/Makefile
new file mode 100644
index 000000000000..16c1165cf9c7
--- /dev/null
+++ b/drivers/video/mbx/Makefile
@@ -0,0 +1,4 @@
1# Makefile for the 2700G controller driver.
2
3obj-$(CONFIG_FB_MBX) += mbxfb.o
4obj-$(CONFIG_FB_MBX_DEBUG) += mbxfbdebugfs.o
diff --git a/drivers/video/mbx/mbxdebugfs.c b/drivers/video/mbx/mbxdebugfs.c
new file mode 100644
index 000000000000..84aab3ad024e
--- /dev/null
+++ b/drivers/video/mbx/mbxdebugfs.c
@@ -0,0 +1,188 @@
1#include <linux/debugfs.h>
2
3#define BIG_BUFFER_SIZE (1024)
4
5static char big_buffer[BIG_BUFFER_SIZE];
6
7struct mbxfb_debugfs_data {
8 struct dentry *dir;
9 struct dentry *sysconf;
10 struct dentry *clock;
11 struct dentry *display;
12 struct dentry *gsctl;
13};
14
15static int open_file_generic(struct inode *inode, struct file *file)
16{
17 file->private_data = inode->u.generic_ip;
18 return 0;
19}
20
21static ssize_t write_file_dummy(struct file *file, const char __user *buf,
22 size_t count, loff_t *ppos)
23{
24 return count;
25}
26
27static ssize_t sysconf_read_file(struct file *file, char __user *userbuf,
28 size_t count, loff_t *ppos)
29{
30 char * s = big_buffer;
31
32 s += sprintf(s, "SYSCFG = %08lx\n", SYSCFG);
33 s += sprintf(s, "PFBASE = %08lx\n", PFBASE);
34 s += sprintf(s, "PFCEIL = %08lx\n", PFCEIL);
35 s += sprintf(s, "POLLFLAG = %08lx\n", POLLFLAG);
36 s += sprintf(s, "SYSRST = %08lx\n", SYSRST);
37
38 return simple_read_from_buffer(userbuf, count, ppos,
39 big_buffer, s-big_buffer);
40}
41
42
43static ssize_t gsctl_read_file(struct file *file, char __user *userbuf,
44 size_t count, loff_t *ppos)
45{
46 char * s = big_buffer;
47
48 s += sprintf(s, "GSCTRL = %08lx\n", GSCTRL);
49 s += sprintf(s, "VSCTRL = %08lx\n", VSCTRL);
50 s += sprintf(s, "GBBASE = %08lx\n", GBBASE);
51 s += sprintf(s, "VBBASE = %08lx\n", VBBASE);
52 s += sprintf(s, "GDRCTRL = %08lx\n", GDRCTRL);
53 s += sprintf(s, "VCMSK = %08lx\n", VCMSK);
54 s += sprintf(s, "GSCADR = %08lx\n", GSCADR);
55 s += sprintf(s, "VSCADR = %08lx\n", VSCADR);
56 s += sprintf(s, "VUBASE = %08lx\n", VUBASE);
57 s += sprintf(s, "VVBASE = %08lx\n", VVBASE);
58 s += sprintf(s, "GSADR = %08lx\n", GSADR);
59 s += sprintf(s, "VSADR = %08lx\n", VSADR);
60 s += sprintf(s, "HCCTRL = %08lx\n", HCCTRL);
61 s += sprintf(s, "HCSIZE = %08lx\n", HCSIZE);
62 s += sprintf(s, "HCPOS = %08lx\n", HCPOS);
63 s += sprintf(s, "HCBADR = %08lx\n", HCBADR);
64 s += sprintf(s, "HCCKMSK = %08lx\n", HCCKMSK);
65 s += sprintf(s, "GPLUT = %08lx\n", GPLUT);
66
67 return simple_read_from_buffer(userbuf, count, ppos,
68 big_buffer, s-big_buffer);
69}
70
71static ssize_t display_read_file(struct file *file, char __user *userbuf,
72 size_t count, loff_t *ppos)
73{
74 char * s = big_buffer;
75
76 s += sprintf(s, "DSCTRL = %08lx\n", DSCTRL);
77 s += sprintf(s, "DHT01 = %08lx\n", DHT01);
78 s += sprintf(s, "DHT02 = %08lx\n", DHT02);
79 s += sprintf(s, "DHT03 = %08lx\n", DHT03);
80 s += sprintf(s, "DVT01 = %08lx\n", DVT01);
81 s += sprintf(s, "DVT02 = %08lx\n", DVT02);
82 s += sprintf(s, "DVT03 = %08lx\n", DVT03);
83 s += sprintf(s, "DBCOL = %08lx\n", DBCOL);
84 s += sprintf(s, "BGCOLOR = %08lx\n", BGCOLOR);
85 s += sprintf(s, "DINTRS = %08lx\n", DINTRS);
86 s += sprintf(s, "DINTRE = %08lx\n", DINTRE);
87 s += sprintf(s, "DINTRCNT = %08lx\n", DINTRCNT);
88 s += sprintf(s, "DSIG = %08lx\n", DSIG);
89 s += sprintf(s, "DMCTRL = %08lx\n", DMCTRL);
90 s += sprintf(s, "CLIPCTRL = %08lx\n", CLIPCTRL);
91 s += sprintf(s, "SPOCTRL = %08lx\n", SPOCTRL);
92 s += sprintf(s, "SVCTRL = %08lx\n", SVCTRL);
93 s += sprintf(s, "DLSTS = %08lx\n", DLSTS);
94 s += sprintf(s, "DLLCTRL = %08lx\n", DLLCTRL);
95 s += sprintf(s, "DVLNUM = %08lx\n", DVLNUM);
96 s += sprintf(s, "DUCTRL = %08lx\n", DUCTRL);
97 s += sprintf(s, "DVECTRL = %08lx\n", DVECTRL);
98 s += sprintf(s, "DHDET = %08lx\n", DHDET);
99 s += sprintf(s, "DVDET = %08lx\n", DVDET);
100 s += sprintf(s, "DODMSK = %08lx\n", DODMSK);
101 s += sprintf(s, "CSC01 = %08lx\n", CSC01);
102 s += sprintf(s, "CSC02 = %08lx\n", CSC02);
103 s += sprintf(s, "CSC03 = %08lx\n", CSC03);
104 s += sprintf(s, "CSC04 = %08lx\n", CSC04);
105 s += sprintf(s, "CSC05 = %08lx\n", CSC05);
106
107 return simple_read_from_buffer(userbuf, count, ppos,
108 big_buffer, s-big_buffer);
109}
110
111static ssize_t clock_read_file(struct file *file, char __user *userbuf,
112 size_t count, loff_t *ppos)
113{
114 char * s = big_buffer;
115
116 s += sprintf(s, "SYSCLKSRC = %08lx\n", SYSCLKSRC);
117 s += sprintf(s, "PIXCLKSRC = %08lx\n", PIXCLKSRC);
118 s += sprintf(s, "CLKSLEEP = %08lx\n", CLKSLEEP);
119 s += sprintf(s, "COREPLL = %08lx\n", COREPLL);
120 s += sprintf(s, "DISPPLL = %08lx\n", DISPPLL);
121 s += sprintf(s, "PLLSTAT = %08lx\n", PLLSTAT);
122 s += sprintf(s, "VOVRCLK = %08lx\n", VOVRCLK);
123 s += sprintf(s, "PIXCLK = %08lx\n", PIXCLK);
124 s += sprintf(s, "MEMCLK = %08lx\n", MEMCLK);
125 s += sprintf(s, "M24CLK = %08lx\n", M24CLK);
126 s += sprintf(s, "MBXCLK = %08lx\n", MBXCLK);
127 s += sprintf(s, "SDCLK = %08lx\n", SDCLK);
128 s += sprintf(s, "PIXCLKDIV = %08lx\n", PIXCLKDIV);
129
130 return simple_read_from_buffer(userbuf, count, ppos,
131 big_buffer, s-big_buffer);
132}
133
134static struct file_operations sysconf_fops = {
135 .read = sysconf_read_file,
136 .write = write_file_dummy,
137 .open = open_file_generic,
138};
139
140static struct file_operations clock_fops = {
141 .read = clock_read_file,
142 .write = write_file_dummy,
143 .open = open_file_generic,
144};
145
146static struct file_operations display_fops = {
147 .read = display_read_file,
148 .write = write_file_dummy,
149 .open = open_file_generic,
150};
151
152static struct file_operations gsctl_fops = {
153 .read = gsctl_read_file,
154 .write = write_file_dummy,
155 .open = open_file_generic,
156};
157
158
159static void __devinit mbxfb_debugfs_init(struct fb_info *fbi)
160{
161 struct mbxfb_info *mfbi = fbi->par;
162 struct mbxfb_debugfs_data *dbg;
163
164 dbg = kzalloc(sizeof(struct mbxfb_debugfs_data), GFP_KERNEL);
165 mfbi->debugfs_data = dbg;
166
167 dbg->dir = debugfs_create_dir("mbxfb", NULL);
168 dbg->sysconf = debugfs_create_file("sysconf", 0444, dbg->dir,
169 fbi, &sysconf_fops);
170 dbg->clock = debugfs_create_file("clock", 0444, dbg->dir,
171 fbi, &clock_fops);
172 dbg->display = debugfs_create_file("display", 0444, dbg->dir,
173 fbi, &display_fops);
174 dbg->gsctl = debugfs_create_file("gsctl", 0444, dbg->dir,
175 fbi, &gsctl_fops);
176}
177
178static void __devexit mbxfb_debugfs_remove(struct fb_info *fbi)
179{
180 struct mbxfb_info *mfbi = fbi->par;
181 struct mbxfb_debugfs_data *dbg = mfbi->debugfs_data;
182
183 debugfs_remove(dbg->gsctl);
184 debugfs_remove(dbg->display);
185 debugfs_remove(dbg->clock);
186 debugfs_remove(dbg->sysconf);
187 debugfs_remove(dbg->dir);
188}
diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c
new file mode 100644
index 000000000000..6849ab75d403
--- /dev/null
+++ b/drivers/video/mbx/mbxfb.c
@@ -0,0 +1,683 @@
1/*
2 * linux/drivers/video/mbx/mbxfb.c
3 *
4 * Copyright (C) 2006 Compulab, Ltd.
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * Based on pxafb.c
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 *
13 * Intel 2700G (Marathon) Graphics Accelerator Frame Buffer Driver
14 *
15 */
16
17#include <linux/delay.h>
18#include <linux/fb.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22
23#include <asm/io.h>
24
25#include <video/mbxfb.h>
26
27#include "regs.h"
28#include "reg_bits.h"
29
30static unsigned long virt_base_2700;
31
32#define MIN_XRES 16
33#define MIN_YRES 16
34#define MAX_XRES 2048
35#define MAX_YRES 2048
36
37#define MAX_PALETTES 16
38
39/* FIXME: take care of different chip revisions with different sizes
40 of ODFB */
41#define MEMORY_OFFSET 0x60000
42
43struct mbxfb_info {
44 struct device *dev;
45
46 struct resource *fb_res;
47 struct resource *fb_req;
48
49 struct resource *reg_res;
50 struct resource *reg_req;
51
52 void __iomem *fb_virt_addr;
53 unsigned long fb_phys_addr;
54
55 void __iomem *reg_virt_addr;
56 unsigned long reg_phys_addr;
57
58 int (*platform_probe) (struct fb_info * fb);
59 int (*platform_remove) (struct fb_info * fb);
60
61 u32 pseudo_palette[MAX_PALETTES];
62#ifdef CONFIG_FB_MBX_DEBUG
63 void *debugfs_data;
64#endif
65
66};
67
68static struct fb_var_screeninfo mbxfb_default __devinitdata = {
69 .xres = 640,
70 .yres = 480,
71 .xres_virtual = 640,
72 .yres_virtual = 480,
73 .bits_per_pixel = 16,
74 .red = {11, 5, 0},
75 .green = {5, 6, 0},
76 .blue = {0, 5, 0},
77 .activate = FB_ACTIVATE_TEST,
78 .height = -1,
79 .width = -1,
80 .pixclock = 40000,
81 .left_margin = 48,
82 .right_margin = 16,
83 .upper_margin = 33,
84 .lower_margin = 10,
85 .hsync_len = 96,
86 .vsync_len = 2,
87 .vmode = FB_VMODE_NONINTERLACED,
88 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
89};
90
91static struct fb_fix_screeninfo mbxfb_fix __devinitdata = {
92 .id = "MBX",
93 .type = FB_TYPE_PACKED_PIXELS,
94 .visual = FB_VISUAL_TRUECOLOR,
95 .xpanstep = 0,
96 .ypanstep = 0,
97 .ywrapstep = 0,
98 .accel = FB_ACCEL_NONE,
99};
100
101struct pixclock_div {
102 u8 m;
103 u8 n;
104 u8 p;
105};
106
107static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps,
108 struct pixclock_div *div)
109{
110 u8 m, n, p;
111 unsigned int err = 0;
112 unsigned int min_err = ~0x0;
113 unsigned int clk;
114 unsigned int best_clk = 0;
115 unsigned int ref_clk = 13000; /* FIXME: take from platform data */
116 unsigned int pixclock;
117
118 /* convert pixclock to KHz */
119 pixclock = PICOS2KHZ(pixclock_ps);
120
121 for (m = 1; m < 64; m++) {
122 for (n = 1; n < 8; n++) {
123 for (p = 0; p < 8; p++) {
124 clk = (ref_clk * m) / (n * (1 << p));
125 err = (clk > pixclock) ? (clk - pixclock) :
126 (pixclock - clk);
127 if (err < min_err) {
128 min_err = err;
129 best_clk = clk;
130 div->m = m;
131 div->n = n;
132 div->p = p;
133 }
134 }
135 }
136 }
137 return KHZ2PICOS(best_clk);
138}
139
140static int mbxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
141 u_int trans, struct fb_info *info)
142{
143 u32 val, ret = 1;
144
145 if (regno < MAX_PALETTES) {
146 u32 *pal = info->pseudo_palette;
147
148 val = (red & 0xf800) | ((green & 0xfc00) >> 5) |
149 ((blue & 0xf800) >> 11);
150 pal[regno] = val;
151 ret = 0;
152 }
153
154 return ret;
155}
156
157static int mbxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
158{
159 struct pixclock_div div;
160
161 var->pixclock = mbxfb_get_pixclock(var->pixclock, &div);
162
163 if (var->xres < MIN_XRES)
164 var->xres = MIN_XRES;
165 if (var->yres < MIN_YRES)
166 var->yres = MIN_YRES;
167 if (var->xres > MAX_XRES)
168 return -EINVAL;
169 if (var->yres > MAX_YRES)
170 return -EINVAL;
171 var->xres_virtual = max(var->xres_virtual, var->xres);
172 var->yres_virtual = max(var->yres_virtual, var->yres);
173
174 switch (var->bits_per_pixel) {
175 /* 8 bits-per-pixel is not supported yet */
176 case 8:
177 return -EINVAL;
178 case 16:
179 var->green.length = (var->green.length == 5) ? 5 : 6;
180 var->red.length = 5;
181 var->blue.length = 5;
182 var->transp.length = 6 - var->green.length;
183 var->blue.offset = 0;
184 var->green.offset = 5;
185 var->red.offset = 5 + var->green.length;
186 var->transp.offset = (5 + var->red.offset) & 15;
187 break;
188 case 24: /* RGB 888 */
189 case 32: /* RGBA 8888 */
190 var->red.offset = 16;
191 var->red.length = 8;
192 var->green.offset = 8;
193 var->green.length = 8;
194 var->blue.offset = 0;
195 var->blue.length = 8;
196 var->transp.length = var->bits_per_pixel - 24;
197 var->transp.offset = (var->transp.length) ? 24 : 0;
198 break;
199 }
200 var->red.msb_right = 0;
201 var->green.msb_right = 0;
202 var->blue.msb_right = 0;
203 var->transp.msb_right = 0;
204
205 return 0;
206}
207
208static int mbxfb_set_par(struct fb_info *info)
209{
210 struct fb_var_screeninfo *var = &info->var;
211 struct pixclock_div div;
212 ushort hbps, ht, hfps, has;
213 ushort vbps, vt, vfps, vas;
214 u32 gsctrl = readl(GSCTRL);
215 u32 gsadr = readl(GSADR);
216
217 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
218
219 /* setup color mode */
220 gsctrl &= ~(FMsk(GSCTRL_GPIXFMT));
221 /* FIXME: add *WORKING* support for 8-bits per color */
222 if (info->var.bits_per_pixel == 8) {
223 return -EINVAL;
224 } else {
225 fb_dealloc_cmap(&info->cmap);
226 gsctrl &= ~GSCTRL_LUT_EN;
227
228 info->fix.visual = FB_VISUAL_TRUECOLOR;
229 switch (info->var.bits_per_pixel) {
230 case 16:
231 if (info->var.green.length == 5)
232 gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
233 else
234 gsctrl |= GSCTRL_GPIXFMT_RGB565;
235 break;
236 case 24:
237 gsctrl |= GSCTRL_GPIXFMT_RGB888;
238 break;
239 case 32:
240 gsctrl |= GSCTRL_GPIXFMT_ARGB8888;
241 break;
242 }
243 }
244
245 /* setup resolution */
246 gsctrl &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
247 gsctrl |= Gsctrl_Width(info->var.xres - 1) |
248 Gsctrl_Height(info->var.yres - 1);
249 writel(gsctrl, GSCTRL);
250 udelay(1000);
251
252 gsadr &= ~(FMsk(GSADR_SRCSTRIDE));
253 gsadr |= Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel /
254 (8 * 16) - 1);
255 writel(gsadr, GSADR);
256 udelay(1000);
257
258 /* setup timings */
259 var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
260
261 writel((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) |
262 Disp_Pll_P(div.p) | DISP_PLL_EN), DISPPLL);
263
264 hbps = var->hsync_len;
265 has = hbps + var->left_margin;
266 hfps = has + var->xres;
267 ht = hfps + var->right_margin;
268
269 vbps = var->vsync_len;
270 vas = vbps + var->upper_margin;
271 vfps = vas + var->yres;
272 vt = vfps + var->lower_margin;
273
274 writel((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01);
275 writel((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02);
276 writel((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03);
277 writel((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET);
278
279 writel((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01);
280 writel((Dvt02_Vtbs(vas) | Dvt02_Vas(vas)), DVT02);
281 writel((Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps)), DVT03);
282 writel((Dvdet_Vdes(vas) | Dvdet_Vdef(vfps)), DVDET);
283 writel((Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps)), DVECTRL);
284
285 writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
286
287 return 0;
288}
289
290static int mbxfb_blank(int blank, struct fb_info *info)
291{
292 switch (blank) {
293 case FB_BLANK_POWERDOWN:
294 case FB_BLANK_VSYNC_SUSPEND:
295 case FB_BLANK_HSYNC_SUSPEND:
296 case FB_BLANK_NORMAL:
297 writel((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL);
298 udelay(1000);
299 writel((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK);
300 udelay(1000);
301 writel((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK);
302 udelay(1000);
303 break;
304 case FB_BLANK_UNBLANK:
305 writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
306 udelay(1000);
307 writel((readl(PIXCLK) | PIXCLK_EN), PIXCLK);
308 udelay(1000);
309 break;
310 }
311 return 0;
312}
313
314static struct fb_ops mbxfb_ops = {
315 .owner = THIS_MODULE,
316 .fb_check_var = mbxfb_check_var,
317 .fb_set_par = mbxfb_set_par,
318 .fb_setcolreg = mbxfb_setcolreg,
319 .fb_fillrect = cfb_fillrect,
320 .fb_copyarea = cfb_copyarea,
321 .fb_imageblit = cfb_imageblit,
322 .fb_blank = mbxfb_blank,
323};
324
325/*
326 Enable external SDRAM controller. Assume that all clocks are active
327 by now.
328*/
329static void __devinit setup_memc(struct fb_info *fbi)
330{
331 struct mbxfb_info *mfbi = fbi->par;
332 unsigned long tmp;
333 int i;
334
335 /* FIXME: use platfrom specific parameters */
336 /* setup SDRAM controller */
337 writel((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS |
338 LMCFG_LMA_TS),
339 LMCFG);
340 udelay(1000);
341
342 writel(LMPWR_MC_PWR_ACT, LMPWR);
343 udelay(1000);
344
345 /* setup SDRAM timings */
346 writel((Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) |
347 Lmtim_Trc(9) | Lmtim_Tdpl(2)),
348 LMTIM);
349 udelay(1000);
350 /* setup SDRAM refresh rate */
351 writel(0xc2b, LMREFRESH);
352 udelay(1000);
353 /* setup SDRAM type parameters */
354 writel((LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
355 LMTYPE_COLSZ_8),
356 LMTYPE);
357 udelay(1000);
358 /* enable memory controller */
359 writel(LMPWR_MC_PWR_ACT, LMPWR);
360 udelay(1000);
361
362 /* perform dummy reads */
363 for ( i = 0; i < 16; i++ ) {
364 tmp = readl(fbi->screen_base);
365 }
366}
367
368static void enable_clocks(struct fb_info *fbi)
369{
370 /* enable clocks */
371 writel(SYSCLKSRC_PLL_2, SYSCLKSRC);
372 udelay(1000);
373 writel(PIXCLKSRC_PLL_1, PIXCLKSRC);
374 udelay(1000);
375 writel(0x00000000, CLKSLEEP);
376 udelay(1000);
377 writel((Core_Pll_M(0x17) | Core_Pll_N(0x3) | Core_Pll_P(0x0) |
378 CORE_PLL_EN),
379 COREPLL);
380 udelay(1000);
381 writel((Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) |
382 DISP_PLL_EN),
383 DISPPLL);
384
385 writel(0x00000000, VOVRCLK);
386 udelay(1000);
387 writel(PIXCLK_EN, PIXCLK);
388 udelay(1000);
389 writel(MEMCLK_EN, MEMCLK);
390 udelay(1000);
391 writel(0x00000006, M24CLK);
392 udelay(1000);
393 writel(0x00000006, MBXCLK);
394 udelay(1000);
395 writel(SDCLK_EN, SDCLK);
396 udelay(1000);
397 writel(0x00000001, PIXCLKDIV);
398 udelay(1000);
399}
400
401static void __devinit setup_graphics(struct fb_info *fbi)
402{
403 unsigned long gsctrl;
404
405 gsctrl = GSCTRL_GAMMA_EN | Gsctrl_Width(fbi->var.xres - 1) |
406 Gsctrl_Height(fbi->var.yres - 1);
407 switch (fbi->var.bits_per_pixel) {
408 case 16:
409 if (fbi->var.green.length == 5)
410 gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
411 else
412 gsctrl |= GSCTRL_GPIXFMT_RGB565;
413 break;
414 case 24:
415 gsctrl |= GSCTRL_GPIXFMT_RGB888;
416 break;
417 case 32:
418 gsctrl |= GSCTRL_GPIXFMT_ARGB8888;
419 break;
420 }
421
422 writel(gsctrl, GSCTRL);
423 udelay(1000);
424 writel(0x00000000, GBBASE);
425 udelay(1000);
426 writel(0x00ffffff, GDRCTRL);
427 udelay(1000);
428 writel((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);
429 udelay(1000);
430 writel(0x00000000, GPLUT);
431 udelay(1000);
432}
433
434static void __devinit setup_display(struct fb_info *fbi)
435{
436 unsigned long dsctrl = 0;
437
438 dsctrl = DSCTRL_BLNK_POL;
439 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
440 dsctrl |= DSCTRL_HS_POL;
441 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
442 dsctrl |= DSCTRL_VS_POL;
443 writel(dsctrl, DSCTRL);
444 udelay(1000);
445 writel(0xd0303010, DMCTRL);
446 udelay(1000);
447 writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
448}
449
450static void __devinit enable_controller(struct fb_info *fbi)
451{
452 writel(SYSRST_RST, SYSRST);
453 udelay(1000);
454
455
456 enable_clocks(fbi);
457 setup_memc(fbi);
458 setup_graphics(fbi);
459 setup_display(fbi);
460}
461
462#ifdef CONFIG_PM
463/*
464 * Power management hooks. Note that we won't be called from IRQ context,
465 * unlike the blank functions above, so we may sleep.
466 */
467static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
468{
469 /* make frame buffer memory enter self-refresh mode */
470 writel(LMPWR_MC_PWR_SRM, LMPWR);
471 while (LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM)
472 ; /* empty statement */
473
474 /* reset the device, since it's initial state is 'mostly sleeping' */
475 writel(SYSRST_RST, SYSRST);
476 return 0;
477}
478
479static int mbxfb_resume(struct platform_device *dev)
480{
481 struct fb_info *fbi = platform_get_drvdata(dev);
482
483 enable_clocks(fbi);
484/* setup_graphics(fbi); */
485/* setup_display(fbi); */
486
487 writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
488 return 0;
489}
490#else
491#define mbxfb_suspend NULL
492#define mbxfb_resume NULL
493#endif
494
495/* debugfs entries */
496#ifndef CONFIG_FB_MBX_DEBUG
497#define mbxfb_debugfs_init(x) do {} while(0)
498#define mbxfb_debugfs_remove(x) do {} while(0)
499#endif
500
501#define res_size(_r) (((_r)->end - (_r)->start) + 1)
502
503static int __devinit mbxfb_probe(struct platform_device *dev)
504{
505 int ret;
506 struct fb_info *fbi;
507 struct mbxfb_info *mfbi;
508 struct mbxfb_platform_data *pdata;
509
510 dev_dbg(dev, "mbxfb_probe\n");
511
512 fbi = framebuffer_alloc(sizeof(struct mbxfb_info), &dev->dev);
513 if (fbi == NULL) {
514 dev_err(&dev->dev, "framebuffer_alloc failed\n");
515 return -ENOMEM;
516 }
517
518 mfbi = fbi->par;
519 fbi->pseudo_palette = mfbi->pseudo_palette;
520 pdata = dev->dev.platform_data;
521 if (pdata->probe)
522 mfbi->platform_probe = pdata->probe;
523 if (pdata->remove)
524 mfbi->platform_remove = pdata->remove;
525
526 mfbi->fb_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
527 mfbi->reg_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
528
529 if (!mfbi->fb_res || !mfbi->reg_res) {
530 dev_err(&dev->dev, "no resources found\n");
531 ret = -ENODEV;
532 goto err1;
533 }
534
535 mfbi->fb_req = request_mem_region(mfbi->fb_res->start,
536 res_size(mfbi->fb_res), dev->name);
537 if (mfbi->fb_req == NULL) {
538 dev_err(&dev->dev, "failed to claim framebuffer memory\n");
539 ret = -EINVAL;
540 goto err1;
541 }
542 mfbi->fb_phys_addr = mfbi->fb_res->start;
543
544 mfbi->reg_req = request_mem_region(mfbi->reg_res->start,
545 res_size(mfbi->reg_res), dev->name);
546 if (mfbi->reg_req == NULL) {
547 dev_err(&dev->dev, "failed to claim Marathon registers\n");
548 ret = -EINVAL;
549 goto err2;
550 }
551 mfbi->reg_phys_addr = mfbi->reg_res->start;
552
553 mfbi->reg_virt_addr = ioremap_nocache(mfbi->reg_phys_addr,
554 res_size(mfbi->reg_req));
555 if (!mfbi->reg_virt_addr) {
556 dev_err(&dev->dev, "failed to ioremap Marathon registers\n");
557 ret = -EINVAL;
558 goto err3;
559 }
560 virt_base_2700 = (unsigned long)mfbi->reg_virt_addr;
561
562 mfbi->fb_virt_addr = ioremap_nocache(mfbi->fb_phys_addr,
563 res_size(mfbi->fb_req));
564 if (!mfbi->reg_virt_addr) {
565 dev_err(&dev->dev, "failed to ioremap frame buffer\n");
566 ret = -EINVAL;
567 goto err4;
568 }
569
570 /* FIXME: get from platform */
571 fbi->screen_base = (char __iomem *)(mfbi->fb_virt_addr + 0x60000);
572 fbi->screen_size = 8 * 1024 * 1024; /* 8 Megs */
573 fbi->fbops = &mbxfb_ops;
574
575 fbi->var = mbxfb_default;
576 fbi->fix = mbxfb_fix;
577 fbi->fix.smem_start = mfbi->fb_phys_addr + 0x60000;
578 fbi->fix.smem_len = 8 * 1024 * 1024;
579 fbi->fix.line_length = 640 * 2;
580
581 ret = fb_alloc_cmap(&fbi->cmap, 256, 0);
582 if (ret < 0) {
583 dev_err(&dev->dev, "fb_alloc_cmap failed\n");
584 ret = -EINVAL;
585 goto err5;
586 }
587
588 platform_set_drvdata(dev, fbi);
589
590 printk(KERN_INFO "fb%d: mbx frame buffer device\n", fbi->node);
591
592 if (mfbi->platform_probe)
593 mfbi->platform_probe(fbi);
594
595 enable_controller(fbi);
596
597 mbxfb_debugfs_init(fbi);
598
599 ret = register_framebuffer(fbi);
600 if (ret < 0) {
601 dev_err(&dev->dev, "register_framebuffer failed\n");
602 ret = -EINVAL;
603 goto err6;
604 }
605
606 return 0;
607
608err6:
609 fb_dealloc_cmap(&fbi->cmap);
610err5:
611 iounmap(mfbi->fb_virt_addr);
612err4:
613 iounmap(mfbi->reg_virt_addr);
614err3:
615 release_mem_region(mfbi->reg_res->start, res_size(mfbi->reg_res));
616err2:
617 release_mem_region(mfbi->fb_res->start, res_size(mfbi->fb_res));
618err1:
619 framebuffer_release(fbi);
620
621 return ret;
622}
623
624static int __devexit mbxfb_remove(struct platform_device *dev)
625{
626 struct fb_info *fbi = platform_get_drvdata(dev);
627
628 writel(SYSRST_RST, SYSRST);
629 udelay(1000);
630
631 mbxfb_debugfs_remove(fbi);
632
633 if (fbi) {
634 struct mbxfb_info *mfbi = fbi->par;
635
636 unregister_framebuffer(fbi);
637 if (mfbi) {
638 if (mfbi->platform_remove)
639 mfbi->platform_remove(fbi);
640
641 if (mfbi->fb_virt_addr)
642 iounmap(mfbi->fb_virt_addr);
643 if (mfbi->reg_virt_addr)
644 iounmap(mfbi->reg_virt_addr);
645 if (mfbi->reg_req)
646 release_mem_region(mfbi->reg_req->start,
647 res_size(mfbi->reg_req));
648 if (mfbi->fb_req)
649 release_mem_region(mfbi->fb_req->start,
650 res_size(mfbi->fb_req));
651 }
652 framebuffer_release(fbi);
653 }
654
655 return 0;
656}
657
658static struct platform_driver mbxfb_driver = {
659 .probe = mbxfb_probe,
660 .remove = mbxfb_remove,
661 .suspend = mbxfb_suspend,
662 .resume = mbxfb_resume,
663 .driver = {
664 .name = "mbx-fb",
665 },
666};
667
668int __devinit mbxfb_init(void)
669{
670 return platform_driver_register(&mbxfb_driver);
671}
672
673static void __devexit mbxfb_exit(void)
674{
675 platform_driver_unregister(&mbxfb_driver);
676}
677
678module_init(mbxfb_init);
679module_exit(mbxfb_exit);
680
681MODULE_DESCRIPTION("loadable framebuffer driver for Marathon device");
682MODULE_AUTHOR("Mike Rapoport, Compulab");
683MODULE_LICENSE("GPL");
diff --git a/drivers/video/mbx/reg_bits.h b/drivers/video/mbx/reg_bits.h
new file mode 100644
index 000000000000..c226a8e45312
--- /dev/null
+++ b/drivers/video/mbx/reg_bits.h
@@ -0,0 +1,418 @@
1#ifndef __REG_BITS_2700G_
2#define __REG_BITS_2700G_
3
4/* use defines from asm-arm/arch-pxa/bitfields.h for bit fields access */
5#define UData(Data) ((unsigned long) (Data))
6#define Fld(Size, Shft) (((Size) << 16) + (Shft))
7#define FSize(Field) ((Field) >> 16)
8#define FShft(Field) ((Field) & 0x0000FFFF)
9#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
10#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
11#define F1stBit(Field) (UData (1) << FShft (Field))
12
13#define SYSRST_RST (1 << 0)
14
15/* SYSCLKSRC - SYSCLK Source Control Register */
16#define SYSCLKSRC_SEL Fld(2,0)
17#define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
18#define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
19#define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
20
21/* PIXCLKSRC - PIXCLK Source Control Register */
22#define PIXCLKSRC_SEL Fld(2,0)
23#define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
24#define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
25#define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
26
27/* Clock Disable Register */
28#define CLKSLEEP_SLP (1 << 0)
29
30/* Core PLL Control Register */
31#define CORE_PLL_M Fld(6,7)
32#define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M))
33#define CORE_PLL_N Fld(3,4)
34#define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N))
35#define CORE_PLL_P Fld(3,1)
36#define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P))
37#define CORE_PLL_EN (1 << 0)
38
39/* Display PLL Control Register */
40#define DISP_PLL_M Fld(6,7)
41#define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M))
42#define DISP_PLL_N Fld(3,4)
43#define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N))
44#define DISP_PLL_P Fld(3,1)
45#define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P))
46#define DISP_PLL_EN (1 << 0)
47
48/* PLL status register */
49#define PLLSTAT_CORE_PLL_LOST_L (1 << 3)
50#define PLLSTAT_CORE_PLL_LSTS (1 << 2)
51#define PLLSTAT_DISP_PLL_LOST_L (1 << 1)
52#define PLLSTAT_DISP_PLL_LSTS (1 << 0)
53
54/* Video and scale clock control register */
55#define VOVRCLK_EN (1 << 0)
56
57/* Pixel clock control register */
58#define PIXCLK_EN (1 << 0)
59
60/* Memory clock control register */
61#define MEMCLK_EN (1 << 0)
62
63/* MBX clock control register */
64#define MBXCLK_DIV Fld(2,2)
65#define MBXCLK_DIV_1 ((0x0) << FShft(MBXCLK_DIV))
66#define MBXCLK_DIV_2 ((0x1) << FShft(MBXCLK_DIV))
67#define MBXCLK_DIV_3 ((0x2) << FShft(MBXCLK_DIV))
68#define MBXCLK_DIV_4 ((0x3) << FShft(MBXCLK_DIV))
69#define MBXCLK_EN Fld(2,0)
70#define MBXCLK_EN_NONE ((0x0) << FShft(MBXCLK_EN))
71#define MBXCLK_EN_2D ((0x1) << FShft(MBXCLK_EN))
72#define MBXCLK_EN_BOTH ((0x2) << FShft(MBXCLK_EN))
73
74/* M24 clock control register */
75#define M24CLK_DIV Fld(2,1)
76#define M24CLK_DIV_1 ((0x0) << FShft(M24CLK_DIV))
77#define M24CLK_DIV_2 ((0x1) << FShft(M24CLK_DIV))
78#define M24CLK_DIV_3 ((0x2) << FShft(M24CLK_DIV))
79#define M24CLK_DIV_4 ((0x3) << FShft(M24CLK_DIV))
80#define M24CLK_EN (1 << 0)
81
82/* SDRAM clock control register */
83#define SDCLK_EN (1 << 0)
84
85/* PixClk Divisor Register */
86#define PIXCLKDIV_PD Fld(9,0)
87#define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD))
88
89/* LCD Config control register */
90#define LCDCFG_IN_FMT Fld(3,28)
91#define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT))
92#define LCDCFG_LCD1DEN_POL (1 << 27)
93#define LCDCFG_LCD1FCLK_POL (1 << 26)
94#define LCDCFG_LCD1LCLK_POL (1 << 25)
95#define LCDCFG_LCD1D_POL (1 << 24)
96#define LCDCFG_LCD2DEN_POL (1 << 23)
97#define LCDCFG_LCD2FCLK_POL (1 << 22)
98#define LCDCFG_LCD2LCLK_POL (1 << 21)
99#define LCDCFG_LCD2D_POL (1 << 20)
100#define LCDCFG_LCD1_TS (1 << 19)
101#define LCDCFG_LCD1D_DS (1 << 18)
102#define LCDCFG_LCD1C_DS (1 << 17)
103#define LCDCFG_LCD1_IS_IN (1 << 16)
104#define LCDCFG_LCD2_TS (1 << 3)
105#define LCDCFG_LCD2D_DS (1 << 2)
106#define LCDCFG_LCD2C_DS (1 << 1)
107#define LCDCFG_LCD2_IS_IN (1 << 0)
108
109/* On-Die Frame Buffer Power Control Register */
110#define ODFBPWR_SLOW (1 << 2)
111#define ODFBPWR_MODE Fld(2,0)
112#define ODFBPWR_MODE_ACT ((0x0) << FShft(ODFBPWR_MODE))
113#define ODFBPWR_MODE_ACT_LP ((0x1) << FShft(ODFBPWR_MODE))
114#define ODFBPWR_MODE_SLEEP ((0x2) << FShft(ODFBPWR_MODE))
115#define ODFBPWR_MODE_SHUTD ((0x3) << FShft(ODFBPWR_MODE))
116
117/* On-Die Frame Buffer Power State Status Register */
118#define ODFBSTAT_ACT (1 << 2)
119#define ODFBSTAT_SLP (1 << 1)
120#define ODFBSTAT_SDN (1 << 0)
121
122/* LMRST - Local Memory (SDRAM) Reset */
123#define LMRST_MC_RST (1 << 0)
124
125/* LMCFG - Local Memory (SDRAM) Configuration Register */
126#define LMCFG_LMC_DS (1 << 5)
127#define LMCFG_LMD_DS (1 << 4)
128#define LMCFG_LMA_DS (1 << 3)
129#define LMCFG_LMC_TS (1 << 2)
130#define LMCFG_LMD_TS (1 << 1)
131#define LMCFG_LMA_TS (1 << 0)
132
133/* LMPWR - Local Memory (SDRAM) Power Control Register */
134#define LMPWR_MC_PWR_CNT Fld(2,0)
135#define LMPWR_MC_PWR_ACT ((0x0) << FShft(LMPWR_MC_PWR_CNT)) /* Active */
136#define LMPWR_MC_PWR_SRM ((0x1) << FShft(LMPWR_MC_PWR_CNT)) /* Self-refresh */
137#define LMPWR_MC_PWR_DPD ((0x3) << FShft(LMPWR_MC_PWR_CNT)) /* deep power down */
138
139/* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
140#define LMPWRSTAT_MC_PWR_CNT Fld(2,0)
141#define LMPWRSTAT_MC_PWR_ACT ((0x0) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Active */
142#define LMPWRSTAT_MC_PWR_SRM ((0x1) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Self-refresh */
143#define LMPWRSTAT_MC_PWR_DPD ((0x3) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* deep power down */
144
145/* LMTYPE - Local Memory (SDRAM) Type Register */
146#define LMTYPE_CASLAT Fld(3,10)
147#define LMTYPE_CASLAT_1 ((0x1) << FShft(LMTYPE_CASLAT))
148#define LMTYPE_CASLAT_2 ((0x2) << FShft(LMTYPE_CASLAT))
149#define LMTYPE_CASLAT_3 ((0x3) << FShft(LMTYPE_CASLAT))
150#define LMTYPE_BKSZ Fld(2,8)
151#define LMTYPE_BKSZ_1 ((0x1) << FShft(LMTYPE_BKSZ))
152#define LMTYPE_BKSZ_2 ((0x2) << FShft(LMTYPE_BKSZ))
153#define LMTYPE_ROWSZ Fld(4,4)
154#define LMTYPE_ROWSZ_11 ((0xb) << FShft(LMTYPE_ROWSZ))
155#define LMTYPE_ROWSZ_12 ((0xc) << FShft(LMTYPE_ROWSZ))
156#define LMTYPE_ROWSZ_13 ((0xd) << FShft(LMTYPE_ROWSZ))
157#define LMTYPE_COLSZ Fld(4,0)
158#define LMTYPE_COLSZ_7 ((0x7) << FShft(LMTYPE_COLSZ))
159#define LMTYPE_COLSZ_8 ((0x8) << FShft(LMTYPE_COLSZ))
160#define LMTYPE_COLSZ_9 ((0x9) << FShft(LMTYPE_COLSZ))
161#define LMTYPE_COLSZ_10 ((0xa) << FShft(LMTYPE_COLSZ))
162#define LMTYPE_COLSZ_11 ((0xb) << FShft(LMTYPE_COLSZ))
163#define LMTYPE_COLSZ_12 ((0xc) << FShft(LMTYPE_COLSZ))
164
165/* LMTIM - Local Memory (SDRAM) Timing Register */
166#define LMTIM_TRAS Fld(4,16)
167#define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS))
168#define LMTIM_TRP Fld(4,12)
169#define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP))
170#define LMTIM_TRCD Fld(4,8)
171#define Lmtim_Trcd(x) ((x) << FShft(LMTIM_TRCD))
172#define LMTIM_TRC Fld(4,4)
173#define Lmtim_Trc(x) ((x) << FShft(LMTIM_TRC))
174#define LMTIM_TDPL Fld(4,0)
175#define Lmtim_Tdpl(x) ((x) << FShft(LMTIM_TDPL))
176
177/* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
178#define LMREFRESH_TREF Fld(2,0)
179#define Lmrefresh_Tref(x) ((x) << FShft(LMREFRESH_TREF))
180
181/* GSCTRL - Graphics surface control register */
182#define GSCTRL_LUT_EN (1 << 31)
183#define GSCTRL_GPIXFMT Fld(4,27)
184#define GSCTRL_GPIXFMT_INDEXED ((0x0) << FShft(GSCTRL_GPIXFMT))
185#define GSCTRL_GPIXFMT_ARGB4444 ((0x4) << FShft(GSCTRL_GPIXFMT))
186#define GSCTRL_GPIXFMT_ARGB1555 ((0x5) << FShft(GSCTRL_GPIXFMT))
187#define GSCTRL_GPIXFMT_RGB888 ((0x6) << FShft(GSCTRL_GPIXFMT))
188#define GSCTRL_GPIXFMT_RGB565 ((0x7) << FShft(GSCTRL_GPIXFMT))
189#define GSCTRL_GPIXFMT_ARGB8888 ((0x8) << FShft(GSCTRL_GPIXFMT))
190#define GSCTRL_GAMMA_EN (1 << 26)
191
192#define GSCTRL_GSWIDTH Fld(11,11)
193#define Gsctrl_Width(Pixel) /* Display Width [1..2048 pix.] */ \
194 (((Pixel) - 1) << FShft(GSCTRL_GSWIDTH))
195
196#define GSCTRL_GSHEIGHT Fld(11,0)
197#define Gsctrl_Height(Pixel) /* Display Height [1..2048 pix.] */ \
198 (((Pixel) - 1) << FShft(GSCTRL_GSHEIGHT))
199
200/* GBBASE fileds */
201#define GBBASE_GLALPHA Fld(8,24)
202#define Gbbase_Glalpha(x) ((x) << FShft(GBBASE_GLALPHA))
203
204#define GBBASE_COLKEY Fld(24,0)
205#define Gbbase_Colkey(x) ((x) << FShft(GBBASE_COLKEY))
206
207/* GDRCTRL fields */
208#define GDRCTRL_PIXDBL (1 << 31)
209#define GDRCTRL_PIXHLV (1 << 30)
210#define GDRCTRL_LNDBL (1 << 29)
211#define GDRCTRL_LNHLV (1 << 28)
212#define GDRCTRL_COLKEYM Fld(24,0)
213#define Gdrctrl_Colkeym(x) ((x) << FShft(GDRCTRL_COLKEYM))
214
215/* GSCADR graphics stream control address register fields */
216#define GSCADR_STR_EN (1 << 31)
217#define GSCADR_COLKEY_EN (1 << 30)
218#define GSCADR_COLKEYSCR (1 << 29)
219#define GSCADR_BLEND_M Fld(2,27)
220#define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
221#define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
222#define GSCADR_BLEND_GLOB ((0x2) << FShft(GSCADR_BLEND_M))
223#define GSCADR_BLEND_PIX ((0x3) << FShft(GSCADR_BLEND_M))
224#define GSCADR_BLEND_POS Fld(2,24)
225#define GSCADR_BLEND_GFX ((0x0) << FShft(GSCADR_BLEND_POS))
226#define GSCADR_BLEND_VID ((0x1) << FShft(GSCADR_BLEND_POS))
227#define GSCADR_BLEND_CUR ((0x2) << FShft(GSCADR_BLEND_POS))
228#define GSCADR_GBASE_ADR Fld(23,0)
229#define Gscadr_Gbase_Adr(x) ((x) << FShft(GSCADR_GBASE_ADR))
230
231/* GSADR graphics stride address register fields */
232#define GSADR_SRCSTRIDE Fld(10,22)
233#define Gsadr_Srcstride(x) ((x) << FShft(GSADR_SRCSTRIDE))
234#define GSADR_XSTART Fld(11,11)
235#define Gsadr_Xstart(x) ((x) << FShft(GSADR_XSTART))
236#define GSADR_YSTART Fld(11,0)
237#define Gsadr_Ystart(y) ((y) << FShft(GSADR_YSTART))
238
239/* GPLUT graphics palette register fields */
240#define GPLUT_LUTADR Fld(8,24)
241#define Gplut_Lutadr(x) ((x) << FShft(GPLUT_LUTADR))
242#define GPLUT_LUTDATA Fld(24,0)
243#define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA))
244
245/* HCCTRL - Hardware Cursor Register fields */
246#define HCCTRL_CUR_EN (1 << 31)
247#define HCCTRL_COLKEY_EN (1 << 29)
248#define HCCTRL_COLKEYSRC (1 << 28)
249#define HCCTRL_BLEND_M Fld(2,26)
250#define HCCTRL_BLEND_NONE ((0x0) << FShft(HCCTRL_BLEND_M))
251#define HCCTRL_BLEND_INV ((0x1) << FShft(HCCTRL_BLEND_M))
252#define HCCTRL_BLEND_GLOB ((0x2) << FShft(HCCTRL_BLEND_M))
253#define HCCTRL_BLEND_PIX ((0x3) << FShft(HCCTRL_BLEND_M))
254#define HCCTRL_CPIXFMT Fld(3,23)
255#define HCCTRL_CPIXFMT_RGB332 ((0x3) << FShft(HCCTRL_CPIXFMT))
256#define HCCTRL_CPIXFMT_ARGB4444 ((0x4) << FShft(HCCTRL_CPIXFMT))
257#define HCCTRL_CPIXFMT_ARGB1555 ((0x5) << FShft(HCCTRL_CPIXFMT))
258#define HCCTRL_CBASE_ADR Fld(23,0)
259#define Hcctrl_Cbase_Adr(x) ((x) << FShft(HCCTRL_CBASE_ADR))
260
261/* HCSIZE Hardware Cursor Size Register fields */
262#define HCSIZE_BLEND_POS Fld(2,29)
263#define HCSIZE_BLEND_GFX ((0x0) << FShft(HCSIZE_BLEND_POS))
264#define HCSIZE_BLEND_VID ((0x1) << FShft(HCSIZE_BLEND_POS))
265#define HCSIZE_BLEND_CUR ((0x2) << FShft(HCSIZE_BLEND_POS))
266#define HCSIZE_CWIDTH Fld(3,16)
267#define Hcsize_Cwidth(x) ((x) << FShft(HCSIZE_CWIDTH))
268#define HCSIZE_CHEIGHT Fld(3,0)
269#define Hcsize_Cheight(x) ((x) << FShft(HCSIZE_CHEIGHT))
270
271/* HCPOS Hardware Cursor Position Register fields */
272#define HCPOS_SWITCHSRC (1 << 30)
273#define HCPOS_CURBLINK Fld(6,24)
274#define Hcpos_Curblink(x) ((x) << FShft(HCPOS_CURBLINK))
275#define HCPOS_XSTART Fld(12,12)
276#define Hcpos_Xstart(x) ((x) << FShft(HCPOS_XSTART))
277#define HCPOS_YSTART Fld(12,0)
278#define Hcpos_Ystart(y) ((y) << FShft(HCPOS_YSTART))
279
280/* HCBADR Hardware Cursor Blend Address Register */
281#define HCBADR_GLALPHA Fld(8,24)
282#define Hcbadr_Glalpha(x) ((x) << FShft(HCBADR_GLALPHA))
283#define HCBADR_COLKEY Fld(24,0)
284#define Hcbadr_Colkey(x) ((x) << FShft(HCBADR_COLKEY))
285
286/* HCCKMSK - Hardware Cursor Color Key Mask Register */
287#define HCCKMSK_COLKEY_M Fld(24,0)
288#define Hcckmsk_Colkey_M(x) ((x) << FShft(HCCKMSK_COLKEY_M))
289
290/* DSCTRL - Display sync control register */
291#define DSCTRL_SYNCGEN_EN (1 << 31)
292#define DSCTRL_DPL_RST (1 << 29)
293#define DSCTRL_PWRDN_M (1 << 28)
294#define DSCTRL_UPDSYNCCNT (1 << 26)
295#define DSCTRL_UPDINTCNT (1 << 25)
296#define DSCTRL_UPDCNT (1 << 24)
297#define DSCTRL_UPDWAIT Fld(4,16)
298#define Dsctrl_Updwait(x) ((x) << FShft(DSCTRL_UPDWAIT))
299#define DSCTRL_CLKPOL (1 << 11)
300#define DSCTRL_CSYNC_EN (1 << 10)
301#define DSCTRL_VS_SLAVE (1 << 7)
302#define DSCTRL_HS_SLAVE (1 << 6)
303#define DSCTRL_BLNK_POL (1 << 5)
304#define DSCTRL_BLNK_DIS (1 << 4)
305#define DSCTRL_VS_POL (1 << 3)
306#define DSCTRL_VS_DIS (1 << 2)
307#define DSCTRL_HS_POL (1 << 1)
308#define DSCTRL_HS_DIS (1 << 0)
309
310/* DHT01 - Display horizontal timing register 01 */
311#define DHT01_HBPS Fld(12,16)
312#define Dht01_Hbps(x) ((x) << FShft(DHT01_HBPS))
313#define DHT01_HT Fld(12,0)
314#define Dht01_Ht(x) ((x) << FShft(DHT01_HT))
315
316/* DHT02 - Display horizontal timing register 02 */
317#define DHT02_HAS Fld(12,16)
318#define Dht02_Has(x) ((x) << FShft(DHT02_HAS))
319#define DHT02_HLBS Fld(12,0)
320#define Dht02_Hlbs(x) ((x) << FShft(DHT02_HLBS))
321
322/* DHT03 - Display horizontal timing register 03 */
323#define DHT03_HFPS Fld(12,16)
324#define Dht03_Hfps(x) ((x) << FShft(DHT03_HFPS))
325#define DHT03_HRBS Fld(12,0)
326#define Dht03_Hrbs(x) ((x) << FShft(DHT03_HRBS))
327
328/* DVT01 - Display vertical timing register 01 */
329#define DVT01_VBPS Fld(12,16)
330#define Dvt01_Vbps(x) ((x) << FShft(DVT01_VBPS))
331#define DVT01_VT Fld(12,0)
332#define Dvt01_Vt(x) ((x) << FShft(DVT01_VT))
333
334/* DVT02 - Display vertical timing register 02 */
335#define DVT02_VAS Fld(12,16)
336#define Dvt02_Vas(x) ((x) << FShft(DVT02_VAS))
337#define DVT02_VTBS Fld(12,0)
338#define Dvt02_Vtbs(x) ((x) << FShft(DVT02_VTBS))
339
340/* DVT03 - Display vertical timing register 03 */
341#define DVT03_VFPS Fld(12,16)
342#define Dvt03_Vfps(x) ((x) << FShft(DVT03_VFPS))
343#define DVT03_VBBS Fld(12,0)
344#define Dvt03_Vbbs(x) ((x) << FShft(DVT03_VBBS))
345
346/* DVECTRL - display vertical event control register */
347#define DVECTRL_VEVENT Fld(12,16)
348#define Dvectrl_Vevent(x) ((x) << FShft(DVECTRL_VEVENT))
349#define DVECTRL_VFETCH Fld(12,0)
350#define Dvectrl_Vfetch(x) ((x) << FShft(DVECTRL_VFETCH))
351
352/* DHDET - display horizontal DE timing register */
353#define DHDET_HDES Fld(12,16)
354#define Dhdet_Hdes(x) ((x) << FShft(DHDET_HDES))
355#define DHDET_HDEF Fld(12,0)
356#define Dhdet_Hdef(x) ((x) << FShft(DHDET_HDEF))
357
358/* DVDET - display vertical DE timing register */
359#define DVDET_VDES Fld(12,16)
360#define Dvdet_Vdes(x) ((x) << FShft(DVDET_VDES))
361#define DVDET_VDEF Fld(12,0)
362#define Dvdet_Vdef(x) ((x) << FShft(DVDET_VDEF))
363
364/* DODMSK - display output data mask register */
365#define DODMSK_MASK_LVL (1 << 31)
366#define DODMSK_BLNK_LVL (1 << 30)
367#define DODMSK_MASK_B Fld(8,16)
368#define Dodmsk_Mask_B(x) ((x) << FShft(DODMSK_MASK_B))
369#define DODMSK_MASK_G Fld(8,8)
370#define Dodmsk_Mask_G(x) ((x) << FShft(DODMSK_MASK_G))
371#define DODMSK_MASK_R Fld(8,0)
372#define Dodmsk_Mask_R(x) ((x) << FShft(DODMSK_MASK_R))
373
374/* DBCOL - display border color control register */
375#define DBCOL_BORDCOL Fld(24,0)
376#define Dbcol_Bordcol(x) ((x) << FShft(DBCOL_BORDCOL))
377
378/* DVLNUM - display vertical line number register */
379#define DVLNUM_VLINE Fld(12,0)
380#define Dvlnum_Vline(x) ((x) << FShft(DVLNUM_VLINE))
381
382/* DMCTRL - Display Memory Control Register */
383#define DMCTRL_MEM_REF Fld(2,30)
384#define DMCTRL_MEM_REF_ACT ((0x0) << FShft(DMCTRL_MEM_REF))
385#define DMCTRL_MEM_REF_HB ((0x1) << FShft(DMCTRL_MEM_REF))
386#define DMCTRL_MEM_REF_VB ((0x2) << FShft(DMCTRL_MEM_REF))
387#define DMCTRL_MEM_REF_BOTH ((0x3) << FShft(DMCTRL_MEM_REF))
388#define DMCTRL_UV_THRHLD Fld(6,24)
389#define Dmctrl_Uv_Thrhld(x) ((x) << FShft(DMCTRL_UV_THRHLD))
390#define DMCTRL_V_THRHLD Fld(7,16)
391#define Dmctrl_V_Thrhld(x) ((x) << FShft(DMCTRL_V_THRHLD))
392#define DMCTRL_D_THRHLD Fld(7,8)
393#define Dmctrl_D_Thrhld(x) ((x) << FShft(DMCTRL_D_THRHLD))
394#define DMCTRL_BURSTLEN Fld(6,0)
395#define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN))
396
397
398/* DLSTS - display load status register */
399#define DLSTS_RLD_ADONE (1 << 23)
400/* #define DLSTS_RLD_ADOUT Fld(23,0) */
401
402/* DLLCTRL - display list load control register */
403#define DLLCTRL_RLD_ADRLN Fld(8,24)
404#define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN))
405
406/* SPOCTRL - Scale Pitch/Order Control Register */
407#define SPOCTRL_H_SC_BP (1 << 31)
408#define SPOCTRL_V_SC_BP (1 << 30)
409#define SPOCTRL_HV_SC_OR (1 << 29)
410#define SPOCTRL_VS_UR_C (1 << 27)
411#define SPOCTRL_VORDER Fld(2,16)
412#define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER))
413#define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER))
414#define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER))
415#define SPOCTRL_VPITCH Fld(16,0)
416#define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH))
417
418#endif /* __REG_BITS_2700G_ */
diff --git a/drivers/video/mbx/regs.h b/drivers/video/mbx/regs.h
new file mode 100644
index 000000000000..ad20be07666b
--- /dev/null
+++ b/drivers/video/mbx/regs.h
@@ -0,0 +1,195 @@
1#ifndef __REGS_2700G_
2#define __REGS_2700G_
3
4/* extern unsigned long virt_base_2700; */
5/* #define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700)) */
6#define __REG_2700G(x) ((x)+virt_base_2700)
7
8/* System Configuration Registers (0x0000_0000 0x0000_0010) */
9#define SYSCFG __REG_2700G(0x00000000)
10#define PFBASE __REG_2700G(0x00000004)
11#define PFCEIL __REG_2700G(0x00000008)
12#define POLLFLAG __REG_2700G(0x0000000c)
13#define SYSRST __REG_2700G(0x00000010)
14
15/* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
16#define NINTPW __REG_2700G(0x00000014)
17#define MINTENABLE __REG_2700G(0x00000018)
18#define MINTSTAT __REG_2700G(0x0000001c)
19#define SINTENABLE __REG_2700G(0x00000020)
20#define SINTSTAT __REG_2700G(0x00000024)
21#define SINTCLR __REG_2700G(0x00000028)
22
23/* Clock Control Registers (0x0000_002C 0x0000_005F) */
24#define SYSCLKSRC __REG_2700G(0x0000002c)
25#define PIXCLKSRC __REG_2700G(0x00000030)
26#define CLKSLEEP __REG_2700G(0x00000034)
27#define COREPLL __REG_2700G(0x00000038)
28#define DISPPLL __REG_2700G(0x0000003c)
29#define PLLSTAT __REG_2700G(0x00000040)
30#define VOVRCLK __REG_2700G(0x00000044)
31#define PIXCLK __REG_2700G(0x00000048)
32#define MEMCLK __REG_2700G(0x0000004c)
33#define M24CLK __REG_2700G(0x00000054)
34#define MBXCLK __REG_2700G(0x00000054)
35#define SDCLK __REG_2700G(0x00000058)
36#define PIXCLKDIV __REG_2700G(0x0000005c)
37
38/* LCD Port Control Register (0x0000_0060 0x0000_006F) */
39#define LCD_CONFIG __REG_2700G(0x00000060)
40
41/* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */
42#define ODFBPWR __REG_2700G(0x00000064)
43#define ODFBSTAT __REG_2700G(0x00000068)
44
45/* GPIO Registers (0x0000_006C 0x0000_007F) */
46#define GPIOCGF __REG_2700G(0x0000006c)
47#define GPIOHI __REG_2700G(0x00000070)
48#define GPIOLO __REG_2700G(0x00000074)
49#define GPIOSTAT __REG_2700G(0x00000078)
50
51/* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
52#define PWMRST __REG_2700G(0x00000200)
53#define PWMCFG __REG_2700G(0x00000204)
54#define PWM0DIV __REG_2700G(0x00000210)
55#define PWM0DUTY __REG_2700G(0x00000214)
56#define PWM0PER __REG_2700G(0x00000218)
57#define PWM1DIV __REG_2700G(0x00000220)
58#define PWM1DUTY __REG_2700G(0x00000224)
59#define PWM1PER __REG_2700G(0x00000228)
60
61/* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */
62#define ID __REG_2700G(0x00000FF0)
63
64/* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */
65#define LMRST __REG_2700G(0x00001000)
66#define LMCFG __REG_2700G(0x00001004)
67#define LMPWR __REG_2700G(0x00001008)
68#define LMPWRSTAT __REG_2700G(0x0000100c)
69#define LMCEMR __REG_2700G(0x00001010)
70#define LMTYPE __REG_2700G(0x00001014)
71#define LMTIM __REG_2700G(0x00001018)
72#define LMREFRESH __REG_2700G(0x0000101c)
73#define LMPROTMIN __REG_2700G(0x00001020)
74#define LMPROTMAX __REG_2700G(0x00001024)
75#define LMPROTCFG __REG_2700G(0x00001028)
76#define LMPROTERR __REG_2700G(0x0000102c)
77
78/* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */
79#define GSCTRL __REG_2700G(0x00002000)
80#define VSCTRL __REG_2700G(0x00002004)
81#define GBBASE __REG_2700G(0x00002020)
82#define VBBASE __REG_2700G(0x00002024)
83#define GDRCTRL __REG_2700G(0x00002040)
84#define VCMSK __REG_2700G(0x00002044)
85#define GSCADR __REG_2700G(0x00002060)
86#define VSCADR __REG_2700G(0x00002064)
87#define VUBASE __REG_2700G(0x00002084)
88#define VVBASE __REG_2700G(0x000020a4)
89#define GSADR __REG_2700G(0x000020c0)
90#define VSADR __REG_2700G(0x000020c4)
91#define HCCTRL __REG_2700G(0x00002100)
92#define HCSIZE __REG_2700G(0x00002110)
93#define HCPOS __REG_2700G(0x00002120)
94#define HCBADR __REG_2700G(0x00002130)
95#define HCCKMSK __REG_2700G(0x00002140)
96#define GPLUT __REG_2700G(0x00002150)
97#define DSCTRL __REG_2700G(0x00002154)
98#define DHT01 __REG_2700G(0x00002158)
99#define DHT02 __REG_2700G(0x0000215c)
100#define DHT03 __REG_2700G(0x00002160)
101#define DVT01 __REG_2700G(0x00002164)
102#define DVT02 __REG_2700G(0x00002168)
103#define DVT03 __REG_2700G(0x0000216c)
104#define DBCOL __REG_2700G(0x00002170)
105#define BGCOLOR __REG_2700G(0x00002174)
106#define DINTRS __REG_2700G(0x00002178)
107#define DINTRE __REG_2700G(0x0000217c)
108#define DINTRCNT __REG_2700G(0x00002180)
109#define DSIG __REG_2700G(0x00002184)
110#define DMCTRL __REG_2700G(0x00002188)
111#define CLIPCTRL __REG_2700G(0x0000218c)
112#define SPOCTRL __REG_2700G(0x00002190)
113#define SVCTRL __REG_2700G(0x00002194)
114
115/* 0x0000_2198 */
116/* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */
117#define VSCOEFF0 __REG_2700G(0x00002198)
118#define VSCOEFF1 __REG_2700G(0x0000219c)
119#define VSCOEFF2 __REG_2700G(0x000021a0)
120#define VSCOEFF3 __REG_2700G(0x000021a4)
121#define VSCOEFF4 __REG_2700G(0x000021a8)
122
123#define SHCTRL __REG_2700G(0x000021b0)
124
125/* 0x0000_21B4 */
126/* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */
127#define HSCOEFF0 __REG_2700G(0x000021b4)
128#define HSCOEFF1 __REG_2700G(0x000021b8)
129#define HSCOEFF2 __REG_2700G(0x000021bc)
130#define HSCOEFF3 __REG_2700G(0x000021b0)
131#define HSCOEFF4 __REG_2700G(0x000021c4)
132#define HSCOEFF5 __REG_2700G(0x000021c8)
133#define HSCOEFF6 __REG_2700G(0x000021cc)
134#define HSCOEFF7 __REG_2700G(0x000021d0)
135#define HSCOEFF8 __REG_2700G(0x000021d4)
136
137#define SSSIZE __REG_2700G(0x000021D8)
138
139/* 0x0000_2200 */
140/* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */
141#define VIDGAM0 __REG_2700G(0x00002200)
142#define VIDGAM1 __REG_2700G(0x00002204)
143#define VIDGAM2 __REG_2700G(0x00002208)
144#define VIDGAM3 __REG_2700G(0x0000220c)
145#define VIDGAM4 __REG_2700G(0x00002210)
146#define VIDGAM5 __REG_2700G(0x00002214)
147#define VIDGAM6 __REG_2700G(0x00002218)
148#define VIDGAM7 __REG_2700G(0x0000221c)
149#define VIDGAM8 __REG_2700G(0x00002220)
150#define VIDGAM9 __REG_2700G(0x00002224)
151#define VIDGAM10 __REG_2700G(0x00002228)
152#define VIDGAM11 __REG_2700G(0x0000222c)
153#define VIDGAM12 __REG_2700G(0x00002230)
154#define VIDGAM13 __REG_2700G(0x00002234)
155#define VIDGAM14 __REG_2700G(0x00002238)
156#define VIDGAM15 __REG_2700G(0x0000223c)
157#define VIDGAM16 __REG_2700G(0x00002240)
158
159/* 0x0000_2250 */
160/* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */
161#define GFXGAM0 __REG_2700G(0x00002250)
162#define GFXGAM1 __REG_2700G(0x00002254)
163#define GFXGAM2 __REG_2700G(0x00002258)
164#define GFXGAM3 __REG_2700G(0x0000225c)
165#define GFXGAM4 __REG_2700G(0x00002260)
166#define GFXGAM5 __REG_2700G(0x00002264)
167#define GFXGAM6 __REG_2700G(0x00002268)
168#define GFXGAM7 __REG_2700G(0x0000226c)
169#define GFXGAM8 __REG_2700G(0x00002270)
170#define GFXGAM9 __REG_2700G(0x00002274)
171#define GFXGAM10 __REG_2700G(0x00002278)
172#define GFXGAM11 __REG_2700G(0x0000227c)
173#define GFXGAM12 __REG_2700G(0x00002280)
174#define GFXGAM13 __REG_2700G(0x00002284)
175#define GFXGAM14 __REG_2700G(0x00002288)
176#define GFXGAM15 __REG_2700G(0x0000228c)
177#define GFXGAM16 __REG_2700G(0x00002290)
178
179#define DLSTS __REG_2700G(0x00002300)
180#define DLLCTRL __REG_2700G(0x00002304)
181#define DVLNUM __REG_2700G(0x00002308)
182#define DUCTRL __REG_2700G(0x0000230c)
183#define DVECTRL __REG_2700G(0x00002310)
184#define DHDET __REG_2700G(0x00002314)
185#define DVDET __REG_2700G(0x00002318)
186#define DODMSK __REG_2700G(0x0000231c)
187#define CSC01 __REG_2700G(0x00002330)
188#define CSC02 __REG_2700G(0x00002334)
189#define CSC03 __REG_2700G(0x00002338)
190#define CSC04 __REG_2700G(0x0000233c)
191#define CSC05 __REG_2700G(0x00002340)
192
193#define FB_MEMORY_START __REG_2700G(0x00060000)
194
195#endif /* __REGS_2700G_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 16:01:15 -0500