aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video/matrox/matroxfb_misc.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/video/matrox/matroxfb_misc.c')
-rw-r--r--drivers/video/matrox/matroxfb_misc.c288
1 files changed, 153 insertions, 135 deletions
diff --git a/drivers/video/matrox/matroxfb_misc.c b/drivers/video/matrox/matroxfb_misc.c
index 5b5f072fc1a8..9948ca2a3046 100644
--- a/drivers/video/matrox/matroxfb_misc.c
+++ b/drivers/video/matrox/matroxfb_misc.c
@@ -89,13 +89,15 @@
89#include <linux/interrupt.h> 89#include <linux/interrupt.h>
90#include <linux/matroxfb.h> 90#include <linux/matroxfb.h>
91 91
92void matroxfb_DAC_out(CPMINFO int reg, int val) { 92void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
93{
93 DBG_REG(__func__) 94 DBG_REG(__func__)
94 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg); 95 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
95 mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val); 96 mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
96} 97}
97 98
98int matroxfb_DAC_in(CPMINFO int reg) { 99int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
100{
99 DBG_REG(__func__) 101 DBG_REG(__func__)
100 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg); 102 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
101 return mga_inb(M_RAMDAC_BASE+M_X_DATAREG); 103 return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
@@ -184,13 +186,14 @@ int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int f
184 return bestvco; 186 return bestvco;
185} 187}
186 188
187int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) { 189int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
190{
188 unsigned int hd, hs, he, hbe, ht; 191 unsigned int hd, hs, he, hbe, ht;
189 unsigned int vd, vs, ve, vt, lc; 192 unsigned int vd, vs, ve, vt, lc;
190 unsigned int wd; 193 unsigned int wd;
191 unsigned int divider; 194 unsigned int divider;
192 int i; 195 int i;
193 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw); 196 struct matrox_hw_state * const hw = &minfo->hw;
194 197
195 DBG(__func__) 198 DBG(__func__)
196 199
@@ -240,7 +243,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
240 /* standard timmings are in 8pixels, but for interleaved we cannot */ 243 /* standard timmings are in 8pixels, but for interleaved we cannot */
241 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */ 244 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
242 /* using 16 or more pixels per unit can save us */ 245 /* using 16 or more pixels per unit can save us */
243 divider = ACCESS_FBINFO(curr.final_bppShift); 246 divider = minfo->curr.final_bppShift;
244 while (divider & 3) { 247 while (divider & 3) {
245 hd >>= 1; 248 hd >>= 1;
246 hs >>= 1; 249 hs >>= 1;
@@ -270,7 +273,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
270 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04)) 273 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
271 ht++; 274 ht++;
272 hbe = ht; 275 hbe = ht;
273 wd = ACCESS_FBINFO(fbcon).var.xres_virtual * ACCESS_FBINFO(curr.final_bppShift) / 64; 276 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
274 277
275 hw->CRTCEXT[0] = 0; 278 hw->CRTCEXT[0] = 0;
276 hw->CRTCEXT[5] = 0; 279 hw->CRTCEXT[5] = 0;
@@ -287,7 +290,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
287 ((hs & 0x100) >> 6) | /* sync start */ 290 ((hs & 0x100) >> 6) | /* sync start */
288 (hbe & 0x040); /* end hor. blanking */ 291 (hbe & 0x040); /* end hor. blanking */
289 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */ 292 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */
290 if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1) 293 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
291 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */ 294 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
292 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) | 295 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
293 ((vd & 0x400) >> 8) | /* disp end */ 296 ((vd & 0x400) >> 8) | /* disp end */
@@ -331,9 +334,10 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
331 return 0; 334 return 0;
332}; 335};
333 336
334void matroxfb_vgaHWrestore(WPMINFO2) { 337void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
338{
335 int i; 339 int i;
336 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw); 340 struct matrox_hw_state * const hw = &minfo->hw;
337 CRITFLAGS 341 CRITFLAGS
338 342
339 DBG(__func__) 343 DBG(__func__)
@@ -522,7 +526,9 @@ static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
522#endif 526#endif
523} 527}
524 528
525static int parse_pins1(WPMINFO const struct matrox_bios* bd) { 529static int parse_pins1(struct matrox_fb_info *minfo,
530 const struct matrox_bios *bd)
531{
526 unsigned int maxdac; 532 unsigned int maxdac;
527 533
528 switch (bd->pins[22]) { 534 switch (bd->pins[22]) {
@@ -533,173 +539,188 @@ static int parse_pins1(WPMINFO const struct matrox_bios* bd) {
533 if (get_unaligned_le16(bd->pins + 24)) { 539 if (get_unaligned_le16(bd->pins + 24)) {
534 maxdac = get_unaligned_le16(bd->pins + 24) * 10; 540 maxdac = get_unaligned_le16(bd->pins + 24) * 10;
535 } 541 }
536 MINFO->limits.pixel.vcomax = maxdac; 542 minfo->limits.pixel.vcomax = maxdac;
537 MINFO->values.pll.system = get_unaligned_le16(bd->pins + 28) ? 543 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
538 get_unaligned_le16(bd->pins + 28) * 10 : 50000; 544 get_unaligned_le16(bd->pins + 28) * 10 : 50000;
539 /* ignore 4MB, 8MB, module clocks */ 545 /* ignore 4MB, 8MB, module clocks */
540 MINFO->features.pll.ref_freq = 14318; 546 minfo->features.pll.ref_freq = 14318;
541 MINFO->values.reg.mctlwtst = 0x00030101; 547 minfo->values.reg.mctlwtst = 0x00030101;
542 return 0; 548 return 0;
543} 549}
544 550
545static void default_pins1(WPMINFO2) { 551static void default_pins1(struct matrox_fb_info *minfo)
552{
546 /* Millennium */ 553 /* Millennium */
547 MINFO->limits.pixel.vcomax = 220000; 554 minfo->limits.pixel.vcomax = 220000;
548 MINFO->values.pll.system = 50000; 555 minfo->values.pll.system = 50000;
549 MINFO->features.pll.ref_freq = 14318; 556 minfo->features.pll.ref_freq = 14318;
550 MINFO->values.reg.mctlwtst = 0x00030101; 557 minfo->values.reg.mctlwtst = 0x00030101;
551} 558}
552 559
553static int parse_pins2(WPMINFO const struct matrox_bios* bd) { 560static int parse_pins2(struct matrox_fb_info *minfo,
554 MINFO->limits.pixel.vcomax = 561 const struct matrox_bios *bd)
555 MINFO->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000); 562{
556 MINFO->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) | 563 minfo->limits.pixel.vcomax =
564 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
565 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
557 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) | 566 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
558 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) | 567 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
559 ((bd->pins[51] & 0x08) ? 0x00020000 : 0); 568 ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
560 MINFO->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000); 569 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
561 MINFO->features.pll.ref_freq = 14318; 570 minfo->features.pll.ref_freq = 14318;
562 return 0; 571 return 0;
563} 572}
564 573
565static void default_pins2(WPMINFO2) { 574static void default_pins2(struct matrox_fb_info *minfo)
575{
566 /* Millennium II, Mystique */ 576 /* Millennium II, Mystique */
567 MINFO->limits.pixel.vcomax = 577 minfo->limits.pixel.vcomax =
568 MINFO->limits.system.vcomax = 230000; 578 minfo->limits.system.vcomax = 230000;
569 MINFO->values.reg.mctlwtst = 0x00030101; 579 minfo->values.reg.mctlwtst = 0x00030101;
570 MINFO->values.pll.system = 50000; 580 minfo->values.pll.system = 50000;
571 MINFO->features.pll.ref_freq = 14318; 581 minfo->features.pll.ref_freq = 14318;
572} 582}
573 583
574static int parse_pins3(WPMINFO const struct matrox_bios* bd) { 584static int parse_pins3(struct matrox_fb_info *minfo,
575 MINFO->limits.pixel.vcomax = 585 const struct matrox_bios *bd)
576 MINFO->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000); 586{
577 MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ? 587 minfo->limits.pixel.vcomax =
588 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
589 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
578 0x01250A21 : get_unaligned_le32(bd->pins + 48); 590 0x01250A21 : get_unaligned_le32(bd->pins + 48);
579 /* memory config */ 591 /* memory config */
580 MINFO->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) | 592 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
581 ((bd->pins[57] << 22) & 0x00C00000) | 593 ((bd->pins[57] << 22) & 0x00C00000) |
582 ((bd->pins[56] << 1) & 0x000001E0) | 594 ((bd->pins[56] << 1) & 0x000001E0) |
583 ( bd->pins[56] & 0x0000000F); 595 ( bd->pins[56] & 0x0000000F);
584 MINFO->values.reg.opt = (bd->pins[54] & 7) << 10; 596 minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
585 MINFO->values.reg.opt2 = bd->pins[58] << 12; 597 minfo->values.reg.opt2 = bd->pins[58] << 12;
586 MINFO->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000; 598 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
587 return 0; 599 return 0;
588} 600}
589 601
590static void default_pins3(WPMINFO2) { 602static void default_pins3(struct matrox_fb_info *minfo)
603{
591 /* G100, G200 */ 604 /* G100, G200 */
592 MINFO->limits.pixel.vcomax = 605 minfo->limits.pixel.vcomax =
593 MINFO->limits.system.vcomax = 230000; 606 minfo->limits.system.vcomax = 230000;
594 MINFO->values.reg.mctlwtst = 0x01250A21; 607 minfo->values.reg.mctlwtst = 0x01250A21;
595 MINFO->values.reg.memrdbk = 0x00000000; 608 minfo->values.reg.memrdbk = 0x00000000;
596 MINFO->values.reg.opt = 0x00000C00; 609 minfo->values.reg.opt = 0x00000C00;
597 MINFO->values.reg.opt2 = 0x00000000; 610 minfo->values.reg.opt2 = 0x00000000;
598 MINFO->features.pll.ref_freq = 27000; 611 minfo->features.pll.ref_freq = 27000;
599} 612}
600 613
601static int parse_pins4(WPMINFO const struct matrox_bios* bd) { 614static int parse_pins4(struct matrox_fb_info *minfo,
602 MINFO->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000; 615 const struct matrox_bios *bd)
603 MINFO->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 38] * 4000; 616{
604 MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71); 617 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
605 MINFO->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) | 618 minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
619 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
620 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
606 ((bd->pins[87] << 22) & 0x00C00000) | 621 ((bd->pins[87] << 22) & 0x00C00000) |
607 ((bd->pins[86] << 1) & 0x000001E0) | 622 ((bd->pins[86] << 1) & 0x000001E0) |
608 ( bd->pins[86] & 0x0000000F); 623 ( bd->pins[86] & 0x0000000F);
609 MINFO->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) | 624 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
610 ((bd->pins[53] << 22) & 0x10000000) | 625 ((bd->pins[53] << 22) & 0x10000000) |
611 ((bd->pins[53] << 7) & 0x00001C00); 626 ((bd->pins[53] << 7) & 0x00001C00);
612 MINFO->values.reg.opt3 = get_unaligned_le32(bd->pins + 67); 627 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
613 MINFO->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000; 628 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
614 MINFO->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000; 629 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
615 return 0; 630 return 0;
616} 631}
617 632
618static void default_pins4(WPMINFO2) { 633static void default_pins4(struct matrox_fb_info *minfo)
634{
619 /* G400 */ 635 /* G400 */
620 MINFO->limits.pixel.vcomax = 636 minfo->limits.pixel.vcomax =
621 MINFO->limits.system.vcomax = 252000; 637 minfo->limits.system.vcomax = 252000;
622 MINFO->values.reg.mctlwtst = 0x04A450A1; 638 minfo->values.reg.mctlwtst = 0x04A450A1;
623 MINFO->values.reg.memrdbk = 0x000000E7; 639 minfo->values.reg.memrdbk = 0x000000E7;
624 MINFO->values.reg.opt = 0x10000400; 640 minfo->values.reg.opt = 0x10000400;
625 MINFO->values.reg.opt3 = 0x0190A419; 641 minfo->values.reg.opt3 = 0x0190A419;
626 MINFO->values.pll.system = 200000; 642 minfo->values.pll.system = 200000;
627 MINFO->features.pll.ref_freq = 27000; 643 minfo->features.pll.ref_freq = 27000;
628} 644}
629 645
630static int parse_pins5(WPMINFO const struct matrox_bios* bd) { 646static int parse_pins5(struct matrox_fb_info *minfo,
647 const struct matrox_bios *bd)
648{
631 unsigned int mult; 649 unsigned int mult;
632 650
633 mult = bd->pins[4]?8000:6000; 651 mult = bd->pins[4]?8000:6000;
634 652
635 MINFO->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult; 653 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
636 MINFO->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 36] * mult; 654 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
637 MINFO->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? MINFO->limits.system.vcomax : bd->pins[ 37] * mult; 655 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
638 MINFO->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult; 656 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
639 MINFO->limits.system.vcomin = (bd->pins[121] == 0xFF) ? MINFO->limits.pixel.vcomin : bd->pins[121] * mult; 657 minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
640 MINFO->limits.video.vcomin = (bd->pins[122] == 0xFF) ? MINFO->limits.system.vcomin : bd->pins[122] * mult; 658 minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
641 MINFO->values.pll.system = 659 minfo->values.pll.system =
642 MINFO->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000; 660 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
643 MINFO->values.reg.opt = get_unaligned_le32(bd->pins + 48); 661 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
644 MINFO->values.reg.opt2 = get_unaligned_le32(bd->pins + 52); 662 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
645 MINFO->values.reg.opt3 = get_unaligned_le32(bd->pins + 94); 663 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
646 MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98); 664 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
647 MINFO->values.reg.memmisc = get_unaligned_le32(bd->pins + 102); 665 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
648 MINFO->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106); 666 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
649 MINFO->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000; 667 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
650 MINFO->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20; 668 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
651 MINFO->values.memory.dll = (bd->pins[115] & 0x02) != 0; 669 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
652 MINFO->values.memory.emrswen = (bd->pins[115] & 0x01) != 0; 670 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
653 MINFO->values.reg.maccess = MINFO->values.memory.emrswen ? 0x00004000 : 0x00000000; 671 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
654 if (bd->pins[115] & 4) { 672 if (bd->pins[115] & 4) {
655 MINFO->values.reg.mctlwtst_core = MINFO->values.reg.mctlwtst; 673 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
656 } else { 674 } else {
657 u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 }; 675 u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 };
658 MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) | 676 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
659 wtst_xlat[MINFO->values.reg.mctlwtst & 7]; 677 wtst_xlat[minfo->values.reg.mctlwtst & 7];
660 } 678 }
661 MINFO->max_pixel_clock_panellink = bd->pins[47] * 4000; 679 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
662 return 0; 680 return 0;
663} 681}
664 682
665static void default_pins5(WPMINFO2) { 683static void default_pins5(struct matrox_fb_info *minfo)
684{
666 /* Mine 16MB G450 with SDRAM DDR */ 685 /* Mine 16MB G450 with SDRAM DDR */
667 MINFO->limits.pixel.vcomax = 686 minfo->limits.pixel.vcomax =
668 MINFO->limits.system.vcomax = 687 minfo->limits.system.vcomax =
669 MINFO->limits.video.vcomax = 600000; 688 minfo->limits.video.vcomax = 600000;
670 MINFO->limits.pixel.vcomin = 689 minfo->limits.pixel.vcomin =
671 MINFO->limits.system.vcomin = 690 minfo->limits.system.vcomin =
672 MINFO->limits.video.vcomin = 256000; 691 minfo->limits.video.vcomin = 256000;
673 MINFO->values.pll.system = 692 minfo->values.pll.system =
674 MINFO->values.pll.video = 284000; 693 minfo->values.pll.video = 284000;
675 MINFO->values.reg.opt = 0x404A1160; 694 minfo->values.reg.opt = 0x404A1160;
676 MINFO->values.reg.opt2 = 0x0000AC00; 695 minfo->values.reg.opt2 = 0x0000AC00;
677 MINFO->values.reg.opt3 = 0x0090A409; 696 minfo->values.reg.opt3 = 0x0090A409;
678 MINFO->values.reg.mctlwtst_core = 697 minfo->values.reg.mctlwtst_core =
679 MINFO->values.reg.mctlwtst = 0x0C81462B; 698 minfo->values.reg.mctlwtst = 0x0C81462B;
680 MINFO->values.reg.memmisc = 0x80000004; 699 minfo->values.reg.memmisc = 0x80000004;
681 MINFO->values.reg.memrdbk = 0x01001103; 700 minfo->values.reg.memrdbk = 0x01001103;
682 MINFO->features.pll.ref_freq = 27000; 701 minfo->features.pll.ref_freq = 27000;
683 MINFO->values.memory.ddr = 1; 702 minfo->values.memory.ddr = 1;
684 MINFO->values.memory.dll = 1; 703 minfo->values.memory.dll = 1;
685 MINFO->values.memory.emrswen = 1; 704 minfo->values.memory.emrswen = 1;
686 MINFO->values.reg.maccess = 0x00004000; 705 minfo->values.reg.maccess = 0x00004000;
687} 706}
688 707
689static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) { 708static int matroxfb_set_limits(struct matrox_fb_info *minfo,
709 const struct matrox_bios *bd)
710{
690 unsigned int pins_version; 711 unsigned int pins_version;
691 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 }; 712 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
692 713
693 switch (ACCESS_FBINFO(chip)) { 714 switch (minfo->chip) {
694 case MGA_2064: default_pins1(PMINFO2); break; 715 case MGA_2064: default_pins1(minfo); break;
695 case MGA_2164: 716 case MGA_2164:
696 case MGA_1064: 717 case MGA_1064:
697 case MGA_1164: default_pins2(PMINFO2); break; 718 case MGA_1164: default_pins2(minfo); break;
698 case MGA_G100: 719 case MGA_G100:
699 case MGA_G200: default_pins3(PMINFO2); break; 720 case MGA_G200: default_pins3(minfo); break;
700 case MGA_G400: default_pins4(PMINFO2); break; 721 case MGA_G400: default_pins4(minfo); break;
701 case MGA_G450: 722 case MGA_G450:
702 case MGA_G550: default_pins5(PMINFO2); break; 723 case MGA_G550: default_pins5(minfo); break;
703 } 724 }
704 if (!bd->bios_valid) { 725 if (!bd->bios_valid) {
705 printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n"); 726 printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
@@ -724,38 +745,39 @@ static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) {
724 } 745 }
725 switch (pins_version) { 746 switch (pins_version) {
726 case 1: 747 case 1:
727 return parse_pins1(PMINFO bd); 748 return parse_pins1(minfo, bd);
728 case 2: 749 case 2:
729 return parse_pins2(PMINFO bd); 750 return parse_pins2(minfo, bd);
730 case 3: 751 case 3:
731 return parse_pins3(PMINFO bd); 752 return parse_pins3(minfo, bd);
732 case 4: 753 case 4:
733 return parse_pins4(PMINFO bd); 754 return parse_pins4(minfo, bd);
734 case 5: 755 case 5:
735 return parse_pins5(PMINFO bd); 756 return parse_pins5(minfo, bd);
736 default: 757 default:
737 printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version); 758 printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
738 return -1; 759 return -1;
739 } 760 }
740} 761}
741 762
742void matroxfb_read_pins(WPMINFO2) { 763void matroxfb_read_pins(struct matrox_fb_info *minfo)
764{
743 u32 opt; 765 u32 opt;
744 u32 biosbase; 766 u32 biosbase;
745 u32 fbbase; 767 u32 fbbase;
746 struct pci_dev* pdev = ACCESS_FBINFO(pcidev); 768 struct pci_dev *pdev = minfo->pcidev;
747 769
748 memset(&ACCESS_FBINFO(bios), 0, sizeof(ACCESS_FBINFO(bios))); 770 memset(&minfo->bios, 0, sizeof(minfo->bios));
749 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt); 771 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
750 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM); 772 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
751 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase); 773 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
752 pci_read_config_dword(pdev, ACCESS_FBINFO(devflags.fbResource), &fbbase); 774 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
753 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE); 775 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
754 parse_bios(vaddr_va(ACCESS_FBINFO(video).vbase), &ACCESS_FBINFO(bios)); 776 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
755 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase); 777 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
756 pci_write_config_dword(pdev, PCI_OPTION_REG, opt); 778 pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
757#ifdef CONFIG_X86 779#ifdef CONFIG_X86
758 if (!ACCESS_FBINFO(bios).bios_valid) { 780 if (!minfo->bios.bios_valid) {
759 unsigned char __iomem* b; 781 unsigned char __iomem* b;
760 782
761 b = ioremap(0x000C0000, 65536); 783 b = ioremap(0x000C0000, 65536);
@@ -769,25 +791,21 @@ void matroxfb_read_pins(WPMINFO2) {
769 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n", 791 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
770 ven, dev, pdev->vendor, pdev->device); 792 ven, dev, pdev->vendor, pdev->device);
771 } else { 793 } else {
772 parse_bios(b, &ACCESS_FBINFO(bios)); 794 parse_bios(b, &minfo->bios);
773 } 795 }
774 iounmap(b); 796 iounmap(b);
775 } 797 }
776 } 798 }
777#endif 799#endif
778 matroxfb_set_limits(PMINFO &ACCESS_FBINFO(bios)); 800 matroxfb_set_limits(minfo, &minfo->bios);
779 printk(KERN_INFO "PInS memtype = %u\n", 801 printk(KERN_INFO "PInS memtype = %u\n",
780 (ACCESS_FBINFO(values).reg.opt & 0x1C00) >> 10); 802 (minfo->values.reg.opt & 0x1C00) >> 10);
781} 803}
782 804
783EXPORT_SYMBOL(matroxfb_DAC_in); 805EXPORT_SYMBOL(matroxfb_DAC_in);
784EXPORT_SYMBOL(matroxfb_DAC_out); 806EXPORT_SYMBOL(matroxfb_DAC_out);
785EXPORT_SYMBOL(matroxfb_var2my); 807EXPORT_SYMBOL(matroxfb_var2my);
786EXPORT_SYMBOL(matroxfb_PLL_calcclock); 808EXPORT_SYMBOL(matroxfb_PLL_calcclock);
787#ifndef CONFIG_FB_MATROX_MULTIHEAD
788struct matrox_fb_info matroxfb_global_mxinfo;
789EXPORT_SYMBOL(matroxfb_global_mxinfo);
790#endif
791EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */ 809EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
792EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */ 810EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
793EXPORT_SYMBOL(matroxfb_read_pins); 811EXPORT_SYMBOL(matroxfb_read_pins);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 19:55:15 -0500