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path: root/drivers/video/matrox/matroxfb_Ti3026.c
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Diffstat (limited to 'drivers/video/matrox/matroxfb_Ti3026.c')
-rw-r--r--drivers/video/matrox/matroxfb_Ti3026.c170
1 files changed, 89 insertions, 81 deletions
diff --git a/drivers/video/matrox/matroxfb_Ti3026.c b/drivers/video/matrox/matroxfb_Ti3026.c
index bc9c27499b39..835aaaae6b96 100644
--- a/drivers/video/matrox/matroxfb_Ti3026.c
+++ b/drivers/video/matrox/matroxfb_Ti3026.c
@@ -279,27 +279,31 @@ static const unsigned char MGADACbpp32[] =
279 TVP3026_XCOLKEYCTRL_ZOOM1, 279 TVP3026_XCOLKEYCTRL_ZOOM1,
280 0x00, 0x00, TVP3026_XCURCTRL_DIS }; 280 0x00, 0x00, TVP3026_XCURCTRL_DIS };
281 281
282static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* in, int* feed, int* post) { 282static int Ti3026_calcclock(const struct matrox_fb_info *minfo,
283 unsigned int freq, unsigned int fmax, int *in,
284 int *feed, int *post)
285{
283 unsigned int fvco; 286 unsigned int fvco;
284 unsigned int lin, lfeed, lpost; 287 unsigned int lin, lfeed, lpost;
285 288
286 DBG(__func__) 289 DBG(__func__)
287 290
288 fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost); 291 fvco = PLL_calcclock(minfo, freq, fmax, &lin, &lfeed, &lpost);
289 fvco >>= (*post = lpost); 292 fvco >>= (*post = lpost);
290 *in = 64 - lin; 293 *in = 64 - lin;
291 *feed = 64 - lfeed; 294 *feed = 64 - lfeed;
292 return fvco; 295 return fvco;
293} 296}
294 297
295static int Ti3026_setpclk(WPMINFO int clk) { 298static int Ti3026_setpclk(struct matrox_fb_info *minfo, int clk)
299{
296 unsigned int f_pll; 300 unsigned int f_pll;
297 unsigned int pixfeed, pixin, pixpost; 301 unsigned int pixfeed, pixin, pixpost;
298 struct matrox_hw_state *hw = &minfo->hw; 302 struct matrox_hw_state *hw = &minfo->hw;
299 303
300 DBG(__func__) 304 DBG(__func__)
301 305
302 f_pll = Ti3026_calcclock(PMINFO clk, minfo->max_pixel_clock, &pixin, &pixfeed, &pixpost); 306 f_pll = Ti3026_calcclock(minfo, clk, minfo->max_pixel_clock, &pixin, &pixfeed, &pixpost);
303 307
304 hw->DACclk[0] = pixin | 0xC0; 308 hw->DACclk[0] = pixin | 0xC0;
305 hw->DACclk[1] = pixfeed; 309 hw->DACclk[1] = pixfeed;
@@ -361,7 +365,8 @@ static int Ti3026_setpclk(WPMINFO int clk) {
361 return 0; 365 return 0;
362} 366}
363 367
364static int Ti3026_init(WPMINFO struct my_timming* m) { 368static int Ti3026_init(struct matrox_fb_info *minfo, struct my_timming *m)
369{
365 u_int8_t muxctrl = isInterleave(minfo) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT; 370 u_int8_t muxctrl = isInterleave(minfo) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
366 struct matrox_hw_state *hw = &minfo->hw; 371 struct matrox_hw_state *hw = &minfo->hw;
367 372
@@ -400,7 +405,7 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
400 default: 405 default:
401 return 1; /* TODO: failed */ 406 return 1; /* TODO: failed */
402 } 407 }
403 if (matroxfb_vgaHWinit(PMINFO m)) return 1; 408 if (matroxfb_vgaHWinit(minfo, m)) return 1;
404 409
405 /* set SYNC */ 410 /* set SYNC */
406 hw->MiscOutReg = 0xCB; 411 hw->MiscOutReg = 0xCB;
@@ -429,11 +434,12 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
429 if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000; 434 if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000;
430 435
431 /* set DAC */ 436 /* set DAC */
432 Ti3026_setpclk(PMINFO m->pixclock); 437 Ti3026_setpclk(minfo, m->pixclock);
433 return 0; 438 return 0;
434} 439}
435 440
436static void ti3026_setMCLK(WPMINFO int fout){ 441static void ti3026_setMCLK(struct matrox_fb_info *minfo, int fout)
442{
437 unsigned int f_pll; 443 unsigned int f_pll;
438 unsigned int pclk_m, pclk_n, pclk_p; 444 unsigned int pclk_m, pclk_n, pclk_p;
439 unsigned int mclk_m, mclk_n, mclk_p; 445 unsigned int mclk_m, mclk_n, mclk_p;
@@ -442,29 +448,29 @@ static void ti3026_setMCLK(WPMINFO int fout){
442 448
443 DBG(__func__) 449 DBG(__func__)
444 450
445 f_pll = Ti3026_calcclock(PMINFO fout, minfo->max_pixel_clock, &mclk_n, &mclk_m, &mclk_p); 451 f_pll = Ti3026_calcclock(minfo, fout, minfo->max_pixel_clock, &mclk_n, &mclk_m, &mclk_p);
446 452
447 /* save pclk */ 453 /* save pclk */
448 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC); 454 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
449 pclk_n = inTi3026(PMINFO TVP3026_XPIXPLLDATA); 455 pclk_n = inTi3026(minfo, TVP3026_XPIXPLLDATA);
450 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFD); 456 outTi3026(minfo, TVP3026_XPLLADDR, 0xFD);
451 pclk_m = inTi3026(PMINFO TVP3026_XPIXPLLDATA); 457 pclk_m = inTi3026(minfo, TVP3026_XPIXPLLDATA);
452 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE); 458 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
453 pclk_p = inTi3026(PMINFO TVP3026_XPIXPLLDATA); 459 pclk_p = inTi3026(minfo, TVP3026_XPIXPLLDATA);
454 460
455 /* stop pclk */ 461 /* stop pclk */
456 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE); 462 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
457 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00); 463 outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
458 464
459 /* set pclk to new mclk */ 465 /* set pclk to new mclk */
460 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC); 466 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
461 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_n | 0xC0); 467 outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
462 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_m); 468 outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_m);
463 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_p | 0xB0); 469 outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
464 470
465 /* wait for PLL to lock */ 471 /* wait for PLL to lock */
466 for (tmout = 500000; tmout; tmout--) { 472 for (tmout = 500000; tmout; tmout--) {
467 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40) 473 if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
468 break; 474 break;
469 udelay(10); 475 udelay(10);
470 }; 476 };
@@ -472,23 +478,23 @@ static void ti3026_setMCLK(WPMINFO int fout){
472 printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n"); 478 printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
473 479
474 /* output pclk on mclk pin */ 480 /* output pclk on mclk pin */
475 mclk_ctl = inTi3026(PMINFO TVP3026_XMEMPLLCTRL); 481 mclk_ctl = inTi3026(minfo, TVP3026_XMEMPLLCTRL);
476 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7); 482 outTi3026(minfo, TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
477 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4); 483 outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
478 484
479 /* stop MCLK */ 485 /* stop MCLK */
480 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFB); 486 outTi3026(minfo, TVP3026_XPLLADDR, 0xFB);
481 outTi3026(PMINFO TVP3026_XMEMPLLDATA, 0x00); 487 outTi3026(minfo, TVP3026_XMEMPLLDATA, 0x00);
482 488
483 /* set mclk to new freq */ 489 /* set mclk to new freq */
484 outTi3026(PMINFO TVP3026_XPLLADDR, 0xF3); 490 outTi3026(minfo, TVP3026_XPLLADDR, 0xF3);
485 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_n | 0xC0); 491 outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
486 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_m); 492 outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_m);
487 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_p | 0xB0); 493 outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
488 494
489 /* wait for PLL to lock */ 495 /* wait for PLL to lock */
490 for (tmout = 500000; tmout; tmout--) { 496 for (tmout = 500000; tmout; tmout--) {
491 if (inTi3026(PMINFO TVP3026_XMEMPLLDATA) & 0x40) 497 if (inTi3026(minfo, TVP3026_XMEMPLLDATA) & 0x40)
492 break; 498 break;
493 udelay(10); 499 udelay(10);
494 } 500 }
@@ -509,22 +515,22 @@ static void ti3026_setMCLK(WPMINFO int fout){
509 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); 515 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
510 516
511 /* output MCLK to MCLK pin */ 517 /* output MCLK to MCLK pin */
512 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL); 518 outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
513 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4); 519 outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
514 520
515 /* stop PCLK */ 521 /* stop PCLK */
516 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE); 522 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
517 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00); 523 outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
518 524
519 /* restore pclk */ 525 /* restore pclk */
520 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC); 526 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
521 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_n); 527 outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_n);
522 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_m); 528 outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_m);
523 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_p); 529 outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_p);
524 530
525 /* wait for PLL to lock */ 531 /* wait for PLL to lock */
526 for (tmout = 500000; tmout; tmout--) { 532 for (tmout = 500000; tmout; tmout--) {
527 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40) 533 if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
528 break; 534 break;
529 udelay(10); 535 udelay(10);
530 } 536 }
@@ -532,8 +538,8 @@ static void ti3026_setMCLK(WPMINFO int fout){
532 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n"); 538 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
533} 539}
534 540
535static void ti3026_ramdac_init(WPMINFO2) { 541static void ti3026_ramdac_init(struct matrox_fb_info *minfo)
536 542{
537 DBG(__func__) 543 DBG(__func__)
538 544
539 minfo->features.pll.vco_freq_min = 110000; 545 minfo->features.pll.vco_freq_min = 110000;
@@ -545,10 +551,11 @@ static void ti3026_ramdac_init(WPMINFO2) {
545 minfo->features.pll.post_shift_max = 3; 551 minfo->features.pll.post_shift_max = 3;
546 if (minfo->devflags.noinit) 552 if (minfo->devflags.noinit)
547 return; 553 return;
548 ti3026_setMCLK(PMINFO 60000); 554 ti3026_setMCLK(minfo, 60000);
549} 555}
550 556
551static void Ti3026_restore(WPMINFO2) { 557static void Ti3026_restore(struct matrox_fb_info *minfo)
558{
552 int i; 559 int i;
553 unsigned char progdac[6]; 560 unsigned char progdac[6];
554 struct matrox_hw_state *hw = &minfo->hw; 561 struct matrox_hw_state *hw = &minfo->hw;
@@ -569,7 +576,7 @@ static void Ti3026_restore(WPMINFO2) {
569 576
570 CRITEND 577 CRITEND
571 578
572 matroxfb_vgaHWrestore(PMINFO2); 579 matroxfb_vgaHWrestore(minfo);
573 580
574 CRITBEGIN 581 CRITBEGIN
575 582
@@ -578,18 +585,18 @@ static void Ti3026_restore(WPMINFO2) {
578 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); 585 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
579 586
580 for (i = 0; i < 21; i++) { 587 for (i = 0; i < 21; i++) {
581 outTi3026(PMINFO DACseq[i], hw->DACreg[i]); 588 outTi3026(minfo, DACseq[i], hw->DACreg[i]);
582 } 589 }
583 590
584 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00); 591 outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
585 progdac[0] = inTi3026(PMINFO TVP3026_XPIXPLLDATA); 592 progdac[0] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
586 progdac[3] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA); 593 progdac[3] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
587 outTi3026(PMINFO TVP3026_XPLLADDR, 0x15); 594 outTi3026(minfo, TVP3026_XPLLADDR, 0x15);
588 progdac[1] = inTi3026(PMINFO TVP3026_XPIXPLLDATA); 595 progdac[1] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
589 progdac[4] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA); 596 progdac[4] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
590 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A); 597 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
591 progdac[2] = inTi3026(PMINFO TVP3026_XPIXPLLDATA); 598 progdac[2] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
592 progdac[5] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA); 599 progdac[5] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
593 600
594 CRITEND 601 CRITEND
595 if (memcmp(hw->DACclk, progdac, 6)) { 602 if (memcmp(hw->DACclk, progdac, 6)) {
@@ -598,20 +605,20 @@ static void Ti3026_restore(WPMINFO2) {
598 /* Maybe even we should call schedule() ? */ 605 /* Maybe even we should call schedule() ? */
599 606
600 CRITBEGIN 607 CRITBEGIN
601 outTi3026(PMINFO TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]); 608 outTi3026(minfo, TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
602 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A); 609 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
603 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0); 610 outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0);
604 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0); 611 outTi3026(minfo, TVP3026_XPIXPLLDATA, 0);
605 612
606 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00); 613 outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
607 for (i = 0; i < 3; i++) 614 for (i = 0; i < 3; i++)
608 outTi3026(PMINFO TVP3026_XPIXPLLDATA, hw->DACclk[i]); 615 outTi3026(minfo, TVP3026_XPIXPLLDATA, hw->DACclk[i]);
609 /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */ 616 /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
610 if (hw->MiscOutReg & 0x08) { 617 if (hw->MiscOutReg & 0x08) {
611 int tmout; 618 int tmout;
612 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F); 619 outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
613 for (tmout = 500000; tmout; --tmout) { 620 for (tmout = 500000; tmout; --tmout) {
614 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40) 621 if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
615 break; 622 break;
616 udelay(10); 623 udelay(10);
617 } 624 }
@@ -624,18 +631,18 @@ static void Ti3026_restore(WPMINFO2) {
624 dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout); 631 dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
625 CRITBEGIN 632 CRITBEGIN
626 } 633 }
627 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]); 634 outTi3026(minfo, TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
628 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00); 635 outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
629 for (i = 3; i < 6; i++) 636 for (i = 3; i < 6; i++)
630 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, hw->DACclk[i]); 637 outTi3026(minfo, TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
631 CRITEND 638 CRITEND
632 if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) { 639 if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
633 int tmout; 640 int tmout;
634 641
635 CRITBEGIN 642 CRITBEGIN
636 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F); 643 outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
637 for (tmout = 500000; tmout; --tmout) { 644 for (tmout = 500000; tmout; --tmout) {
638 if (inTi3026(PMINFO TVP3026_XLOOPPLLDATA) & 0x40) 645 if (inTi3026(minfo, TVP3026_XLOOPPLLDATA) & 0x40)
639 break; 646 break;
640 udelay(10); 647 udelay(10);
641 } 648 }
@@ -660,18 +667,19 @@ static void Ti3026_restore(WPMINFO2) {
660#endif 667#endif
661} 668}
662 669
663static void Ti3026_reset(WPMINFO2) { 670static void Ti3026_reset(struct matrox_fb_info *minfo)
664 671{
665 DBG(__func__) 672 DBG(__func__)
666 673
667 ti3026_ramdac_init(PMINFO2); 674 ti3026_ramdac_init(minfo);
668} 675}
669 676
670static struct matrox_altout ti3026_output = { 677static struct matrox_altout ti3026_output = {
671 .name = "Primary output", 678 .name = "Primary output",
672}; 679};
673 680
674static int Ti3026_preinit(WPMINFO2) { 681static int Ti3026_preinit(struct matrox_fb_info *minfo)
682{
675 static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960, 683 static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
676 1024, 1152, 1280, 1600, 1664, 1920, 684 1024, 1152, 1280, 1600, 1664, 1920,
677 2048, 0}; 685 2048, 0};
@@ -706,19 +714,19 @@ static int Ti3026_preinit(WPMINFO2) {
706 hw->MXoptionReg |= 0x20000000; 714 hw->MXoptionReg |= 0x20000000;
707 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); 715 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
708 716
709 minfo->accel.ramdac_rev = inTi3026(PMINFO TVP3026_XSILICONREV); 717 minfo->accel.ramdac_rev = inTi3026(minfo, TVP3026_XSILICONREV);
710 718
711 outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED); 719 outTi3026(minfo, TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
712 outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR); 720 outTi3026(minfo, TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
713 outTi3026(PMINFO TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA); 721 outTi3026(minfo, TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
714 722
715 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A); 723 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
716 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0x00); 724 outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0x00);
717 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00); 725 outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
718 726
719 mga_outb(M_MISC_REG, 0x67); 727 mga_outb(M_MISC_REG, 0x67);
720 728
721 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL); 729 outTi3026(minfo, TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
722 730
723 mga_outl(M_RESET, 1); 731 mga_outl(M_RESET, 1);
724 udelay(250); 732 udelay(250);