aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video/intelfb/intelfbhw.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/video/intelfb/intelfbhw.c')
-rw-r--r--drivers/video/intelfb/intelfbhw.c104
1 files changed, 32 insertions, 72 deletions
diff --git a/drivers/video/intelfb/intelfbhw.c b/drivers/video/intelfb/intelfbhw.c
index 16c9c192b4be..426b7430b125 100644
--- a/drivers/video/intelfb/intelfbhw.c
+++ b/drivers/video/intelfb/intelfbhw.c
@@ -615,6 +615,33 @@ static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvd
615 return vco / p; 615 return vco / p;
616} 616}
617 617
618static void
619intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
620{
621 int p1, p2;
622
623 if (IS_I9XX(dinfo)) {
624 if (dpll & DPLL_P1_FORCE_DIV2)
625 p1 = 1;
626 else
627 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
628
629 p1 = ffs(p1);
630
631 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
632 } else {
633 if (dpll & DPLL_P1_FORCE_DIV2)
634 p1 = 0;
635 else
636 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
637 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
638 }
639
640 *o_p1 = p1;
641 *o_p2 = p2;
642}
643
644
618void 645void
619intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) 646intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
620{ 647{
@@ -633,12 +660,8 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
633 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 660 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
634 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 661 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
635 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 662 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
636 if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
637 p1 = 0;
638 else
639 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
640 663
641 p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK; 664 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
642 665
643 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 666 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
644 m1, m2, n, p1, p2); 667 m1, m2, n, p1, p2);
@@ -648,11 +671,8 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
648 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 671 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
649 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 672 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
650 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 673 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
651 if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2) 674
652 p1 = 0; 675 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
653 else
654 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
655 p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
656 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 676 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
657 m1, m2, n, p1, p2); 677 m1, m2, n, p1, p2);
658 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0)); 678 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
@@ -668,38 +688,7 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
668 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 688 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
669 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 689 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
670 690
671 if (IS_I9XX(dinfo)) { 691 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
672 int tmpp1;
673
674 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
675 p1 = 0;
676 else
677 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
678
679 tmpp1 = p1;
680
681 switch (tmpp1)
682 {
683 case 0x1: p1 = 1; break;
684 case 0x2: p1 = 2; break;
685 case 0x4: p1 = 3; break;
686 case 0x8: p1 = 4; break;
687 case 0x10: p1 = 5; break;
688 case 0x20: p1 = 6; break;
689 case 0x40: p1 = 7; break;
690 case 0x80: p1 = 8; break;
691 default: break;
692 }
693
694 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
695
696 } else {
697 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
698 p1 = 0;
699 else
700 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
701 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
702 }
703 692
704 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 693 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
705 m1, m2, n, p1, p2); 694 m1, m2, n, p1, p2);
@@ -709,37 +698,8 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
709 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 698 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
710 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 699 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
711 700
712 if (IS_I9XX(dinfo)) { 701 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
713 int tmpp1;
714
715 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
716 p1 = 0;
717 else
718 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
719
720 tmpp1 = p1;
721
722 switch (tmpp1) {
723 case 0x1: p1 = 1; break;
724 case 0x2: p1 = 2; break;
725 case 0x4: p1 = 3; break;
726 case 0x8: p1 = 4; break;
727 case 0x10: p1 = 5; break;
728 case 0x20: p1 = 6; break;
729 case 0x40: p1 = 7; break;
730 case 0x80: p1 = 8; break;
731 default: break;
732 }
733
734 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
735 702
736 } else {
737 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
738 p1 = 0;
739 else
740 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
741 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
742 }
743 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 703 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
744 m1, m2, n, p1, p2); 704 m1, m2, n, p1, p2);
745 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0)); 705 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));