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path: root/drivers/video/geode
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-rw-r--r--drivers/video/geode/lxfb.h52
-rw-r--r--drivers/video/geode/lxfb_ops.c37
2 files changed, 46 insertions, 43 deletions
diff --git a/drivers/video/geode/lxfb.h b/drivers/video/geode/lxfb.h
index 0e3cb9191009..b3fbc56ccbd7 100644
--- a/drivers/video/geode/lxfb.h
+++ b/drivers/video/geode/lxfb.h
@@ -27,31 +27,6 @@ int lx_blank_display(struct fb_info *, int);
27void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int, 27void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
28 unsigned int, unsigned int); 28 unsigned int, unsigned int);
29 29
30/* MSRS */
31
32#define GLCP_DOTPLL_RESET (1 << 0)
33#define GLCP_DOTPLL_BYPASS (1 << 15)
34#define GLCP_DOTPLL_HALFPIX (1 << 24)
35#define GLCP_DOTPLL_LOCK (1 << 25)
36
37#define DF_CONFIG_OUTPUT_MASK 0x38
38#define DF_OUTPUT_PANEL 0x08
39#define DF_OUTPUT_CRT 0x00
40#define DF_SIMULTANEOUS_CRT_AND_FP (1 << 15)
41
42#define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF
43#define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F
44
45#define DC_SPARE_DISABLE_CFIFO_HGO 0x00000800
46#define DC_SPARE_VFIFO_ARB_SELECT 0x00000400
47#define DC_SPARE_WM_LPEN_OVRD 0x00000200
48#define DC_SPARE_LOAD_WM_LPEN_MASK 0x00000100
49#define DC_SPARE_DISABLE_INIT_VID_PRI 0x00000080
50#define DC_SPARE_DISABLE_VFIFO_WM 0x00000040
51#define DC_SPARE_DISABLE_CWD_CHECK 0x00000020
52#define DC_SPARE_PIX8_PAN_FIX 0x00000010
53#define DC_SPARE_FIRST_REQ_MASK 0x00000002
54
55 30
56/* Graphics Processor registers (table 6-29 from the data book) */ 31/* Graphics Processor registers (table 6-29 from the data book) */
57enum gp_registers { 32enum gp_registers {
@@ -390,4 +365,31 @@ static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
390 writel(val, par->vp_regs + 8*reg + VP_FP_START); 365 writel(val, par->vp_regs + 8*reg + VP_FP_START);
391} 366}
392 367
368
369/* MSRs are defined in asm/geode.h; their bitfields are here */
370
371#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
372#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
373#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
374#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
375
376/* note: this is actually the VP's GLD_MSR_CONFIG */
377#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
378#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
379#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
380#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP *and* CRT */
381
382#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
383#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
384
385#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
386#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
387#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
388#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
389#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
390#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
391#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
392#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
393#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
394
393#endif 395#endif
diff --git a/drivers/video/geode/lxfb_ops.c b/drivers/video/geode/lxfb_ops.c
index 7be6f578e87e..a68def88c92b 100644
--- a/drivers/video/geode/lxfb_ops.c
+++ b/drivers/video/geode/lxfb_ops.c
@@ -154,12 +154,12 @@ static void lx_set_dotpll(u32 pllval)
154 154
155 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 155 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
156 156
157 if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval)) 157 if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
158 return; 158 return;
159 159
160 dotpll_hi = pllval; 160 dotpll_hi = pllval;
161 dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX); 161 dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
162 dotpll_lo |= GLCP_DOTPLL_RESET; 162 dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
163 163
164 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 164 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
165 165
@@ -171,13 +171,13 @@ static void lx_set_dotpll(u32 pllval)
171 171
172 for (i = 0; i < 1000; i++) { 172 for (i = 0; i < 1000; i++) {
173 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 173 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
174 if (dotpll_lo & GLCP_DOTPLL_LOCK) 174 if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
175 break; 175 break;
176 } 176 }
177 177
178 /* Clear the reset bit */ 178 /* Clear the reset bit */
179 179
180 dotpll_lo &= ~GLCP_DOTPLL_RESET; 180 dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
181 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 181 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
182} 182}
183 183
@@ -299,8 +299,8 @@ static void lx_graphics_enable(struct fb_info *info)
299 write_fp(par, FP_PT2, FP_PT2_SCRC); 299 write_fp(par, FP_PT2, FP_PT2_SCRC);
300 write_fp(par, FP_DFC, FP_DFC_BC); 300 write_fp(par, FP_DFC, FP_DFC_BC);
301 301
302 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW; 302 msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
303 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH; 303 msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
304 304
305 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi); 305 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
306 } 306 }
@@ -366,18 +366,17 @@ void lx_set_mode(struct fb_info *info)
366 /* Set output mode */ 366 /* Set output mode */
367 367
368 rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); 368 rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
369 msrval &= ~DF_CONFIG_OUTPUT_MASK; 369 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
370 370
371 if (par->output & OUTPUT_PANEL) { 371 if (par->output & OUTPUT_PANEL) {
372 msrval |= DF_OUTPUT_PANEL; 372 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP;
373 373
374 if (par->output & OUTPUT_CRT) 374 if (par->output & OUTPUT_CRT)
375 msrval |= DF_SIMULTANEOUS_CRT_AND_FP; 375 msrval |= MSR_LX_GLD_MSR_CONFIG_FPC;
376 else 376 else
377 msrval &= ~DF_SIMULTANEOUS_CRT_AND_FP; 377 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC;
378 } else { 378 } else
379 msrval |= DF_OUTPUT_CRT; 379 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT;
380 }
381 380
382 wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); 381 wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
383 382
@@ -429,10 +428,12 @@ void lx_set_mode(struct fb_info *info)
429 428
430 rdmsrl(MSR_LX_SPARE_MSR, msrval); 429 rdmsrl(MSR_LX_SPARE_MSR, msrval);
431 430
432 msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT | 431 msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
433 DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD | 432 | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
434 DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM); 433 | MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M
435 msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI; 434 | MSR_LX_SPARE_MSR_WM_LPEN_OVRD);
435 msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM |
436 MSR_LX_SPARE_MSR_DIS_INIT_V_PRI;
436 wrmsrl(MSR_LX_SPARE_MSR, msrval); 437 wrmsrl(MSR_LX_SPARE_MSR, msrval);
437 438
438 gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */ 439 gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */