diff options
Diffstat (limited to 'drivers/video/geode/lxfb.h')
-rw-r--r-- | drivers/video/geode/lxfb.h | 199 |
1 files changed, 199 insertions, 0 deletions
diff --git a/drivers/video/geode/lxfb.h b/drivers/video/geode/lxfb.h new file mode 100644 index 000000000000..6c227f9592a5 --- /dev/null +++ b/drivers/video/geode/lxfb.h | |||
@@ -0,0 +1,199 @@ | |||
1 | #ifndef _LXFB_H_ | ||
2 | #define _LXFB_H_ | ||
3 | |||
4 | #include <linux/fb.h> | ||
5 | |||
6 | #define OUTPUT_CRT 0x01 | ||
7 | #define OUTPUT_PANEL 0x02 | ||
8 | |||
9 | struct lxfb_par { | ||
10 | int output; | ||
11 | int panel_width; | ||
12 | int panel_height; | ||
13 | |||
14 | void __iomem *gp_regs; | ||
15 | void __iomem *dc_regs; | ||
16 | void __iomem *df_regs; | ||
17 | }; | ||
18 | |||
19 | static inline unsigned int lx_get_pitch(unsigned int xres, int bpp) | ||
20 | { | ||
21 | return (((xres * (bpp >> 3)) + 7) & ~7); | ||
22 | } | ||
23 | |||
24 | void lx_set_mode(struct fb_info *); | ||
25 | void lx_get_gamma(struct fb_info *, unsigned int *, int); | ||
26 | void lx_set_gamma(struct fb_info *, unsigned int *, int); | ||
27 | unsigned int lx_framebuffer_size(void); | ||
28 | int lx_blank_display(struct fb_info *, int); | ||
29 | void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int, | ||
30 | unsigned int, unsigned int); | ||
31 | |||
32 | /* MSRS */ | ||
33 | |||
34 | #define MSR_LX_GLD_CONFIG 0x48002001 | ||
35 | #define MSR_LX_GLCP_DOTPLL 0x4c000015 | ||
36 | #define MSR_LX_DF_PADSEL 0x48000011 | ||
37 | #define MSR_LX_DC_SPARE 0x80000011 | ||
38 | #define MSR_LX_DF_GLCONFIG 0x48002001 | ||
39 | |||
40 | #define MSR_LX_GLIU0_P2D_RO0 0x10000029 | ||
41 | |||
42 | #define GLCP_DOTPLL_RESET (1 << 0) | ||
43 | #define GLCP_DOTPLL_BYPASS (1 << 15) | ||
44 | #define GLCP_DOTPLL_HALFPIX (1 << 24) | ||
45 | #define GLCP_DOTPLL_LOCK (1 << 25) | ||
46 | |||
47 | #define DF_CONFIG_OUTPUT_MASK 0x38 | ||
48 | #define DF_OUTPUT_PANEL 0x08 | ||
49 | #define DF_OUTPUT_CRT 0x00 | ||
50 | #define DF_SIMULTANEOUS_CRT_AND_FP (1 << 15) | ||
51 | |||
52 | #define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF | ||
53 | #define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F | ||
54 | |||
55 | #define DC_SPARE_DISABLE_CFIFO_HGO 0x00000800 | ||
56 | #define DC_SPARE_VFIFO_ARB_SELECT 0x00000400 | ||
57 | #define DC_SPARE_WM_LPEN_OVRD 0x00000200 | ||
58 | #define DC_SPARE_LOAD_WM_LPEN_MASK 0x00000100 | ||
59 | #define DC_SPARE_DISABLE_INIT_VID_PRI 0x00000080 | ||
60 | #define DC_SPARE_DISABLE_VFIFO_WM 0x00000040 | ||
61 | #define DC_SPARE_DISABLE_CWD_CHECK 0x00000020 | ||
62 | #define DC_SPARE_PIX8_PAN_FIX 0x00000010 | ||
63 | #define DC_SPARE_FIRST_REQ_MASK 0x00000002 | ||
64 | |||
65 | /* Registers */ | ||
66 | |||
67 | #define DC_UNLOCK 0x00 | ||
68 | #define DC_UNLOCK_CODE 0x4758 | ||
69 | |||
70 | #define DC_GENERAL_CFG 0x04 | ||
71 | #define DC_GCFG_DFLE (1 << 0) | ||
72 | #define DC_GCFG_VIDE (1 << 3) | ||
73 | #define DC_GCFG_VGAE (1 << 7) | ||
74 | #define DC_GCFG_CMPE (1 << 5) | ||
75 | #define DC_GCFG_DECE (1 << 6) | ||
76 | #define DC_GCFG_FDTY (1 << 17) | ||
77 | |||
78 | #define DC_DISPLAY_CFG 0x08 | ||
79 | #define DC_DCFG_TGEN (1 << 0) | ||
80 | #define DC_DCFG_GDEN (1 << 3) | ||
81 | #define DC_DCFG_VDEN (1 << 4) | ||
82 | #define DC_DCFG_TRUP (1 << 6) | ||
83 | #define DC_DCFG_DCEN (1 << 24) | ||
84 | #define DC_DCFG_PALB (1 << 25) | ||
85 | #define DC_DCFG_VISL (1 << 27) | ||
86 | |||
87 | #define DC_DCFG_16BPP 0x0 | ||
88 | |||
89 | #define DC_DCFG_DISP_MODE_MASK 0x00000300 | ||
90 | #define DC_DCFG_DISP_MODE_8BPP 0x00000000 | ||
91 | #define DC_DCFG_DISP_MODE_16BPP 0x00000100 | ||
92 | #define DC_DCFG_DISP_MODE_24BPP 0x00000200 | ||
93 | #define DC_DCFG_DISP_MODE_32BPP 0x00000300 | ||
94 | |||
95 | |||
96 | #define DC_ARB_CFG 0x0C | ||
97 | |||
98 | #define DC_FB_START 0x10 | ||
99 | #define DC_CB_START 0x14 | ||
100 | #define DC_CURSOR_START 0x18 | ||
101 | |||
102 | #define DC_DV_TOP 0x2C | ||
103 | #define DC_DV_TOP_ENABLE (1 << 0) | ||
104 | |||
105 | #define DC_LINE_SIZE 0x30 | ||
106 | #define DC_GRAPHICS_PITCH 0x34 | ||
107 | #define DC_H_ACTIVE_TIMING 0x40 | ||
108 | #define DC_H_BLANK_TIMING 0x44 | ||
109 | #define DC_H_SYNC_TIMING 0x48 | ||
110 | #define DC_V_ACTIVE_TIMING 0x50 | ||
111 | #define DC_V_BLANK_TIMING 0x54 | ||
112 | #define DC_V_SYNC_TIMING 0x58 | ||
113 | #define DC_FB_ACTIVE 0x5C | ||
114 | |||
115 | #define DC_PAL_ADDRESS 0x70 | ||
116 | #define DC_PAL_DATA 0x74 | ||
117 | |||
118 | #define DC_PHY_MEM_OFFSET 0x84 | ||
119 | |||
120 | #define DC_DV_CTL 0x88 | ||
121 | #define DC_DV_LINE_SIZE_MASK 0x00000C00 | ||
122 | #define DC_DV_LINE_SIZE_1024 0x00000000 | ||
123 | #define DC_DV_LINE_SIZE_2048 0x00000400 | ||
124 | #define DC_DV_LINE_SIZE_4096 0x00000800 | ||
125 | #define DC_DV_LINE_SIZE_8192 0x00000C00 | ||
126 | |||
127 | |||
128 | #define DC_GFX_SCALE 0x90 | ||
129 | #define DC_IRQ_FILT_CTL 0x94 | ||
130 | |||
131 | |||
132 | #define DC_IRQ 0xC8 | ||
133 | #define DC_IRQ_MASK (1 << 0) | ||
134 | #define DC_VSYNC_IRQ_MASK (1 << 1) | ||
135 | #define DC_IRQ_STATUS (1 << 20) | ||
136 | #define DC_VSYNC_IRQ_STATUS (1 << 21) | ||
137 | |||
138 | #define DC_GENLCK_CTRL 0xD4 | ||
139 | #define DC_GENLCK_ENABLE (1 << 18) | ||
140 | #define DC_GC_ALPHA_FLICK_ENABLE (1 << 25) | ||
141 | #define DC_GC_FLICKER_FILTER_ENABLE (1 << 24) | ||
142 | #define DC_GC_FLICKER_FILTER_MASK (0x0F << 28) | ||
143 | |||
144 | #define DC_COLOR_KEY 0xB8 | ||
145 | #define DC_CLR_KEY_ENABLE (1 << 24) | ||
146 | |||
147 | |||
148 | #define DC3_DV_LINE_SIZE_MASK 0x00000C00 | ||
149 | #define DC3_DV_LINE_SIZE_1024 0x00000000 | ||
150 | #define DC3_DV_LINE_SIZE_2048 0x00000400 | ||
151 | #define DC3_DV_LINE_SIZE_4096 0x00000800 | ||
152 | #define DC3_DV_LINE_SIZE_8192 0x00000C00 | ||
153 | |||
154 | #define DF_VIDEO_CFG 0x0 | ||
155 | #define DF_VCFG_VID_EN (1 << 0) | ||
156 | |||
157 | #define DF_DISPLAY_CFG 0x08 | ||
158 | |||
159 | #define DF_DCFG_CRT_EN (1 << 0) | ||
160 | #define DF_DCFG_HSYNC_EN (1 << 1) | ||
161 | #define DF_DCFG_VSYNC_EN (1 << 2) | ||
162 | #define DF_DCFG_DAC_BL_EN (1 << 3) | ||
163 | #define DF_DCFG_CRT_HSYNC_POL (1 << 8) | ||
164 | #define DF_DCFG_CRT_VSYNC_POL (1 << 9) | ||
165 | #define DF_DCFG_GV_PAL_BYP (1 << 21) | ||
166 | |||
167 | #define DF_DCFG_CRT_SYNC_SKW_INIT 0x10000 | ||
168 | #define DF_DCFG_CRT_SYNC_SKW_MASK 0x1c000 | ||
169 | |||
170 | #define DF_DCFG_PWR_SEQ_DLY_INIT 0x80000 | ||
171 | #define DF_DCFG_PWR_SEQ_DLY_MASK 0xe0000 | ||
172 | |||
173 | #define DF_MISC 0x50 | ||
174 | |||
175 | #define DF_MISC_GAM_BYPASS (1 << 0) | ||
176 | #define DF_MISC_DAC_PWRDN (1 << 10) | ||
177 | #define DF_MISC_A_PWRDN (1 << 11) | ||
178 | |||
179 | #define DF_PAR 0x38 | ||
180 | #define DF_PDR 0x40 | ||
181 | #define DF_ALPHA_CONTROL_1 0xD8 | ||
182 | #define DF_VIDEO_REQUEST 0x120 | ||
183 | |||
184 | #define DF_PANEL_TIM1 0x400 | ||
185 | #define DF_DEFAULT_TFT_PMTIM1 0x0 | ||
186 | |||
187 | #define DF_PANEL_TIM2 0x408 | ||
188 | #define DF_DEFAULT_TFT_PMTIM2 0x08000000 | ||
189 | |||
190 | #define DF_FP_PM 0x410 | ||
191 | #define DF_FP_PM_P (1 << 24) | ||
192 | |||
193 | #define DF_DITHER_CONTROL 0x418 | ||
194 | #define DF_DEFAULT_TFT_DITHCTL 0x00000070 | ||
195 | #define GP_BLT_STATUS 0x44 | ||
196 | #define GP_BS_BLT_BUSY (1 << 0) | ||
197 | #define GP_BS_CB_EMPTY (1 << 4) | ||
198 | |||
199 | #endif | ||