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path: root/drivers/video/geode/display_gx.c
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Diffstat (limited to 'drivers/video/geode/display_gx.c')
-rw-r--r--drivers/video/geode/display_gx.c48
1 files changed, 27 insertions, 21 deletions
diff --git a/drivers/video/geode/display_gx.c b/drivers/video/geode/display_gx.c
index 8cd75725a31b..47f422e19974 100644
--- a/drivers/video/geode/display_gx.c
+++ b/drivers/video/geode/display_gx.c
@@ -20,6 +20,7 @@
20 20
21#include "geodefb.h" 21#include "geodefb.h"
22#include "display_gx.h" 22#include "display_gx.h"
23#include "gxfb.h"
23 24
24unsigned int gx_frame_buffer_size(void) 25unsigned int gx_frame_buffer_size(void)
25{ 26{
@@ -50,22 +51,21 @@ static void gx_set_mode(struct fb_info *info)
50 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; 51 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
51 52
52 /* Unlock the display controller registers. */ 53 /* Unlock the display controller registers. */
53 readl(par->dc_regs + DC_UNLOCK); 54 write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE);
54 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
55 55
56 gcfg = readl(par->dc_regs + DC_GENERAL_CFG); 56 gcfg = read_dc(par, DC_GENERAL_CFG);
57 dcfg = readl(par->dc_regs + DC_DISPLAY_CFG); 57 dcfg = read_dc(par, DC_DISPLAY_CFG);
58 58
59 /* Disable the timing generator. */ 59 /* Disable the timing generator. */
60 dcfg &= ~(DC_DCFG_TGEN); 60 dcfg &= ~(DC_DCFG_TGEN);
61 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); 61 write_dc(par, DC_DISPLAY_CFG, dcfg);
62 62
63 /* Wait for pending memory requests before disabling the FIFO load. */ 63 /* Wait for pending memory requests before disabling the FIFO load. */
64 udelay(100); 64 udelay(100);
65 65
66 /* Disable FIFO load and compression. */ 66 /* Disable FIFO load and compression. */
67 gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); 67 gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
68 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 68 write_dc(par, DC_GENERAL_CFG, gcfg);
69 69
70 /* Setup DCLK and its divisor. */ 70 /* Setup DCLK and its divisor. */
71 par->vid_ops->set_dclk(info); 71 par->vid_ops->set_dclk(info);
@@ -83,12 +83,12 @@ static void gx_set_mode(struct fb_info *info)
83 gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; 83 gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
84 84
85 /* Framebuffer start offset. */ 85 /* Framebuffer start offset. */
86 writel(0, par->dc_regs + DC_FB_ST_OFFSET); 86 write_dc(par, DC_FB_ST_OFFSET, 0);
87 87
88 /* Line delta and line buffer length. */ 88 /* Line delta and line buffer length. */
89 writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); 89 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
90 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, 90 write_dc(par, DC_LINE_SIZE,
91 par->dc_regs + DC_LINE_SIZE); 91 ((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
92 92
93 93
94 /* Enable graphics and video data and unmask address lines. */ 94 /* Enable graphics and video data and unmask address lines. */
@@ -127,22 +127,28 @@ static void gx_set_mode(struct fb_info *info)
127 vblankend = vsyncend + info->var.upper_margin; 127 vblankend = vsyncend + info->var.upper_margin;
128 vtotal = vblankend; 128 vtotal = vblankend;
129 129
130 writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); 130 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) |
131 writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); 131 ((htotal - 1) << 16));
132 writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); 132 write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
133 ((hblankend - 1) << 16));
134 write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1) |
135 ((hsyncend - 1) << 16));
133 136
134 writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); 137 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) |
135 writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); 138 ((vtotal - 1) << 16));
136 writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); 139 write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
140 ((vblankend - 1) << 16));
141 write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1) |
142 ((vsyncend - 1) << 16));
137 143
138 /* Write final register values. */ 144 /* Write final register values. */
139 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); 145 write_dc(par, DC_DISPLAY_CFG, dcfg);
140 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); 146 write_dc(par, DC_GENERAL_CFG, gcfg);
141 147
142 par->vid_ops->configure_display(info); 148 par->vid_ops->configure_display(info);
143 149
144 /* Relock display controller registers */ 150 /* Relock display controller registers */
145 writel(0, par->dc_regs + DC_UNLOCK); 151 write_dc(par, DC_UNLOCK, 0);
146} 152}
147 153
148static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno, 154static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
@@ -156,8 +162,8 @@ static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
156 val |= (green) & 0x00ff00; 162 val |= (green) & 0x00ff00;
157 val |= (blue >> 8) & 0x0000ff; 163 val |= (blue >> 8) & 0x0000ff;
158 164
159 writel(regno, par->dc_regs + DC_PAL_ADDRESS); 165 write_dc(par, DC_PAL_ADDRESS, regno);
160 writel(val, par->dc_regs + DC_PAL_DATA); 166 write_dc(par, DC_PAL_DATA, val);
161} 167}
162 168
163struct geode_dc_ops gx_dc_ops = { 169struct geode_dc_ops gx_dc_ops = {