aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c')
-rw-r--r--drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c480
1 files changed, 480 insertions, 0 deletions
diff --git a/drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c b/drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c
new file mode 100644
index 000000000000..fae6adc005a7
--- /dev/null
+++ b/drivers/video/fbdev/omap2/displays-new/panel-tpo-td028ttec1.c
@@ -0,0 +1,480 @@
1/*
2 * Toppoly TD028TTEC1 panel support
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Neo 1973 code (jbt6k74.c):
8 * Copyright (C) 2006-2007 by OpenMoko, Inc.
9 * Author: Harald Welte <laforge@openmoko.org>
10 *
11 * Ported and adapted from Neo 1973 U-Boot by:
12 * H. Nikolaus Schaller <hns@goldelico.com>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 *
23 * You should have received a copy of the GNU General Public License along with
24 * this program. If not, see <http://www.gnu.org/licenses/>.
25 */
26
27#include <linux/module.h>
28#include <linux/delay.h>
29#include <linux/spi/spi.h>
30#include <linux/gpio.h>
31#include <video/omapdss.h>
32#include <video/omap-panel-data.h>
33
34struct panel_drv_data {
35 struct omap_dss_device dssdev;
36 struct omap_dss_device *in;
37
38 int data_lines;
39
40 struct omap_video_timings videomode;
41
42 struct spi_device *spi_dev;
43};
44
45static struct omap_video_timings td028ttec1_panel_timings = {
46 .x_res = 480,
47 .y_res = 640,
48 .pixelclock = 22153000,
49 .hfp = 24,
50 .hsw = 8,
51 .hbp = 8,
52 .vfp = 4,
53 .vsw = 2,
54 .vbp = 2,
55
56 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
57 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
58
59 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
60 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
61 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
62};
63
64#define JBT_COMMAND 0x000
65#define JBT_DATA 0x100
66
67static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
68{
69 int rc;
70 u16 tx_buf = JBT_COMMAND | reg;
71
72 rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
73 1*sizeof(u16));
74 if (rc != 0)
75 dev_err(&ddata->spi_dev->dev,
76 "jbt_ret_write_0 spi_write ret %d\n", rc);
77
78 return rc;
79}
80
81static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
82{
83 int rc;
84 u16 tx_buf[2];
85
86 tx_buf[0] = JBT_COMMAND | reg;
87 tx_buf[1] = JBT_DATA | data;
88 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
89 2*sizeof(u16));
90 if (rc != 0)
91 dev_err(&ddata->spi_dev->dev,
92 "jbt_reg_write_1 spi_write ret %d\n", rc);
93
94 return rc;
95}
96
97static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
98{
99 int rc;
100 u16 tx_buf[3];
101
102 tx_buf[0] = JBT_COMMAND | reg;
103 tx_buf[1] = JBT_DATA | (data >> 8);
104 tx_buf[2] = JBT_DATA | (data & 0xff);
105
106 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
107 3*sizeof(u16));
108
109 if (rc != 0)
110 dev_err(&ddata->spi_dev->dev,
111 "jbt_reg_write_2 spi_write ret %d\n", rc);
112
113 return rc;
114}
115
116enum jbt_register {
117 JBT_REG_SLEEP_IN = 0x10,
118 JBT_REG_SLEEP_OUT = 0x11,
119
120 JBT_REG_DISPLAY_OFF = 0x28,
121 JBT_REG_DISPLAY_ON = 0x29,
122
123 JBT_REG_RGB_FORMAT = 0x3a,
124 JBT_REG_QUAD_RATE = 0x3b,
125
126 JBT_REG_POWER_ON_OFF = 0xb0,
127 JBT_REG_BOOSTER_OP = 0xb1,
128 JBT_REG_BOOSTER_MODE = 0xb2,
129 JBT_REG_BOOSTER_FREQ = 0xb3,
130 JBT_REG_OPAMP_SYSCLK = 0xb4,
131 JBT_REG_VSC_VOLTAGE = 0xb5,
132 JBT_REG_VCOM_VOLTAGE = 0xb6,
133 JBT_REG_EXT_DISPL = 0xb7,
134 JBT_REG_OUTPUT_CONTROL = 0xb8,
135 JBT_REG_DCCLK_DCEV = 0xb9,
136 JBT_REG_DISPLAY_MODE1 = 0xba,
137 JBT_REG_DISPLAY_MODE2 = 0xbb,
138 JBT_REG_DISPLAY_MODE = 0xbc,
139 JBT_REG_ASW_SLEW = 0xbd,
140 JBT_REG_DUMMY_DISPLAY = 0xbe,
141 JBT_REG_DRIVE_SYSTEM = 0xbf,
142
143 JBT_REG_SLEEP_OUT_FR_A = 0xc0,
144 JBT_REG_SLEEP_OUT_FR_B = 0xc1,
145 JBT_REG_SLEEP_OUT_FR_C = 0xc2,
146 JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
147 JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
148 JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
149 JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
150
151 JBT_REG_GAMMA1_FINE_1 = 0xc7,
152 JBT_REG_GAMMA1_FINE_2 = 0xc8,
153 JBT_REG_GAMMA1_INCLINATION = 0xc9,
154 JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
155
156 JBT_REG_BLANK_CONTROL = 0xcf,
157 JBT_REG_BLANK_TH_TV = 0xd0,
158 JBT_REG_CKV_ON_OFF = 0xd1,
159 JBT_REG_CKV_1_2 = 0xd2,
160 JBT_REG_OEV_TIMING = 0xd3,
161 JBT_REG_ASW_TIMING_1 = 0xd4,
162 JBT_REG_ASW_TIMING_2 = 0xd5,
163
164 JBT_REG_HCLOCK_VGA = 0xec,
165 JBT_REG_HCLOCK_QVGA = 0xed,
166};
167
168#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
169
170static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
171{
172 struct panel_drv_data *ddata = to_panel_data(dssdev);
173 struct omap_dss_device *in = ddata->in;
174 int r;
175
176 if (omapdss_device_is_connected(dssdev))
177 return 0;
178
179 r = in->ops.dpi->connect(in, dssdev);
180 if (r)
181 return r;
182
183 return 0;
184}
185
186static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
187{
188 struct panel_drv_data *ddata = to_panel_data(dssdev);
189 struct omap_dss_device *in = ddata->in;
190
191 if (!omapdss_device_is_connected(dssdev))
192 return;
193
194 in->ops.dpi->disconnect(in, dssdev);
195}
196
197static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
198{
199 struct panel_drv_data *ddata = to_panel_data(dssdev);
200 struct omap_dss_device *in = ddata->in;
201 int r;
202
203 if (!omapdss_device_is_connected(dssdev))
204 return -ENODEV;
205
206 if (omapdss_device_is_enabled(dssdev))
207 return 0;
208
209 in->ops.dpi->set_data_lines(in, ddata->data_lines);
210 in->ops.dpi->set_timings(in, &ddata->videomode);
211
212 r = in->ops.dpi->enable(in);
213 if (r)
214 return r;
215
216 dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
217 dssdev->state);
218
219 /* three times command zero */
220 r |= jbt_ret_write_0(ddata, 0x00);
221 usleep_range(1000, 2000);
222 r |= jbt_ret_write_0(ddata, 0x00);
223 usleep_range(1000, 2000);
224 r |= jbt_ret_write_0(ddata, 0x00);
225 usleep_range(1000, 2000);
226
227 if (r) {
228 dev_warn(dssdev->dev, "transfer error\n");
229 goto transfer_err;
230 }
231
232 /* deep standby out */
233 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
234
235 /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
236 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
237
238 /* Quad mode off */
239 r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
240
241 /* AVDD on, XVDD on */
242 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
243
244 /* Output control */
245 r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
246
247 /* Sleep mode off */
248 r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
249
250 /* at this point we have like 50% grey */
251
252 /* initialize register set */
253 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
254 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
255 r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
256 r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
257 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
258 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
259 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
260 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
261 r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
262 r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
263 r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
264 r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
265 r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
266 /*
267 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
268 * to avoid red / blue flicker
269 */
270 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
271 r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
272
273 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
274 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
275 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
276 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
277 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
278 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
279 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
280
281 r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
282 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
283 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
284 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
285
286 r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
287 r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
288 r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
289
290 r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
291 r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
292
293 r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
294 r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
295 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
296
297 r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
298
299 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
300
301transfer_err:
302
303 return r ? -EIO : 0;
304}
305
306static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
307{
308 struct panel_drv_data *ddata = to_panel_data(dssdev);
309 struct omap_dss_device *in = ddata->in;
310
311 if (!omapdss_device_is_enabled(dssdev))
312 return;
313
314 dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
315
316 jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
317 jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
318 jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
319 jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
320
321 in->ops.dpi->disable(in);
322
323 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
324}
325
326static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
327 struct omap_video_timings *timings)
328{
329 struct panel_drv_data *ddata = to_panel_data(dssdev);
330 struct omap_dss_device *in = ddata->in;
331
332 ddata->videomode = *timings;
333 dssdev->panel.timings = *timings;
334
335 in->ops.dpi->set_timings(in, timings);
336}
337
338static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
339 struct omap_video_timings *timings)
340{
341 struct panel_drv_data *ddata = to_panel_data(dssdev);
342
343 *timings = ddata->videomode;
344}
345
346static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
347 struct omap_video_timings *timings)
348{
349 struct panel_drv_data *ddata = to_panel_data(dssdev);
350 struct omap_dss_device *in = ddata->in;
351
352 return in->ops.dpi->check_timings(in, timings);
353}
354
355static struct omap_dss_driver td028ttec1_ops = {
356 .connect = td028ttec1_panel_connect,
357 .disconnect = td028ttec1_panel_disconnect,
358
359 .enable = td028ttec1_panel_enable,
360 .disable = td028ttec1_panel_disable,
361
362 .set_timings = td028ttec1_panel_set_timings,
363 .get_timings = td028ttec1_panel_get_timings,
364 .check_timings = td028ttec1_panel_check_timings,
365};
366
367static int td028ttec1_panel_probe_pdata(struct spi_device *spi)
368{
369 const struct panel_tpo_td028ttec1_platform_data *pdata;
370 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
371 struct omap_dss_device *dssdev, *in;
372
373 pdata = dev_get_platdata(&spi->dev);
374
375 in = omap_dss_find_output(pdata->source);
376 if (in == NULL) {
377 dev_err(&spi->dev, "failed to find video source '%s'\n",
378 pdata->source);
379 return -EPROBE_DEFER;
380 }
381
382 ddata->in = in;
383
384 ddata->data_lines = pdata->data_lines;
385
386 dssdev = &ddata->dssdev;
387 dssdev->name = pdata->name;
388
389 return 0;
390}
391
392static int td028ttec1_panel_probe(struct spi_device *spi)
393{
394 struct panel_drv_data *ddata;
395 struct omap_dss_device *dssdev;
396 int r;
397
398 dev_dbg(&spi->dev, "%s\n", __func__);
399
400 spi->bits_per_word = 9;
401 spi->mode = SPI_MODE_3;
402
403 r = spi_setup(spi);
404 if (r < 0) {
405 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
406 return r;
407 }
408
409 ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
410 if (ddata == NULL)
411 return -ENOMEM;
412
413 dev_set_drvdata(&spi->dev, ddata);
414
415 ddata->spi_dev = spi;
416
417 if (dev_get_platdata(&spi->dev)) {
418 r = td028ttec1_panel_probe_pdata(spi);
419 if (r)
420 return r;
421 } else {
422 return -ENODEV;
423 }
424
425 ddata->videomode = td028ttec1_panel_timings;
426
427 dssdev = &ddata->dssdev;
428 dssdev->dev = &spi->dev;
429 dssdev->driver = &td028ttec1_ops;
430 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
431 dssdev->owner = THIS_MODULE;
432 dssdev->panel.timings = ddata->videomode;
433 dssdev->phy.dpi.data_lines = ddata->data_lines;
434
435 r = omapdss_register_display(dssdev);
436 if (r) {
437 dev_err(&spi->dev, "Failed to register panel\n");
438 goto err_reg;
439 }
440
441 return 0;
442
443err_reg:
444 omap_dss_put_device(ddata->in);
445 return r;
446}
447
448static int td028ttec1_panel_remove(struct spi_device *spi)
449{
450 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
451 struct omap_dss_device *dssdev = &ddata->dssdev;
452 struct omap_dss_device *in = ddata->in;
453
454 dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
455
456 omapdss_unregister_display(dssdev);
457
458 td028ttec1_panel_disable(dssdev);
459 td028ttec1_panel_disconnect(dssdev);
460
461 omap_dss_put_device(in);
462
463 return 0;
464}
465
466static struct spi_driver td028ttec1_spi_driver = {
467 .probe = td028ttec1_panel_probe,
468 .remove = td028ttec1_panel_remove,
469
470 .driver = {
471 .name = "panel-tpo-td028ttec1",
472 .owner = THIS_MODULE,
473 },
474};
475
476module_spi_driver(td028ttec1_spi_driver);
477
478MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
479MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
480MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 03:36:21 -0500