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-rw-r--r--drivers/video/fbdev/aty/radeon_base.c2568
1 files changed, 2568 insertions, 0 deletions
diff --git a/drivers/video/fbdev/aty/radeon_base.c b/drivers/video/fbdev/aty/radeon_base.c
new file mode 100644
index 000000000000..26d80a4486fb
--- /dev/null
+++ b/drivers/video/fbdev/aty/radeon_base.c
@@ -0,0 +1,2568 @@
1/*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53#define RADEON_VERSION "0.2.0"
54
55#include "radeonfb.h"
56
57#include <linux/module.h>
58#include <linux/moduleparam.h>
59#include <linux/kernel.h>
60#include <linux/errno.h>
61#include <linux/string.h>
62#include <linux/ctype.h>
63#include <linux/mm.h>
64#include <linux/slab.h>
65#include <linux/delay.h>
66#include <linux/time.h>
67#include <linux/fb.h>
68#include <linux/ioport.h>
69#include <linux/init.h>
70#include <linux/pci.h>
71#include <linux/vmalloc.h>
72#include <linux/device.h>
73
74#include <asm/io.h>
75#include <linux/uaccess.h>
76
77#ifdef CONFIG_PPC_OF
78
79#include <asm/pci-bridge.h>
80#include "../macmodes.h"
81
82#ifdef CONFIG_BOOTX_TEXT
83#include <asm/btext.h>
84#endif
85
86#endif /* CONFIG_PPC_OF */
87
88#ifdef CONFIG_MTRR
89#include <asm/mtrr.h>
90#endif
91
92#include <video/radeon.h>
93#include <linux/radeonfb.h>
94
95#include "../edid.h" // MOVE THAT TO include/video
96#include "ati_ids.h"
97
98#define MAX_MAPPED_VRAM (2048*2048*4)
99#define MIN_MAPPED_VRAM (1024*768*1)
100
101#define CHIP_DEF(id, family, flags) \
102 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
103
104static struct pci_device_id radeonfb_pci_table[] = {
105 /* Radeon Xpress 200m */
106 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
107 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
108 /* Mobility M6 */
109 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
110 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
111 /* Radeon VE/7000 */
112 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
113 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
114 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
115 /* Radeon IGP320M (U1) */
116 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* Radeon IGP320 (A3) */
118 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* IGP330M/340M/350M (U2) */
120 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121 /* IGP330/340/350 (A4) */
122 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123 /* Mobility 7000 IGP */
124 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
125 /* 7000 IGP (A4+) */
126 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
127 /* 8500 AIW */
128 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
130 /* 8700/8800 */
131 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
132 /* 8500 */
133 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
134 /* 9100 */
135 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
136 /* Mobility M7 */
137 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
138 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 /* 7500 */
140 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
141 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
142 /* Mobility M9 */
143 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 /* 9000/Pro */
148 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
149 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
150
151 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
152 /* Mobility 9100 IGP (U3) */
153 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
155 /* 9100 IGP (A5) */
156 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
158 /* Mobility 9200 (M9+) */
159 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
161 /* 9200 */
162 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
165 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
166 /* 9500 */
167 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
169 /* 9600TX / FireGL Z1 */
170 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
172 /* 9700/9500/Pro/FireGL X1 */
173 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
176 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
177 /* Mobility M10/M11 */
178 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
184 /* 9600/FireGL T2 */
185 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
191 /* 9800/Pro/FileGL X2 */
192 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
200 /* Newer stuff */
201 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
205 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
212 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
219 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
226 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
227 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
228 /* Original Radeon/7200 */
229 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
231 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
232 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
233 { 0, }
234};
235MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
236
237
238typedef struct {
239 u16 reg;
240 u32 val;
241} reg_val;
242
243
244/* these common regs are cleared before mode setting so they do not
245 * interfere with anything
246 */
247static reg_val common_regs[] = {
248 { OVR_CLR, 0 },
249 { OVR_WID_LEFT_RIGHT, 0 },
250 { OVR_WID_TOP_BOTTOM, 0 },
251 { OV0_SCALE_CNTL, 0 },
252 { SUBPIC_CNTL, 0 },
253 { VIPH_CONTROL, 0 },
254 { I2C_CNTL_1, 0 },
255 { GEN_INT_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 },
257 { CAP1_TRIG_CNTL, 0 },
258};
259
260/*
261 * globals
262 */
263
264static char *mode_option;
265static char *monitor_layout;
266static bool noaccel = 0;
267static int default_dynclk = -2;
268static bool nomodeset = 0;
269static bool ignore_edid = 0;
270static bool mirror = 0;
271static int panel_yres = 0;
272static bool force_dfp = 0;
273static bool force_measure_pll = 0;
274#ifdef CONFIG_MTRR
275static bool nomtrr = 0;
276#endif
277static bool force_sleep;
278static bool ignore_devlist;
279#ifdef CONFIG_PMAC_BACKLIGHT
280static int backlight = 1;
281#else
282static int backlight = 0;
283#endif
284
285/*
286 * prototypes
287 */
288
289static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
290{
291 if (!rinfo->bios_seg)
292 return;
293 pci_unmap_rom(dev, rinfo->bios_seg);
294}
295
296static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
297{
298 void __iomem *rom;
299 u16 dptr;
300 u8 rom_type;
301 size_t rom_size;
302
303 /* If this is a primary card, there is a shadow copy of the
304 * ROM somewhere in the first meg. We will just ignore the copy
305 * and use the ROM directly.
306 */
307
308 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
309 unsigned int temp;
310 temp = INREG(MPP_TB_CONFIG);
311 temp &= 0x00ffffffu;
312 temp |= 0x04 << 24;
313 OUTREG(MPP_TB_CONFIG, temp);
314 temp = INREG(MPP_TB_CONFIG);
315
316 rom = pci_map_rom(dev, &rom_size);
317 if (!rom) {
318 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
319 pci_name(rinfo->pdev));
320 return -ENOMEM;
321 }
322
323 rinfo->bios_seg = rom;
324
325 /* Very simple test to make sure it appeared */
326 if (BIOS_IN16(0) != 0xaa55) {
327 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
328 "should be 0xaa55\n",
329 pci_name(rinfo->pdev), BIOS_IN16(0));
330 goto failed;
331 }
332 /* Look for the PCI data to check the ROM type */
333 dptr = BIOS_IN16(0x18);
334
335 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
336 * for now, until I've verified this works everywhere. The goal here is more
337 * to phase out Open Firmware images.
338 *
339 * Currently, we only look at the first PCI data, we could iteratre and deal with
340 * them all, and we should use fb_bios_start relative to start of image and not
341 * relative start of ROM, but so far, I never found a dual-image ATI card
342 *
343 * typedef struct {
344 * u32 signature; + 0x00
345 * u16 vendor; + 0x04
346 * u16 device; + 0x06
347 * u16 reserved_1; + 0x08
348 * u16 dlen; + 0x0a
349 * u8 drevision; + 0x0c
350 * u8 class_hi; + 0x0d
351 * u16 class_lo; + 0x0e
352 * u16 ilen; + 0x10
353 * u16 irevision; + 0x12
354 * u8 type; + 0x14
355 * u8 indicator; + 0x15
356 * u16 reserved_2; + 0x16
357 * } pci_data_t;
358 */
359 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
360 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
361 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
362 goto anyway;
363 }
364 rom_type = BIOS_IN8(dptr + 0x14);
365 switch(rom_type) {
366 case 0:
367 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
368 break;
369 case 1:
370 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
371 goto failed;
372 case 2:
373 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
374 goto failed;
375 default:
376 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
377 goto failed;
378 }
379 anyway:
380 /* Locate the flat panel infos, do some sanity checking !!! */
381 rinfo->fp_bios_start = BIOS_IN16(0x48);
382 return 0;
383
384 failed:
385 rinfo->bios_seg = NULL;
386 radeon_unmap_ROM(rinfo, dev);
387 return -ENXIO;
388}
389
390#ifdef CONFIG_X86
391static int radeon_find_mem_vbios(struct radeonfb_info *rinfo)
392{
393 /* I simplified this code as we used to miss the signatures in
394 * a lot of case. It's now closer to XFree, we just don't check
395 * for signatures at all... Something better will have to be done
396 * if we end up having conflicts
397 */
398 u32 segstart;
399 void __iomem *rom_base = NULL;
400
401 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
402 rom_base = ioremap(segstart, 0x10000);
403 if (rom_base == NULL)
404 return -ENOMEM;
405 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
406 break;
407 iounmap(rom_base);
408 rom_base = NULL;
409 }
410 if (rom_base == NULL)
411 return -ENXIO;
412
413 /* Locate the flat panel infos, do some sanity checking !!! */
414 rinfo->bios_seg = rom_base;
415 rinfo->fp_bios_start = BIOS_IN16(0x48);
416
417 return 0;
418}
419#endif
420
421#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
422/*
423 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
424 * tree. Hopefully, ATI OF driver is kind enough to fill these
425 */
426static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
427{
428 struct device_node *dp = rinfo->of_node;
429 const u32 *val;
430
431 if (dp == NULL)
432 return -ENODEV;
433 val = of_get_property(dp, "ATY,RefCLK", NULL);
434 if (!val || !*val) {
435 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
436 return -EINVAL;
437 }
438
439 rinfo->pll.ref_clk = (*val) / 10;
440
441 val = of_get_property(dp, "ATY,SCLK", NULL);
442 if (val && *val)
443 rinfo->pll.sclk = (*val) / 10;
444
445 val = of_get_property(dp, "ATY,MCLK", NULL);
446 if (val && *val)
447 rinfo->pll.mclk = (*val) / 10;
448
449 return 0;
450}
451#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
452
453/*
454 * Read PLL infos from chip registers
455 */
456static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
457{
458 unsigned char ppll_div_sel;
459 unsigned Ns, Nm, M;
460 unsigned sclk, mclk, tmp, ref_div;
461 int hTotal, vTotal, num, denom, m, n;
462 unsigned long long hz, vclk;
463 long xtal;
464 struct timeval start_tv, stop_tv;
465 long total_secs, total_usecs;
466 int i;
467
468 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
469 * here, so... --BenH
470 */
471
472 /* Flush PCI buffers ? */
473 tmp = INREG16(DEVICE_ID);
474
475 local_irq_disable();
476
477 for(i=0; i<1000000; i++)
478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
479 break;
480
481 do_gettimeofday(&start_tv);
482
483 for(i=0; i<1000000; i++)
484 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
485 break;
486
487 for(i=0; i<1000000; i++)
488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
489 break;
490
491 do_gettimeofday(&stop_tv);
492
493 local_irq_enable();
494
495 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
496 if (total_secs > 10)
497 return -1;
498 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
499 total_usecs += total_secs * 1000000;
500 if (total_usecs < 0)
501 total_usecs = -total_usecs;
502 hz = 1000000/total_usecs;
503
504 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
505 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
506 vclk = (long long)hTotal * (long long)vTotal * hz;
507
508 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
509 case 0:
510 default:
511 num = 1;
512 denom = 1;
513 break;
514 case 1:
515 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
516 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
517 num = 2*n;
518 denom = 2*m;
519 break;
520 case 2:
521 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
522 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
523 num = 2*n;
524 denom = 2*m;
525 break;
526 }
527
528 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
529 radeon_pll_errata_after_index(rinfo);
530
531 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
532 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
533
534 num *= n;
535 denom *= m;
536
537 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
538 case 1:
539 denom *= 2;
540 break;
541 case 2:
542 denom *= 4;
543 break;
544 case 3:
545 denom *= 8;
546 break;
547 case 4:
548 denom *= 3;
549 break;
550 case 6:
551 denom *= 6;
552 break;
553 case 7:
554 denom *= 12;
555 break;
556 }
557
558 vclk *= denom;
559 do_div(vclk, 1000 * num);
560 xtal = vclk;
561
562 if ((xtal > 26900) && (xtal < 27100))
563 xtal = 2700;
564 else if ((xtal > 14200) && (xtal < 14400))
565 xtal = 1432;
566 else if ((xtal > 29400) && (xtal < 29600))
567 xtal = 2950;
568 else {
569 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
570 return -1;
571 }
572
573 tmp = INPLL(M_SPLL_REF_FB_DIV);
574 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
575
576 Ns = (tmp & 0xff0000) >> 16;
577 Nm = (tmp & 0xff00) >> 8;
578 M = (tmp & 0xff);
579 sclk = round_div((2 * Ns * xtal), (2 * M));
580 mclk = round_div((2 * Nm * xtal), (2 * M));
581
582 /* we're done, hopefully these are sane values */
583 rinfo->pll.ref_clk = xtal;
584 rinfo->pll.ref_div = ref_div;
585 rinfo->pll.sclk = sclk;
586 rinfo->pll.mclk = mclk;
587
588 return 0;
589}
590
591/*
592 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
593 */
594static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
595{
596 /*
597 * In the case nothing works, these are defaults; they are mostly
598 * incomplete, however. It does provide ppll_max and _min values
599 * even for most other methods, however.
600 */
601 switch (rinfo->chipset) {
602 case PCI_DEVICE_ID_ATI_RADEON_QW:
603 case PCI_DEVICE_ID_ATI_RADEON_QX:
604 rinfo->pll.ppll_max = 35000;
605 rinfo->pll.ppll_min = 12000;
606 rinfo->pll.mclk = 23000;
607 rinfo->pll.sclk = 23000;
608 rinfo->pll.ref_clk = 2700;
609 break;
610 case PCI_DEVICE_ID_ATI_RADEON_QL:
611 case PCI_DEVICE_ID_ATI_RADEON_QN:
612 case PCI_DEVICE_ID_ATI_RADEON_QO:
613 case PCI_DEVICE_ID_ATI_RADEON_Ql:
614 case PCI_DEVICE_ID_ATI_RADEON_BB:
615 rinfo->pll.ppll_max = 35000;
616 rinfo->pll.ppll_min = 12000;
617 rinfo->pll.mclk = 27500;
618 rinfo->pll.sclk = 27500;
619 rinfo->pll.ref_clk = 2700;
620 break;
621 case PCI_DEVICE_ID_ATI_RADEON_Id:
622 case PCI_DEVICE_ID_ATI_RADEON_Ie:
623 case PCI_DEVICE_ID_ATI_RADEON_If:
624 case PCI_DEVICE_ID_ATI_RADEON_Ig:
625 rinfo->pll.ppll_max = 35000;
626 rinfo->pll.ppll_min = 12000;
627 rinfo->pll.mclk = 25000;
628 rinfo->pll.sclk = 25000;
629 rinfo->pll.ref_clk = 2700;
630 break;
631 case PCI_DEVICE_ID_ATI_RADEON_ND:
632 case PCI_DEVICE_ID_ATI_RADEON_NE:
633 case PCI_DEVICE_ID_ATI_RADEON_NF:
634 case PCI_DEVICE_ID_ATI_RADEON_NG:
635 rinfo->pll.ppll_max = 40000;
636 rinfo->pll.ppll_min = 20000;
637 rinfo->pll.mclk = 27000;
638 rinfo->pll.sclk = 27000;
639 rinfo->pll.ref_clk = 2700;
640 break;
641 case PCI_DEVICE_ID_ATI_RADEON_QD:
642 case PCI_DEVICE_ID_ATI_RADEON_QE:
643 case PCI_DEVICE_ID_ATI_RADEON_QF:
644 case PCI_DEVICE_ID_ATI_RADEON_QG:
645 default:
646 rinfo->pll.ppll_max = 35000;
647 rinfo->pll.ppll_min = 12000;
648 rinfo->pll.mclk = 16600;
649 rinfo->pll.sclk = 16600;
650 rinfo->pll.ref_clk = 2700;
651 break;
652 }
653 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
654
655
656#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
657 /*
658 * Retrieve PLL infos from Open Firmware first
659 */
660 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
661 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
662 goto found;
663 }
664#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
665
666 /*
667 * Check out if we have an X86 which gave us some PLL informations
668 * and if yes, retrieve them
669 */
670 if (!force_measure_pll && rinfo->bios_seg) {
671 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
672
673 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
674 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
675 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
676 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
677 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
678 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
679
680 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
681 goto found;
682 }
683
684 /*
685 * We didn't get PLL parameters from either OF or BIOS, we try to
686 * probe them
687 */
688 if (radeon_probe_pll_params(rinfo) == 0) {
689 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
690 goto found;
691 }
692
693 /*
694 * Fall back to already-set defaults...
695 */
696 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
697
698found:
699 /*
700 * Some methods fail to retrieve SCLK and MCLK values, we apply default
701 * settings in this case (200Mhz). If that really happens often, we
702 * could fetch from registers instead...
703 */
704 if (rinfo->pll.mclk == 0)
705 rinfo->pll.mclk = 20000;
706 if (rinfo->pll.sclk == 0)
707 rinfo->pll.sclk = 20000;
708
709 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
710 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
711 rinfo->pll.ref_div,
712 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
713 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
714 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
715}
716
717static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
718{
719 struct radeonfb_info *rinfo = info->par;
720 struct fb_var_screeninfo v;
721 int nom, den;
722 unsigned int pitch;
723
724 if (radeon_match_mode(rinfo, &v, var))
725 return -EINVAL;
726
727 switch (v.bits_per_pixel) {
728 case 0 ... 8:
729 v.bits_per_pixel = 8;
730 break;
731 case 9 ... 16:
732 v.bits_per_pixel = 16;
733 break;
734 case 17 ... 24:
735#if 0 /* Doesn't seem to work */
736 v.bits_per_pixel = 24;
737 break;
738#endif
739 return -EINVAL;
740 case 25 ... 32:
741 v.bits_per_pixel = 32;
742 break;
743 default:
744 return -EINVAL;
745 }
746
747 switch (var_to_depth(&v)) {
748 case 8:
749 nom = den = 1;
750 v.red.offset = v.green.offset = v.blue.offset = 0;
751 v.red.length = v.green.length = v.blue.length = 8;
752 v.transp.offset = v.transp.length = 0;
753 break;
754 case 15:
755 nom = 2;
756 den = 1;
757 v.red.offset = 10;
758 v.green.offset = 5;
759 v.blue.offset = 0;
760 v.red.length = v.green.length = v.blue.length = 5;
761 v.transp.offset = v.transp.length = 0;
762 break;
763 case 16:
764 nom = 2;
765 den = 1;
766 v.red.offset = 11;
767 v.green.offset = 5;
768 v.blue.offset = 0;
769 v.red.length = 5;
770 v.green.length = 6;
771 v.blue.length = 5;
772 v.transp.offset = v.transp.length = 0;
773 break;
774 case 24:
775 nom = 4;
776 den = 1;
777 v.red.offset = 16;
778 v.green.offset = 8;
779 v.blue.offset = 0;
780 v.red.length = v.blue.length = v.green.length = 8;
781 v.transp.offset = v.transp.length = 0;
782 break;
783 case 32:
784 nom = 4;
785 den = 1;
786 v.red.offset = 16;
787 v.green.offset = 8;
788 v.blue.offset = 0;
789 v.red.length = v.blue.length = v.green.length = 8;
790 v.transp.offset = 24;
791 v.transp.length = 8;
792 break;
793 default:
794 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
795 var->xres, var->yres, var->bits_per_pixel);
796 return -EINVAL;
797 }
798
799 if (v.yres_virtual < v.yres)
800 v.yres_virtual = v.yres;
801 if (v.xres_virtual < v.xres)
802 v.xres_virtual = v.xres;
803
804
805 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
806 * with some panels, though I don't quite like this solution
807 */
808 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
809 v.xres_virtual = v.xres_virtual & ~7ul;
810 } else {
811 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
812 & ~(0x3f)) >> 6;
813 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
814 }
815
816 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
817 return -EINVAL;
818
819 if (v.xres_virtual < v.xres)
820 v.xres = v.xres_virtual;
821
822 if (v.xoffset > v.xres_virtual - v.xres)
823 v.xoffset = v.xres_virtual - v.xres - 1;
824
825 if (v.yoffset > v.yres_virtual - v.yres)
826 v.yoffset = v.yres_virtual - v.yres - 1;
827
828 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
829 v.transp.offset = v.transp.length =
830 v.transp.msb_right = 0;
831
832 memcpy(var, &v, sizeof(v));
833
834 return 0;
835}
836
837
838static int radeonfb_pan_display (struct fb_var_screeninfo *var,
839 struct fb_info *info)
840{
841 struct radeonfb_info *rinfo = info->par;
842
843 if ((var->xoffset + info->var.xres > info->var.xres_virtual)
844 || (var->yoffset + info->var.yres > info->var.yres_virtual))
845 return -EINVAL;
846
847 if (rinfo->asleep)
848 return 0;
849
850 radeon_fifo_wait(2);
851 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +
852 var->xoffset * info->var.bits_per_pixel / 8) & ~7);
853 return 0;
854}
855
856
857static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
858 unsigned long arg)
859{
860 struct radeonfb_info *rinfo = info->par;
861 unsigned int tmp;
862 u32 value = 0;
863 int rc;
864
865 switch (cmd) {
866 /*
867 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
868 * and do something better using 2nd CRTC instead of just hackish
869 * routing to second output
870 */
871 case FBIO_RADEON_SET_MIRROR:
872 if (!rinfo->is_mobility)
873 return -EINVAL;
874
875 rc = get_user(value, (__u32 __user *)arg);
876
877 if (rc)
878 return rc;
879
880 radeon_fifo_wait(2);
881 if (value & 0x01) {
882 tmp = INREG(LVDS_GEN_CNTL);
883
884 tmp |= (LVDS_ON | LVDS_BLON);
885 } else {
886 tmp = INREG(LVDS_GEN_CNTL);
887
888 tmp &= ~(LVDS_ON | LVDS_BLON);
889 }
890
891 OUTREG(LVDS_GEN_CNTL, tmp);
892
893 if (value & 0x02) {
894 tmp = INREG(CRTC_EXT_CNTL);
895 tmp |= CRTC_CRT_ON;
896
897 mirror = 1;
898 } else {
899 tmp = INREG(CRTC_EXT_CNTL);
900 tmp &= ~CRTC_CRT_ON;
901
902 mirror = 0;
903 }
904
905 OUTREG(CRTC_EXT_CNTL, tmp);
906
907 return 0;
908 case FBIO_RADEON_GET_MIRROR:
909 if (!rinfo->is_mobility)
910 return -EINVAL;
911
912 tmp = INREG(LVDS_GEN_CNTL);
913 if ((LVDS_ON | LVDS_BLON) & tmp)
914 value |= 0x01;
915
916 tmp = INREG(CRTC_EXT_CNTL);
917 if (CRTC_CRT_ON & tmp)
918 value |= 0x02;
919
920 return put_user(value, (__u32 __user *)arg);
921 default:
922 return -EINVAL;
923 }
924
925 return -EINVAL;
926}
927
928
929int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
930{
931 u32 val;
932 u32 tmp_pix_clks;
933 int unblank = 0;
934
935 if (rinfo->lock_blank)
936 return 0;
937
938 radeon_engine_idle();
939
940 val = INREG(CRTC_EXT_CNTL);
941 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
942 CRTC_VSYNC_DIS);
943 switch (blank) {
944 case FB_BLANK_VSYNC_SUSPEND:
945 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
946 break;
947 case FB_BLANK_HSYNC_SUSPEND:
948 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
949 break;
950 case FB_BLANK_POWERDOWN:
951 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
952 CRTC_HSYNC_DIS);
953 break;
954 case FB_BLANK_NORMAL:
955 val |= CRTC_DISPLAY_DIS;
956 break;
957 case FB_BLANK_UNBLANK:
958 default:
959 unblank = 1;
960 }
961 OUTREG(CRTC_EXT_CNTL, val);
962
963
964 switch (rinfo->mon1_type) {
965 case MT_DFP:
966 if (unblank)
967 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
968 ~(FP_FPON | FP_TMDS_EN));
969 else {
970 if (mode_switch || blank == FB_BLANK_NORMAL)
971 break;
972 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
973 }
974 break;
975 case MT_LCD:
976 del_timer_sync(&rinfo->lvds_timer);
977 val = INREG(LVDS_GEN_CNTL);
978 if (unblank) {
979 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
980 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
981 & (LVDS_DIGON | LVDS_BL_MOD_EN));
982 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
983 OUTREG(LVDS_GEN_CNTL, target_val);
984 else if ((val ^ target_val) != 0) {
985 OUTREG(LVDS_GEN_CNTL, target_val
986 & ~(LVDS_ON | LVDS_BL_MOD_EN));
987 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
988 rinfo->init_state.lvds_gen_cntl |=
989 target_val & LVDS_STATE_MASK;
990 if (mode_switch) {
991 radeon_msleep(rinfo->panel_info.pwr_delay);
992 OUTREG(LVDS_GEN_CNTL, target_val);
993 }
994 else {
995 rinfo->pending_lvds_gen_cntl = target_val;
996 mod_timer(&rinfo->lvds_timer,
997 jiffies +
998 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
999 }
1000 }
1001 } else {
1002 val |= LVDS_DISPLAY_DIS;
1003 OUTREG(LVDS_GEN_CNTL, val);
1004
1005 /* We don't do a full switch-off on a simple mode switch */
1006 if (mode_switch || blank == FB_BLANK_NORMAL)
1007 break;
1008
1009 /* Asic bug, when turning off LVDS_ON, we have to make sure
1010 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1011 */
1012 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1013 if (rinfo->is_mobility || rinfo->is_IGP)
1014 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1015 val &= ~(LVDS_BL_MOD_EN);
1016 OUTREG(LVDS_GEN_CNTL, val);
1017 udelay(100);
1018 val &= ~(LVDS_ON | LVDS_EN);
1019 OUTREG(LVDS_GEN_CNTL, val);
1020 val &= ~LVDS_DIGON;
1021 rinfo->pending_lvds_gen_cntl = val;
1022 mod_timer(&rinfo->lvds_timer,
1023 jiffies +
1024 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1025 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1026 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1027 if (rinfo->is_mobility || rinfo->is_IGP)
1028 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1029 }
1030 break;
1031 case MT_CRT:
1032 // todo: powerdown DAC
1033 default:
1034 break;
1035 }
1036
1037 return 0;
1038}
1039
1040static int radeonfb_blank (int blank, struct fb_info *info)
1041{
1042 struct radeonfb_info *rinfo = info->par;
1043
1044 if (rinfo->asleep)
1045 return 0;
1046
1047 return radeon_screen_blank(rinfo, blank, 0);
1048}
1049
1050static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1051 unsigned blue, unsigned transp,
1052 struct radeonfb_info *rinfo)
1053{
1054 u32 pindex;
1055 unsigned int i;
1056
1057
1058 if (regno > 255)
1059 return -EINVAL;
1060
1061 red >>= 8;
1062 green >>= 8;
1063 blue >>= 8;
1064 rinfo->palette[regno].red = red;
1065 rinfo->palette[regno].green = green;
1066 rinfo->palette[regno].blue = blue;
1067
1068 /* default */
1069 pindex = regno;
1070
1071 if (!rinfo->asleep) {
1072 radeon_fifo_wait(9);
1073
1074 if (rinfo->bpp == 16) {
1075 pindex = regno * 8;
1076
1077 if (rinfo->depth == 16 && regno > 63)
1078 return -EINVAL;
1079 if (rinfo->depth == 15 && regno > 31)
1080 return -EINVAL;
1081
1082 /* For 565, the green component is mixed one order
1083 * below
1084 */
1085 if (rinfo->depth == 16) {
1086 OUTREG(PALETTE_INDEX, pindex>>1);
1087 OUTREG(PALETTE_DATA,
1088 (rinfo->palette[regno>>1].red << 16) |
1089 (green << 8) |
1090 (rinfo->palette[regno>>1].blue));
1091 green = rinfo->palette[regno<<1].green;
1092 }
1093 }
1094
1095 if (rinfo->depth != 16 || regno < 32) {
1096 OUTREG(PALETTE_INDEX, pindex);
1097 OUTREG(PALETTE_DATA, (red << 16) |
1098 (green << 8) | blue);
1099 }
1100 }
1101 if (regno < 16) {
1102 u32 *pal = rinfo->info->pseudo_palette;
1103 switch (rinfo->depth) {
1104 case 15:
1105 pal[regno] = (regno << 10) | (regno << 5) | regno;
1106 break;
1107 case 16:
1108 pal[regno] = (regno << 11) | (regno << 5) | regno;
1109 break;
1110 case 24:
1111 pal[regno] = (regno << 16) | (regno << 8) | regno;
1112 break;
1113 case 32:
1114 i = (regno << 8) | regno;
1115 pal[regno] = (i << 16) | i;
1116 break;
1117 }
1118 }
1119 return 0;
1120}
1121
1122static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1123 unsigned blue, unsigned transp,
1124 struct fb_info *info)
1125{
1126 struct radeonfb_info *rinfo = info->par;
1127 u32 dac_cntl2, vclk_cntl = 0;
1128 int rc;
1129
1130 if (!rinfo->asleep) {
1131 if (rinfo->is_mobility) {
1132 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1133 OUTPLL(VCLK_ECP_CNTL,
1134 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1135 }
1136
1137 /* Make sure we are on first palette */
1138 if (rinfo->has_CRTC2) {
1139 dac_cntl2 = INREG(DAC_CNTL2);
1140 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1141 OUTREG(DAC_CNTL2, dac_cntl2);
1142 }
1143 }
1144
1145 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1146
1147 if (!rinfo->asleep && rinfo->is_mobility)
1148 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1149
1150 return rc;
1151}
1152
1153static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1154{
1155 struct radeonfb_info *rinfo = info->par;
1156 u16 *red, *green, *blue, *transp;
1157 u32 dac_cntl2, vclk_cntl = 0;
1158 int i, start, rc = 0;
1159
1160 if (!rinfo->asleep) {
1161 if (rinfo->is_mobility) {
1162 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1163 OUTPLL(VCLK_ECP_CNTL,
1164 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1165 }
1166
1167 /* Make sure we are on first palette */
1168 if (rinfo->has_CRTC2) {
1169 dac_cntl2 = INREG(DAC_CNTL2);
1170 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1171 OUTREG(DAC_CNTL2, dac_cntl2);
1172 }
1173 }
1174
1175 red = cmap->red;
1176 green = cmap->green;
1177 blue = cmap->blue;
1178 transp = cmap->transp;
1179 start = cmap->start;
1180
1181 for (i = 0; i < cmap->len; i++) {
1182 u_int hred, hgreen, hblue, htransp = 0xffff;
1183
1184 hred = *red++;
1185 hgreen = *green++;
1186 hblue = *blue++;
1187 if (transp)
1188 htransp = *transp++;
1189 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1190 rinfo);
1191 if (rc)
1192 break;
1193 }
1194
1195 if (!rinfo->asleep && rinfo->is_mobility)
1196 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1197
1198 return rc;
1199}
1200
1201static void radeon_save_state (struct radeonfb_info *rinfo,
1202 struct radeon_regs *save)
1203{
1204 /* CRTC regs */
1205 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1206 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1207 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1208 save->dac_cntl = INREG(DAC_CNTL);
1209 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1210 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1211 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1212 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1213 save->crtc_pitch = INREG(CRTC_PITCH);
1214 save->surface_cntl = INREG(SURFACE_CNTL);
1215
1216 /* FP regs */
1217 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1218 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1219 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1220 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1221 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1222 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1223 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1224 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1225 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1226 save->tmds_crc = INREG(TMDS_CRC);
1227 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1228 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1229
1230 /* PLL regs */
1231 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1232 radeon_pll_errata_after_index(rinfo);
1233 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1234 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1235}
1236
1237
1238static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1239{
1240 int i;
1241
1242 radeon_fifo_wait(20);
1243
1244 /* Workaround from XFree */
1245 if (rinfo->is_mobility) {
1246 /* A temporal workaround for the occasional blanking on certain laptop
1247 * panels. This appears to related to the PLL divider registers
1248 * (fail to lock?). It occurs even when all dividers are the same
1249 * with their old settings. In this case we really don't need to
1250 * fiddle with PLL registers. By doing this we can avoid the blanking
1251 * problem with some panels.
1252 */
1253 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1254 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1255 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1256 /* We still have to force a switch to selected PPLL div thanks to
1257 * an XFree86 driver bug which will switch it away in some cases
1258 * even when using UseFDev */
1259 OUTREGP(CLOCK_CNTL_INDEX,
1260 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1261 ~PPLL_DIV_SEL_MASK);
1262 radeon_pll_errata_after_index(rinfo);
1263 radeon_pll_errata_after_data(rinfo);
1264 return;
1265 }
1266 }
1267
1268 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1269 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1270
1271 /* Reset PPLL & enable atomic update */
1272 OUTPLLP(PPLL_CNTL,
1273 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1274 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1275
1276 /* Switch to selected PPLL divider */
1277 OUTREGP(CLOCK_CNTL_INDEX,
1278 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1279 ~PPLL_DIV_SEL_MASK);
1280 radeon_pll_errata_after_index(rinfo);
1281 radeon_pll_errata_after_data(rinfo);
1282
1283 /* Set PPLL ref. div */
1284 if (IS_R300_VARIANT(rinfo) ||
1285 rinfo->family == CHIP_FAMILY_RS300 ||
1286 rinfo->family == CHIP_FAMILY_RS400 ||
1287 rinfo->family == CHIP_FAMILY_RS480) {
1288 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1289 /* When restoring console mode, use saved PPLL_REF_DIV
1290 * setting.
1291 */
1292 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1293 } else {
1294 /* R300 uses ref_div_acc field as real ref divider */
1295 OUTPLLP(PPLL_REF_DIV,
1296 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1297 ~R300_PPLL_REF_DIV_ACC_MASK);
1298 }
1299 } else
1300 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1301
1302 /* Set PPLL divider 3 & post divider*/
1303 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1304 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1305
1306 /* Write update */
1307 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1308 ;
1309 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1310
1311 /* Wait read update complete */
1312 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1313 the cause yet, but this workaround will mask the problem for now.
1314 Other chips usually will pass at the very first test, so the
1315 workaround shouldn't have any effect on them. */
1316 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1317 ;
1318
1319 OUTPLL(HTOTAL_CNTL, 0);
1320
1321 /* Clear reset & atomic update */
1322 OUTPLLP(PPLL_CNTL, 0,
1323 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1324
1325 /* We may want some locking ... oh well */
1326 radeon_msleep(5);
1327
1328 /* Switch back VCLK source to PPLL */
1329 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1330}
1331
1332/*
1333 * Timer function for delayed LVDS panel power up/down
1334 */
1335static void radeon_lvds_timer_func(unsigned long data)
1336{
1337 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1338
1339 radeon_engine_idle();
1340
1341 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1342}
1343
1344/*
1345 * Apply a video mode. This will apply the whole register set, including
1346 * the PLL registers, to the card
1347 */
1348void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1349 int regs_only)
1350{
1351 int i;
1352 int primary_mon = PRIMARY_MONITOR(rinfo);
1353
1354 if (nomodeset)
1355 return;
1356
1357 if (!regs_only)
1358 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1359
1360 radeon_fifo_wait(31);
1361 for (i=0; i<10; i++)
1362 OUTREG(common_regs[i].reg, common_regs[i].val);
1363
1364 /* Apply surface registers */
1365 for (i=0; i<8; i++) {
1366 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1367 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1368 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1369 }
1370
1371 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1372 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1373 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1374 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1375 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1376 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1377 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1378 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1379 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1380 OUTREG(CRTC_OFFSET, 0);
1381 OUTREG(CRTC_OFFSET_CNTL, 0);
1382 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1383 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1384
1385 radeon_write_pll_regs(rinfo, mode);
1386
1387 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1388 radeon_fifo_wait(10);
1389 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1390 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1391 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1392 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1393 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1394 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1395 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1396 OUTREG(TMDS_CRC, mode->tmds_crc);
1397 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1398 }
1399
1400 if (!regs_only)
1401 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1402
1403 radeon_fifo_wait(2);
1404 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1405
1406 return;
1407}
1408
1409/*
1410 * Calculate the PLL values for a given mode
1411 */
1412static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1413 unsigned long freq)
1414{
1415 const struct {
1416 int divider;
1417 int bitvalue;
1418 } *post_div,
1419 post_divs[] = {
1420 { 1, 0 },
1421 { 2, 1 },
1422 { 4, 2 },
1423 { 8, 3 },
1424 { 3, 4 },
1425 { 16, 5 },
1426 { 6, 6 },
1427 { 12, 7 },
1428 { 0, 0 },
1429 };
1430 int fb_div, pll_output_freq = 0;
1431 int uses_dvo = 0;
1432
1433 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1434 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1435 * recent than an r(v)100...
1436 */
1437#if 1
1438 /* XXX I had reports of flicker happening with the cinema display
1439 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1440 * this case. This could just be a bandwidth calculation issue, I
1441 * haven't implemented the bandwidth code yet, but in the meantime,
1442 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1443 * I haven't seen a case were were absolutely needed an odd PLL
1444 * divider. I'll find a better fix once I have more infos on the
1445 * real cause of the problem.
1446 */
1447 while (rinfo->has_CRTC2) {
1448 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1449 u32 disp_output_cntl;
1450 int source;
1451
1452 /* FP2 path not enabled */
1453 if ((fp2_gen_cntl & FP2_ON) == 0)
1454 break;
1455 /* Not all chip revs have the same format for this register,
1456 * extract the source selection
1457 */
1458 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1459 source = (fp2_gen_cntl >> 10) & 0x3;
1460 /* sourced from transform unit, check for transform unit
1461 * own source
1462 */
1463 if (source == 3) {
1464 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1465 source = (disp_output_cntl >> 12) & 0x3;
1466 }
1467 } else
1468 source = (fp2_gen_cntl >> 13) & 0x1;
1469 /* sourced from CRTC2 -> exit */
1470 if (source == 1)
1471 break;
1472
1473 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1474 uses_dvo = 1;
1475 break;
1476 }
1477#else
1478 uses_dvo = 1;
1479#endif
1480 if (freq > rinfo->pll.ppll_max)
1481 freq = rinfo->pll.ppll_max;
1482 if (freq*12 < rinfo->pll.ppll_min)
1483 freq = rinfo->pll.ppll_min / 12;
1484 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1485 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1486
1487 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1488 pll_output_freq = post_div->divider * freq;
1489 /* If we output to the DVO port (external TMDS), we don't allow an
1490 * odd PLL divider as those aren't supported on this path
1491 */
1492 if (uses_dvo && (post_div->divider & 1))
1493 continue;
1494 if (pll_output_freq >= rinfo->pll.ppll_min &&
1495 pll_output_freq <= rinfo->pll.ppll_max)
1496 break;
1497 }
1498
1499 /* If we fall through the bottom, try the "default value"
1500 given by the terminal post_div->bitvalue */
1501 if ( !post_div->divider ) {
1502 post_div = &post_divs[post_div->bitvalue];
1503 pll_output_freq = post_div->divider * freq;
1504 }
1505 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1506 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1507 pll_output_freq);
1508
1509 /* If we fall through the bottom, try the "default value"
1510 given by the terminal post_div->bitvalue */
1511 if ( !post_div->divider ) {
1512 post_div = &post_divs[post_div->bitvalue];
1513 pll_output_freq = post_div->divider * freq;
1514 }
1515 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1516 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1517 pll_output_freq);
1518
1519 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1520 rinfo->pll.ref_clk);
1521 regs->ppll_ref_div = rinfo->pll.ref_div;
1522 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1523
1524 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1525 pr_debug("fb_div = 0x%x\n", fb_div);
1526 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1527}
1528
1529static int radeonfb_set_par(struct fb_info *info)
1530{
1531 struct radeonfb_info *rinfo = info->par;
1532 struct fb_var_screeninfo *mode = &info->var;
1533 struct radeon_regs *newmode;
1534 int hTotal, vTotal, hSyncStart, hSyncEnd,
1535 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1536 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1537 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1538 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1539 int i, freq;
1540 int format = 0;
1541 int nopllcalc = 0;
1542 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1543 int primary_mon = PRIMARY_MONITOR(rinfo);
1544 int depth = var_to_depth(mode);
1545 int use_rmx = 0;
1546
1547 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1548 if (!newmode)
1549 return -ENOMEM;
1550
1551 /* We always want engine to be idle on a mode switch, even
1552 * if we won't actually change the mode
1553 */
1554 radeon_engine_idle();
1555
1556 hSyncStart = mode->xres + mode->right_margin;
1557 hSyncEnd = hSyncStart + mode->hsync_len;
1558 hTotal = hSyncEnd + mode->left_margin;
1559
1560 vSyncStart = mode->yres + mode->lower_margin;
1561 vSyncEnd = vSyncStart + mode->vsync_len;
1562 vTotal = vSyncEnd + mode->upper_margin;
1563 pixClock = mode->pixclock;
1564
1565 sync = mode->sync;
1566 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1567 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1568
1569 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1570 if (rinfo->panel_info.xres < mode->xres)
1571 mode->xres = rinfo->panel_info.xres;
1572 if (rinfo->panel_info.yres < mode->yres)
1573 mode->yres = rinfo->panel_info.yres;
1574
1575 hTotal = mode->xres + rinfo->panel_info.hblank;
1576 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1577 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1578
1579 vTotal = mode->yres + rinfo->panel_info.vblank;
1580 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1581 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1582
1583 h_sync_pol = !rinfo->panel_info.hAct_high;
1584 v_sync_pol = !rinfo->panel_info.vAct_high;
1585
1586 pixClock = 100000000 / rinfo->panel_info.clock;
1587
1588 if (rinfo->panel_info.use_bios_dividers) {
1589 nopllcalc = 1;
1590 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1591 (rinfo->panel_info.post_divider << 16);
1592 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1593 }
1594 }
1595 dotClock = 1000000000 / pixClock;
1596 freq = dotClock / 10; /* x100 */
1597
1598 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1599 hSyncStart, hSyncEnd, hTotal);
1600 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1601 vSyncStart, vSyncEnd, vTotal);
1602
1603 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1604 vsync_wid = vSyncEnd - vSyncStart;
1605 if (hsync_wid == 0)
1606 hsync_wid = 1;
1607 else if (hsync_wid > 0x3f) /* max */
1608 hsync_wid = 0x3f;
1609
1610 if (vsync_wid == 0)
1611 vsync_wid = 1;
1612 else if (vsync_wid > 0x1f) /* max */
1613 vsync_wid = 0x1f;
1614
1615 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1616 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1617
1618 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1619
1620 format = radeon_get_dstbpp(depth);
1621 bytpp = mode->bits_per_pixel >> 3;
1622
1623 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1624 hsync_fudge = hsync_fudge_fp[format-1];
1625 else
1626 hsync_fudge = hsync_adj_tab[format-1];
1627
1628 hsync_start = hSyncStart - 8 + hsync_fudge;
1629
1630 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1631 (format << 8);
1632
1633 /* Clear auto-center etc... */
1634 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1635 newmode->crtc_more_cntl &= 0xfffffff0;
1636
1637 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1638 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1639 if (mirror)
1640 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1641
1642 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1643 CRTC_INTERLACE_EN);
1644 } else {
1645 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1646 CRTC_CRT_ON;
1647 }
1648
1649 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1650 DAC_8BIT_EN;
1651
1652 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1653 (((mode->xres / 8) - 1) << 16));
1654
1655 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1656 (hsync_wid << 16) | (h_sync_pol << 23));
1657
1658 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1659 ((mode->yres - 1) << 16);
1660
1661 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1662 (vsync_wid << 16) | (v_sync_pol << 23));
1663
1664 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1665 /* We first calculate the engine pitch */
1666 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1667 & ~(0x3f)) >> 6;
1668
1669 /* Then, re-multiply it to get the CRTC pitch */
1670 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1671 } else
1672 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1673
1674 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1675
1676 /*
1677 * It looks like recent chips have a problem with SURFACE_CNTL,
1678 * setting SURF_TRANSLATION_DIS completely disables the
1679 * swapper as well, so we leave it unset now.
1680 */
1681 newmode->surface_cntl = 0;
1682
1683#if defined(__BIG_ENDIAN)
1684
1685 /* Setup swapping on both apertures, though we currently
1686 * only use aperture 0, enabling swapper on aperture 1
1687 * won't harm
1688 */
1689 switch (mode->bits_per_pixel) {
1690 case 16:
1691 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1692 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1693 break;
1694 case 24:
1695 case 32:
1696 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1697 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1698 break;
1699 }
1700#endif
1701
1702 /* Clear surface registers */
1703 for (i=0; i<8; i++) {
1704 newmode->surf_lower_bound[i] = 0;
1705 newmode->surf_upper_bound[i] = 0x1f;
1706 newmode->surf_info[i] = 0;
1707 }
1708
1709 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1710 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1711 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1712 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1713
1714 rinfo->bpp = mode->bits_per_pixel;
1715 rinfo->depth = depth;
1716
1717 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1718 pr_debug("freq = %lu\n", (unsigned long)freq);
1719
1720 /* We use PPLL_DIV_3 */
1721 newmode->clk_cntl_index = 0x300;
1722
1723 /* Calculate PPLL value if necessary */
1724 if (!nopllcalc)
1725 radeon_calc_pll_regs(rinfo, newmode, freq);
1726
1727 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1728
1729 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1730 unsigned int hRatio, vRatio;
1731
1732 if (mode->xres > rinfo->panel_info.xres)
1733 mode->xres = rinfo->panel_info.xres;
1734 if (mode->yres > rinfo->panel_info.yres)
1735 mode->yres = rinfo->panel_info.yres;
1736
1737 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1738 << HORZ_PANEL_SHIFT);
1739 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1740 << VERT_PANEL_SHIFT);
1741
1742 if (mode->xres != rinfo->panel_info.xres) {
1743 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1744 rinfo->panel_info.xres);
1745 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1746 (newmode->fp_horz_stretch &
1747 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1748 HORZ_AUTO_RATIO_INC)));
1749 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1750 HORZ_STRETCH_ENABLE);
1751 use_rmx = 1;
1752 }
1753 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1754
1755 if (mode->yres != rinfo->panel_info.yres) {
1756 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1757 rinfo->panel_info.yres);
1758 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1759 (newmode->fp_vert_stretch &
1760 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1761 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1762 VERT_STRETCH_ENABLE);
1763 use_rmx = 1;
1764 }
1765 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1766
1767 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1768 ~(FP_SEL_CRTC2 |
1769 FP_RMX_HVSYNC_CONTROL_EN |
1770 FP_DFP_SYNC_SEL |
1771 FP_CRT_SYNC_SEL |
1772 FP_CRTC_LOCK_8DOT |
1773 FP_USE_SHADOW_EN |
1774 FP_CRTC_USE_SHADOW_VEND |
1775 FP_CRT_SYNC_ALT));
1776
1777 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1778 FP_CRTC_DONT_SHADOW_HEND |
1779 FP_PANEL_FORMAT);
1780
1781 if (IS_R300_VARIANT(rinfo) ||
1782 (rinfo->family == CHIP_FAMILY_R200)) {
1783 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1784 if (use_rmx)
1785 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1786 else
1787 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1788 } else
1789 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1790
1791 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1792 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1793 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1794 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1795
1796 if (primary_mon == MT_LCD) {
1797 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1798 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1799 } else {
1800 /* DFP */
1801 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1802 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1803 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1804 if (IS_R300_VARIANT(rinfo) ||
1805 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1806 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1807 else
1808 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1809 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1810 }
1811
1812 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1813 (((mode->xres / 8) - 1) << 16));
1814 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1815 ((mode->yres - 1) << 16);
1816 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1817 (hsync_wid << 16) | (h_sync_pol << 23));
1818 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1819 (vsync_wid << 16) | (v_sync_pol << 23));
1820 }
1821
1822 /* do it! */
1823 if (!rinfo->asleep) {
1824 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1825 radeon_write_mode (rinfo, newmode, 0);
1826 /* (re)initialize the engine */
1827 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1828 radeonfb_engine_init (rinfo);
1829 }
1830 /* Update fix */
1831 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1832 info->fix.line_length = rinfo->pitch*64;
1833 else
1834 info->fix.line_length = mode->xres_virtual
1835 * ((mode->bits_per_pixel + 1) / 8);
1836 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1837 : FB_VISUAL_DIRECTCOLOR;
1838
1839#ifdef CONFIG_BOOTX_TEXT
1840 /* Update debug text engine */
1841 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1842 rinfo->depth, info->fix.line_length);
1843#endif
1844
1845 kfree(newmode);
1846 return 0;
1847}
1848
1849
1850static struct fb_ops radeonfb_ops = {
1851 .owner = THIS_MODULE,
1852 .fb_check_var = radeonfb_check_var,
1853 .fb_set_par = radeonfb_set_par,
1854 .fb_setcolreg = radeonfb_setcolreg,
1855 .fb_setcmap = radeonfb_setcmap,
1856 .fb_pan_display = radeonfb_pan_display,
1857 .fb_blank = radeonfb_blank,
1858 .fb_ioctl = radeonfb_ioctl,
1859 .fb_sync = radeonfb_sync,
1860 .fb_fillrect = radeonfb_fillrect,
1861 .fb_copyarea = radeonfb_copyarea,
1862 .fb_imageblit = radeonfb_imageblit,
1863};
1864
1865
1866static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
1867{
1868 struct fb_info *info = rinfo->info;
1869
1870 info->par = rinfo;
1871 info->pseudo_palette = rinfo->pseudo_palette;
1872 info->flags = FBINFO_DEFAULT
1873 | FBINFO_HWACCEL_COPYAREA
1874 | FBINFO_HWACCEL_FILLRECT
1875 | FBINFO_HWACCEL_XPAN
1876 | FBINFO_HWACCEL_YPAN;
1877 info->fbops = &radeonfb_ops;
1878 info->screen_base = rinfo->fb_base;
1879 info->screen_size = rinfo->mapped_vram;
1880 /* Fill fix common fields */
1881 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1882 info->fix.smem_start = rinfo->fb_base_phys;
1883 info->fix.smem_len = rinfo->video_ram;
1884 info->fix.type = FB_TYPE_PACKED_PIXELS;
1885 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1886 info->fix.xpanstep = 8;
1887 info->fix.ypanstep = 1;
1888 info->fix.ywrapstep = 0;
1889 info->fix.type_aux = 0;
1890 info->fix.mmio_start = rinfo->mmio_base_phys;
1891 info->fix.mmio_len = RADEON_REGSIZE;
1892 info->fix.accel = FB_ACCEL_ATI_RADEON;
1893
1894 fb_alloc_cmap(&info->cmap, 256, 0);
1895
1896 if (noaccel)
1897 info->flags |= FBINFO_HWACCEL_DISABLED;
1898
1899 return 0;
1900}
1901
1902/*
1903 * This reconfigure the card's internal memory map. In theory, we'd like
1904 * to setup the card's memory at the same address as it's PCI bus address,
1905 * and the AGP aperture right after that so that system RAM on 32 bits
1906 * machines at least, is directly accessible. However, doing so would
1907 * conflict with the current XFree drivers...
1908 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1909 * on the proper way to set this up and duplicate this here. In the meantime,
1910 * I put the card's memory at 0 in card space and AGP at some random high
1911 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1912 */
1913#ifdef CONFIG_PPC_OF
1914#undef SET_MC_FB_FROM_APERTURE
1915static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1916{
1917 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1918 u32 save_crtc_ext_cntl;
1919 u32 aper_base, aper_size;
1920 u32 agp_base;
1921
1922 /* First, we disable display to avoid interfering */
1923 if (rinfo->has_CRTC2) {
1924 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1925 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1926 }
1927 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1928 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1929
1930 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1931 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1932 mdelay(100);
1933
1934 aper_base = INREG(CNFG_APER_0_BASE);
1935 aper_size = INREG(CNFG_APER_SIZE);
1936
1937#ifdef SET_MC_FB_FROM_APERTURE
1938 /* Set framebuffer to be at the same address as set in PCI BAR */
1939 OUTREG(MC_FB_LOCATION,
1940 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1941 rinfo->fb_local_base = aper_base;
1942#else
1943 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1944 rinfo->fb_local_base = 0;
1945#endif
1946 agp_base = aper_base + aper_size;
1947 if (agp_base & 0xf0000000)
1948 agp_base = (aper_base | 0x0fffffff) + 1;
1949
1950 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1951 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1952 * always the case on PPCs afaik.
1953 */
1954#ifdef SET_MC_FB_FROM_APERTURE
1955 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1956#else
1957 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1958#endif
1959
1960 /* Fixup the display base addresses & engine offsets while we
1961 * are at it as well
1962 */
1963#ifdef SET_MC_FB_FROM_APERTURE
1964 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1965 if (rinfo->has_CRTC2)
1966 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1967 OUTREG(OV0_BASE_ADDR, aper_base);
1968#else
1969 OUTREG(DISPLAY_BASE_ADDR, 0);
1970 if (rinfo->has_CRTC2)
1971 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1972 OUTREG(OV0_BASE_ADDR, 0);
1973#endif
1974 mdelay(100);
1975
1976 /* Restore display settings */
1977 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1978 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1979 if (rinfo->has_CRTC2)
1980 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1981
1982 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1983 aper_base,
1984 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1985 0xffff0000 | (agp_base >> 16));
1986}
1987#endif /* CONFIG_PPC_OF */
1988
1989
1990static void radeon_identify_vram(struct radeonfb_info *rinfo)
1991{
1992 u32 tmp;
1993
1994 /* framebuffer size */
1995 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1996 (rinfo->family == CHIP_FAMILY_RS200) ||
1997 (rinfo->family == CHIP_FAMILY_RS300) ||
1998 (rinfo->family == CHIP_FAMILY_RC410) ||
1999 (rinfo->family == CHIP_FAMILY_RS400) ||
2000 (rinfo->family == CHIP_FAMILY_RS480) ) {
2001 u32 tom = INREG(NB_TOM);
2002 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2003
2004 radeon_fifo_wait(6);
2005 OUTREG(MC_FB_LOCATION, tom);
2006 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2007 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2008 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2009
2010 /* This is supposed to fix the crtc2 noise problem. */
2011 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2012
2013 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2014 (rinfo->family == CHIP_FAMILY_RS200)) {
2015 /* This is to workaround the asic bug for RMX, some versions
2016 of BIOS doesn't have this register initialized correctly.
2017 */
2018 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2019 ~CRTC_H_CUTOFF_ACTIVE_EN);
2020 }
2021 } else {
2022 tmp = INREG(CNFG_MEMSIZE);
2023 }
2024
2025 /* mem size is bits [28:0], mask off the rest */
2026 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2027
2028 /*
2029 * Hack to get around some busted production M6's
2030 * reporting no ram
2031 */
2032 if (rinfo->video_ram == 0) {
2033 switch (rinfo->pdev->device) {
2034 case PCI_CHIP_RADEON_LY:
2035 case PCI_CHIP_RADEON_LZ:
2036 rinfo->video_ram = 8192 * 1024;
2037 break;
2038 default:
2039 break;
2040 }
2041 }
2042
2043
2044 /*
2045 * Now try to identify VRAM type
2046 */
2047 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2048 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2049 rinfo->vram_ddr = 1;
2050 else
2051 rinfo->vram_ddr = 0;
2052
2053 tmp = INREG(MEM_CNTL);
2054 if (IS_R300_VARIANT(rinfo)) {
2055 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2056 switch (tmp) {
2057 case 0: rinfo->vram_width = 64; break;
2058 case 1: rinfo->vram_width = 128; break;
2059 case 2: rinfo->vram_width = 256; break;
2060 default: rinfo->vram_width = 128; break;
2061 }
2062 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2063 (rinfo->family == CHIP_FAMILY_RS100) ||
2064 (rinfo->family == CHIP_FAMILY_RS200)){
2065 if (tmp & RV100_MEM_HALF_MODE)
2066 rinfo->vram_width = 32;
2067 else
2068 rinfo->vram_width = 64;
2069 } else {
2070 if (tmp & MEM_NUM_CHANNELS_MASK)
2071 rinfo->vram_width = 128;
2072 else
2073 rinfo->vram_width = 64;
2074 }
2075
2076 /* This may not be correct, as some cards can have half of channel disabled
2077 * ToDo: identify these cases
2078 */
2079
2080 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2081 pci_name(rinfo->pdev),
2082 rinfo->video_ram / 1024,
2083 rinfo->vram_ddr ? "DDR" : "SDRAM",
2084 rinfo->vram_width);
2085}
2086
2087/*
2088 * Sysfs
2089 */
2090
2091static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2092{
2093 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
2094}
2095
2096
2097static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
2098 struct bin_attribute *bin_attr,
2099 char *buf, loff_t off, size_t count)
2100{
2101 struct device *dev = container_of(kobj, struct device, kobj);
2102 struct pci_dev *pdev = to_pci_dev(dev);
2103 struct fb_info *info = pci_get_drvdata(pdev);
2104 struct radeonfb_info *rinfo = info->par;
2105
2106 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2107}
2108
2109
2110static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
2111 struct bin_attribute *bin_attr,
2112 char *buf, loff_t off, size_t count)
2113{
2114 struct device *dev = container_of(kobj, struct device, kobj);
2115 struct pci_dev *pdev = to_pci_dev(dev);
2116 struct fb_info *info = pci_get_drvdata(pdev);
2117 struct radeonfb_info *rinfo = info->par;
2118
2119 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2120}
2121
2122static struct bin_attribute edid1_attr = {
2123 .attr = {
2124 .name = "edid1",
2125 .mode = 0444,
2126 },
2127 .size = EDID_LENGTH,
2128 .read = radeon_show_edid1,
2129};
2130
2131static struct bin_attribute edid2_attr = {
2132 .attr = {
2133 .name = "edid2",
2134 .mode = 0444,
2135 },
2136 .size = EDID_LENGTH,
2137 .read = radeon_show_edid2,
2138};
2139
2140
2141static int radeonfb_pci_register(struct pci_dev *pdev,
2142 const struct pci_device_id *ent)
2143{
2144 struct fb_info *info;
2145 struct radeonfb_info *rinfo;
2146 int ret;
2147 unsigned char c1, c2;
2148 int err = 0;
2149
2150 pr_debug("radeonfb_pci_register BEGIN\n");
2151
2152 /* Enable device in PCI config */
2153 ret = pci_enable_device(pdev);
2154 if (ret < 0) {
2155 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2156 pci_name(pdev));
2157 goto err_out;
2158 }
2159
2160 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2161 if (!info) {
2162 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2163 pci_name(pdev));
2164 ret = -ENOMEM;
2165 goto err_disable;
2166 }
2167 rinfo = info->par;
2168 rinfo->info = info;
2169 rinfo->pdev = pdev;
2170
2171 spin_lock_init(&rinfo->reg_lock);
2172 init_timer(&rinfo->lvds_timer);
2173 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2174 rinfo->lvds_timer.data = (unsigned long)rinfo;
2175
2176 c1 = ent->device >> 8;
2177 c2 = ent->device & 0xff;
2178 if (isprint(c1) && isprint(c2))
2179 snprintf(rinfo->name, sizeof(rinfo->name),
2180 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2181 else
2182 snprintf(rinfo->name, sizeof(rinfo->name),
2183 "ATI Radeon %x", ent->device & 0xffff);
2184
2185 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2186 rinfo->chipset = pdev->device;
2187 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2188 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2189 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2190
2191 /* Set base addrs */
2192 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2193 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2194
2195 /* request the mem regions */
2196 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2197 if (ret < 0) {
2198 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2199 pci_name(rinfo->pdev));
2200 goto err_release_fb;
2201 }
2202
2203 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2204 if (ret < 0) {
2205 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2206 pci_name(rinfo->pdev));
2207 goto err_release_pci0;
2208 }
2209
2210 /* map the regions */
2211 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2212 if (!rinfo->mmio_base) {
2213 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2214 pci_name(rinfo->pdev));
2215 ret = -EIO;
2216 goto err_release_pci2;
2217 }
2218
2219 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2220
2221 /*
2222 * Check for errata
2223 */
2224 rinfo->errata = 0;
2225 if (rinfo->family == CHIP_FAMILY_R300 &&
2226 (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
2227 == CFG_ATI_REV_A11)
2228 rinfo->errata |= CHIP_ERRATA_R300_CG;
2229
2230 if (rinfo->family == CHIP_FAMILY_RV200 ||
2231 rinfo->family == CHIP_FAMILY_RS200)
2232 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2233
2234 if (rinfo->family == CHIP_FAMILY_RV100 ||
2235 rinfo->family == CHIP_FAMILY_RS100 ||
2236 rinfo->family == CHIP_FAMILY_RS200)
2237 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2238
2239#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2240 /* On PPC, we obtain the OF device-node pointer to the firmware
2241 * data for this chip
2242 */
2243 rinfo->of_node = pci_device_to_OF_node(pdev);
2244 if (rinfo->of_node == NULL)
2245 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2246 pci_name(rinfo->pdev));
2247
2248#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2249#ifdef CONFIG_PPC_OF
2250 /* On PPC, the firmware sets up a memory mapping that tends
2251 * to cause lockups when enabling the engine. We reconfigure
2252 * the card internal memory mappings properly
2253 */
2254 fixup_memory_mappings(rinfo);
2255#endif /* CONFIG_PPC_OF */
2256
2257 /* Get VRAM size and type */
2258 radeon_identify_vram(rinfo);
2259
2260 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2261
2262 do {
2263 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2264 rinfo->mapped_vram);
2265 } while (rinfo->fb_base == NULL &&
2266 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2267
2268 if (rinfo->fb_base == NULL) {
2269 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2270 pci_name(rinfo->pdev));
2271 ret = -EIO;
2272 goto err_unmap_rom;
2273 }
2274
2275 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2276 rinfo->mapped_vram/1024);
2277
2278 /*
2279 * Map the BIOS ROM if any and retrieve PLL parameters from
2280 * the BIOS. We skip that on mobility chips as the real panel
2281 * values we need aren't in the ROM but in the BIOS image in
2282 * memory. This is definitely not the best meacnism though,
2283 * we really need the arch code to tell us which is the "primary"
2284 * video adapter to use the memory image (or better, the arch
2285 * should provide us a copy of the BIOS image to shield us from
2286 * archs who would store that elsewhere and/or could initialize
2287 * more than one adapter during boot).
2288 */
2289 if (!rinfo->is_mobility)
2290 radeon_map_ROM(rinfo, pdev);
2291
2292 /*
2293 * On x86, the primary display on laptop may have it's BIOS
2294 * ROM elsewhere, try to locate it at the legacy memory hole.
2295 * We probably need to make sure this is the primary display,
2296 * but that is difficult without some arch support.
2297 */
2298#ifdef CONFIG_X86
2299 if (rinfo->bios_seg == NULL)
2300 radeon_find_mem_vbios(rinfo);
2301#endif
2302
2303 /* If both above failed, try the BIOS ROM again for mobility
2304 * chips
2305 */
2306 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2307 radeon_map_ROM(rinfo, pdev);
2308
2309 /* Get informations about the board's PLL */
2310 radeon_get_pllinfo(rinfo);
2311
2312#ifdef CONFIG_FB_RADEON_I2C
2313 /* Register I2C bus */
2314 radeon_create_i2c_busses(rinfo);
2315#endif
2316
2317 /* set all the vital stuff */
2318 radeon_set_fbinfo (rinfo);
2319
2320 /* Probe screen types */
2321 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2322
2323 /* Build mode list, check out panel native model */
2324 radeon_check_modes(rinfo, mode_option);
2325
2326 /* Register some sysfs stuff (should be done better) */
2327 if (rinfo->mon1_EDID)
2328 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2329 &edid1_attr);
2330 if (rinfo->mon2_EDID)
2331 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2332 &edid2_attr);
2333 if (err)
2334 pr_warning("%s() Creating sysfs files failed, continuing\n",
2335 __func__);
2336
2337 /* save current mode regs before we switch into the new one
2338 * so we can restore this upon __exit
2339 */
2340 radeon_save_state (rinfo, &rinfo->init_state);
2341 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2342
2343 /* Setup Power Management capabilities */
2344 if (default_dynclk < -1) {
2345 /* -2 is special: means ON on mobility chips and do not
2346 * change on others
2347 */
2348 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2349 } else
2350 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2351
2352 pci_set_drvdata(pdev, info);
2353
2354 /* Register with fbdev layer */
2355 ret = register_framebuffer(info);
2356 if (ret < 0) {
2357 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2358 pci_name(rinfo->pdev));
2359 goto err_unmap_fb;
2360 }
2361
2362#ifdef CONFIG_MTRR
2363 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2364 rinfo->video_ram,
2365 MTRR_TYPE_WRCOMB, 1);
2366#endif
2367
2368 if (backlight)
2369 radeonfb_bl_init(rinfo);
2370
2371 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2372
2373 if (rinfo->bios_seg)
2374 radeon_unmap_ROM(rinfo, pdev);
2375 pr_debug("radeonfb_pci_register END\n");
2376
2377 return 0;
2378err_unmap_fb:
2379 iounmap(rinfo->fb_base);
2380err_unmap_rom:
2381 kfree(rinfo->mon1_EDID);
2382 kfree(rinfo->mon2_EDID);
2383 if (rinfo->mon1_modedb)
2384 fb_destroy_modedb(rinfo->mon1_modedb);
2385 fb_dealloc_cmap(&info->cmap);
2386#ifdef CONFIG_FB_RADEON_I2C
2387 radeon_delete_i2c_busses(rinfo);
2388#endif
2389 if (rinfo->bios_seg)
2390 radeon_unmap_ROM(rinfo, pdev);
2391 iounmap(rinfo->mmio_base);
2392err_release_pci2:
2393 pci_release_region(pdev, 2);
2394err_release_pci0:
2395 pci_release_region(pdev, 0);
2396err_release_fb:
2397 framebuffer_release(info);
2398err_disable:
2399err_out:
2400 return ret;
2401}
2402
2403
2404
2405static void radeonfb_pci_unregister(struct pci_dev *pdev)
2406{
2407 struct fb_info *info = pci_get_drvdata(pdev);
2408 struct radeonfb_info *rinfo = info->par;
2409
2410 if (!rinfo)
2411 return;
2412
2413 radeonfb_pm_exit(rinfo);
2414
2415 if (rinfo->mon1_EDID)
2416 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2417 if (rinfo->mon2_EDID)
2418 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2419
2420#if 0
2421 /* restore original state
2422 *
2423 * Doesn't quite work yet, I suspect if we come from a legacy
2424 * VGA mode (or worse, text mode), we need to do some VGA black
2425 * magic here that I know nothing about. --BenH
2426 */
2427 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2428 #endif
2429
2430 del_timer_sync(&rinfo->lvds_timer);
2431
2432#ifdef CONFIG_MTRR
2433 if (rinfo->mtrr_hdl >= 0)
2434 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2435#endif
2436
2437 unregister_framebuffer(info);
2438
2439 radeonfb_bl_exit(rinfo);
2440
2441 iounmap(rinfo->mmio_base);
2442 iounmap(rinfo->fb_base);
2443
2444 pci_release_region(pdev, 2);
2445 pci_release_region(pdev, 0);
2446
2447 kfree(rinfo->mon1_EDID);
2448 kfree(rinfo->mon2_EDID);
2449 if (rinfo->mon1_modedb)
2450 fb_destroy_modedb(rinfo->mon1_modedb);
2451#ifdef CONFIG_FB_RADEON_I2C
2452 radeon_delete_i2c_busses(rinfo);
2453#endif
2454 fb_dealloc_cmap(&info->cmap);
2455 framebuffer_release(info);
2456}
2457
2458
2459static struct pci_driver radeonfb_driver = {
2460 .name = "radeonfb",
2461 .id_table = radeonfb_pci_table,
2462 .probe = radeonfb_pci_register,
2463 .remove = radeonfb_pci_unregister,
2464#ifdef CONFIG_PM
2465 .suspend = radeonfb_pci_suspend,
2466 .resume = radeonfb_pci_resume,
2467#endif /* CONFIG_PM */
2468};
2469
2470#ifndef MODULE
2471static int __init radeonfb_setup (char *options)
2472{
2473 char *this_opt;
2474
2475 if (!options || !*options)
2476 return 0;
2477
2478 while ((this_opt = strsep (&options, ",")) != NULL) {
2479 if (!*this_opt)
2480 continue;
2481
2482 if (!strncmp(this_opt, "noaccel", 7)) {
2483 noaccel = 1;
2484 } else if (!strncmp(this_opt, "mirror", 6)) {
2485 mirror = 1;
2486 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2487 force_dfp = 1;
2488 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2489 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2490 } else if (!strncmp(this_opt, "backlight:", 10)) {
2491 backlight = simple_strtoul(this_opt+10, NULL, 0);
2492#ifdef CONFIG_MTRR
2493 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2494 nomtrr = 1;
2495#endif
2496 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2497 nomodeset = 1;
2498 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2499 force_measure_pll = 1;
2500 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2501 ignore_edid = 1;
2502#if defined(CONFIG_PM) && defined(CONFIG_X86)
2503 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2504 force_sleep = 1;
2505 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2506 ignore_devlist = 1;
2507#endif
2508 } else
2509 mode_option = this_opt;
2510 }
2511 return 0;
2512}
2513#endif /* MODULE */
2514
2515static int __init radeonfb_init (void)
2516{
2517#ifndef MODULE
2518 char *option = NULL;
2519
2520 if (fb_get_options("radeonfb", &option))
2521 return -ENODEV;
2522 radeonfb_setup(option);
2523#endif
2524 return pci_register_driver (&radeonfb_driver);
2525}
2526
2527
2528static void __exit radeonfb_exit (void)
2529{
2530 pci_unregister_driver (&radeonfb_driver);
2531}
2532
2533module_init(radeonfb_init);
2534module_exit(radeonfb_exit);
2535
2536MODULE_AUTHOR("Ani Joshi");
2537MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2538MODULE_LICENSE("GPL");
2539module_param(noaccel, bool, 0);
2540module_param(default_dynclk, int, 0);
2541MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2542MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2543module_param(nomodeset, bool, 0);
2544MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2545module_param(mirror, bool, 0);
2546MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2547module_param(force_dfp, bool, 0);
2548MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2549module_param(ignore_edid, bool, 0);
2550MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2551module_param(monitor_layout, charp, 0);
2552MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2553module_param(force_measure_pll, bool, 0);
2554MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2555#ifdef CONFIG_MTRR
2556module_param(nomtrr, bool, 0);
2557MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2558#endif
2559module_param(panel_yres, int, 0);
2560MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2561module_param(mode_option, charp, 0);
2562MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2563#if defined(CONFIG_PM) && defined(CONFIG_X86)
2564module_param(force_sleep, bool, 0);
2565MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2566module_param(ignore_devlist, bool, 0);
2567MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2568#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 20:35:43 -0500