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path: root/drivers/video/cirrusfb.c
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Diffstat (limited to 'drivers/video/cirrusfb.c')
-rw-r--r--drivers/video/cirrusfb.c70
1 files changed, 16 insertions, 54 deletions
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c
index e9a2661669eb..620327436082 100644
--- a/drivers/video/cirrusfb.c
+++ b/drivers/video/cirrusfb.c
@@ -146,7 +146,7 @@ static const struct cirrusfb_board_info_rec {
146 .sr07 = 0xF0, 146 .sr07 = 0xF0,
147 .sr07_1bpp = 0xF0, 147 .sr07_1bpp = 0xF0,
148 .sr07_8bpp = 0xF1, 148 .sr07_8bpp = 0xF1,
149 .sr1f = 0x20 149 .sr1f = 0x1E
150 }, 150 },
151 [BT_PICCOLO] = { 151 [BT_PICCOLO] = {
152 .name = "CL Piccolo", 152 .name = "CL Piccolo",
@@ -482,6 +482,7 @@ static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
482 if (var->bits_per_pixel == 8) { 482 if (var->bits_per_pixel == 8) {
483 switch (cinfo->btype) { 483 switch (cinfo->btype) {
484 case BT_ALPINE: 484 case BT_ALPINE:
485 case BT_SD64:
485 case BT_PICASSO4: 486 case BT_PICASSO4:
486 if (freq > 85500) 487 if (freq > 85500)
487 cinfo->multiplexing = 1; 488 cinfo->multiplexing = 1;
@@ -492,10 +493,7 @@ static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
492 break; 493 break;
493 494
494 default: 495 default:
495 dev_err(info->device, 496 break;
496 "Frequency greater than maxclock (%ld kHz)\n",
497 maxclock);
498 return -EINVAL;
499 } 497 }
500 } 498 }
501#if 0 499#if 0
@@ -847,7 +845,8 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
847 /* formula: VClk = (OSC * N) / (D * (1+P)) */ 845 /* formula: VClk = (OSC * N) / (D * (1+P)) */
848 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */ 846 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
849 847
850 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4) { 848 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
849 cinfo->btype == BT_SD64) {
851 /* if freq is close to mclk or mclk/2 select mclk 850 /* if freq is close to mclk or mclk/2 select mclk
852 * as clock source 851 * as clock source
853 */ 852 */
@@ -966,30 +965,19 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
966 965
967 /* Extended Sequencer Mode */ 966 /* Extended Sequencer Mode */
968 switch (cinfo->btype) { 967 switch (cinfo->btype) {
969 case BT_SD64:
970 /* setting the SEQRF on SD64 is not necessary
971 * (only during init)
972 */
973 /* MCLK select */
974 vga_wseq(regbase, CL_SEQR1F, 0x1a);
975 break;
976 968
977 case BT_PICCOLO: 969 case BT_PICCOLO:
978 case BT_SPECTRUM: 970 case BT_SPECTRUM:
979 /* ### ueberall 0x22? */
980 /* ##vorher 1c MCLK select */
981 vga_wseq(regbase, CL_SEQR1F, 0x22);
982 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */ 971 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
983 vga_wseq(regbase, CL_SEQRF, 0xb0); 972 vga_wseq(regbase, CL_SEQRF, 0xb0);
984 break; 973 break;
985 974
986 case BT_PICASSO: 975 case BT_PICASSO:
987 /* ##vorher 22 MCLK select */
988 vga_wseq(regbase, CL_SEQR1F, 0x22);
989 /* ## vorher d0 avoid FIFO underruns..? */ 976 /* ## vorher d0 avoid FIFO underruns..? */
990 vga_wseq(regbase, CL_SEQRF, 0xd0); 977 vga_wseq(regbase, CL_SEQRF, 0xd0);
991 break; 978 break;
992 979
980 case BT_SD64:
993 case BT_PICASSO4: 981 case BT_PICASSO4:
994 case BT_ALPINE: 982 case BT_ALPINE:
995 case BT_GD5480: 983 case BT_GD5480:
@@ -1051,16 +1039,9 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
1051 } 1039 }
1052 1040
1053 switch (cinfo->btype) { 1041 switch (cinfo->btype) {
1054 case BT_SD64:
1055 /* MCLK select */
1056 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1057 break;
1058
1059 case BT_PICCOLO: 1042 case BT_PICCOLO:
1060 case BT_PICASSO: 1043 case BT_PICASSO:
1061 case BT_SPECTRUM: 1044 case BT_SPECTRUM:
1062 /* ### vorher 1c MCLK select */
1063 vga_wseq(regbase, CL_SEQR1F, 0x22);
1064 /* Fast Page-Mode writes */ 1045 /* Fast Page-Mode writes */
1065 vga_wseq(regbase, CL_SEQRF, 0xb0); 1046 vga_wseq(regbase, CL_SEQRF, 0xb0);
1066 break; 1047 break;
@@ -1074,6 +1055,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
1074 /* We already set SRF and SR1F */ 1055 /* We already set SRF and SR1F */
1075 break; 1056 break;
1076 1057
1058 case BT_SD64:
1077 case BT_GD5480: 1059 case BT_GD5480:
1078 case BT_LAGUNA: 1060 case BT_LAGUNA:
1079 case BT_LAGUNAB: 1061 case BT_LAGUNAB:
@@ -1104,32 +1086,23 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
1104 else if (var->bits_per_pixel == 16) { 1086 else if (var->bits_per_pixel == 16) {
1105 dev_dbg(info->device, "preparing for 16 bit deep display\n"); 1087 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1106 switch (cinfo->btype) { 1088 switch (cinfo->btype) {
1107 case BT_SD64:
1108 /* Extended Sequencer Mode: 256c col. mode */
1109 vga_wseq(regbase, CL_SEQR7, 0xf7);
1110 /* MCLK select */
1111 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1112 break;
1113
1114 case BT_PICCOLO: 1089 case BT_PICCOLO:
1115 case BT_SPECTRUM: 1090 case BT_SPECTRUM:
1116 vga_wseq(regbase, CL_SEQR7, 0x87); 1091 vga_wseq(regbase, CL_SEQR7, 0x87);
1117 /* Fast Page-Mode writes */ 1092 /* Fast Page-Mode writes */
1118 vga_wseq(regbase, CL_SEQRF, 0xb0); 1093 vga_wseq(regbase, CL_SEQRF, 0xb0);
1119 /* MCLK select */
1120 vga_wseq(regbase, CL_SEQR1F, 0x22);
1121 break; 1094 break;
1122 1095
1123 case BT_PICASSO: 1096 case BT_PICASSO:
1124 vga_wseq(regbase, CL_SEQR7, 0x27); 1097 vga_wseq(regbase, CL_SEQR7, 0x27);
1125 /* Fast Page-Mode writes */ 1098 /* Fast Page-Mode writes */
1126 vga_wseq(regbase, CL_SEQRF, 0xb0); 1099 vga_wseq(regbase, CL_SEQRF, 0xb0);
1127 /* MCLK select */
1128 vga_wseq(regbase, CL_SEQR1F, 0x22);
1129 break; 1100 break;
1130 1101
1102 case BT_SD64:
1131 case BT_PICASSO4: 1103 case BT_PICASSO4:
1132 case BT_ALPINE: 1104 case BT_ALPINE:
1105 /* Extended Sequencer Mode: 256c col. mode */
1133 vga_wseq(regbase, CL_SEQR7, 0xa7); 1106 vga_wseq(regbase, CL_SEQR7, 0xa7);
1134 break; 1107 break;
1135 1108
@@ -1171,32 +1144,23 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
1171 else if (var->bits_per_pixel == 24) { 1144 else if (var->bits_per_pixel == 24) {
1172 dev_dbg(info->device, "preparing for 24 bit deep display\n"); 1145 dev_dbg(info->device, "preparing for 24 bit deep display\n");
1173 switch (cinfo->btype) { 1146 switch (cinfo->btype) {
1174 case BT_SD64:
1175 /* Extended Sequencer Mode: 256c col. mode */
1176 vga_wseq(regbase, CL_SEQR7, 0xf5);
1177 /* MCLK select */
1178 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1179 break;
1180
1181 case BT_PICCOLO: 1147 case BT_PICCOLO:
1182 case BT_SPECTRUM: 1148 case BT_SPECTRUM:
1183 vga_wseq(regbase, CL_SEQR7, 0x85); 1149 vga_wseq(regbase, CL_SEQR7, 0x85);
1184 /* Fast Page-Mode writes */ 1150 /* Fast Page-Mode writes */
1185 vga_wseq(regbase, CL_SEQRF, 0xb0); 1151 vga_wseq(regbase, CL_SEQRF, 0xb0);
1186 /* MCLK select */
1187 vga_wseq(regbase, CL_SEQR1F, 0x22);
1188 break; 1152 break;
1189 1153
1190 case BT_PICASSO: 1154 case BT_PICASSO:
1191 vga_wseq(regbase, CL_SEQR7, 0x25); 1155 vga_wseq(regbase, CL_SEQR7, 0x25);
1192 /* Fast Page-Mode writes */ 1156 /* Fast Page-Mode writes */
1193 vga_wseq(regbase, CL_SEQRF, 0xb0); 1157 vga_wseq(regbase, CL_SEQRF, 0xb0);
1194 /* MCLK select */
1195 vga_wseq(regbase, CL_SEQR1F, 0x22);
1196 break; 1158 break;
1197 1159
1160 case BT_SD64:
1198 case BT_PICASSO4: 1161 case BT_PICASSO4:
1199 case BT_ALPINE: 1162 case BT_ALPINE:
1163 /* Extended Sequencer Mode: 256c col. mode */
1200 vga_wseq(regbase, CL_SEQR7, 0xa5); 1164 vga_wseq(regbase, CL_SEQR7, 0xa5);
1201 break; 1165 break;
1202 1166
@@ -1353,9 +1317,6 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1353 unsigned char tmp, xpix; 1317 unsigned char tmp, xpix;
1354 struct cirrusfb_info *cinfo = info->par; 1318 struct cirrusfb_info *cinfo = info->par;
1355 1319
1356 dev_dbg(info->device,
1357 "virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1358
1359 /* no range checks for xoffset and yoffset, */ 1320 /* no range checks for xoffset and yoffset, */
1360 /* as fb_pan_display has already done this */ 1321 /* as fb_pan_display has already done this */
1361 if (var->vmode & FB_VMODE_YWRAP) 1322 if (var->vmode & FB_VMODE_YWRAP)
@@ -1607,10 +1568,6 @@ static void init_vgachip(struct fb_info *info)
1607 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02); 1568 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1608 } 1569 }
1609 1570
1610 /* MCLK select etc. */
1611 if (bi->init_sr1f)
1612 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1613
1614 /* Screen A preset row scan: none */ 1571 /* Screen A preset row scan: none */
1615 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); 1572 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1616 /* Text cursor start: disable text cursor */ 1573 /* Text cursor start: disable text cursor */
@@ -2346,6 +2303,11 @@ static int __devinit cirrusfb_zorro_register(struct zorro_dev *z,
2346 2303
2347 zorro_set_drvdata(z, info); 2304 zorro_set_drvdata(z, info);
2348 2305
2306 /* MCLK select etc. */
2307 if (cirrusfb_board_info[btype].init_sr1f)
2308 vga_wseq(cinfo->regbase, CL_SEQR1F,
2309 cirrusfb_board_info[btype].sr1f);
2310
2349 ret = cirrusfb_register(info); 2311 ret = cirrusfb_register(info);
2350 if (!ret) 2312 if (!ret)
2351 return 0; 2313 return 0;