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Diffstat (limited to 'drivers/video/cirrusfb.c')
-rw-r--r--drivers/video/cirrusfb.c69
1 files changed, 30 insertions, 39 deletions
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c
index 2c4bc6205738..8269d704ab2a 100644
--- a/drivers/video/cirrusfb.c
+++ b/drivers/video/cirrusfb.c
@@ -98,15 +98,6 @@
98#define assert(expr) 98#define assert(expr)
99#endif 99#endif
100 100
101#ifdef TRUE
102#undef TRUE
103#endif
104#ifdef FALSE
105#undef FALSE
106#endif
107#define TRUE 1
108#define FALSE 0
109
110#define MB_ (1024*1024) 101#define MB_ (1024*1024)
111#define KB_ (1024) 102#define KB_ (1024)
112 103
@@ -146,9 +137,9 @@ static const struct cirrusfb_board_info_rec {
146 char *name; /* ASCII name of chipset */ 137 char *name; /* ASCII name of chipset */
147 long maxclock[5]; /* maximum video clock */ 138 long maxclock[5]; /* maximum video clock */
148 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */ 139 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
149 unsigned init_sr07 : 1; /* init SR07 during init_vgachip() */ 140 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
150 unsigned init_sr1f : 1; /* write SR1F during init_vgachip() */ 141 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
151 unsigned scrn_start_bit19 : 1; /* construct bit 19 of screen start address */ 142 bool scrn_start_bit19 : 1; /* construct bit 19 of screen start address */
152 143
153 /* initial SR07 value, then for each mode */ 144 /* initial SR07 value, then for each mode */
154 unsigned char sr07; 145 unsigned char sr07;
@@ -166,9 +157,9 @@ static const struct cirrusfb_board_info_rec {
166 /* the SD64/P4 have a higher max. videoclock */ 157 /* the SD64/P4 have a higher max. videoclock */
167 140000, 140000, 140000, 140000, 140000, 158 140000, 140000, 140000, 140000, 140000,
168 }, 159 },
169 .init_sr07 = TRUE, 160 .init_sr07 = true,
170 .init_sr1f = TRUE, 161 .init_sr1f = true,
171 .scrn_start_bit19 = TRUE, 162 .scrn_start_bit19 = true,
172 .sr07 = 0xF0, 163 .sr07 = 0xF0,
173 .sr07_1bpp = 0xF0, 164 .sr07_1bpp = 0xF0,
174 .sr07_8bpp = 0xF1, 165 .sr07_8bpp = 0xF1,
@@ -180,9 +171,9 @@ static const struct cirrusfb_board_info_rec {
180 /* guess */ 171 /* guess */
181 90000, 90000, 90000, 90000, 90000 172 90000, 90000, 90000, 90000, 90000
182 }, 173 },
183 .init_sr07 = TRUE, 174 .init_sr07 = true,
184 .init_sr1f = TRUE, 175 .init_sr1f = true,
185 .scrn_start_bit19 = FALSE, 176 .scrn_start_bit19 = false,
186 .sr07 = 0x80, 177 .sr07 = 0x80,
187 .sr07_1bpp = 0x80, 178 .sr07_1bpp = 0x80,
188 .sr07_8bpp = 0x81, 179 .sr07_8bpp = 0x81,
@@ -194,9 +185,9 @@ static const struct cirrusfb_board_info_rec {
194 /* guess */ 185 /* guess */
195 90000, 90000, 90000, 90000, 90000 186 90000, 90000, 90000, 90000, 90000
196 }, 187 },
197 .init_sr07 = TRUE, 188 .init_sr07 = true,
198 .init_sr1f = TRUE, 189 .init_sr1f = true,
199 .scrn_start_bit19 = FALSE, 190 .scrn_start_bit19 = false,
200 .sr07 = 0x20, 191 .sr07 = 0x20,
201 .sr07_1bpp = 0x20, 192 .sr07_1bpp = 0x20,
202 .sr07_8bpp = 0x21, 193 .sr07_8bpp = 0x21,
@@ -208,9 +199,9 @@ static const struct cirrusfb_board_info_rec {
208 /* guess */ 199 /* guess */
209 90000, 90000, 90000, 90000, 90000 200 90000, 90000, 90000, 90000, 90000
210 }, 201 },
211 .init_sr07 = TRUE, 202 .init_sr07 = true,
212 .init_sr1f = TRUE, 203 .init_sr1f = true,
213 .scrn_start_bit19 = FALSE, 204 .scrn_start_bit19 = false,
214 .sr07 = 0x80, 205 .sr07 = 0x80,
215 .sr07_1bpp = 0x80, 206 .sr07_1bpp = 0x80,
216 .sr07_8bpp = 0x81, 207 .sr07_8bpp = 0x81,
@@ -221,9 +212,9 @@ static const struct cirrusfb_board_info_rec {
221 .maxclock = { 212 .maxclock = {
222 135100, 135100, 85500, 85500, 0 213 135100, 135100, 85500, 85500, 0
223 }, 214 },
224 .init_sr07 = TRUE, 215 .init_sr07 = true,
225 .init_sr1f = FALSE, 216 .init_sr1f = false,
226 .scrn_start_bit19 = TRUE, 217 .scrn_start_bit19 = true,
227 .sr07 = 0x20, 218 .sr07 = 0x20,
228 .sr07_1bpp = 0x20, 219 .sr07_1bpp = 0x20,
229 .sr07_8bpp = 0x21, 220 .sr07_8bpp = 0x21,
@@ -235,9 +226,9 @@ static const struct cirrusfb_board_info_rec {
235 /* for the GD5430. GD5446 can do more... */ 226 /* for the GD5430. GD5446 can do more... */
236 85500, 85500, 50000, 28500, 0 227 85500, 85500, 50000, 28500, 0
237 }, 228 },
238 .init_sr07 = TRUE, 229 .init_sr07 = true,
239 .init_sr1f = TRUE, 230 .init_sr1f = true,
240 .scrn_start_bit19 = TRUE, 231 .scrn_start_bit19 = true,
241 .sr07 = 0xA0, 232 .sr07 = 0xA0,
242 .sr07_1bpp = 0xA1, 233 .sr07_1bpp = 0xA1,
243 .sr07_1bpp_mux = 0xA7, 234 .sr07_1bpp_mux = 0xA7,
@@ -250,9 +241,9 @@ static const struct cirrusfb_board_info_rec {
250 .maxclock = { 241 .maxclock = {
251 135100, 200000, 200000, 135100, 135100 242 135100, 200000, 200000, 135100, 135100
252 }, 243 },
253 .init_sr07 = TRUE, 244 .init_sr07 = true,
254 .init_sr1f = TRUE, 245 .init_sr1f = true,
255 .scrn_start_bit19 = TRUE, 246 .scrn_start_bit19 = true,
256 .sr07 = 0x10, 247 .sr07 = 0x10,
257 .sr07_1bpp = 0x11, 248 .sr07_1bpp = 0x11,
258 .sr07_8bpp = 0x11, 249 .sr07_8bpp = 0x11,
@@ -264,9 +255,9 @@ static const struct cirrusfb_board_info_rec {
264 /* guess */ 255 /* guess */
265 135100, 135100, 135100, 135100, 135100, 256 135100, 135100, 135100, 135100, 135100,
266 }, 257 },
267 .init_sr07 = FALSE, 258 .init_sr07 = false,
268 .init_sr1f = FALSE, 259 .init_sr1f = false,
269 .scrn_start_bit19 = TRUE, 260 .scrn_start_bit19 = true,
270 } 261 }
271}; 262};
272 263
@@ -815,7 +806,7 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
815 806
816 default: 807 default:
817 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel); 808 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
818 assert (FALSE); 809 assert(false);
819 /* should never occur */ 810 /* should never occur */
820 break; 811 break;
821 } 812 }
@@ -886,7 +877,7 @@ static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
886 877
887 default: 878 default:
888 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel); 879 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
889 assert (FALSE); 880 assert(false);
890 /* should never occur */ 881 /* should never occur */
891 break; 882 break;
892 } 883 }
@@ -3203,7 +3194,7 @@ void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_clas
3203 break; 3194 break;
3204 default: 3195 default:
3205 /* should never occur */ 3196 /* should never occur */
3206 assert (FALSE); 3197 assert(false);
3207 break; 3198 break;
3208 } 3199 }
3209 3200
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 21:30:55 -0500