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-rw-r--r--drivers/video/cg6.c801
1 files changed, 801 insertions, 0 deletions
diff --git a/drivers/video/cg6.c b/drivers/video/cg6.c
new file mode 100644
index 000000000000..49a2545671d9
--- /dev/null
+++ b/drivers/video/cg6.c
@@ -0,0 +1,801 @@
1/* cg6.c: CGSIX (GX, GXplus, TGX) frame buffer driver
2 *
3 * Copyright (C) 2003 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
5 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 *
8 * Driver layout based loosely on tgafb.c, see that file for credits.
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/fb.h>
19#include <linux/mm.h>
20
21#include <asm/io.h>
22#include <asm/sbus.h>
23#include <asm/oplib.h>
24#include <asm/fbio.h>
25
26#include "sbuslib.h"
27
28/*
29 * Local functions.
30 */
31
32static int cg6_setcolreg(unsigned, unsigned, unsigned, unsigned,
33 unsigned, struct fb_info *);
34static int cg6_blank(int, struct fb_info *);
35
36static void cg6_imageblit(struct fb_info *, const struct fb_image *);
37static void cg6_fillrect(struct fb_info *, const struct fb_fillrect *);
38static int cg6_sync(struct fb_info *);
39static int cg6_mmap(struct fb_info *, struct file *, struct vm_area_struct *);
40static int cg6_ioctl(struct inode *, struct file *, unsigned int,
41 unsigned long, struct fb_info *);
42
43/*
44 * Frame buffer operations
45 */
46
47static struct fb_ops cg6_ops = {
48 .owner = THIS_MODULE,
49 .fb_setcolreg = cg6_setcolreg,
50 .fb_blank = cg6_blank,
51 .fb_fillrect = cg6_fillrect,
52 .fb_copyarea = cfb_copyarea,
53 .fb_imageblit = cg6_imageblit,
54 .fb_sync = cg6_sync,
55 .fb_mmap = cg6_mmap,
56 .fb_ioctl = cg6_ioctl,
57 .fb_cursor = soft_cursor,
58};
59
60/* Offset of interesting structures in the OBIO space */
61/*
62 * Brooktree is the video dac and is funny to program on the cg6.
63 * (it's even funnier on the cg3)
64 * The FBC could be the frame buffer control
65 * The FHC could is the frame buffer hardware control.
66 */
67#define CG6_ROM_OFFSET 0x0UL
68#define CG6_BROOKTREE_OFFSET 0x200000UL
69#define CG6_DHC_OFFSET 0x240000UL
70#define CG6_ALT_OFFSET 0x280000UL
71#define CG6_FHC_OFFSET 0x300000UL
72#define CG6_THC_OFFSET 0x301000UL
73#define CG6_FBC_OFFSET 0x700000UL
74#define CG6_TEC_OFFSET 0x701000UL
75#define CG6_RAM_OFFSET 0x800000UL
76
77/* FHC definitions */
78#define CG6_FHC_FBID_SHIFT 24
79#define CG6_FHC_FBID_MASK 255
80#define CG6_FHC_REV_SHIFT 20
81#define CG6_FHC_REV_MASK 15
82#define CG6_FHC_FROP_DISABLE (1 << 19)
83#define CG6_FHC_ROW_DISABLE (1 << 18)
84#define CG6_FHC_SRC_DISABLE (1 << 17)
85#define CG6_FHC_DST_DISABLE (1 << 16)
86#define CG6_FHC_RESET (1 << 15)
87#define CG6_FHC_LITTLE_ENDIAN (1 << 13)
88#define CG6_FHC_RES_MASK (3 << 11)
89#define CG6_FHC_1024 (0 << 11)
90#define CG6_FHC_1152 (1 << 11)
91#define CG6_FHC_1280 (2 << 11)
92#define CG6_FHC_1600 (3 << 11)
93#define CG6_FHC_CPU_MASK (3 << 9)
94#define CG6_FHC_CPU_SPARC (0 << 9)
95#define CG6_FHC_CPU_68020 (1 << 9)
96#define CG6_FHC_CPU_386 (2 << 9)
97#define CG6_FHC_TEST (1 << 8)
98#define CG6_FHC_TEST_X_SHIFT 4
99#define CG6_FHC_TEST_X_MASK 15
100#define CG6_FHC_TEST_Y_SHIFT 0
101#define CG6_FHC_TEST_Y_MASK 15
102
103/* FBC mode definitions */
104#define CG6_FBC_BLIT_IGNORE 0x00000000
105#define CG6_FBC_BLIT_NOSRC 0x00100000
106#define CG6_FBC_BLIT_SRC 0x00200000
107#define CG6_FBC_BLIT_ILLEGAL 0x00300000
108#define CG6_FBC_BLIT_MASK 0x00300000
109
110#define CG6_FBC_VBLANK 0x00080000
111
112#define CG6_FBC_MODE_IGNORE 0x00000000
113#define CG6_FBC_MODE_COLOR8 0x00020000
114#define CG6_FBC_MODE_COLOR1 0x00040000
115#define CG6_FBC_MODE_HRMONO 0x00060000
116#define CG6_FBC_MODE_MASK 0x00060000
117
118#define CG6_FBC_DRAW_IGNORE 0x00000000
119#define CG6_FBC_DRAW_RENDER 0x00008000
120#define CG6_FBC_DRAW_PICK 0x00010000
121#define CG6_FBC_DRAW_ILLEGAL 0x00018000
122#define CG6_FBC_DRAW_MASK 0x00018000
123
124#define CG6_FBC_BWRITE0_IGNORE 0x00000000
125#define CG6_FBC_BWRITE0_ENABLE 0x00002000
126#define CG6_FBC_BWRITE0_DISABLE 0x00004000
127#define CG6_FBC_BWRITE0_ILLEGAL 0x00006000
128#define CG6_FBC_BWRITE0_MASK 0x00006000
129
130#define CG6_FBC_BWRITE1_IGNORE 0x00000000
131#define CG6_FBC_BWRITE1_ENABLE 0x00000800
132#define CG6_FBC_BWRITE1_DISABLE 0x00001000
133#define CG6_FBC_BWRITE1_ILLEGAL 0x00001800
134#define CG6_FBC_BWRITE1_MASK 0x00001800
135
136#define CG6_FBC_BREAD_IGNORE 0x00000000
137#define CG6_FBC_BREAD_0 0x00000200
138#define CG6_FBC_BREAD_1 0x00000400
139#define CG6_FBC_BREAD_ILLEGAL 0x00000600
140#define CG6_FBC_BREAD_MASK 0x00000600
141
142#define CG6_FBC_BDISP_IGNORE 0x00000000
143#define CG6_FBC_BDISP_0 0x00000080
144#define CG6_FBC_BDISP_1 0x00000100
145#define CG6_FBC_BDISP_ILLEGAL 0x00000180
146#define CG6_FBC_BDISP_MASK 0x00000180
147
148#define CG6_FBC_INDEX_MOD 0x00000040
149#define CG6_FBC_INDEX_MASK 0x00000030
150
151/* THC definitions */
152#define CG6_THC_MISC_REV_SHIFT 16
153#define CG6_THC_MISC_REV_MASK 15
154#define CG6_THC_MISC_RESET (1 << 12)
155#define CG6_THC_MISC_VIDEO (1 << 10)
156#define CG6_THC_MISC_SYNC (1 << 9)
157#define CG6_THC_MISC_VSYNC (1 << 8)
158#define CG6_THC_MISC_SYNC_ENAB (1 << 7)
159#define CG6_THC_MISC_CURS_RES (1 << 6)
160#define CG6_THC_MISC_INT_ENAB (1 << 5)
161#define CG6_THC_MISC_INT (1 << 4)
162#define CG6_THC_MISC_INIT 0x9f
163
164/* The contents are unknown */
165struct cg6_tec {
166 volatile int tec_matrix;
167 volatile int tec_clip;
168 volatile int tec_vdc;
169};
170
171struct cg6_thc {
172 uint thc_pad0[512];
173 volatile uint thc_hs; /* hsync timing */
174 volatile uint thc_hsdvs;
175 volatile uint thc_hd;
176 volatile uint thc_vs; /* vsync timing */
177 volatile uint thc_vd;
178 volatile uint thc_refresh;
179 volatile uint thc_misc;
180 uint thc_pad1[56];
181 volatile uint thc_cursxy; /* cursor x,y position (16 bits each) */
182 volatile uint thc_cursmask[32]; /* cursor mask bits */
183 volatile uint thc_cursbits[32]; /* what to show where mask enabled */
184};
185
186struct cg6_fbc {
187 u32 xxx0[1];
188 volatile u32 mode;
189 volatile u32 clip;
190 u32 xxx1[1];
191 volatile u32 s;
192 volatile u32 draw;
193 volatile u32 blit;
194 volatile u32 font;
195 u32 xxx2[24];
196 volatile u32 x0, y0, z0, color0;
197 volatile u32 x1, y1, z1, color1;
198 volatile u32 x2, y2, z2, color2;
199 volatile u32 x3, y3, z3, color3;
200 volatile u32 offx, offy;
201 u32 xxx3[2];
202 volatile u32 incx, incy;
203 u32 xxx4[2];
204 volatile u32 clipminx, clipminy;
205 u32 xxx5[2];
206 volatile u32 clipmaxx, clipmaxy;
207 u32 xxx6[2];
208 volatile u32 fg;
209 volatile u32 bg;
210 volatile u32 alu;
211 volatile u32 pm;
212 volatile u32 pixelm;
213 u32 xxx7[2];
214 volatile u32 patalign;
215 volatile u32 pattern[8];
216 u32 xxx8[432];
217 volatile u32 apointx, apointy, apointz;
218 u32 xxx9[1];
219 volatile u32 rpointx, rpointy, rpointz;
220 u32 xxx10[5];
221 volatile u32 pointr, pointg, pointb, pointa;
222 volatile u32 alinex, aliney, alinez;
223 u32 xxx11[1];
224 volatile u32 rlinex, rliney, rlinez;
225 u32 xxx12[5];
226 volatile u32 liner, lineg, lineb, linea;
227 volatile u32 atrix, atriy, atriz;
228 u32 xxx13[1];
229 volatile u32 rtrix, rtriy, rtriz;
230 u32 xxx14[5];
231 volatile u32 trir, trig, trib, tria;
232 volatile u32 aquadx, aquady, aquadz;
233 u32 xxx15[1];
234 volatile u32 rquadx, rquady, rquadz;
235 u32 xxx16[5];
236 volatile u32 quadr, quadg, quadb, quada;
237 volatile u32 arectx, arecty, arectz;
238 u32 xxx17[1];
239 volatile u32 rrectx, rrecty, rrectz;
240 u32 xxx18[5];
241 volatile u32 rectr, rectg, rectb, recta;
242};
243
244struct bt_regs {
245 volatile u32 addr;
246 volatile u32 color_map;
247 volatile u32 control;
248 volatile u32 cursor;
249};
250
251struct cg6_par {
252 spinlock_t lock;
253 struct bt_regs __iomem *bt;
254 struct cg6_fbc __iomem *fbc;
255 struct cg6_thc __iomem *thc;
256 struct cg6_tec __iomem *tec;
257 volatile u32 __iomem *fhc;
258
259 u32 flags;
260#define CG6_FLAG_BLANKED 0x00000001
261
262 unsigned long physbase;
263 unsigned long fbsize;
264
265 struct sbus_dev *sdev;
266 struct list_head list;
267};
268
269static int cg6_sync(struct fb_info *info)
270{
271 struct cg6_par *par = (struct cg6_par *) info->par;
272 struct cg6_fbc __iomem *fbc = par->fbc;
273 int limit = 10000;
274
275 do {
276 if (!(sbus_readl(&fbc->s) & 0x10000000))
277 break;
278 udelay(10);
279 } while (--limit > 0);
280
281 return 0;
282}
283
284/**
285 * cg6_fillrect - REQUIRED function. Can use generic routines if
286 * non acclerated hardware and packed pixel based.
287 * Draws a rectangle on the screen.
288 *
289 * @info: frame buffer structure that represents a single frame buffer
290 * @rect: structure defining the rectagle and operation.
291 */
292static void cg6_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
293{
294 struct cg6_par *par = (struct cg6_par *) info->par;
295 struct cg6_fbc __iomem *fbc = par->fbc;
296 unsigned long flags;
297 s32 val;
298
299 /* XXX doesn't handle ROP_XOR */
300
301 spin_lock_irqsave(&par->lock, flags);
302 cg6_sync(info);
303 sbus_writel(rect->color, &fbc->fg);
304 sbus_writel(~(u32)0, &fbc->pixelm);
305 sbus_writel(0xea80ff00, &fbc->alu);
306 sbus_writel(0, &fbc->s);
307 sbus_writel(0, &fbc->clip);
308 sbus_writel(~(u32)0, &fbc->pm);
309 sbus_writel(rect->dy, &fbc->arecty);
310 sbus_writel(rect->dx, &fbc->arectx);
311 sbus_writel(rect->dy + rect->height, &fbc->arecty);
312 sbus_writel(rect->dx + rect->width, &fbc->arectx);
313 do {
314 val = sbus_readl(&fbc->draw);
315 } while (val < 0 && (val & 0x20000000));
316 spin_unlock_irqrestore(&par->lock, flags);
317}
318
319/**
320 * cg6_imageblit - REQUIRED function. Can use generic routines if
321 * non acclerated hardware and packed pixel based.
322 * Copies a image from system memory to the screen.
323 *
324 * @info: frame buffer structure that represents a single frame buffer
325 * @image: structure defining the image.
326 */
327static void cg6_imageblit(struct fb_info *info, const struct fb_image *image)
328{
329 struct cg6_par *par = (struct cg6_par *) info->par;
330 struct cg6_fbc __iomem *fbc = par->fbc;
331 const u8 *data = image->data;
332 unsigned long flags;
333 u32 x, y;
334 int i, width;
335
336 if (image->depth > 1) {
337 cfb_imageblit(info, image);
338 return;
339 }
340
341 spin_lock_irqsave(&par->lock, flags);
342
343 cg6_sync(info);
344
345 sbus_writel(image->fg_color, &fbc->fg);
346 sbus_writel(image->bg_color, &fbc->bg);
347 sbus_writel(0x140000, &fbc->mode);
348 sbus_writel(0xe880fc30, &fbc->alu);
349 sbus_writel(~(u32)0, &fbc->pixelm);
350 sbus_writel(0, &fbc->s);
351 sbus_writel(0, &fbc->clip);
352 sbus_writel(0xff, &fbc->pm);
353 sbus_writel(32, &fbc->incx);
354 sbus_writel(0, &fbc->incy);
355
356 x = image->dx;
357 y = image->dy;
358 for (i = 0; i < image->height; i++) {
359 width = image->width;
360
361 while (width >= 32) {
362 u32 val;
363
364 sbus_writel(y, &fbc->y0);
365 sbus_writel(x, &fbc->x0);
366 sbus_writel(x + 32 - 1, &fbc->x1);
367
368 val = ((u32)data[0] << 24) |
369 ((u32)data[1] << 16) |
370 ((u32)data[2] << 8) |
371 ((u32)data[3] << 0);
372 sbus_writel(val, &fbc->font);
373
374 data += 4;
375 x += 32;
376 width -= 32;
377 }
378 if (width) {
379 u32 val;
380
381 sbus_writel(y, &fbc->y0);
382 sbus_writel(x, &fbc->x0);
383 sbus_writel(x + width - 1, &fbc->x1);
384 if (width <= 8) {
385 val = (u32) data[0] << 24;
386 data += 1;
387 } else if (width <= 16) {
388 val = ((u32) data[0] << 24) |
389 ((u32) data[1] << 16);
390 data += 2;
391 } else {
392 val = ((u32) data[0] << 24) |
393 ((u32) data[1] << 16) |
394 ((u32) data[2] << 8);
395 data += 3;
396 }
397 sbus_writel(val, &fbc->font);
398 }
399
400 y += 1;
401 x = image->dx;
402 }
403
404 spin_unlock_irqrestore(&par->lock, flags);
405}
406
407/**
408 * cg6_setcolreg - Optional function. Sets a color register.
409 * @regno: boolean, 0 copy local, 1 get_user() function
410 * @red: frame buffer colormap structure
411 * @green: The green value which can be up to 16 bits wide
412 * @blue: The blue value which can be up to 16 bits wide.
413 * @transp: If supported the alpha value which can be up to 16 bits wide.
414 * @info: frame buffer info structure
415 */
416static int cg6_setcolreg(unsigned regno,
417 unsigned red, unsigned green, unsigned blue,
418 unsigned transp, struct fb_info *info)
419{
420 struct cg6_par *par = (struct cg6_par *) info->par;
421 struct bt_regs __iomem *bt = par->bt;
422 unsigned long flags;
423
424 if (regno >= 256)
425 return 1;
426
427 red >>= 8;
428 green >>= 8;
429 blue >>= 8;
430
431 spin_lock_irqsave(&par->lock, flags);
432
433 sbus_writel((u32)regno << 24, &bt->addr);
434 sbus_writel((u32)red << 24, &bt->color_map);
435 sbus_writel((u32)green << 24, &bt->color_map);
436 sbus_writel((u32)blue << 24, &bt->color_map);
437
438 spin_unlock_irqrestore(&par->lock, flags);
439
440 return 0;
441}
442
443/**
444 * cg6_blank - Optional function. Blanks the display.
445 * @blank_mode: the blank mode we want.
446 * @info: frame buffer structure that represents a single frame buffer
447 */
448static int
449cg6_blank(int blank, struct fb_info *info)
450{
451 struct cg6_par *par = (struct cg6_par *) info->par;
452 struct cg6_thc __iomem *thc = par->thc;
453 unsigned long flags;
454 u32 val;
455
456 spin_lock_irqsave(&par->lock, flags);
457
458 switch (blank) {
459 case FB_BLANK_UNBLANK: /* Unblanking */
460 val = sbus_readl(&thc->thc_misc);
461 val |= CG6_THC_MISC_VIDEO;
462 sbus_writel(val, &thc->thc_misc);
463 par->flags &= ~CG6_FLAG_BLANKED;
464 break;
465
466 case FB_BLANK_NORMAL: /* Normal blanking */
467 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
468 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
469 case FB_BLANK_POWERDOWN: /* Poweroff */
470 val = sbus_readl(&thc->thc_misc);
471 val &= ~CG6_THC_MISC_VIDEO;
472 sbus_writel(val, &thc->thc_misc);
473 par->flags |= CG6_FLAG_BLANKED;
474 break;
475 }
476
477 spin_unlock_irqrestore(&par->lock, flags);
478
479 return 0;
480}
481
482static struct sbus_mmap_map cg6_mmap_map[] = {
483 {
484 .voff = CG6_FBC,
485 .poff = CG6_FBC_OFFSET,
486 .size = PAGE_SIZE
487 },
488 {
489 .voff = CG6_TEC,
490 .poff = CG6_TEC_OFFSET,
491 .size = PAGE_SIZE
492 },
493 {
494 .voff = CG6_BTREGS,
495 .poff = CG6_BROOKTREE_OFFSET,
496 .size = PAGE_SIZE
497 },
498 {
499 .voff = CG6_FHC,
500 .poff = CG6_FHC_OFFSET,
501 .size = PAGE_SIZE
502 },
503 {
504 .voff = CG6_THC,
505 .poff = CG6_THC_OFFSET,
506 .size = PAGE_SIZE
507 },
508 {
509 .voff = CG6_ROM,
510 .poff = CG6_ROM_OFFSET,
511 .size = 0x10000
512 },
513 {
514 .voff = CG6_RAM,
515 .poff = CG6_RAM_OFFSET,
516 .size = SBUS_MMAP_FBSIZE(1)
517 },
518 {
519 .voff = CG6_DHC,
520 .poff = CG6_DHC_OFFSET,
521 .size = 0x40000
522 },
523 { .size = 0 }
524};
525
526static int cg6_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
527{
528 struct cg6_par *par = (struct cg6_par *)info->par;
529
530 return sbusfb_mmap_helper(cg6_mmap_map,
531 par->physbase, par->fbsize,
532 par->sdev->reg_addrs[0].which_io,
533 vma);
534}
535
536static int cg6_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
537 unsigned long arg, struct fb_info *info)
538{
539 struct cg6_par *par = (struct cg6_par *) info->par;
540
541 return sbusfb_ioctl_helper(cmd, arg, info,
542 FBTYPE_SUNFAST_COLOR, 8, par->fbsize);
543}
544
545/*
546 * Initialisation
547 */
548
549static void
550cg6_init_fix(struct fb_info *info, int linebytes)
551{
552 struct cg6_par *par = (struct cg6_par *)info->par;
553 const char *cg6_cpu_name, *cg6_card_name;
554 u32 conf;
555
556 conf = sbus_readl(par->fhc);
557 switch(conf & CG6_FHC_CPU_MASK) {
558 case CG6_FHC_CPU_SPARC:
559 cg6_cpu_name = "sparc";
560 break;
561 case CG6_FHC_CPU_68020:
562 cg6_cpu_name = "68020";
563 break;
564 default:
565 cg6_cpu_name = "i386";
566 break;
567 };
568 if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) {
569 if (par->fbsize <= 0x100000) {
570 cg6_card_name = "TGX";
571 } else {
572 cg6_card_name = "TGX+";
573 }
574 } else {
575 if (par->fbsize <= 0x100000) {
576 cg6_card_name = "GX";
577 } else {
578 cg6_card_name = "GX+";
579 }
580 }
581
582 sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name);
583 info->fix.id[sizeof(info->fix.id)-1] = 0;
584
585 info->fix.type = FB_TYPE_PACKED_PIXELS;
586 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
587
588 info->fix.line_length = linebytes;
589
590 info->fix.accel = FB_ACCEL_SUN_CGSIX;
591}
592
593/* Initialize Brooktree DAC */
594static void cg6_bt_init(struct cg6_par *par)
595{
596 struct bt_regs __iomem *bt = par->bt;
597
598 sbus_writel(0x04 << 24, &bt->addr); /* color planes */
599 sbus_writel(0xff << 24, &bt->control);
600 sbus_writel(0x05 << 24, &bt->addr);
601 sbus_writel(0x00 << 24, &bt->control);
602 sbus_writel(0x06 << 24, &bt->addr); /* overlay plane */
603 sbus_writel(0x73 << 24, &bt->control);
604 sbus_writel(0x07 << 24, &bt->addr);
605 sbus_writel(0x00 << 24, &bt->control);
606}
607
608static void cg6_chip_init(struct fb_info *info)
609{
610 struct cg6_par *par = (struct cg6_par *) info->par;
611 struct cg6_tec __iomem *tec = par->tec;
612 struct cg6_fbc __iomem *fbc = par->fbc;
613 u32 rev, conf, mode, tmp;
614 int i;
615
616 /* Turn off stuff in the Transform Engine. */
617 sbus_writel(0, &tec->tec_matrix);
618 sbus_writel(0, &tec->tec_clip);
619 sbus_writel(0, &tec->tec_vdc);
620
621 /* Take care of bugs in old revisions. */
622 rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK;
623 if (rev < 5) {
624 conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) |
625 CG6_FHC_CPU_68020 | CG6_FHC_TEST |
626 (11 << CG6_FHC_TEST_X_SHIFT) |
627 (11 << CG6_FHC_TEST_Y_SHIFT);
628 if (rev < 2)
629 conf |= CG6_FHC_DST_DISABLE;
630 sbus_writel(conf, par->fhc);
631 }
632
633 /* Set things in the FBC. Bad things appear to happen if we do
634 * back to back store/loads on the mode register, so copy it
635 * out instead. */
636 mode = sbus_readl(&fbc->mode);
637 do {
638 i = sbus_readl(&fbc->s);
639 } while (i & 0x10000000);
640 mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK |
641 CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK |
642 CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK |
643 CG6_FBC_BDISP_MASK);
644 mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 |
645 CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE |
646 CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 |
647 CG6_FBC_BDISP_0);
648 sbus_writel(mode, &fbc->mode);
649
650 sbus_writel(0, &fbc->clip);
651 sbus_writel(0, &fbc->offx);
652 sbus_writel(0, &fbc->offy);
653 sbus_writel(0, &fbc->clipminx);
654 sbus_writel(0, &fbc->clipminy);
655 sbus_writel(info->var.xres - 1, &fbc->clipmaxx);
656 sbus_writel(info->var.yres - 1, &fbc->clipmaxy);
657
658 /* Disable cursor in Brooktree DAC. */
659 sbus_writel(0x06 << 24, &par->bt->addr);
660 tmp = sbus_readl(&par->bt->control);
661 tmp &= ~(0x03 << 24);
662 sbus_writel(tmp, &par->bt->control);
663}
664
665struct all_info {
666 struct fb_info info;
667 struct cg6_par par;
668 struct list_head list;
669};
670static LIST_HEAD(cg6_list);
671
672static void cg6_init_one(struct sbus_dev *sdev)
673{
674 struct all_info *all;
675 int linebytes;
676
677 all = kmalloc(sizeof(*all), GFP_KERNEL);
678 if (!all) {
679 printk(KERN_ERR "cg6: Cannot allocate memory.\n");
680 return;
681 }
682 memset(all, 0, sizeof(*all));
683
684 INIT_LIST_HEAD(&all->list);
685
686 spin_lock_init(&all->par.lock);
687 all->par.sdev = sdev;
688
689 all->par.physbase = sdev->reg_addrs[0].phys_addr;
690
691 sbusfb_fill_var(&all->info.var, sdev->prom_node, 8);
692 all->info.var.red.length = 8;
693 all->info.var.green.length = 8;
694 all->info.var.blue.length = 8;
695
696 linebytes = prom_getintdefault(sdev->prom_node, "linebytes",
697 all->info.var.xres);
698 all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
699 if (prom_getbool(sdev->prom_node, "dblbuf"))
700 all->par.fbsize *= 4;
701
702 all->par.fbc = sbus_ioremap(&sdev->resource[0], CG6_FBC_OFFSET,
703 4096, "cgsix fbc");
704 all->par.tec = sbus_ioremap(&sdev->resource[0], CG6_TEC_OFFSET,
705 sizeof(struct cg6_tec), "cgsix tec");
706 all->par.thc = sbus_ioremap(&sdev->resource[0], CG6_THC_OFFSET,
707 sizeof(struct cg6_thc), "cgsix thc");
708 all->par.bt = sbus_ioremap(&sdev->resource[0], CG6_BROOKTREE_OFFSET,
709 sizeof(struct bt_regs), "cgsix dac");
710 all->par.fhc = sbus_ioremap(&sdev->resource[0], CG6_FHC_OFFSET,
711 sizeof(u32), "cgsix fhc");
712
713 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT |
714 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
715 all->info.fbops = &cg6_ops;
716#ifdef CONFIG_SPARC32
717 all->info.screen_base = (char __iomem *)
718 prom_getintdefault(sdev->prom_node, "address", 0);
719#endif
720 if (!all->info.screen_base)
721 all->info.screen_base =
722 sbus_ioremap(&sdev->resource[0], CG6_RAM_OFFSET,
723 all->par.fbsize, "cgsix ram");
724 all->info.par = &all->par;
725
726 all->info.var.accel_flags = FB_ACCELF_TEXT;
727
728 cg6_bt_init(&all->par);
729 cg6_chip_init(&all->info);
730 cg6_blank(0, &all->info);
731
732 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
733 printk(KERN_ERR "cg6: Could not allocate color map.\n");
734 kfree(all);
735 return;
736 }
737
738 fb_set_cmap(&all->info.cmap, &all->info);
739 cg6_init_fix(&all->info, linebytes);
740
741 if (register_framebuffer(&all->info) < 0) {
742 printk(KERN_ERR "cg6: Could not register framebuffer.\n");
743 fb_dealloc_cmap(&all->info.cmap);
744 kfree(all);
745 return;
746 }
747
748 list_add(&all->list, &cg6_list);
749
750 printk("cg6: CGsix [%s] at %lx:%lx\n",
751 all->info.fix.id,
752 (long) sdev->reg_addrs[0].which_io,
753 (long) sdev->reg_addrs[0].phys_addr);
754}
755
756int __init cg6_init(void)
757{
758 struct sbus_bus *sbus;
759 struct sbus_dev *sdev;
760
761 if (fb_get_options("cg6fb", NULL))
762 return -ENODEV;
763
764 for_all_sbusdev(sdev, sbus) {
765 if (!strcmp(sdev->prom_name, "cgsix") ||
766 !strcmp(sdev->prom_name, "cgthree+"))
767 cg6_init_one(sdev);
768 }
769
770 return 0;
771}
772
773void __exit cg6_exit(void)
774{
775 struct list_head *pos, *tmp;
776
777 list_for_each_safe(pos, tmp, &cg6_list) {
778 struct all_info *all = list_entry(pos, typeof(*all), list);
779
780 unregister_framebuffer(&all->info);
781 fb_dealloc_cmap(&all->info.cmap);
782 kfree(all);
783 }
784}
785
786int __init
787cg6_setup(char *arg)
788{
789 /* No cmdline options yet... */
790 return 0;
791}
792
793module_init(cg6_init);
794
795#ifdef MODULE
796module_exit(cg6_exit);
797#endif
798
799MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets");
800MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
801MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 06:34:32 -0500