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-rw-r--r--drivers/video/aty/Makefile15
-rw-r--r--drivers/video/aty/ati_ids.h211
-rw-r--r--drivers/video/aty/aty128fb.c2485
-rw-r--r--drivers/video/aty/atyfb.h359
-rw-r--r--drivers/video/aty/atyfb_base.c3720
-rw-r--r--drivers/video/aty/mach64_accel.c433
-rw-r--r--drivers/video/aty/mach64_ct.c619
-rw-r--r--drivers/video/aty/mach64_cursor.c226
-rw-r--r--drivers/video/aty/mach64_gx.c912
-rw-r--r--drivers/video/aty/radeon_accel.c316
-rw-r--r--drivers/video/aty/radeon_base.c2587
-rw-r--r--drivers/video/aty/radeon_i2c.c265
-rw-r--r--drivers/video/aty/radeon_monitor.c1010
-rw-r--r--drivers/video/aty/radeon_pm.c2801
-rw-r--r--drivers/video/aty/radeonfb.h625
-rw-r--r--drivers/video/aty/xlinit.c354
16 files changed, 16938 insertions, 0 deletions
diff --git a/drivers/video/aty/Makefile b/drivers/video/aty/Makefile
new file mode 100644
index 000000000000..9dec96249ffb
--- /dev/null
+++ b/drivers/video/aty/Makefile
@@ -0,0 +1,15 @@
1obj-$(CONFIG_FB_ATY) += atyfb.o
2obj-$(CONFIG_FB_ATY128) += aty128fb.o
3obj-$(CONFIG_FB_RADEON) += radeonfb.o
4
5atyfb-y := atyfb_base.o mach64_accel.o mach64_cursor.o
6atyfb-$(CONFIG_FB_ATY_GX) += mach64_gx.o
7atyfb-$(CONFIG_FB_ATY_CT) += mach64_ct.o
8atyfb-$(CONFIG_FB_ATY_XL_INIT) += xlinit.o
9
10atyfb-objs := $(atyfb-y)
11
12radeonfb-y := radeon_base.o radeon_pm.o radeon_monitor.o radeon_accel.o
13radeonfb-$(CONFIG_FB_RADEON_I2C) += radeon_i2c.o
14radeonfb-objs := $(radeonfb-y)
15
diff --git a/drivers/video/aty/ati_ids.h b/drivers/video/aty/ati_ids.h
new file mode 100644
index 000000000000..13321c689cf6
--- /dev/null
+++ b/drivers/video/aty/ati_ids.h
@@ -0,0 +1,211 @@
1/*
2 * ATI PCI IDs from XFree86, kept here to make sync'ing with
3 * XFree much simpler. Currently, this list is only used by
4 * radeonfb
5 */
6
7#define PCI_CHIP_RV380_3150 0x3150
8#define PCI_CHIP_RV380_3151 0x3151
9#define PCI_CHIP_RV380_3152 0x3152
10#define PCI_CHIP_RV380_3153 0x3153
11#define PCI_CHIP_RV380_3154 0x3154
12#define PCI_CHIP_RV380_3156 0x3156
13#define PCI_CHIP_RV380_3E50 0x3E50
14#define PCI_CHIP_RV380_3E51 0x3E51
15#define PCI_CHIP_RV380_3E52 0x3E52
16#define PCI_CHIP_RV380_3E53 0x3E53
17#define PCI_CHIP_RV380_3E54 0x3E54
18#define PCI_CHIP_RV380_3E56 0x3E56
19#define PCI_CHIP_RS100_4136 0x4136
20#define PCI_CHIP_RS200_4137 0x4137
21#define PCI_CHIP_R300_AD 0x4144
22#define PCI_CHIP_R300_AE 0x4145
23#define PCI_CHIP_R300_AF 0x4146
24#define PCI_CHIP_R300_AG 0x4147
25#define PCI_CHIP_R350_AH 0x4148
26#define PCI_CHIP_R350_AI 0x4149
27#define PCI_CHIP_R350_AJ 0x414A
28#define PCI_CHIP_R350_AK 0x414B
29#define PCI_CHIP_RV350_AP 0x4150
30#define PCI_CHIP_RV350_AQ 0x4151
31#define PCI_CHIP_RV360_AR 0x4152
32#define PCI_CHIP_RV350_AS 0x4153
33#define PCI_CHIP_RV350_AT 0x4154
34#define PCI_CHIP_RV350_AV 0x4156
35#define PCI_CHIP_MACH32 0x4158
36#define PCI_CHIP_RS250_4237 0x4237
37#define PCI_CHIP_R200_BB 0x4242
38#define PCI_CHIP_R200_BC 0x4243
39#define PCI_CHIP_RS100_4336 0x4336
40#define PCI_CHIP_RS200_4337 0x4337
41#define PCI_CHIP_MACH64CT 0x4354
42#define PCI_CHIP_MACH64CX 0x4358
43#define PCI_CHIP_RS250_4437 0x4437
44#define PCI_CHIP_MACH64ET 0x4554
45#define PCI_CHIP_MACH64GB 0x4742
46#define PCI_CHIP_MACH64GD 0x4744
47#define PCI_CHIP_MACH64GI 0x4749
48#define PCI_CHIP_MACH64GL 0x474C
49#define PCI_CHIP_MACH64GM 0x474D
50#define PCI_CHIP_MACH64GN 0x474E
51#define PCI_CHIP_MACH64GO 0x474F
52#define PCI_CHIP_MACH64GP 0x4750
53#define PCI_CHIP_MACH64GQ 0x4751
54#define PCI_CHIP_MACH64GR 0x4752
55#define PCI_CHIP_MACH64GS 0x4753
56#define PCI_CHIP_MACH64GT 0x4754
57#define PCI_CHIP_MACH64GU 0x4755
58#define PCI_CHIP_MACH64GV 0x4756
59#define PCI_CHIP_MACH64GW 0x4757
60#define PCI_CHIP_MACH64GX 0x4758
61#define PCI_CHIP_MACH64GY 0x4759
62#define PCI_CHIP_MACH64GZ 0x475A
63#define PCI_CHIP_RV250_Id 0x4964
64#define PCI_CHIP_RV250_Ie 0x4965
65#define PCI_CHIP_RV250_If 0x4966
66#define PCI_CHIP_RV250_Ig 0x4967
67#define PCI_CHIP_R420_JH 0x4A48
68#define PCI_CHIP_R420_JI 0x4A49
69#define PCI_CHIP_R420_JJ 0x4A4A
70#define PCI_CHIP_R420_JK 0x4A4B
71#define PCI_CHIP_R420_JL 0x4A4C
72#define PCI_CHIP_R420_JM 0x4A4D
73#define PCI_CHIP_R420_JN 0x4A4E
74#define PCI_CHIP_R420_JP 0x4A50
75#define PCI_CHIP_MACH64LB 0x4C42
76#define PCI_CHIP_MACH64LD 0x4C44
77#define PCI_CHIP_RAGE128LE 0x4C45
78#define PCI_CHIP_RAGE128LF 0x4C46
79#define PCI_CHIP_MACH64LG 0x4C47
80#define PCI_CHIP_MACH64LI 0x4C49
81#define PCI_CHIP_MACH64LM 0x4C4D
82#define PCI_CHIP_MACH64LN 0x4C4E
83#define PCI_CHIP_MACH64LP 0x4C50
84#define PCI_CHIP_MACH64LQ 0x4C51
85#define PCI_CHIP_MACH64LR 0x4C52
86#define PCI_CHIP_MACH64LS 0x4C53
87#define PCI_CHIP_MACH64LT 0x4C54
88#define PCI_CHIP_RADEON_LW 0x4C57
89#define PCI_CHIP_RADEON_LX 0x4C58
90#define PCI_CHIP_RADEON_LY 0x4C59
91#define PCI_CHIP_RADEON_LZ 0x4C5A
92#define PCI_CHIP_RV250_Ld 0x4C64
93#define PCI_CHIP_RV250_Le 0x4C65
94#define PCI_CHIP_RV250_Lf 0x4C66
95#define PCI_CHIP_RV250_Lg 0x4C67
96#define PCI_CHIP_RV250_Ln 0x4C6E
97#define PCI_CHIP_RAGE128MF 0x4D46
98#define PCI_CHIP_RAGE128ML 0x4D4C
99#define PCI_CHIP_R300_ND 0x4E44
100#define PCI_CHIP_R300_NE 0x4E45
101#define PCI_CHIP_R300_NF 0x4E46
102#define PCI_CHIP_R300_NG 0x4E47
103#define PCI_CHIP_R350_NH 0x4E48
104#define PCI_CHIP_R350_NI 0x4E49
105#define PCI_CHIP_R360_NJ 0x4E4A
106#define PCI_CHIP_R350_NK 0x4E4B
107#define PCI_CHIP_RV350_NP 0x4E50
108#define PCI_CHIP_RV350_NQ 0x4E51
109#define PCI_CHIP_RV350_NR 0x4E52
110#define PCI_CHIP_RV350_NS 0x4E53
111#define PCI_CHIP_RV350_NT 0x4E54
112#define PCI_CHIP_RV350_NV 0x4E56
113#define PCI_CHIP_RAGE128PA 0x5041
114#define PCI_CHIP_RAGE128PB 0x5042
115#define PCI_CHIP_RAGE128PC 0x5043
116#define PCI_CHIP_RAGE128PD 0x5044
117#define PCI_CHIP_RAGE128PE 0x5045
118#define PCI_CHIP_RAGE128PF 0x5046
119#define PCI_CHIP_RAGE128PG 0x5047
120#define PCI_CHIP_RAGE128PH 0x5048
121#define PCI_CHIP_RAGE128PI 0x5049
122#define PCI_CHIP_RAGE128PJ 0x504A
123#define PCI_CHIP_RAGE128PK 0x504B
124#define PCI_CHIP_RAGE128PL 0x504C
125#define PCI_CHIP_RAGE128PM 0x504D
126#define PCI_CHIP_RAGE128PN 0x504E
127#define PCI_CHIP_RAGE128PO 0x504F
128#define PCI_CHIP_RAGE128PP 0x5050
129#define PCI_CHIP_RAGE128PQ 0x5051
130#define PCI_CHIP_RAGE128PR 0x5052
131#define PCI_CHIP_RAGE128PS 0x5053
132#define PCI_CHIP_RAGE128PT 0x5054
133#define PCI_CHIP_RAGE128PU 0x5055
134#define PCI_CHIP_RAGE128PV 0x5056
135#define PCI_CHIP_RAGE128PW 0x5057
136#define PCI_CHIP_RAGE128PX 0x5058
137#define PCI_CHIP_RADEON_QD 0x5144
138#define PCI_CHIP_RADEON_QE 0x5145
139#define PCI_CHIP_RADEON_QF 0x5146
140#define PCI_CHIP_RADEON_QG 0x5147
141#define PCI_CHIP_R200_QH 0x5148
142#define PCI_CHIP_R200_QI 0x5149
143#define PCI_CHIP_R200_QJ 0x514A
144#define PCI_CHIP_R200_QK 0x514B
145#define PCI_CHIP_R200_QL 0x514C
146#define PCI_CHIP_R200_QM 0x514D
147#define PCI_CHIP_R200_QN 0x514E
148#define PCI_CHIP_R200_QO 0x514F
149#define PCI_CHIP_RV200_QW 0x5157
150#define PCI_CHIP_RV200_QX 0x5158
151#define PCI_CHIP_RV100_QY 0x5159
152#define PCI_CHIP_RV100_QZ 0x515A
153#define PCI_CHIP_RAGE128RE 0x5245
154#define PCI_CHIP_RAGE128RF 0x5246
155#define PCI_CHIP_RAGE128RG 0x5247
156#define PCI_CHIP_RAGE128RK 0x524B
157#define PCI_CHIP_RAGE128RL 0x524C
158#define PCI_CHIP_RAGE128SE 0x5345
159#define PCI_CHIP_RAGE128SF 0x5346
160#define PCI_CHIP_RAGE128SG 0x5347
161#define PCI_CHIP_RAGE128SH 0x5348
162#define PCI_CHIP_RAGE128SK 0x534B
163#define PCI_CHIP_RAGE128SL 0x534C
164#define PCI_CHIP_RAGE128SM 0x534D
165#define PCI_CHIP_RAGE128SN 0x534E
166#define PCI_CHIP_RAGE128TF 0x5446
167#define PCI_CHIP_RAGE128TL 0x544C
168#define PCI_CHIP_RAGE128TR 0x5452
169#define PCI_CHIP_RAGE128TS 0x5453
170#define PCI_CHIP_RAGE128TT 0x5454
171#define PCI_CHIP_RAGE128TU 0x5455
172#define PCI_CHIP_RV370_5460 0x5460
173#define PCI_CHIP_RV370_5461 0x5461
174#define PCI_CHIP_RV370_5462 0x5462
175#define PCI_CHIP_RV370_5463 0x5463
176#define PCI_CHIP_RV370_5464 0x5464
177#define PCI_CHIP_RV370_5465 0x5465
178#define PCI_CHIP_RV370_5466 0x5466
179#define PCI_CHIP_RV370_5467 0x5467
180#define PCI_CHIP_R423_UH 0x5548
181#define PCI_CHIP_R423_UI 0x5549
182#define PCI_CHIP_R423_UJ 0x554A
183#define PCI_CHIP_R423_UK 0x554B
184#define PCI_CHIP_R423_UQ 0x5551
185#define PCI_CHIP_R423_UR 0x5552
186#define PCI_CHIP_R423_UT 0x5554
187#define PCI_CHIP_MACH64VT 0x5654
188#define PCI_CHIP_MACH64VU 0x5655
189#define PCI_CHIP_MACH64VV 0x5656
190#define PCI_CHIP_RS300_5834 0x5834
191#define PCI_CHIP_RS300_5835 0x5835
192#define PCI_CHIP_RS300_5836 0x5836
193#define PCI_CHIP_RS300_5837 0x5837
194#define PCI_CHIP_RV370_5B60 0x5B60
195#define PCI_CHIP_RV370_5B61 0x5B61
196#define PCI_CHIP_RV370_5B62 0x5B62
197#define PCI_CHIP_RV370_5B63 0x5B63
198#define PCI_CHIP_RV370_5B64 0x5B64
199#define PCI_CHIP_RV370_5B65 0x5B65
200#define PCI_CHIP_RV370_5B66 0x5B66
201#define PCI_CHIP_RV370_5B67 0x5B67
202#define PCI_CHIP_RV280_5960 0x5960
203#define PCI_CHIP_RV280_5961 0x5961
204#define PCI_CHIP_RV280_5962 0x5962
205#define PCI_CHIP_RV280_5964 0x5964
206#define PCI_CHIP_RV280_5C61 0x5C61
207#define PCI_CHIP_RV280_5C63 0x5C63
208#define PCI_CHIP_R423_5D57 0x5D57
209#define PCI_CHIP_RS350_7834 0x7834
210#define PCI_CHIP_RS350_7835 0x7835
211
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c
new file mode 100644
index 000000000000..8a4ba3bb9872
--- /dev/null
+++ b/drivers/video/aty/aty128fb.c
@@ -0,0 +1,2485 @@
1/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43/*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49#include <linux/config.h>
50#include <linux/module.h>
51#include <linux/moduleparam.h>
52#include <linux/kernel.h>
53#include <linux/errno.h>
54#include <linux/string.h>
55#include <linux/mm.h>
56#include <linux/tty.h>
57#include <linux/slab.h>
58#include <linux/vmalloc.h>
59#include <linux/delay.h>
60#include <linux/interrupt.h>
61#include <asm/uaccess.h>
62#include <linux/fb.h>
63#include <linux/init.h>
64#include <linux/pci.h>
65#include <linux/ioport.h>
66#include <linux/console.h>
67#include <asm/io.h>
68
69#ifdef CONFIG_PPC_PMAC
70#include <asm/pmac_feature.h>
71#include <asm/prom.h>
72#include <asm/pci-bridge.h>
73#include "../macmodes.h"
74#endif
75
76#ifdef CONFIG_PMAC_BACKLIGHT
77#include <asm/backlight.h>
78#endif
79
80#ifdef CONFIG_BOOTX_TEXT
81#include <asm/btext.h>
82#endif /* CONFIG_BOOTX_TEXT */
83
84#ifdef CONFIG_MTRR
85#include <asm/mtrr.h>
86#endif
87
88#include <video/aty128.h>
89
90/* Debug flag */
91#undef DEBUG
92
93#ifdef DEBUG
94#define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
95#else
96#define DBG(fmt, args...)
97#endif
98
99#ifndef CONFIG_PPC_PMAC
100/* default mode */
101static struct fb_var_screeninfo default_var __initdata = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
107};
108
109#else /* CONFIG_PPC_PMAC */
110/* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
119};
120#endif /* CONFIG_PPC_PMAC */
121
122/* default modedb mode */
123/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124static struct fb_videomode defaultmode __initdata = {
125 .refresh = 60,
126 .xres = 640,
127 .yres = 480,
128 .pixclock = 39722,
129 .left_margin = 48,
130 .right_margin = 16,
131 .upper_margin = 33,
132 .lower_margin = 10,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .sync = 0,
136 .vmode = FB_VMODE_NONINTERLACED
137};
138
139/* Chip generations */
140enum {
141 rage_128,
142 rage_128_pci,
143 rage_128_pro,
144 rage_128_pro_pci,
145 rage_M3,
146 rage_M3_pci,
147 rage_M4,
148 rage_128_ultra,
149};
150
151/* Must match above enum */
152static const char *r128_family[] __devinitdata = {
153 "AGP",
154 "PCI",
155 "PRO AGP",
156 "PRO PCI",
157 "M3 AGP",
158 "M3 PCI",
159 "M4 AGP",
160 "Ultra AGP",
161};
162
163/*
164 * PCI driver prototypes
165 */
166static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168static void aty128_remove(struct pci_dev *pdev);
169static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170static int aty128_pci_resume(struct pci_dev *pdev);
171static int aty128_do_resume(struct pci_dev *pdev);
172
173/* supported Rage128 chipsets */
174static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
269 { 0, }
270};
271
272MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
273
274static struct pci_driver aty128fb_driver = {
275 .name = "aty128fb",
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = __devexit_p(aty128_remove),
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
281};
282
283/* packed BIOS settings */
284#ifndef CONFIG_PPC
285typedef struct {
286 u8 clock_chip_type;
287 u8 struct_size;
288 u8 accelerator_entry;
289 u8 VGA_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
292 u16 XCLK;
293 u16 MCLK;
294 u8 num_PLL_blocks;
295 u8 size_PLL_blocks;
296 u16 PCLK_ref_freq;
297 u16 PCLK_ref_divider;
298 u32 PCLK_min_freq;
299 u32 PCLK_max_freq;
300 u16 MCLK_ref_freq;
301 u16 MCLK_ref_divider;
302 u32 MCLK_min_freq;
303 u32 MCLK_max_freq;
304 u16 XCLK_ref_freq;
305 u16 XCLK_ref_divider;
306 u32 XCLK_min_freq;
307 u32 XCLK_max_freq;
308} __attribute__ ((packed)) PLL_BLOCK;
309#endif /* !CONFIG_PPC */
310
311/* onboard memory information */
312struct aty128_meminfo {
313 u8 ML;
314 u8 MB;
315 u8 Trcd;
316 u8 Trp;
317 u8 Twr;
318 u8 CL;
319 u8 Tr2w;
320 u8 LoopLatency;
321 u8 DspOn;
322 u8 Rloop;
323 const char *name;
324};
325
326/* various memory configurations */
327static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
335
336static struct fb_fix_screeninfo aty128fb_fix __initdata = {
337 .id = "ATY Rage128",
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
340 .xpanstep = 8,
341 .ypanstep = 1,
342 .mmio_len = 0x2000,
343 .accel = FB_ACCEL_ATI_RAGE128,
344};
345
346static char *mode_option __initdata = NULL;
347
348#ifdef CONFIG_PPC_PMAC
349static int default_vmode __initdata = VMODE_1024_768_60;
350static int default_cmode __initdata = CMODE_8;
351#endif
352
353#ifdef CONFIG_PMAC_PBOOK
354static int default_crt_on __initdata = 0;
355static int default_lcd_on __initdata = 1;
356#endif
357
358#ifdef CONFIG_MTRR
359static int mtrr = 1;
360#endif
361
362/* PLL constants */
363struct aty128_constants {
364 u32 ref_clk;
365 u32 ppll_min;
366 u32 ppll_max;
367 u32 ref_divider;
368 u32 xclk;
369 u32 fifo_width;
370 u32 fifo_depth;
371};
372
373struct aty128_crtc {
374 u32 gen_cntl;
375 u32 h_total, h_sync_strt_wid;
376 u32 v_total, v_sync_strt_wid;
377 u32 pitch;
378 u32 offset, offset_cntl;
379 u32 xoffset, yoffset;
380 u32 vxres, vyres;
381 u32 depth, bpp;
382};
383
384struct aty128_pll {
385 u32 post_divider;
386 u32 feedback_divider;
387 u32 vclk;
388};
389
390struct aty128_ddafifo {
391 u32 dda_config;
392 u32 dda_on_off;
393};
394
395/* register values for a specific mode */
396struct aty128fb_par {
397 struct aty128_crtc crtc;
398 struct aty128_pll pll;
399 struct aty128_ddafifo fifo_reg;
400 u32 accel_flags;
401 struct aty128_constants constants; /* PLL and others */
402 void __iomem *regbase; /* remapped mmio */
403 u32 vram_size; /* onboard video ram */
404 int chip_gen;
405 const struct aty128_meminfo *mem; /* onboard mem info */
406#ifdef CONFIG_MTRR
407 struct { int vram; int vram_valid; } mtrr;
408#endif
409 int blitter_may_be_busy;
410 int fifo_slots; /* free slots in FIFO (64 max) */
411
412 int pm_reg;
413 int crt_on, lcd_on;
414 struct pci_dev *pdev;
415 struct fb_info *next;
416 int asleep;
417 int lock_blank;
418
419 u8 red[32]; /* see aty128fb_setcolreg */
420 u8 green[64];
421 u8 blue[32];
422 u32 pseudo_palette[16]; /* used for TRUECOLOR */
423};
424
425
426#define round_div(n, d) ((n+(d/2))/d)
427
428static int aty128fb_check_var(struct fb_var_screeninfo *var,
429 struct fb_info *info);
430static int aty128fb_set_par(struct fb_info *info);
431static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
432 u_int transp, struct fb_info *info);
433static int aty128fb_pan_display(struct fb_var_screeninfo *var,
434 struct fb_info *fb);
435static int aty128fb_blank(int blank, struct fb_info *fb);
436static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
437 u_long arg, struct fb_info *info);
438static int aty128fb_sync(struct fb_info *info);
439
440 /*
441 * Internal routines
442 */
443
444static int aty128_encode_var(struct fb_var_screeninfo *var,
445 const struct aty128fb_par *par);
446static int aty128_decode_var(struct fb_var_screeninfo *var,
447 struct aty128fb_par *par);
448#if 0
449static void __init aty128_get_pllinfo(struct aty128fb_par *par,
450 void __iomem *bios);
451static void __init __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
452#endif
453static void aty128_timings(struct aty128fb_par *par);
454static void aty128_init_engine(struct aty128fb_par *par);
455static void aty128_reset_engine(const struct aty128fb_par *par);
456static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
457static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
458static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
459static void wait_for_idle(struct aty128fb_par *par);
460static u32 depth_to_dst(u32 depth);
461
462#define BIOS_IN8(v) (readb(bios + (v)))
463#define BIOS_IN16(v) (readb(bios + (v)) | \
464 (readb(bios + (v) + 1) << 8))
465#define BIOS_IN32(v) (readb(bios + (v)) | \
466 (readb(bios + (v) + 1) << 8) | \
467 (readb(bios + (v) + 2) << 16) | \
468 (readb(bios + (v) + 3) << 24))
469
470
471static struct fb_ops aty128fb_ops = {
472 .owner = THIS_MODULE,
473 .fb_check_var = aty128fb_check_var,
474 .fb_set_par = aty128fb_set_par,
475 .fb_setcolreg = aty128fb_setcolreg,
476 .fb_pan_display = aty128fb_pan_display,
477 .fb_blank = aty128fb_blank,
478 .fb_ioctl = aty128fb_ioctl,
479 .fb_sync = aty128fb_sync,
480 .fb_fillrect = cfb_fillrect,
481 .fb_copyarea = cfb_copyarea,
482 .fb_imageblit = cfb_imageblit,
483 .fb_cursor = soft_cursor,
484};
485
486#ifdef CONFIG_PMAC_BACKLIGHT
487static int aty128_set_backlight_enable(int on, int level, void* data);
488static int aty128_set_backlight_level(int level, void* data);
489
490static struct backlight_controller aty128_backlight_controller = {
491 aty128_set_backlight_enable,
492 aty128_set_backlight_level
493};
494#endif /* CONFIG_PMAC_BACKLIGHT */
495
496 /*
497 * Functions to read from/write to the mmio registers
498 * - endian conversions may possibly be avoided by
499 * using the other register aperture. TODO.
500 */
501static inline u32 _aty_ld_le32(volatile unsigned int regindex,
502 const struct aty128fb_par *par)
503{
504 return readl (par->regbase + regindex);
505}
506
507static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
508 const struct aty128fb_par *par)
509{
510 writel (val, par->regbase + regindex);
511}
512
513static inline u8 _aty_ld_8(unsigned int regindex,
514 const struct aty128fb_par *par)
515{
516 return readb (par->regbase + regindex);
517}
518
519static inline void _aty_st_8(unsigned int regindex, u8 val,
520 const struct aty128fb_par *par)
521{
522 writeb (val, par->regbase + regindex);
523}
524
525#define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
526#define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
527#define aty_ld_8(regindex) _aty_ld_8(regindex, par)
528#define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
529
530 /*
531 * Functions to read from/write to the pll registers
532 */
533
534#define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
535#define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
536
537
538static u32 _aty_ld_pll(unsigned int pll_index,
539 const struct aty128fb_par *par)
540{
541 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
542 return aty_ld_le32(CLOCK_CNTL_DATA);
543}
544
545
546static void _aty_st_pll(unsigned int pll_index, u32 val,
547 const struct aty128fb_par *par)
548{
549 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
550 aty_st_le32(CLOCK_CNTL_DATA, val);
551}
552
553
554/* return true when the PLL has completed an atomic update */
555static int aty_pll_readupdate(const struct aty128fb_par *par)
556{
557 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
558}
559
560
561static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
562{
563 unsigned long timeout = jiffies + HZ/100; // should be more than enough
564 int reset = 1;
565
566 while (time_before(jiffies, timeout))
567 if (aty_pll_readupdate(par)) {
568 reset = 0;
569 break;
570 }
571
572 if (reset) /* reset engine?? */
573 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
574}
575
576
577/* tell PLL to update */
578static void aty_pll_writeupdate(const struct aty128fb_par *par)
579{
580 aty_pll_wait_readupdate(par);
581
582 aty_st_pll(PPLL_REF_DIV,
583 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
584}
585
586
587/* write to the scratch register to test r/w functionality */
588static int __init register_test(const struct aty128fb_par *par)
589{
590 u32 val;
591 int flag = 0;
592
593 val = aty_ld_le32(BIOS_0_SCRATCH);
594
595 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
596 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
597 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
598
599 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
600 flag = 1;
601 }
602
603 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
604 return flag;
605}
606
607
608/*
609 * Accelerator engine functions
610 */
611static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
612{
613 int i;
614
615 for (;;) {
616 for (i = 0; i < 2000000; i++) {
617 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
618 if (par->fifo_slots >= entries)
619 return;
620 }
621 aty128_reset_engine(par);
622 }
623}
624
625
626static void wait_for_idle(struct aty128fb_par *par)
627{
628 int i;
629
630 do_wait_for_fifo(64, par);
631
632 for (;;) {
633 for (i = 0; i < 2000000; i++) {
634 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
635 aty128_flush_pixel_cache(par);
636 par->blitter_may_be_busy = 0;
637 return;
638 }
639 }
640 aty128_reset_engine(par);
641 }
642}
643
644
645static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
646{
647 if (par->fifo_slots < entries)
648 do_wait_for_fifo(64, par);
649 par->fifo_slots -= entries;
650}
651
652
653static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
654{
655 int i;
656 u32 tmp;
657
658 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
659 tmp &= ~(0x00ff);
660 tmp |= 0x00ff;
661 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
662
663 for (i = 0; i < 2000000; i++)
664 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
665 break;
666}
667
668
669static void aty128_reset_engine(const struct aty128fb_par *par)
670{
671 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
672
673 aty128_flush_pixel_cache(par);
674
675 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
676 mclk_cntl = aty_ld_pll(MCLK_CNTL);
677
678 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
679
680 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
681 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
682 aty_ld_le32(GEN_RESET_CNTL);
683 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
684 aty_ld_le32(GEN_RESET_CNTL);
685
686 aty_st_pll(MCLK_CNTL, mclk_cntl);
687 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
688 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
689
690 /* use old pio mode */
691 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
692
693 DBG("engine reset");
694}
695
696
697static void aty128_init_engine(struct aty128fb_par *par)
698{
699 u32 pitch_value;
700
701 wait_for_idle(par);
702
703 /* 3D scaler not spoken here */
704 wait_for_fifo(1, par);
705 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
706
707 aty128_reset_engine(par);
708
709 pitch_value = par->crtc.pitch;
710 if (par->crtc.bpp == 24) {
711 pitch_value = pitch_value * 3;
712 }
713
714 wait_for_fifo(4, par);
715 /* setup engine offset registers */
716 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
717
718 /* setup engine pitch registers */
719 aty_st_le32(DEFAULT_PITCH, pitch_value);
720
721 /* set the default scissor register to max dimensions */
722 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
723
724 /* set the drawing controls registers */
725 aty_st_le32(DP_GUI_MASTER_CNTL,
726 GMC_SRC_PITCH_OFFSET_DEFAULT |
727 GMC_DST_PITCH_OFFSET_DEFAULT |
728 GMC_SRC_CLIP_DEFAULT |
729 GMC_DST_CLIP_DEFAULT |
730 GMC_BRUSH_SOLIDCOLOR |
731 (depth_to_dst(par->crtc.depth) << 8) |
732 GMC_SRC_DSTCOLOR |
733 GMC_BYTE_ORDER_MSB_TO_LSB |
734 GMC_DP_CONVERSION_TEMP_6500 |
735 ROP3_PATCOPY |
736 GMC_DP_SRC_RECT |
737 GMC_3D_FCN_EN_CLR |
738 GMC_DST_CLR_CMP_FCN_CLEAR |
739 GMC_AUX_CLIP_CLEAR |
740 GMC_WRITE_MASK_SET);
741
742 wait_for_fifo(8, par);
743 /* clear the line drawing registers */
744 aty_st_le32(DST_BRES_ERR, 0);
745 aty_st_le32(DST_BRES_INC, 0);
746 aty_st_le32(DST_BRES_DEC, 0);
747
748 /* set brush color registers */
749 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
750 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
751
752 /* set source color registers */
753 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
754 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
755
756 /* default write mask */
757 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
758
759 /* Wait for all the writes to be completed before returning */
760 wait_for_idle(par);
761}
762
763
764/* convert depth values to their register representation */
765static u32 depth_to_dst(u32 depth)
766{
767 if (depth <= 8)
768 return DST_8BPP;
769 else if (depth <= 15)
770 return DST_15BPP;
771 else if (depth == 16)
772 return DST_16BPP;
773 else if (depth <= 24)
774 return DST_24BPP;
775 else if (depth <= 32)
776 return DST_32BPP;
777
778 return -EINVAL;
779}
780
781/*
782 * PLL informations retreival
783 */
784
785
786#ifndef __sparc__
787static void __iomem * __init aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
788{
789 u16 dptr;
790 u8 rom_type;
791 void __iomem *bios;
792 size_t rom_size;
793
794 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
795 unsigned int temp;
796 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
797 temp &= 0x00ffffffu;
798 temp |= 0x04 << 24;
799 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
800 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
801
802 bios = pci_map_rom(dev, &rom_size);
803
804 if (!bios) {
805 printk(KERN_ERR "aty128fb: ROM failed to map\n");
806 return NULL;
807 }
808
809 /* Very simple test to make sure it appeared */
810 if (BIOS_IN16(0) != 0xaa55) {
811 printk(KERN_ERR "aty128fb: Invalid ROM signature %x should be 0xaa55\n",
812 BIOS_IN16(0));
813 goto failed;
814 }
815
816 /* Look for the PCI data to check the ROM type */
817 dptr = BIOS_IN16(0x18);
818
819 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
820 * for now, until I've verified this works everywhere. The goal here is more
821 * to phase out Open Firmware images.
822 *
823 * Currently, we only look at the first PCI data, we could iteratre and deal with
824 * them all, and we should use fb_bios_start relative to start of image and not
825 * relative start of ROM, but so far, I never found a dual-image ATI card
826 *
827 * typedef struct {
828 * u32 signature; + 0x00
829 * u16 vendor; + 0x04
830 * u16 device; + 0x06
831 * u16 reserved_1; + 0x08
832 * u16 dlen; + 0x0a
833 * u8 drevision; + 0x0c
834 * u8 class_hi; + 0x0d
835 * u16 class_lo; + 0x0e
836 * u16 ilen; + 0x10
837 * u16 irevision; + 0x12
838 * u8 type; + 0x14
839 * u8 indicator; + 0x15
840 * u16 reserved_2; + 0x16
841 * } pci_data_t;
842 */
843 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
844 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
845 BIOS_IN32(dptr));
846 goto anyway;
847 }
848 rom_type = BIOS_IN8(dptr + 0x14);
849 switch(rom_type) {
850 case 0:
851 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
852 break;
853 case 1:
854 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
855 goto failed;
856 case 2:
857 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
858 goto failed;
859 default:
860 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
861 goto failed;
862 }
863 anyway:
864 return bios;
865
866 failed:
867 pci_unmap_rom(dev, bios);
868 return NULL;
869}
870
871static void __init aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios)
872{
873 unsigned int bios_hdr;
874 unsigned int bios_pll;
875
876 bios_hdr = BIOS_IN16(0x48);
877 bios_pll = BIOS_IN16(bios_hdr + 0x30);
878
879 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
880 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
881 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
882 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
883 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
884
885 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
886 par->constants.ppll_max, par->constants.ppll_min,
887 par->constants.xclk, par->constants.ref_divider,
888 par->constants.ref_clk);
889
890}
891
892#ifdef CONFIG_X86
893static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
894{
895 /* I simplified this code as we used to miss the signatures in
896 * a lot of case. It's now closer to XFree, we just don't check
897 * for signatures at all... Something better will have to be done
898 * if we end up having conflicts
899 */
900 u32 segstart;
901 unsigned char __iomem *rom_base = NULL;
902
903 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
904 rom_base = ioremap(segstart, 0x10000);
905 if (rom_base == NULL)
906 return NULL;
907 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
908 break;
909 iounmap(rom_base);
910 rom_base = NULL;
911 }
912 return rom_base;
913}
914#endif
915#endif /* ndef(__sparc__) */
916
917/* fill in known card constants if pll_block is not available */
918static void __init aty128_timings(struct aty128fb_par *par)
919{
920#ifdef CONFIG_PPC_OF
921 /* instead of a table lookup, assume OF has properly
922 * setup the PLL registers and use their values
923 * to set the XCLK values and reference divider values */
924
925 u32 x_mpll_ref_fb_div;
926 u32 xclk_cntl;
927 u32 Nx, M;
928 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
929#endif
930
931 if (!par->constants.ref_clk)
932 par->constants.ref_clk = 2950;
933
934#ifdef CONFIG_PPC_OF
935 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
936 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
937 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
938 M = x_mpll_ref_fb_div & 0x0000ff;
939
940 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
941 (M * PostDivSet[xclk_cntl]));
942
943 par->constants.ref_divider =
944 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
945#endif
946
947 if (!par->constants.ref_divider) {
948 par->constants.ref_divider = 0x3b;
949
950 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
951 aty_pll_writeupdate(par);
952 }
953 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
954 aty_pll_writeupdate(par);
955
956 /* from documentation */
957 if (!par->constants.ppll_min)
958 par->constants.ppll_min = 12500;
959 if (!par->constants.ppll_max)
960 par->constants.ppll_max = 25000; /* 23000 on some cards? */
961 if (!par->constants.xclk)
962 par->constants.xclk = 0x1d4d; /* same as mclk */
963
964 par->constants.fifo_width = 128;
965 par->constants.fifo_depth = 32;
966
967 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
968 case 0:
969 par->mem = &sdr_128;
970 break;
971 case 1:
972 par->mem = &sdr_sgram;
973 break;
974 case 2:
975 par->mem = &ddr_sgram;
976 break;
977 default:
978 par->mem = &sdr_sgram;
979 }
980}
981
982
983
984/*
985 * CRTC programming
986 */
987
988/* Program the CRTC registers */
989static void aty128_set_crtc(const struct aty128_crtc *crtc,
990 const struct aty128fb_par *par)
991{
992 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
993 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
994 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
995 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
996 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
997 aty_st_le32(CRTC_PITCH, crtc->pitch);
998 aty_st_le32(CRTC_OFFSET, crtc->offset);
999 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1000 /* Disable ATOMIC updating. Is this the right place? */
1001 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1002}
1003
1004
1005static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1006 struct aty128_crtc *crtc,
1007 const struct aty128fb_par *par)
1008{
1009 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1010 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1011 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1012 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1013 u32 depth, bytpp;
1014 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1015
1016 /* input */
1017 xres = var->xres;
1018 yres = var->yres;
1019 vxres = var->xres_virtual;
1020 vyres = var->yres_virtual;
1021 xoffset = var->xoffset;
1022 yoffset = var->yoffset;
1023 bpp = var->bits_per_pixel;
1024 left = var->left_margin;
1025 right = var->right_margin;
1026 upper = var->upper_margin;
1027 lower = var->lower_margin;
1028 hslen = var->hsync_len;
1029 vslen = var->vsync_len;
1030 sync = var->sync;
1031 vmode = var->vmode;
1032
1033 if (bpp != 16)
1034 depth = bpp;
1035 else
1036 depth = (var->green.length == 6) ? 16 : 15;
1037
1038 /* check for mode eligibility
1039 * accept only non interlaced modes */
1040 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1041 return -EINVAL;
1042
1043 /* convert (and round up) and validate */
1044 xres = (xres + 7) & ~7;
1045 xoffset = (xoffset + 7) & ~7;
1046
1047 if (vxres < xres + xoffset)
1048 vxres = xres + xoffset;
1049
1050 if (vyres < yres + yoffset)
1051 vyres = yres + yoffset;
1052
1053 /* convert depth into ATI register depth */
1054 dst = depth_to_dst(depth);
1055
1056 if (dst == -EINVAL) {
1057 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1058 return -EINVAL;
1059 }
1060
1061 /* convert register depth to bytes per pixel */
1062 bytpp = mode_bytpp[dst];
1063
1064 /* make sure there is enough video ram for the mode */
1065 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1066 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1067 return -EINVAL;
1068 }
1069
1070 h_disp = (xres >> 3) - 1;
1071 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1072
1073 v_disp = yres - 1;
1074 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1075
1076 /* check to make sure h_total and v_total are in range */
1077 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1078 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1079 return -EINVAL;
1080 }
1081
1082 h_sync_wid = (hslen + 7) >> 3;
1083 if (h_sync_wid == 0)
1084 h_sync_wid = 1;
1085 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1086 h_sync_wid = 0x3f;
1087
1088 h_sync_strt = (h_disp << 3) + right;
1089
1090 v_sync_wid = vslen;
1091 if (v_sync_wid == 0)
1092 v_sync_wid = 1;
1093 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1094 v_sync_wid = 0x1f;
1095
1096 v_sync_strt = v_disp + lower;
1097
1098 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1099 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1100
1101 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1102
1103 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1104
1105 crtc->h_total = h_total | (h_disp << 16);
1106 crtc->v_total = v_total | (v_disp << 16);
1107
1108 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1109 (h_sync_pol << 23);
1110 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1111 (v_sync_pol << 23);
1112
1113 crtc->pitch = vxres >> 3;
1114
1115 crtc->offset = 0;
1116
1117 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1118 crtc->offset_cntl = 0x00010000;
1119 else
1120 crtc->offset_cntl = 0;
1121
1122 crtc->vxres = vxres;
1123 crtc->vyres = vyres;
1124 crtc->xoffset = xoffset;
1125 crtc->yoffset = yoffset;
1126 crtc->depth = depth;
1127 crtc->bpp = bpp;
1128
1129 return 0;
1130}
1131
1132
1133static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1134{
1135
1136 /* fill in pixel info */
1137 var->red.msb_right = 0;
1138 var->green.msb_right = 0;
1139 var->blue.offset = 0;
1140 var->blue.msb_right = 0;
1141 var->transp.offset = 0;
1142 var->transp.length = 0;
1143 var->transp.msb_right = 0;
1144 switch (pix_width) {
1145 case CRTC_PIX_WIDTH_8BPP:
1146 var->bits_per_pixel = 8;
1147 var->red.offset = 0;
1148 var->red.length = 8;
1149 var->green.offset = 0;
1150 var->green.length = 8;
1151 var->blue.length = 8;
1152 break;
1153 case CRTC_PIX_WIDTH_15BPP:
1154 var->bits_per_pixel = 16;
1155 var->red.offset = 10;
1156 var->red.length = 5;
1157 var->green.offset = 5;
1158 var->green.length = 5;
1159 var->blue.length = 5;
1160 break;
1161 case CRTC_PIX_WIDTH_16BPP:
1162 var->bits_per_pixel = 16;
1163 var->red.offset = 11;
1164 var->red.length = 5;
1165 var->green.offset = 5;
1166 var->green.length = 6;
1167 var->blue.length = 5;
1168 break;
1169 case CRTC_PIX_WIDTH_24BPP:
1170 var->bits_per_pixel = 24;
1171 var->red.offset = 16;
1172 var->red.length = 8;
1173 var->green.offset = 8;
1174 var->green.length = 8;
1175 var->blue.length = 8;
1176 break;
1177 case CRTC_PIX_WIDTH_32BPP:
1178 var->bits_per_pixel = 32;
1179 var->red.offset = 16;
1180 var->red.length = 8;
1181 var->green.offset = 8;
1182 var->green.length = 8;
1183 var->blue.length = 8;
1184 var->transp.offset = 24;
1185 var->transp.length = 8;
1186 break;
1187 default:
1188 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1189 return -EINVAL;
1190 }
1191
1192 return 0;
1193}
1194
1195
1196static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1197 struct fb_var_screeninfo *var)
1198{
1199 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1200 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1201 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1202 u32 pix_width;
1203
1204 /* fun with masking */
1205 h_total = crtc->h_total & 0x1ff;
1206 h_disp = (crtc->h_total >> 16) & 0xff;
1207 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1208 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1209 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1210 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1211 v_total = crtc->v_total & 0x7ff;
1212 v_disp = (crtc->v_total >> 16) & 0x7ff;
1213 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1214 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1215 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1216 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1217 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1218
1219 /* do conversions */
1220 xres = (h_disp + 1) << 3;
1221 yres = v_disp + 1;
1222 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1223 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1224 hslen = h_sync_wid << 3;
1225 upper = v_total - v_sync_strt - v_sync_wid;
1226 lower = v_sync_strt - v_disp;
1227 vslen = v_sync_wid;
1228 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1229 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1230 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1231
1232 aty128_pix_width_to_var(pix_width, var);
1233
1234 var->xres = xres;
1235 var->yres = yres;
1236 var->xres_virtual = crtc->vxres;
1237 var->yres_virtual = crtc->vyres;
1238 var->xoffset = crtc->xoffset;
1239 var->yoffset = crtc->yoffset;
1240 var->left_margin = left;
1241 var->right_margin = right;
1242 var->upper_margin = upper;
1243 var->lower_margin = lower;
1244 var->hsync_len = hslen;
1245 var->vsync_len = vslen;
1246 var->sync = sync;
1247 var->vmode = FB_VMODE_NONINTERLACED;
1248
1249 return 0;
1250}
1251
1252#ifdef CONFIG_PMAC_PBOOK
1253static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1254{
1255 if (on) {
1256 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1257 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1258 } else
1259 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1260}
1261
1262static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1263{
1264 u32 reg;
1265
1266 if (on) {
1267 reg = aty_ld_le32(LVDS_GEN_CNTL);
1268 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1269 reg &= ~LVDS_DISPLAY_DIS;
1270 aty_st_le32(LVDS_GEN_CNTL, reg);
1271#ifdef CONFIG_PMAC_BACKLIGHT
1272 aty128_set_backlight_enable(get_backlight_enable(),
1273 get_backlight_level(), par);
1274#endif
1275 } else {
1276#ifdef CONFIG_PMAC_BACKLIGHT
1277 aty128_set_backlight_enable(0, 0, par);
1278#endif
1279 reg = aty_ld_le32(LVDS_GEN_CNTL);
1280 reg |= LVDS_DISPLAY_DIS;
1281 aty_st_le32(LVDS_GEN_CNTL, reg);
1282 mdelay(100);
1283 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1284 aty_st_le32(LVDS_GEN_CNTL, reg);
1285 }
1286}
1287#endif /* CONFIG_PMAC_PBOOK */
1288
1289static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1290{
1291 u32 div3;
1292
1293 unsigned char post_conv[] = /* register values for post dividers */
1294 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1295
1296 /* select PPLL_DIV_3 */
1297 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1298
1299 /* reset PLL */
1300 aty_st_pll(PPLL_CNTL,
1301 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1302
1303 /* write the reference divider */
1304 aty_pll_wait_readupdate(par);
1305 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1306 aty_pll_writeupdate(par);
1307
1308 div3 = aty_ld_pll(PPLL_DIV_3);
1309 div3 &= ~PPLL_FB3_DIV_MASK;
1310 div3 |= pll->feedback_divider;
1311 div3 &= ~PPLL_POST3_DIV_MASK;
1312 div3 |= post_conv[pll->post_divider] << 16;
1313
1314 /* write feedback and post dividers */
1315 aty_pll_wait_readupdate(par);
1316 aty_st_pll(PPLL_DIV_3, div3);
1317 aty_pll_writeupdate(par);
1318
1319 aty_pll_wait_readupdate(par);
1320 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1321 aty_pll_writeupdate(par);
1322
1323 /* clear the reset, just in case */
1324 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1325}
1326
1327
1328static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1329 const struct aty128fb_par *par)
1330{
1331 const struct aty128_constants c = par->constants;
1332 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1333 u32 output_freq;
1334 u32 vclk; /* in .01 MHz */
1335 int i;
1336 u32 n, d;
1337
1338 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1339
1340 /* adjust pixel clock if necessary */
1341 if (vclk > c.ppll_max)
1342 vclk = c.ppll_max;
1343 if (vclk * 12 < c.ppll_min)
1344 vclk = c.ppll_min/12;
1345
1346 /* now, find an acceptable divider */
1347 for (i = 0; i < sizeof(post_dividers); i++) {
1348 output_freq = post_dividers[i] * vclk;
1349 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1350 break;
1351 }
1352
1353 /* calculate feedback divider */
1354 n = c.ref_divider * output_freq;
1355 d = c.ref_clk;
1356
1357 pll->post_divider = post_dividers[i];
1358 pll->feedback_divider = round_div(n, d);
1359 pll->vclk = vclk;
1360
1361 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1362 "vclk_per: %d\n", pll->post_divider,
1363 pll->feedback_divider, vclk, output_freq,
1364 c.ref_divider, period_in_ps);
1365
1366 return 0;
1367}
1368
1369
1370static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1371{
1372 var->pixclock = 100000000 / pll->vclk;
1373
1374 return 0;
1375}
1376
1377
1378static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1379 const struct aty128fb_par *par)
1380{
1381 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1382 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1383}
1384
1385
1386static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1387 const struct aty128_pll *pll,
1388 u32 depth,
1389 const struct aty128fb_par *par)
1390{
1391 const struct aty128_meminfo *m = par->mem;
1392 u32 xclk = par->constants.xclk;
1393 u32 fifo_width = par->constants.fifo_width;
1394 u32 fifo_depth = par->constants.fifo_depth;
1395 s32 x, b, p, ron, roff;
1396 u32 n, d, bpp;
1397
1398 /* round up to multiple of 8 */
1399 bpp = (depth+7) & ~7;
1400
1401 n = xclk * fifo_width;
1402 d = pll->vclk * bpp;
1403 x = round_div(n, d);
1404
1405 ron = 4 * m->MB +
1406 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1407 2 * m->Trp +
1408 m->Twr +
1409 m->CL +
1410 m->Tr2w +
1411 x;
1412
1413 DBG("x %x\n", x);
1414
1415 b = 0;
1416 while (x) {
1417 x >>= 1;
1418 b++;
1419 }
1420 p = b + 1;
1421
1422 ron <<= (11 - p);
1423
1424 n <<= (11 - p);
1425 x = round_div(n, d);
1426 roff = x * (fifo_depth - 4);
1427
1428 if ((ron + m->Rloop) >= roff) {
1429 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1430 return -EINVAL;
1431 }
1432
1433 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1434 p, m->Rloop, x, ron, roff);
1435
1436 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1437 dsp->dda_on_off = ron << 16 | roff;
1438
1439 return 0;
1440}
1441
1442
1443/*
1444 * This actually sets the video mode.
1445 */
1446static int aty128fb_set_par(struct fb_info *info)
1447{
1448 struct aty128fb_par *par = info->par;
1449 u32 config;
1450 int err;
1451
1452 if ((err = aty128_decode_var(&info->var, par)) != 0)
1453 return err;
1454
1455 if (par->blitter_may_be_busy)
1456 wait_for_idle(par);
1457
1458 /* clear all registers that may interfere with mode setting */
1459 aty_st_le32(OVR_CLR, 0);
1460 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1461 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1462 aty_st_le32(OV0_SCALE_CNTL, 0);
1463 aty_st_le32(MPP_TB_CONFIG, 0);
1464 aty_st_le32(MPP_GP_CONFIG, 0);
1465 aty_st_le32(SUBPIC_CNTL, 0);
1466 aty_st_le32(VIPH_CONTROL, 0);
1467 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1468 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1469 aty_st_le32(CAP0_TRIG_CNTL, 0);
1470 aty_st_le32(CAP1_TRIG_CNTL, 0);
1471
1472 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1473
1474 aty128_set_crtc(&par->crtc, par);
1475 aty128_set_pll(&par->pll, par);
1476 aty128_set_fifo(&par->fifo_reg, par);
1477
1478 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1479
1480#if defined(__BIG_ENDIAN)
1481 if (par->crtc.bpp == 32)
1482 config |= 2; /* make aperture do 32 bit swapping */
1483 else if (par->crtc.bpp == 16)
1484 config |= 1; /* make aperture do 16 bit swapping */
1485#endif
1486
1487 aty_st_le32(CONFIG_CNTL, config);
1488 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1489
1490 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1491 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1492 : FB_VISUAL_DIRECTCOLOR;
1493
1494#ifdef CONFIG_PMAC_PBOOK
1495 if (par->chip_gen == rage_M3) {
1496 aty128_set_crt_enable(par, par->crt_on);
1497 aty128_set_lcd_enable(par, par->lcd_on);
1498 }
1499#endif
1500 if (par->accel_flags & FB_ACCELF_TEXT)
1501 aty128_init_engine(par);
1502
1503#ifdef CONFIG_BOOTX_TEXT
1504 btext_update_display(info->fix.smem_start,
1505 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1506 ((par->crtc.v_total>>16) & 0x7ff)+1,
1507 par->crtc.bpp,
1508 par->crtc.vxres*par->crtc.bpp/8);
1509#endif /* CONFIG_BOOTX_TEXT */
1510
1511 return 0;
1512}
1513
1514/*
1515 * encode/decode the User Defined Part of the Display
1516 */
1517
1518static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1519{
1520 int err;
1521 struct aty128_crtc crtc;
1522 struct aty128_pll pll;
1523 struct aty128_ddafifo fifo_reg;
1524
1525 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1526 return err;
1527
1528 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1529 return err;
1530
1531 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1532 return err;
1533
1534 par->crtc = crtc;
1535 par->pll = pll;
1536 par->fifo_reg = fifo_reg;
1537 par->accel_flags = var->accel_flags;
1538
1539 return 0;
1540}
1541
1542
1543static int aty128_encode_var(struct fb_var_screeninfo *var,
1544 const struct aty128fb_par *par)
1545{
1546 int err;
1547
1548 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1549 return err;
1550
1551 if ((err = aty128_pll_to_var(&par->pll, var)))
1552 return err;
1553
1554 var->nonstd = 0;
1555 var->activate = 0;
1556
1557 var->height = -1;
1558 var->width = -1;
1559 var->accel_flags = par->accel_flags;
1560
1561 return 0;
1562}
1563
1564
1565static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1566{
1567 struct aty128fb_par par;
1568 int err;
1569
1570 par = *(struct aty128fb_par *)info->par;
1571 if ((err = aty128_decode_var(var, &par)) != 0)
1572 return err;
1573 aty128_encode_var(var, &par);
1574 return 0;
1575}
1576
1577
1578/*
1579 * Pan or Wrap the Display
1580 */
1581static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb)
1582{
1583 struct aty128fb_par *par = fb->par;
1584 u32 xoffset, yoffset;
1585 u32 offset;
1586 u32 xres, yres;
1587
1588 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1589 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1590
1591 xoffset = (var->xoffset +7) & ~7;
1592 yoffset = var->yoffset;
1593
1594 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1595 return -EINVAL;
1596
1597 par->crtc.xoffset = xoffset;
1598 par->crtc.yoffset = yoffset;
1599
1600 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1601
1602 if (par->crtc.bpp == 24)
1603 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1604
1605 aty_st_le32(CRTC_OFFSET, offset);
1606
1607 return 0;
1608}
1609
1610
1611/*
1612 * Helper function to store a single palette register
1613 */
1614static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1615 struct aty128fb_par *par)
1616{
1617 if (par->chip_gen == rage_M3) {
1618#if 0
1619 /* Note: For now, on M3, we set palette on both heads, which may
1620 * be useless. Can someone with a M3 check this ?
1621 *
1622 * This code would still be useful if using the second CRTC to
1623 * do mirroring
1624 */
1625
1626 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1627 aty_st_8(PALETTE_INDEX, regno);
1628 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1629#endif
1630 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1631 }
1632
1633 aty_st_8(PALETTE_INDEX, regno);
1634 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1635}
1636
1637static int aty128fb_sync(struct fb_info *info)
1638{
1639 struct aty128fb_par *par = info->par;
1640
1641 if (par->blitter_may_be_busy)
1642 wait_for_idle(par);
1643 return 0;
1644}
1645
1646#ifndef MODULE
1647static int __init aty128fb_setup(char *options)
1648{
1649 char *this_opt;
1650
1651 if (!options || !*options)
1652 return 0;
1653
1654 while ((this_opt = strsep(&options, ",")) != NULL) {
1655#ifdef CONFIG_PMAC_PBOOK
1656 if (!strncmp(this_opt, "lcd:", 4)) {
1657 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1658 continue;
1659 } else if (!strncmp(this_opt, "crt:", 4)) {
1660 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1661 continue;
1662 }
1663#endif
1664#ifdef CONFIG_MTRR
1665 if(!strncmp(this_opt, "nomtrr", 6)) {
1666 mtrr = 0;
1667 continue;
1668 }
1669#endif
1670#ifdef CONFIG_PPC_PMAC
1671 /* vmode and cmode deprecated */
1672 if (!strncmp(this_opt, "vmode:", 6)) {
1673 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1674 if (vmode > 0 && vmode <= VMODE_MAX)
1675 default_vmode = vmode;
1676 continue;
1677 } else if (!strncmp(this_opt, "cmode:", 6)) {
1678 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1679 switch (cmode) {
1680 case 0:
1681 case 8:
1682 default_cmode = CMODE_8;
1683 break;
1684 case 15:
1685 case 16:
1686 default_cmode = CMODE_16;
1687 break;
1688 case 24:
1689 case 32:
1690 default_cmode = CMODE_32;
1691 break;
1692 }
1693 continue;
1694 }
1695#endif /* CONFIG_PPC_PMAC */
1696 mode_option = this_opt;
1697 }
1698 return 0;
1699}
1700#endif /* MODULE */
1701
1702
1703/*
1704 * Initialisation
1705 */
1706
1707#ifdef CONFIG_PPC_PMAC
1708static void aty128_early_resume(void *data)
1709{
1710 struct aty128fb_par *par = data;
1711
1712 if (try_acquire_console_sem())
1713 return;
1714 aty128_do_resume(par->pdev);
1715 release_console_sem();
1716}
1717#endif /* CONFIG_PPC_PMAC */
1718
1719static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1720{
1721 struct fb_info *info = pci_get_drvdata(pdev);
1722 struct aty128fb_par *par = info->par;
1723 struct fb_var_screeninfo var;
1724 char video_card[DEVICE_NAME_SIZE];
1725 u8 chip_rev;
1726 u32 dac;
1727
1728 if (!par->vram_size) /* may have already been probed */
1729 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1730
1731 /* Get the chip revision */
1732 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1733
1734 strcpy(video_card, "Rage128 XX ");
1735 video_card[8] = ent->device >> 8;
1736 video_card[9] = ent->device & 0xFF;
1737
1738 /* range check to make sure */
1739 if (ent->driver_data < (sizeof(r128_family)/sizeof(char *)))
1740 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1741
1742 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1743
1744 if (par->vram_size % (1024 * 1024) == 0)
1745 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1746 else
1747 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1748
1749 par->chip_gen = ent->driver_data;
1750
1751 /* fill in info */
1752 info->fbops = &aty128fb_ops;
1753 info->flags = FBINFO_FLAG_DEFAULT;
1754
1755#ifdef CONFIG_PMAC_PBOOK
1756 par->lcd_on = default_lcd_on;
1757 par->crt_on = default_crt_on;
1758#endif
1759
1760 var = default_var;
1761#ifdef CONFIG_PPC_PMAC
1762 if (_machine == _MACH_Pmac) {
1763 /* Indicate sleep capability */
1764 if (par->chip_gen == rage_M3) {
1765 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1766 pmac_set_early_video_resume(aty128_early_resume, par);
1767 }
1768
1769 /* Find default mode */
1770 if (mode_option) {
1771 if (!mac_find_mode(&var, info, mode_option, 8))
1772 var = default_var;
1773 } else {
1774 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1775 default_vmode = VMODE_1024_768_60;
1776
1777 /* iMacs need that resolution
1778 * PowerMac2,1 first r128 iMacs
1779 * PowerMac2,2 summer 2000 iMacs
1780 * PowerMac4,1 january 2001 iMacs "flower power"
1781 */
1782 if (machine_is_compatible("PowerMac2,1") ||
1783 machine_is_compatible("PowerMac2,2") ||
1784 machine_is_compatible("PowerMac4,1"))
1785 default_vmode = VMODE_1024_768_75;
1786
1787 /* iBook SE */
1788 if (machine_is_compatible("PowerBook2,2"))
1789 default_vmode = VMODE_800_600_60;
1790
1791 /* PowerBook Firewire (Pismo), iBook Dual USB */
1792 if (machine_is_compatible("PowerBook3,1") ||
1793 machine_is_compatible("PowerBook4,1"))
1794 default_vmode = VMODE_1024_768_60;
1795
1796 /* PowerBook Titanium */
1797 if (machine_is_compatible("PowerBook3,2"))
1798 default_vmode = VMODE_1152_768_60;
1799
1800 if (default_cmode > 16)
1801 default_cmode = CMODE_32;
1802 else if (default_cmode > 8)
1803 default_cmode = CMODE_16;
1804 else
1805 default_cmode = CMODE_8;
1806
1807 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1808 var = default_var;
1809 }
1810 } else
1811#endif /* CONFIG_PPC_PMAC */
1812 {
1813 if (mode_option)
1814 if (fb_find_mode(&var, info, mode_option, NULL,
1815 0, &defaultmode, 8) == 0)
1816 var = default_var;
1817 }
1818
1819 var.accel_flags &= ~FB_ACCELF_TEXT;
1820// var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1821
1822 if (aty128fb_check_var(&var, info)) {
1823 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1824 return 0;
1825 }
1826
1827 /* setup the DAC the way we like it */
1828 dac = aty_ld_le32(DAC_CNTL);
1829 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1830 dac |= DAC_MASK;
1831 if (par->chip_gen == rage_M3)
1832 dac |= DAC_PALETTE2_SNOOP_EN;
1833 aty_st_le32(DAC_CNTL, dac);
1834
1835 /* turn off bus mastering, just in case */
1836 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1837
1838 info->var = var;
1839 fb_alloc_cmap(&info->cmap, 256, 0);
1840
1841 var.activate = FB_ACTIVATE_NOW;
1842
1843 aty128_init_engine(par);
1844
1845 if (register_framebuffer(info) < 0)
1846 return 0;
1847
1848#ifdef CONFIG_PMAC_BACKLIGHT
1849 /* Could be extended to Rage128Pro LVDS output too */
1850 if (par->chip_gen == rage_M3)
1851 register_backlight_controller(&aty128_backlight_controller, par, "ati");
1852#endif /* CONFIG_PMAC_BACKLIGHT */
1853
1854 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1855 par->pdev = pdev;
1856 par->asleep = 0;
1857 par->lock_blank = 0;
1858
1859 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1860 info->node, info->fix.id, video_card);
1861
1862 return 1; /* success! */
1863}
1864
1865#ifdef CONFIG_PCI
1866/* register a card ++ajoshi */
1867static int __init aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1868{
1869 unsigned long fb_addr, reg_addr;
1870 struct aty128fb_par *par;
1871 struct fb_info *info;
1872 int err;
1873#ifndef __sparc__
1874 void __iomem *bios = NULL;
1875#endif
1876
1877 /* Enable device in PCI config */
1878 if ((err = pci_enable_device(pdev))) {
1879 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
1880 err);
1881 return -ENODEV;
1882 }
1883
1884 fb_addr = pci_resource_start(pdev, 0);
1885 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
1886 "aty128fb FB")) {
1887 printk(KERN_ERR "aty128fb: cannot reserve frame "
1888 "buffer memory\n");
1889 return -ENODEV;
1890 }
1891
1892 reg_addr = pci_resource_start(pdev, 2);
1893 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
1894 "aty128fb MMIO")) {
1895 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
1896 goto err_free_fb;
1897 }
1898
1899 /* We have the resources. Now virtualize them */
1900 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
1901 if (info == NULL) {
1902 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
1903 goto err_free_mmio;
1904 }
1905 par = info->par;
1906
1907 info->pseudo_palette = par->pseudo_palette;
1908 info->fix = aty128fb_fix;
1909
1910 /* Virtualize mmio region */
1911 info->fix.mmio_start = reg_addr;
1912 par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2));
1913 if (!par->regbase)
1914 goto err_free_info;
1915
1916 /* Grab memory size from the card */
1917 // How does this relate to the resource length from the PCI hardware?
1918 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1919
1920 /* Virtualize the framebuffer */
1921 info->screen_base = ioremap(fb_addr, par->vram_size);
1922 if (!info->screen_base)
1923 goto err_unmap_out;
1924
1925 /* Set up info->fix */
1926 info->fix = aty128fb_fix;
1927 info->fix.smem_start = fb_addr;
1928 info->fix.smem_len = par->vram_size;
1929 info->fix.mmio_start = reg_addr;
1930
1931 /* If we can't test scratch registers, something is seriously wrong */
1932 if (!register_test(par)) {
1933 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
1934 goto err_out;
1935 }
1936
1937#ifndef __sparc__
1938 bios = aty128_map_ROM(par, pdev);
1939#ifdef CONFIG_X86
1940 if (bios == NULL)
1941 bios = aty128_find_mem_vbios(par);
1942#endif
1943 if (bios == NULL)
1944 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
1945 else {
1946 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
1947 aty128_get_pllinfo(par, bios);
1948 pci_unmap_rom(pdev, bios);
1949 }
1950#endif /* __sparc__ */
1951
1952 aty128_timings(par);
1953 pci_set_drvdata(pdev, info);
1954
1955 if (!aty128_init(pdev, ent))
1956 goto err_out;
1957
1958#ifdef CONFIG_MTRR
1959 if (mtrr) {
1960 par->mtrr.vram = mtrr_add(info->fix.smem_start,
1961 par->vram_size, MTRR_TYPE_WRCOMB, 1);
1962 par->mtrr.vram_valid = 1;
1963 /* let there be speed */
1964 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
1965 }
1966#endif /* CONFIG_MTRR */
1967 return 0;
1968
1969err_out:
1970 iounmap(info->screen_base);
1971err_unmap_out:
1972 iounmap(par->regbase);
1973err_free_info:
1974 framebuffer_release(info);
1975err_free_mmio:
1976 release_mem_region(pci_resource_start(pdev, 2),
1977 pci_resource_len(pdev, 2));
1978err_free_fb:
1979 release_mem_region(pci_resource_start(pdev, 0),
1980 pci_resource_len(pdev, 0));
1981 return -ENODEV;
1982}
1983
1984static void __devexit aty128_remove(struct pci_dev *pdev)
1985{
1986 struct fb_info *info = pci_get_drvdata(pdev);
1987 struct aty128fb_par *par;
1988
1989 if (!info)
1990 return;
1991
1992 par = info->par;
1993
1994 unregister_framebuffer(info);
1995#ifdef CONFIG_MTRR
1996 if (par->mtrr.vram_valid)
1997 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1998 par->vram_size);
1999#endif /* CONFIG_MTRR */
2000 iounmap(par->regbase);
2001 iounmap(info->screen_base);
2002
2003 release_mem_region(pci_resource_start(pdev, 0),
2004 pci_resource_len(pdev, 0));
2005 release_mem_region(pci_resource_start(pdev, 2),
2006 pci_resource_len(pdev, 2));
2007 framebuffer_release(info);
2008}
2009#endif /* CONFIG_PCI */
2010
2011
2012
2013 /*
2014 * Blank the display.
2015 */
2016static int aty128fb_blank(int blank, struct fb_info *fb)
2017{
2018 struct aty128fb_par *par = fb->par;
2019 u8 state = 0;
2020
2021 if (par->lock_blank || par->asleep)
2022 return 0;
2023
2024#ifdef CONFIG_PMAC_BACKLIGHT
2025 if ((_machine == _MACH_Pmac) && blank)
2026 set_backlight_enable(0);
2027#endif /* CONFIG_PMAC_BACKLIGHT */
2028
2029 if (blank & FB_BLANK_VSYNC_SUSPEND)
2030 state |= 2;
2031 if (blank & FB_BLANK_HSYNC_SUSPEND)
2032 state |= 1;
2033 if (blank & FB_BLANK_POWERDOWN)
2034 state |= 4;
2035
2036 aty_st_8(CRTC_EXT_CNTL+1, state);
2037
2038#ifdef CONFIG_PMAC_PBOOK
2039 if (par->chip_gen == rage_M3) {
2040 aty128_set_crt_enable(par, par->crt_on && !blank);
2041 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2042 }
2043#endif
2044#ifdef CONFIG_PMAC_BACKLIGHT
2045 if ((_machine == _MACH_Pmac) && !blank)
2046 set_backlight_enable(1);
2047#endif /* CONFIG_PMAC_BACKLIGHT */
2048 return 0;
2049}
2050
2051/*
2052 * Set a single color register. The values supplied are already
2053 * rounded down to the hardware's capabilities (according to the
2054 * entries in the var structure). Return != 0 for invalid regno.
2055 */
2056static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2057 u_int transp, struct fb_info *info)
2058{
2059 struct aty128fb_par *par = info->par;
2060
2061 if (regno > 255
2062 || (par->crtc.depth == 16 && regno > 63)
2063 || (par->crtc.depth == 15 && regno > 31))
2064 return 1;
2065
2066 red >>= 8;
2067 green >>= 8;
2068 blue >>= 8;
2069
2070 if (regno < 16) {
2071 int i;
2072 u32 *pal = info->pseudo_palette;
2073
2074 switch (par->crtc.depth) {
2075 case 15:
2076 pal[regno] = (regno << 10) | (regno << 5) | regno;
2077 break;
2078 case 16:
2079 pal[regno] = (regno << 11) | (regno << 6) | regno;
2080 break;
2081 case 24:
2082 pal[regno] = (regno << 16) | (regno << 8) | regno;
2083 break;
2084 case 32:
2085 i = (regno << 8) | regno;
2086 pal[regno] = (i << 16) | i;
2087 break;
2088 }
2089 }
2090
2091 if (par->crtc.depth == 16 && regno > 0) {
2092 /*
2093 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2094 * have 32 slots for R and B values but 64 slots for G values.
2095 * Thus the R and B values go in one slot but the G value
2096 * goes in a different slot, and we have to avoid disturbing
2097 * the other fields in the slots we touch.
2098 */
2099 par->green[regno] = green;
2100 if (regno < 32) {
2101 par->red[regno] = red;
2102 par->blue[regno] = blue;
2103 aty128_st_pal(regno * 8, red, par->green[regno*2],
2104 blue, par);
2105 }
2106 red = par->red[regno/2];
2107 blue = par->blue[regno/2];
2108 regno <<= 2;
2109 } else if (par->crtc.bpp == 16)
2110 regno <<= 3;
2111 aty128_st_pal(regno, red, green, blue, par);
2112
2113 return 0;
2114}
2115
2116#define ATY_MIRROR_LCD_ON 0x00000001
2117#define ATY_MIRROR_CRT_ON 0x00000002
2118
2119/* out param: u32* backlight value: 0 to 15 */
2120#define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2121/* in param: u32* backlight value: 0 to 15 */
2122#define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2123
2124static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
2125 u_long arg, struct fb_info *info)
2126{
2127#ifdef CONFIG_PMAC_PBOOK
2128 struct aty128fb_par *par = info->par;
2129 u32 value;
2130 int rc;
2131
2132 switch (cmd) {
2133 case FBIO_ATY128_SET_MIRROR:
2134 if (par->chip_gen != rage_M3)
2135 return -EINVAL;
2136 rc = get_user(value, (__u32 __user *)arg);
2137 if (rc)
2138 return rc;
2139 par->lcd_on = (value & 0x01) != 0;
2140 par->crt_on = (value & 0x02) != 0;
2141 if (!par->crt_on && !par->lcd_on)
2142 par->lcd_on = 1;
2143 aty128_set_crt_enable(par, par->crt_on);
2144 aty128_set_lcd_enable(par, par->lcd_on);
2145 return 0;
2146 case FBIO_ATY128_GET_MIRROR:
2147 if (par->chip_gen != rage_M3)
2148 return -EINVAL;
2149 value = (par->crt_on << 1) | par->lcd_on;
2150 return put_user(value, (__u32 __user *)arg);
2151 }
2152#endif
2153 return -EINVAL;
2154}
2155
2156#ifdef CONFIG_PMAC_BACKLIGHT
2157static int backlight_conv[] = {
2158 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2159 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2160};
2161
2162/* We turn off the LCD completely instead of just dimming the backlight.
2163 * This provides greater power saving and the display is useless without
2164 * backlight anyway
2165 */
2166#define BACKLIGHT_LVDS_OFF
2167/* That one prevents proper CRT output with LCD off */
2168#undef BACKLIGHT_DAC_OFF
2169
2170static int aty128_set_backlight_enable(int on, int level, void *data)
2171{
2172 struct aty128fb_par *par = data;
2173 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
2174
2175 if (!par->lcd_on)
2176 on = 0;
2177 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
2178 if (on && level > BACKLIGHT_OFF) {
2179 reg |= LVDS_DIGION;
2180 if (!(reg & LVDS_ON)) {
2181 reg &= ~LVDS_BLON;
2182 aty_st_le32(LVDS_GEN_CNTL, reg);
2183 (void)aty_ld_le32(LVDS_GEN_CNTL);
2184 mdelay(10);
2185 reg |= LVDS_BLON;
2186 aty_st_le32(LVDS_GEN_CNTL, reg);
2187 }
2188 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2189 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT);
2190#ifdef BACKLIGHT_LVDS_OFF
2191 reg |= LVDS_ON | LVDS_EN;
2192 reg &= ~LVDS_DISPLAY_DIS;
2193#endif
2194 aty_st_le32(LVDS_GEN_CNTL, reg);
2195#ifdef BACKLIGHT_DAC_OFF
2196 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
2197#endif
2198 } else {
2199 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2200 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT);
2201#ifdef BACKLIGHT_LVDS_OFF
2202 reg |= LVDS_DISPLAY_DIS;
2203 aty_st_le32(LVDS_GEN_CNTL, reg);
2204 (void)aty_ld_le32(LVDS_GEN_CNTL);
2205 udelay(10);
2206 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
2207#endif
2208 aty_st_le32(LVDS_GEN_CNTL, reg);
2209#ifdef BACKLIGHT_DAC_OFF
2210 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
2211#endif
2212 }
2213
2214 return 0;
2215}
2216
2217static int aty128_set_backlight_level(int level, void* data)
2218{
2219 return aty128_set_backlight_enable(1, level, data);
2220}
2221#endif /* CONFIG_PMAC_BACKLIGHT */
2222
2223#if 0
2224 /*
2225 * Accelerated functions
2226 */
2227
2228static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2229 u_int width, u_int height,
2230 struct fb_info_aty128 *par)
2231{
2232 u32 save_dp_datatype, save_dp_cntl, dstval;
2233
2234 if (!width || !height)
2235 return;
2236
2237 dstval = depth_to_dst(par->current_par.crtc.depth);
2238 if (dstval == DST_24BPP) {
2239 srcx *= 3;
2240 dstx *= 3;
2241 width *= 3;
2242 } else if (dstval == -EINVAL) {
2243 printk("aty128fb: invalid depth or RGBA\n");
2244 return;
2245 }
2246
2247 wait_for_fifo(2, par);
2248 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2249 save_dp_cntl = aty_ld_le32(DP_CNTL);
2250
2251 wait_for_fifo(6, par);
2252 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2253 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2254 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2255 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2256
2257 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2258 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2259
2260 par->blitter_may_be_busy = 1;
2261
2262 wait_for_fifo(2, par);
2263 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2264 aty_st_le32(DP_CNTL, save_dp_cntl);
2265}
2266
2267
2268 /*
2269 * Text mode accelerated functions
2270 */
2271
2272static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2273 int height, int width)
2274{
2275 sx *= fontwidth(p);
2276 sy *= fontheight(p);
2277 dx *= fontwidth(p);
2278 dy *= fontheight(p);
2279 width *= fontwidth(p);
2280 height *= fontheight(p);
2281
2282 aty128_rectcopy(sx, sy, dx, dy, width, height,
2283 (struct fb_info_aty128 *)p->fb_info);
2284}
2285#endif /* 0 */
2286
2287static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2288{
2289 u32 pmgt;
2290 u16 pwr_command;
2291 struct pci_dev *pdev = par->pdev;
2292
2293 if (!par->pm_reg)
2294 return;
2295
2296 /* Set the chip into the appropriate suspend mode (we use D2,
2297 * D3 would require a complete re-initialisation of the chip,
2298 * including PCI config registers, clocks, AGP configuration, ...)
2299 */
2300 if (suspend) {
2301 /* Make sure CRTC2 is reset. Remove that the day we decide to
2302 * actually use CRTC2 and replace it with real code for disabling
2303 * the CRTC2 output during sleep
2304 */
2305 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2306 ~(CRTC2_EN));
2307
2308 /* Set the power management mode to be PCI based */
2309 /* Use this magic value for now */
2310 pmgt = 0x0c005407;
2311 aty_st_pll(POWER_MANAGEMENT, pmgt);
2312 (void)aty_ld_pll(POWER_MANAGEMENT);
2313 aty_st_le32(BUS_CNTL1, 0x00000010);
2314 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2315 mdelay(100);
2316 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2317 /* Switch PCI power management to D2 */
2318 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
2319 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2320 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2321 } else {
2322 /* Switch back PCI power management to D0 */
2323 mdelay(100);
2324 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2325 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2326 mdelay(100);
2327 }
2328}
2329
2330static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2331{
2332 struct fb_info *info = pci_get_drvdata(pdev);
2333 struct aty128fb_par *par = info->par;
2334 u8 agp;
2335
2336 /* We don't do anything but D2, for now we return 0, but
2337 * we may want to change that. How do we know if the BIOS
2338 * can properly take care of D3 ? Also, with swsusp, we
2339 * know we'll be rebooted, ...
2340 */
2341#ifdef CONFIG_PPC_PMAC
2342 /* HACK ALERT ! Once I find a proper way to say to each driver
2343 * individually what will happen with it's PCI slot, I'll change
2344 * that. On laptops, the AGP slot is just unclocked, so D2 is
2345 * expected, while on desktops, the card is powered off
2346 */
2347 if (state >= 3)
2348 state = 2;
2349#endif /* CONFIG_PPC_PMAC */
2350
2351 if (state != 2 || state == pdev->dev.power.power_state)
2352 return 0;
2353
2354 printk(KERN_DEBUG "aty128fb: suspending...\n");
2355
2356 acquire_console_sem();
2357
2358 fb_set_suspend(info, 1);
2359
2360 /* Make sure engine is reset */
2361 wait_for_idle(par);
2362 aty128_reset_engine(par);
2363 wait_for_idle(par);
2364
2365 /* Blank display and LCD */
2366 aty128fb_blank(VESA_POWERDOWN, info);
2367
2368 /* Sleep */
2369 par->asleep = 1;
2370 par->lock_blank = 1;
2371
2372 /* Disable AGP. The AGP host should have done it, but since ordering
2373 * isn't always properly guaranteed in this specific case, let's make
2374 * sure it's disabled on card side now. Ultimately, when merging fbdev
2375 * and dri into some common infrastructure, this will be handled
2376 * more nicely. The host bridge side will (or will not) be dealt with
2377 * by the bridge AGP driver, we don't attempt to touch it here.
2378 */
2379 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2380 if (agp) {
2381 u32 cmd;
2382
2383 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
2384 if (cmd & PCI_AGP_COMMAND_AGP) {
2385 printk(KERN_INFO "aty128fb: AGP was enabled, "
2386 "disabling ...\n");
2387 cmd &= ~PCI_AGP_COMMAND_AGP;
2388 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND,
2389 cmd);
2390 }
2391 }
2392
2393 /* We need a way to make sure the fbdev layer will _not_ touch the
2394 * framebuffer before we put the chip to suspend state. On 2.4, I
2395 * used dummy fb ops, 2.5 need proper support for this at the
2396 * fbdev level
2397 */
2398 if (state == 2)
2399 aty128_set_suspend(par, 1);
2400
2401 release_console_sem();
2402
2403 pdev->dev.power.power_state = state;
2404
2405 return 0;
2406}
2407
2408static int aty128_do_resume(struct pci_dev *pdev)
2409{
2410 struct fb_info *info = pci_get_drvdata(pdev);
2411 struct aty128fb_par *par = info->par;
2412
2413 if (pdev->dev.power.power_state == 0)
2414 return 0;
2415
2416 /* Wakeup chip */
2417 if (pdev->dev.power.power_state == 2)
2418 aty128_set_suspend(par, 0);
2419 par->asleep = 0;
2420
2421 /* Restore display & engine */
2422 aty128_reset_engine(par);
2423 wait_for_idle(par);
2424 aty128fb_set_par(info);
2425 fb_pan_display(info, &info->var);
2426 fb_set_cmap(&info->cmap, info);
2427
2428 /* Refresh */
2429 fb_set_suspend(info, 0);
2430
2431 /* Unblank */
2432 par->lock_blank = 0;
2433 aty128fb_blank(0, info);
2434
2435 pdev->dev.power.power_state = PMSG_ON;
2436
2437 printk(KERN_DEBUG "aty128fb: resumed !\n");
2438
2439 return 0;
2440}
2441
2442static int aty128_pci_resume(struct pci_dev *pdev)
2443{
2444 int rc;
2445
2446 acquire_console_sem();
2447 rc = aty128_do_resume(pdev);
2448 release_console_sem();
2449
2450 return rc;
2451}
2452
2453
2454static int __init aty128fb_init(void)
2455{
2456#ifndef MODULE
2457 char *option = NULL;
2458
2459 if (fb_get_options("aty128fb", &option))
2460 return -ENODEV;
2461 aty128fb_setup(option);
2462#endif
2463
2464 return pci_register_driver(&aty128fb_driver);
2465}
2466
2467static void __exit aty128fb_exit(void)
2468{
2469 pci_unregister_driver(&aty128fb_driver);
2470}
2471
2472module_init(aty128fb_init);
2473
2474module_exit(aty128fb_exit);
2475
2476MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2477MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2478MODULE_LICENSE("GPL");
2479module_param(mode_option, charp, 0);
2480MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2481#ifdef CONFIG_MTRR
2482module_param_named(nomtrr, mtrr, invbool, 0);
2483MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2484#endif
2485
diff --git a/drivers/video/aty/atyfb.h b/drivers/video/aty/atyfb.h
new file mode 100644
index 000000000000..09de173c1164
--- /dev/null
+++ b/drivers/video/aty/atyfb.h
@@ -0,0 +1,359 @@
1/*
2 * ATI Frame Buffer Device Driver Core Definitions
3 */
4
5#include <linux/config.h>
6#include <linux/spinlock.h>
7#include <linux/wait.h>
8 /*
9 * Elements of the hardware specific atyfb_par structure
10 */
11
12struct crtc {
13 u32 vxres;
14 u32 vyres;
15 u32 xoffset;
16 u32 yoffset;
17 u32 bpp;
18 u32 h_tot_disp;
19 u32 h_sync_strt_wid;
20 u32 v_tot_disp;
21 u32 v_sync_strt_wid;
22 u32 vline_crnt_vline;
23 u32 off_pitch;
24 u32 gen_cntl;
25 u32 dp_pix_width; /* acceleration */
26 u32 dp_chain_mask; /* acceleration */
27#ifdef CONFIG_FB_ATY_GENERIC_LCD
28 u32 horz_stretching;
29 u32 vert_stretching;
30 u32 ext_vert_stretch;
31 u32 shadow_h_tot_disp;
32 u32 shadow_h_sync_strt_wid;
33 u32 shadow_v_tot_disp;
34 u32 shadow_v_sync_strt_wid;
35 u32 lcd_gen_cntl;
36 u32 lcd_config_panel;
37 u32 lcd_index;
38#endif
39};
40
41struct aty_interrupt {
42 wait_queue_head_t wait;
43 unsigned int count;
44 int pan_display;
45};
46
47struct pll_info {
48 int pll_max;
49 int pll_min;
50 int sclk, mclk, mclk_pm, xclk;
51 int ref_div;
52 int ref_clk;
53};
54
55typedef struct {
56 u16 unknown1;
57 u16 PCLK_min_freq;
58 u16 PCLK_max_freq;
59 u16 unknown2;
60 u16 ref_freq;
61 u16 ref_divider;
62 u16 unknown3;
63 u16 MCLK_pwd;
64 u16 MCLK_max_freq;
65 u16 XCLK_max_freq;
66 u16 SCLK_freq;
67} __attribute__ ((packed)) PLL_BLOCK_MACH64;
68
69struct pll_514 {
70 u8 m;
71 u8 n;
72};
73
74struct pll_18818 {
75 u32 program_bits;
76 u32 locationAddr;
77 u32 period_in_ps;
78 u32 post_divider;
79};
80
81struct pll_ct {
82 u8 pll_ref_div;
83 u8 pll_gen_cntl;
84 u8 mclk_fb_div;
85 u8 mclk_fb_mult; /* 2 ro 4 */
86 u8 sclk_fb_div;
87 u8 pll_vclk_cntl;
88 u8 vclk_post_div;
89 u8 vclk_fb_div;
90 u8 pll_ext_cntl;
91 u8 ext_vpll_cntl;
92 u8 spll_cntl2;
93 u32 dsp_config; /* Mach64 GTB DSP */
94 u32 dsp_on_off; /* Mach64 GTB DSP */
95 u32 dsp_loop_latency;
96 u32 fifo_size;
97 u32 xclkpagefaultdelay;
98 u32 xclkmaxrasdelay;
99 u8 xclk_ref_div;
100 u8 xclk_post_div;
101 u8 mclk_post_div_real;
102 u8 xclk_post_div_real;
103 u8 vclk_post_div_real;
104 u8 features;
105#ifdef CONFIG_FB_ATY_GENERIC_LCD
106 u32 xres; /* use for LCD stretching/scaling */
107#endif
108};
109
110/*
111 for pll_ct.features
112*/
113#define DONT_USE_SPLL 0x1
114#define DONT_USE_XDLL 0x2
115#define USE_CPUCLK 0x4
116#define POWERDOWN_PLL 0x8
117
118union aty_pll {
119 struct pll_ct ct;
120 struct pll_514 ibm514;
121 struct pll_18818 ics2595;
122};
123
124 /*
125 * The hardware parameters for each card
126 */
127
128struct atyfb_par {
129 struct aty_cmap_regs __iomem *aty_cmap_regs;
130 struct { u8 red, green, blue; } palette[256];
131 const struct aty_dac_ops *dac_ops;
132 const struct aty_pll_ops *pll_ops;
133 void __iomem *ati_regbase;
134 unsigned long clk_wr_offset; /* meaning overloaded, clock id by CT */
135 struct crtc crtc;
136 union aty_pll pll;
137 struct pll_info pll_limits;
138 u32 features;
139 u32 ref_clk_per;
140 u32 pll_per;
141 u32 mclk_per;
142 u32 xclk_per;
143 u8 bus_type;
144 u8 ram_type;
145 u8 mem_refresh_rate;
146 u16 pci_id;
147 u32 accel_flags;
148 int blitter_may_be_busy;
149 int asleep;
150 int lock_blank;
151 unsigned long res_start;
152 unsigned long res_size;
153#ifdef __sparc__
154 struct pci_mmap_map *mmap_map;
155 u8 mmaped;
156#endif
157 int open;
158#ifdef CONFIG_FB_ATY_GENERIC_LCD
159 unsigned long bios_base_phys;
160 unsigned long bios_base;
161 unsigned long lcd_table;
162 u16 lcd_width;
163 u16 lcd_height;
164 u32 lcd_pixclock;
165 u16 lcd_refreshrate;
166 u16 lcd_htotal;
167 u16 lcd_hdisp;
168 u16 lcd_hsync_dly;
169 u16 lcd_hsync_len;
170 u16 lcd_vtotal;
171 u16 lcd_vdisp;
172 u16 lcd_vsync_len;
173 u16 lcd_right_margin;
174 u16 lcd_lower_margin;
175 u16 lcd_hblank_len;
176 u16 lcd_vblank_len;
177#endif
178 unsigned long aux_start; /* auxiliary aperture */
179 unsigned long aux_size;
180 struct aty_interrupt vblank;
181 unsigned long irq_flags;
182 unsigned int irq;
183 spinlock_t int_lock;
184#ifdef CONFIG_MTRR
185 int mtrr_aper;
186 int mtrr_reg;
187#endif
188};
189
190 /*
191 * ATI Mach64 features
192 */
193
194#define M64_HAS(feature) ((par)->features & (M64F_##feature))
195
196#define M64F_RESET_3D 0x00000001
197#define M64F_MAGIC_FIFO 0x00000002
198#define M64F_GTB_DSP 0x00000004
199#define M64F_FIFO_32 0x00000008
200#define M64F_SDRAM_MAGIC_PLL 0x00000010
201#define M64F_MAGIC_POSTDIV 0x00000020
202#define M64F_INTEGRATED 0x00000040
203#define M64F_CT_BUS 0x00000080
204#define M64F_VT_BUS 0x00000100
205#define M64F_MOBIL_BUS 0x00000200
206#define M64F_GX 0x00000400
207#define M64F_CT 0x00000800
208#define M64F_VT 0x00001000
209#define M64F_GT 0x00002000
210#define M64F_MAGIC_VRAM_SIZE 0x00004000
211#define M64F_G3_PB_1_1 0x00008000
212#define M64F_G3_PB_1024x768 0x00010000
213#define M64F_EXTRA_BRIGHT 0x00020000
214#define M64F_LT_LCD_REGS 0x00040000
215#define M64F_XL_DLL 0x00080000
216#define M64F_MFB_FORCE_4 0x00100000
217#define M64F_HW_TRIPLE 0x00200000
218 /*
219 * Register access
220 */
221
222static inline u32 aty_ld_le32(int regindex, const struct atyfb_par *par)
223{
224 /* Hack for bloc 1, should be cleanly optimized by compiler */
225 if (regindex >= 0x400)
226 regindex -= 0x800;
227
228#ifdef CONFIG_ATARI
229 return in_le32((volatile u32 *)(par->ati_regbase + regindex));
230#else
231 return readl(par->ati_regbase + regindex);
232#endif
233}
234
235static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par)
236{
237 /* Hack for bloc 1, should be cleanly optimized by compiler */
238 if (regindex >= 0x400)
239 regindex -= 0x800;
240
241#ifdef CONFIG_ATARI
242 out_le32((volatile u32 *)(par->ati_regbase + regindex), val);
243#else
244 writel(val, par->ati_regbase + regindex);
245#endif
246}
247
248static inline void aty_st_le16(int regindex, u16 val,
249 const struct atyfb_par *par)
250{
251 /* Hack for bloc 1, should be cleanly optimized by compiler */
252 if (regindex >= 0x400)
253 regindex -= 0x800;
254#ifdef CONFIG_ATARI
255 out_le16((volatile u16 *)(par->ati_regbase + regindex), val);
256#else
257 writel(val, par->ati_regbase + regindex);
258#endif
259}
260
261static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
262{
263 /* Hack for bloc 1, should be cleanly optimized by compiler */
264 if (regindex >= 0x400)
265 regindex -= 0x800;
266#ifdef CONFIG_ATARI
267 return in_8(par->ati_regbase + regindex);
268#else
269 return readb(par->ati_regbase + regindex);
270#endif
271}
272
273static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par)
274{
275 /* Hack for bloc 1, should be cleanly optimized by compiler */
276 if (regindex >= 0x400)
277 regindex -= 0x800;
278
279#ifdef CONFIG_ATARI
280 out_8(par->ati_regbase + regindex, val);
281#else
282 writeb(val, par->ati_regbase + regindex);
283#endif
284}
285
286#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
287extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par);
288extern u32 aty_ld_lcd(int index, const struct atyfb_par *par);
289#endif
290
291 /*
292 * DAC operations
293 */
294
295struct aty_dac_ops {
296 int (*set_dac) (const struct fb_info * info,
297 const union aty_pll * pll, u32 bpp, u32 accel);
298};
299
300extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
301extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
302extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
303extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
304extern const struct aty_dac_ops aty_dac_ct; /* Integrated */
305
306
307 /*
308 * Clock operations
309 */
310
311struct aty_pll_ops {
312 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
313 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
314 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
315 void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
316 int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
317};
318
319extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
320extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
321extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
322extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
323extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
324extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
325extern const struct aty_pll_ops aty_pll_ct; /* Integrated */
326
327
328extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
329extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
330
331
332 /*
333 * Hardware cursor support
334 */
335
336extern int aty_init_cursor(struct fb_info *info);
337
338 /*
339 * Hardware acceleration
340 */
341
342static inline void wait_for_fifo(u16 entries, const struct atyfb_par *par)
343{
344 while ((aty_ld_le32(FIFO_STAT, par) & 0xffff) >
345 ((u32) (0x8000 >> entries)));
346}
347
348static inline void wait_for_idle(struct atyfb_par *par)
349{
350 wait_for_fifo(16, par);
351 while ((aty_ld_le32(GUI_STAT, par) & 1) != 0);
352 par->blitter_may_be_busy = 0;
353}
354
355extern void aty_reset_engine(const struct atyfb_par *par);
356extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info);
357extern int atyfb_xl_init(struct fb_info *info);
358extern void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par);
359extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c
new file mode 100644
index 000000000000..8c42538dc8c1
--- /dev/null
+++ b/drivers/video/aty/atyfb_base.c
@@ -0,0 +1,3720 @@
1/*
2 * ATI Frame Buffer Device Driver Core
3 *
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
8 *
9 * This driver supports the following ATI graphics chips:
10 * - ATI Mach64
11 *
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
15 *
16 * This driver is partly based on the PowerMac console driver:
17 *
18 * Copyright (C) 1996 Paul Mackerras
19 *
20 * and on the PowerMac ATI/mach64 display driver:
21 *
22 * Copyright (C) 1997 Michael AK Tesch
23 *
24 * with work by Jon Howell
25 * Harry AC Eaton
26 * Anthony Tong <atong@uiuc.edu>
27 *
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30 *
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
33 * more details.
34 *
35 * Many thanks to Nitya from ATI devrel for support and patience !
36 */
37
38/******************************************************************************
39
40 TODO:
41
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
46
47 (Anyone with Mac to help with this?)
48
49******************************************************************************/
50
51
52#include <linux/config.h>
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/kernel.h>
56#include <linux/errno.h>
57#include <linux/string.h>
58#include <linux/mm.h>
59#include <linux/slab.h>
60#include <linux/vmalloc.h>
61#include <linux/delay.h>
62#include <linux/console.h>
63#include <linux/fb.h>
64#include <linux/init.h>
65#include <linux/pci.h>
66#include <linux/interrupt.h>
67#include <linux/spinlock.h>
68#include <linux/wait.h>
69
70#include <asm/io.h>
71#include <asm/uaccess.h>
72
73#include <video/mach64.h>
74#include "atyfb.h"
75#include "ati_ids.h"
76
77#ifdef __powerpc__
78#include <asm/prom.h>
79#include "../macmodes.h"
80#endif
81#ifdef __sparc__
82#include <asm/pbm.h>
83#include <asm/fbio.h>
84#endif
85
86#ifdef CONFIG_ADB_PMU
87#include <linux/adb.h>
88#include <linux/pmu.h>
89#endif
90#ifdef CONFIG_BOOTX_TEXT
91#include <asm/btext.h>
92#endif
93#ifdef CONFIG_PMAC_BACKLIGHT
94#include <asm/backlight.h>
95#endif
96#ifdef CONFIG_MTRR
97#include <asm/mtrr.h>
98#endif
99
100/*
101 * Debug flags.
102 */
103#undef DEBUG
104/*#define DEBUG*/
105
106/* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
107/* - must be large enough to catch all GUI-Regs */
108/* - must be aligned to a PAGE boundary */
109#define GUI_RESERVE (1 * PAGE_SIZE)
110
111/* FIXME: remove the FAIL definition */
112#define FAIL(msg) do { printk(KERN_CRIT "atyfb: " msg "\n"); return -EINVAL; } while (0)
113#define FAIL_MAX(msg, x, _max_) do { if(x > _max_) { printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); return -EINVAL; } } while (0)
114
115#ifdef DEBUG
116#define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
117#else
118#define DPRINTK(fmt, args...)
119#endif
120
121#define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
122#define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
123
124#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
125static const u32 lt_lcd_regs[] = {
126 CONFIG_PANEL_LG,
127 LCD_GEN_CNTL_LG,
128 DSTN_CONTROL_LG,
129 HFB_PITCH_ADDR_LG,
130 HORZ_STRETCHING_LG,
131 VERT_STRETCHING_LG,
132 0, /* EXT_VERT_STRETCH */
133 LT_GIO_LG,
134 POWER_MANAGEMENT_LG
135};
136
137void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
138{
139 if (M64_HAS(LT_LCD_REGS)) {
140 aty_st_le32(lt_lcd_regs[index], val, par);
141 } else {
142 unsigned long temp;
143
144 /* write addr byte */
145 temp = aty_ld_le32(LCD_INDEX, par);
146 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
147 /* write the register value */
148 aty_st_le32(LCD_DATA, val, par);
149 }
150}
151
152u32 aty_ld_lcd(int index, const struct atyfb_par *par)
153{
154 if (M64_HAS(LT_LCD_REGS)) {
155 return aty_ld_le32(lt_lcd_regs[index], par);
156 } else {
157 unsigned long temp;
158
159 /* write addr byte */
160 temp = aty_ld_le32(LCD_INDEX, par);
161 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
162 /* read the register value */
163 return aty_ld_le32(LCD_DATA, par);
164 }
165}
166#endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
167
168#ifdef CONFIG_FB_ATY_GENERIC_LCD
169/*
170 * ATIReduceRatio --
171 *
172 * Reduce a fraction by factoring out the largest common divider of the
173 * fraction's numerator and denominator.
174 */
175static void ATIReduceRatio(int *Numerator, int *Denominator)
176{
177 int Multiplier, Divider, Remainder;
178
179 Multiplier = *Numerator;
180 Divider = *Denominator;
181
182 while ((Remainder = Multiplier % Divider))
183 {
184 Multiplier = Divider;
185 Divider = Remainder;
186 }
187
188 *Numerator /= Divider;
189 *Denominator /= Divider;
190}
191#endif
192 /*
193 * The Hardware parameters for each card
194 */
195
196struct aty_cmap_regs {
197 u8 windex;
198 u8 lut;
199 u8 mask;
200 u8 rindex;
201 u8 cntl;
202};
203
204struct pci_mmap_map {
205 unsigned long voff;
206 unsigned long poff;
207 unsigned long size;
208 unsigned long prot_flag;
209 unsigned long prot_mask;
210};
211
212static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
213 .id = "ATY Mach64",
214 .type = FB_TYPE_PACKED_PIXELS,
215 .visual = FB_VISUAL_PSEUDOCOLOR,
216 .xpanstep = 8,
217 .ypanstep = 1,
218};
219
220 /*
221 * Frame buffer device API
222 */
223
224static int atyfb_open(struct fb_info *info, int user);
225static int atyfb_release(struct fb_info *info, int user);
226static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
227static int atyfb_set_par(struct fb_info *info);
228static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
229 u_int transp, struct fb_info *info);
230static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
231static int atyfb_blank(int blank, struct fb_info *info);
232static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
233 u_long arg, struct fb_info *info);
234extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
235extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
236extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
237#ifdef __sparc__
238static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
239#endif
240static int atyfb_sync(struct fb_info *info);
241
242 /*
243 * Internal routines
244 */
245
246static int aty_init(struct fb_info *info, const char *name);
247#ifdef CONFIG_ATARI
248static int store_video_par(char *videopar, unsigned char m64_num);
249#endif
250
251static struct crtc saved_crtc;
252static union aty_pll saved_pll;
253static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
254
255static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
256static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
257static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
258static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
259#ifdef CONFIG_PPC
260static int read_aty_sense(const struct atyfb_par *par);
261#endif
262
263
264 /*
265 * Interface used by the world
266 */
267
268static struct fb_var_screeninfo default_var = {
269 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
270 640, 480, 640, 480, 0, 0, 8, 0,
271 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
272 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
273 0, FB_VMODE_NONINTERLACED
274};
275
276static struct fb_videomode defmode = {
277 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
278 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
279 0, FB_VMODE_NONINTERLACED
280};
281
282static struct fb_ops atyfb_ops = {
283 .owner = THIS_MODULE,
284 .fb_open = atyfb_open,
285 .fb_release = atyfb_release,
286 .fb_check_var = atyfb_check_var,
287 .fb_set_par = atyfb_set_par,
288 .fb_setcolreg = atyfb_setcolreg,
289 .fb_pan_display = atyfb_pan_display,
290 .fb_blank = atyfb_blank,
291 .fb_ioctl = atyfb_ioctl,
292 .fb_fillrect = atyfb_fillrect,
293 .fb_copyarea = atyfb_copyarea,
294 .fb_imageblit = atyfb_imageblit,
295 .fb_cursor = soft_cursor,
296#ifdef __sparc__
297 .fb_mmap = atyfb_mmap,
298#endif
299 .fb_sync = atyfb_sync,
300};
301
302static int noaccel;
303#ifdef CONFIG_MTRR
304static int nomtrr;
305#endif
306static int vram;
307static int pll;
308static int mclk;
309static int xclk;
310static int comp_sync __initdata = -1;
311static char *mode;
312
313#ifdef CONFIG_PPC
314static int default_vmode __initdata = VMODE_CHOOSE;
315static int default_cmode __initdata = CMODE_CHOOSE;
316
317module_param_named(vmode, default_vmode, int, 0);
318MODULE_PARM_DESC(vmode, "int: video mode for mac");
319module_param_named(cmode, default_cmode, int, 0);
320MODULE_PARM_DESC(cmode, "int: color mode for mac");
321#endif
322
323#ifdef CONFIG_ATARI
324static unsigned int mach64_count __initdata = 0;
325static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
326static unsigned long phys_size[FB_MAX] __initdata = { 0, };
327static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
328#endif
329
330/* top -> down is an evolution of mach64 chipset, any corrections? */
331#define ATI_CHIP_88800GX (M64F_GX)
332#define ATI_CHIP_88800CX (M64F_GX)
333
334#define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
335#define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
336
337#define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
338#define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
339
340#define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
341#define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
342#define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
343
344#define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
345
346/* make sets shorter */
347#define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
348
349#define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
350/*#define ATI_CHIP_264GTDVD ?*/
351#define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
352
353#define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
354#define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
355#define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
356
357#define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
358#define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
359
360static struct {
361 u16 pci_id;
362 const char *name;
363 int pll, mclk, xclk;
364 u32 features;
365} aty_chips[] __devinitdata = {
366#ifdef CONFIG_FB_ATY_GX
367 /* Mach64 GX */
368 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX },
369 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX },
370#endif /* CONFIG_FB_ATY_GX */
371
372#ifdef CONFIG_FB_ATY_CT
373 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT },
374 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET },
375 { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT },
376 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT },
377 /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
378 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB },
379 { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 },
380
381 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT },
382 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
383 { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
384
385 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 },
386
387 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
388 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
389 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
390 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
391
392 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO },
393 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO },
394 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
395 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO },
396 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO },
397
398 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO },
399 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO },
400 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
401 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
402 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
403
404 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL },
405 { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL },
406 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL },
407 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 230, 83, 63, ATI_CHIP_264XL },
408 { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL },
409 { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL },
410
411 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
412 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
413 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
414 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
415#endif /* CONFIG_FB_ATY_CT */
416};
417
418/* can not fail */
419static int __devinit correct_chipset(struct atyfb_par *par)
420{
421 u8 rev;
422 u16 type;
423 u32 chip_id;
424 const char *name;
425 int i;
426
427 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
428 if (par->pci_id == aty_chips[i].pci_id)
429 break;
430
431 name = aty_chips[i].name;
432 par->pll_limits.pll_max = aty_chips[i].pll;
433 par->pll_limits.mclk = aty_chips[i].mclk;
434 par->pll_limits.xclk = aty_chips[i].xclk;
435 par->features = aty_chips[i].features;
436
437 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
438 type = chip_id & CFG_CHIP_TYPE;
439 rev = (chip_id & CFG_CHIP_REV) >> 24;
440
441 switch(par->pci_id) {
442#ifdef CONFIG_FB_ATY_GX
443 case PCI_CHIP_MACH64GX:
444 if(type != 0x00d7)
445 return -ENODEV;
446 break;
447 case PCI_CHIP_MACH64CX:
448 if(type != 0x0057)
449 return -ENODEV;
450 break;
451#endif
452#ifdef CONFIG_FB_ATY_CT
453 case PCI_CHIP_MACH64VT:
454 rev &= 0xc7;
455 if(rev == 0x00) {
456 name = "ATI264VTA3 (Mach64 VT)";
457 par->pll_limits.pll_max = 170;
458 par->pll_limits.mclk = 67;
459 par->pll_limits.xclk = 67;
460 par->features = ATI_CHIP_264VT;
461 } else if(rev == 0x40) {
462 name = "ATI264VTA4 (Mach64 VT)";
463 par->pll_limits.pll_max = 200;
464 par->pll_limits.mclk = 67;
465 par->pll_limits.xclk = 67;
466 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
467 } else {
468 name = "ATI264VTB (Mach64 VT)";
469 par->pll_limits.pll_max = 200;
470 par->pll_limits.mclk = 67;
471 par->pll_limits.xclk = 67;
472 par->features = ATI_CHIP_264VTB;
473 }
474 break;
475 case PCI_CHIP_MACH64GT:
476 rev &= 0x07;
477 if(rev == 0x01) {
478 par->pll_limits.pll_max = 170;
479 par->pll_limits.mclk = 67;
480 par->pll_limits.xclk = 67;
481 par->features = ATI_CHIP_264GTB;
482 } else if(rev == 0x02) {
483 par->pll_limits.pll_max = 200;
484 par->pll_limits.mclk = 67;
485 par->pll_limits.xclk = 67;
486 par->features = ATI_CHIP_264GTB;
487 }
488 break;
489#endif
490 }
491
492 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
493 return 0;
494}
495
496static char ram_dram[] __devinitdata = "DRAM";
497static char ram_resv[] __devinitdata = "RESV";
498#ifdef CONFIG_FB_ATY_GX
499static char ram_vram[] __devinitdata = "VRAM";
500#endif /* CONFIG_FB_ATY_GX */
501#ifdef CONFIG_FB_ATY_CT
502static char ram_edo[] __devinitdata = "EDO";
503static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
504static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
505static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
506static char ram_off[] __devinitdata = "OFF";
507#endif /* CONFIG_FB_ATY_CT */
508
509
510static u32 pseudo_palette[17];
511
512#ifdef CONFIG_FB_ATY_GX
513static char *aty_gx_ram[8] __devinitdata = {
514 ram_dram, ram_vram, ram_vram, ram_dram,
515 ram_dram, ram_vram, ram_vram, ram_resv
516};
517#endif /* CONFIG_FB_ATY_GX */
518
519#ifdef CONFIG_FB_ATY_CT
520static char *aty_ct_ram[8] __devinitdata = {
521 ram_off, ram_dram, ram_edo, ram_edo,
522 ram_sdram, ram_sgram, ram_sdram32, ram_resv
523};
524#endif /* CONFIG_FB_ATY_CT */
525
526static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
527{
528 u32 pixclock = var->pixclock;
529#ifdef CONFIG_FB_ATY_GENERIC_LCD
530 u32 lcd_on_off;
531 par->pll.ct.xres = 0;
532 if (par->lcd_table != 0) {
533 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
534 if(lcd_on_off & LCD_ON) {
535 par->pll.ct.xres = var->xres;
536 pixclock = par->lcd_pixclock;
537 }
538 }
539#endif
540 return pixclock;
541}
542
543#if defined(CONFIG_PPC)
544
545/*
546 * Apple monitor sense
547 */
548
549static int __init read_aty_sense(const struct atyfb_par *par)
550{
551 int sense, i;
552
553 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
554 __delay(200);
555 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
556 __delay(2000);
557 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
558 sense = ((i & 0x3000) >> 3) | (i & 0x100);
559
560 /* drive each sense line low in turn and collect the other 2 */
561 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
562 __delay(2000);
563 i = aty_ld_le32(GP_IO, par);
564 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
565 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
566 __delay(200);
567
568 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
569 __delay(2000);
570 i = aty_ld_le32(GP_IO, par);
571 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
572 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
573 __delay(200);
574
575 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
576 __delay(2000);
577 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
578 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
579 return sense;
580}
581
582#endif /* defined(CONFIG_PPC) */
583
584/* ------------------------------------------------------------------------- */
585
586/*
587 * CRTC programming
588 */
589
590static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
591{
592#ifdef CONFIG_FB_ATY_GENERIC_LCD
593 if (par->lcd_table != 0) {
594 if(!M64_HAS(LT_LCD_REGS)) {
595 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
596 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
597 }
598 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
599 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
600
601
602 /* switch to non shadow registers */
603 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
604 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
605
606 /* save stretching */
607 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
608 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
609 if (!M64_HAS(LT_LCD_REGS))
610 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
611 }
612#endif
613 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
614 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
615 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
616 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
617 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
618 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
619 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
620
621#ifdef CONFIG_FB_ATY_GENERIC_LCD
622 if (par->lcd_table != 0) {
623 /* switch to shadow registers */
624 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
625 SHADOW_EN | SHADOW_RW_EN, par);
626
627 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
628 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
629 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
630 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
631
632 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
633 }
634#endif /* CONFIG_FB_ATY_GENERIC_LCD */
635}
636
637static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
638{
639#ifdef CONFIG_FB_ATY_GENERIC_LCD
640 if (par->lcd_table != 0) {
641 /* stop CRTC */
642 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
643
644 /* update non-shadow registers first */
645 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
646 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
647 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
648
649 /* temporarily disable stretching */
650 aty_st_lcd(HORZ_STRETCHING,
651 crtc->horz_stretching &
652 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
653 aty_st_lcd(VERT_STRETCHING,
654 crtc->vert_stretching &
655 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
656 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
657 }
658#endif
659 /* turn off CRT */
660 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
661
662 DPRINTK("setting up CRTC\n");
663 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
664 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
665 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
666 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
667
668 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
669 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
670 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
671 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
672 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
673 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
674 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
675
676 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
677 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
678 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
679 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
680 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
681 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
682
683 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
684#if 0
685 FIXME
686 if (par->accel_flags & FB_ACCELF_TEXT)
687 aty_init_engine(par, info);
688#endif
689#ifdef CONFIG_FB_ATY_GENERIC_LCD
690 /* after setting the CRTC registers we should set the LCD registers. */
691 if (par->lcd_table != 0) {
692 /* switch to shadow registers */
693 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
694 (SHADOW_EN | SHADOW_RW_EN), par);
695
696 DPRINTK("set secondary CRT to %ix%i %c%c\n",
697 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
698 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
699
700 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
701 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
702 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
703 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
704
705 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
706 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
707 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
708 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
709
710 /* restore CRTC selection & shadow state and enable stretching */
711 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
712 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
713 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
714 if(!M64_HAS(LT_LCD_REGS))
715 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
716
717 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
718 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
719 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
720 if(!M64_HAS(LT_LCD_REGS)) {
721 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
722 aty_ld_le32(LCD_INDEX, par);
723 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
724 }
725 }
726#endif /* CONFIG_FB_ATY_GENERIC_LCD */
727}
728
729static int aty_var_to_crtc(const struct fb_info *info,
730 const struct fb_var_screeninfo *var, struct crtc *crtc)
731{
732 struct atyfb_par *par = (struct atyfb_par *) info->par;
733 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
734 u32 sync, vmode, vdisplay;
735 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
736 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
737 u32 pix_width, dp_pix_width, dp_chain_mask;
738
739 /* input */
740 xres = var->xres;
741 yres = var->yres;
742 vxres = var->xres_virtual;
743 vyres = var->yres_virtual;
744 xoffset = var->xoffset;
745 yoffset = var->yoffset;
746 bpp = var->bits_per_pixel;
747 if (bpp == 16)
748 bpp = (var->green.length == 5) ? 15 : 16;
749 sync = var->sync;
750 vmode = var->vmode;
751
752 /* convert (and round up) and validate */
753 if (vxres < xres + xoffset)
754 vxres = xres + xoffset;
755 h_disp = xres;
756
757 if (vyres < yres + yoffset)
758 vyres = yres + yoffset;
759 v_disp = yres;
760
761 if (bpp <= 8) {
762 bpp = 8;
763 pix_width = CRTC_PIX_WIDTH_8BPP;
764 dp_pix_width =
765 HOST_8BPP | SRC_8BPP | DST_8BPP |
766 BYTE_ORDER_LSB_TO_MSB;
767 dp_chain_mask = DP_CHAIN_8BPP;
768 } else if (bpp <= 15) {
769 bpp = 16;
770 pix_width = CRTC_PIX_WIDTH_15BPP;
771 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
772 BYTE_ORDER_LSB_TO_MSB;
773 dp_chain_mask = DP_CHAIN_15BPP;
774 } else if (bpp <= 16) {
775 bpp = 16;
776 pix_width = CRTC_PIX_WIDTH_16BPP;
777 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
778 BYTE_ORDER_LSB_TO_MSB;
779 dp_chain_mask = DP_CHAIN_16BPP;
780 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
781 bpp = 24;
782 pix_width = CRTC_PIX_WIDTH_24BPP;
783 dp_pix_width =
784 HOST_8BPP | SRC_8BPP | DST_8BPP |
785 BYTE_ORDER_LSB_TO_MSB;
786 dp_chain_mask = DP_CHAIN_24BPP;
787 } else if (bpp <= 32) {
788 bpp = 32;
789 pix_width = CRTC_PIX_WIDTH_32BPP;
790 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
791 BYTE_ORDER_LSB_TO_MSB;
792 dp_chain_mask = DP_CHAIN_32BPP;
793 } else
794 FAIL("invalid bpp");
795
796 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
797 FAIL("not enough video RAM");
798
799 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
800 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
801
802 if((xres > 1600) || (yres > 1200)) {
803 FAIL("MACH64 chips are designed for max 1600x1200\n"
804 "select anoter resolution.");
805 }
806 h_sync_strt = h_disp + var->right_margin;
807 h_sync_end = h_sync_strt + var->hsync_len;
808 h_sync_dly = var->right_margin & 7;
809 h_total = h_sync_end + h_sync_dly + var->left_margin;
810
811 v_sync_strt = v_disp + var->lower_margin;
812 v_sync_end = v_sync_strt + var->vsync_len;
813 v_total = v_sync_end + var->upper_margin;
814
815#ifdef CONFIG_FB_ATY_GENERIC_LCD
816 if (par->lcd_table != 0) {
817 if(!M64_HAS(LT_LCD_REGS)) {
818 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
819 crtc->lcd_index = lcd_index &
820 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
821 aty_st_le32(LCD_INDEX, lcd_index, par);
822 }
823
824 if (!M64_HAS(MOBIL_BUS))
825 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
826
827 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
828 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
829
830 crtc->lcd_gen_cntl &=
831 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
832 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
833 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
834 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
835
836 if((crtc->lcd_gen_cntl & LCD_ON) &&
837 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
838 /* We cannot display the mode on the LCD. If the CRT is enabled
839 we can turn off the LCD.
840 If the CRT is off, it isn't a good idea to switch it on; we don't
841 know if one is connected. So it's better to fail then.
842 */
843 if (crtc->lcd_gen_cntl & CRT_ON) {
844 PRINTKI("Disable lcd panel, because video mode does not fit.\n");
845 crtc->lcd_gen_cntl &= ~LCD_ON;
846 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
847 } else {
848 FAIL("Video mode exceeds size of lcd panel.\nConnect this computer to a conventional monitor if you really need this mode.");
849 }
850 }
851 }
852
853 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
854 int VScan = 1;
855 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
856 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
857 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
858
859 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
860
861 /* This is horror! When we simulate, say 640x480 on an 800x600
862 lcd monitor, the CRTC should be programmed 800x600 values for
863 the non visible part, but 640x480 for the visible part.
864 This code has been tested on a laptop with it's 1400x1050 lcd
865 monitor and a conventional monitor both switched on.
866 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
867 works with little glitches also with DOUBLESCAN modes
868 */
869 if (yres < par->lcd_height) {
870 VScan = par->lcd_height / yres;
871 if(VScan > 1) {
872 VScan = 2;
873 vmode |= FB_VMODE_DOUBLE;
874 }
875 }
876
877 h_sync_strt = h_disp + par->lcd_right_margin;
878 h_sync_end = h_sync_strt + par->lcd_hsync_len;
879 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
880 h_total = h_disp + par->lcd_hblank_len;
881
882 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
883 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
884 v_total = v_disp + par->lcd_vblank_len / VScan;
885 }
886#endif /* CONFIG_FB_ATY_GENERIC_LCD */
887
888 h_disp = (h_disp >> 3) - 1;
889 h_sync_strt = (h_sync_strt >> 3) - 1;
890 h_sync_end = (h_sync_end >> 3) - 1;
891 h_total = (h_total >> 3) - 1;
892 h_sync_wid = h_sync_end - h_sync_strt;
893
894 FAIL_MAX("h_disp too large", h_disp, 0xff);
895 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
896 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
897 if(h_sync_wid > 0x1f)
898 h_sync_wid = 0x1f;
899 FAIL_MAX("h_total too large", h_total, 0x1ff);
900
901 if (vmode & FB_VMODE_DOUBLE) {
902 v_disp <<= 1;
903 v_sync_strt <<= 1;
904 v_sync_end <<= 1;
905 v_total <<= 1;
906 }
907
908 vdisplay = yres;
909#ifdef CONFIG_FB_ATY_GENERIC_LCD
910 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
911 vdisplay = par->lcd_height;
912#endif
913
914 if(vdisplay < 400) {
915 h_sync_pol = 1;
916 v_sync_pol = 0;
917 } else if(vdisplay < 480) {
918 h_sync_pol = 0;
919 v_sync_pol = 1;
920 } else if(vdisplay < 768) {
921 h_sync_pol = 0;
922 v_sync_pol = 0;
923 } else {
924 h_sync_pol = 1;
925 v_sync_pol = 1;
926 }
927
928 v_disp--;
929 v_sync_strt--;
930 v_sync_end--;
931 v_total--;
932 v_sync_wid = v_sync_end - v_sync_strt;
933
934 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
935 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
936 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
937 if(v_sync_wid > 0x1f)
938 v_sync_wid = 0x1f;
939 FAIL_MAX("v_total too large", v_total, 0x7ff);
940
941 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
942
943 /* output */
944 crtc->vxres = vxres;
945 crtc->vyres = vyres;
946 crtc->xoffset = xoffset;
947 crtc->yoffset = yoffset;
948 crtc->bpp = bpp;
949 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
950 crtc->vline_crnt_vline = 0;
951
952 crtc->h_tot_disp = h_total | (h_disp<<16);
953 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
954 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
955 crtc->v_tot_disp = v_total | (v_disp<<16);
956 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
957
958 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
959 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
960 crtc->gen_cntl |= CRTC_VGA_LINEAR;
961
962 /* Enable doublescan mode if requested */
963 if (vmode & FB_VMODE_DOUBLE)
964 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
965 /* Enable interlaced mode if requested */
966 if (vmode & FB_VMODE_INTERLACED)
967 crtc->gen_cntl |= CRTC_INTERLACE_EN;
968#ifdef CONFIG_FB_ATY_GENERIC_LCD
969 if (par->lcd_table != 0) {
970 vdisplay = yres;
971 if(vmode & FB_VMODE_DOUBLE)
972 vdisplay <<= 1;
973 if(vmode & FB_VMODE_INTERLACED) {
974 vdisplay >>= 1;
975
976 /* The prefered mode for the lcd is not interlaced, so disable it if
977 it was enabled. For doublescan there is no problem, because we can
978 compensate for it in the hardware stretching (we stretch half as much)
979 */
980 vmode &= ~FB_VMODE_INTERLACED;
981 /*crtc->gen_cntl &= ~CRTC_INTERLACE_EN;*/
982 }
983 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
984 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
985 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
986 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
987 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
988
989 /* MOBILITY M1 tested, FIXME: LT */
990 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
991 if (!M64_HAS(LT_LCD_REGS))
992 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
993 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
994
995 crtc->horz_stretching &=
996 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
997 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
998 if (xres < par->lcd_width) {
999 do {
1000 /*
1001 * The horizontal blender misbehaves when HDisplay is less than a
1002 * a certain threshold (440 for a 1024-wide panel). It doesn't
1003 * stretch such modes enough. Use pixel replication instead of
1004 * blending to stretch modes that can be made to exactly fit the
1005 * panel width. The undocumented "NoLCDBlend" option allows the
1006 * pixel-replicated mode to be slightly wider or narrower than the
1007 * panel width. It also causes a mode that is exactly half as wide
1008 * as the panel to be pixel-replicated, rather than blended.
1009 */
1010 int HDisplay = xres & ~7;
1011 int nStretch = par->lcd_width / HDisplay;
1012 int Remainder = par->lcd_width % HDisplay;
1013
1014 if ((!Remainder && ((nStretch > 2))) ||
1015 (((HDisplay * 16) / par->lcd_width) < 7)) {
1016 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1017 int horz_stretch_loop = -1, BestRemainder;
1018 int Numerator = HDisplay, Denominator = par->lcd_width;
1019 int Index = 5;
1020 ATIReduceRatio(&Numerator, &Denominator);
1021
1022 BestRemainder = (Numerator * 16) / Denominator;
1023 while (--Index >= 0) {
1024 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1025 Denominator;
1026 if (Remainder < BestRemainder) {
1027 horz_stretch_loop = Index;
1028 if (!(BestRemainder = Remainder))
1029 break;
1030 }
1031 }
1032
1033 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1034 int horz_stretch_ratio = 0, Accumulator = 0;
1035 int reuse_previous = 1;
1036
1037 Index = StretchLoops[horz_stretch_loop];
1038
1039 while (--Index >= 0) {
1040 if (Accumulator > 0)
1041 horz_stretch_ratio |= reuse_previous;
1042 else
1043 Accumulator += Denominator;
1044 Accumulator -= Numerator;
1045 reuse_previous <<= 1;
1046 }
1047
1048 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1049 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1050 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1051 break; /* Out of the do { ... } while (0) */
1052 }
1053 }
1054
1055 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1056 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1057 } while (0);
1058 }
1059
1060 if (vdisplay < par->lcd_height) {
1061 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1062 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1063
1064 if (!M64_HAS(LT_LCD_REGS) &&
1065 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1066 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1067 } else {
1068 /*
1069 * Don't use vertical blending if the mode is too wide or not
1070 * vertically stretched.
1071 */
1072 crtc->vert_stretching = 0;
1073 }
1074 /* copy to shadow crtc */
1075 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1076 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1077 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1078 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1079 }
1080#endif /* CONFIG_FB_ATY_GENERIC_LCD */
1081
1082 if (M64_HAS(MAGIC_FIFO)) {
1083 /* Not VTB/GTB */
1084 /* FIXME: magic FIFO values */
1085 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC2_PIX_WIDTH);
1086 }
1087 crtc->dp_pix_width = dp_pix_width;
1088 crtc->dp_chain_mask = dp_chain_mask;
1089
1090 return 0;
1091}
1092
1093static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1094{
1095 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1096 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1097 h_sync_pol;
1098 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1099 u32 pix_width;
1100 u32 double_scan, interlace;
1101
1102 /* input */
1103 h_total = crtc->h_tot_disp & 0x1ff;
1104 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1105 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1106 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1107 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1108 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1109 v_total = crtc->v_tot_disp & 0x7ff;
1110 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1111 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1112 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1113 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1114 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1115 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1116 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1117 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1118
1119 /* convert */
1120 xres = (h_disp + 1) * 8;
1121 yres = v_disp + 1;
1122 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1123 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1124 hslen = h_sync_wid * 8;
1125 upper = v_total - v_sync_strt - v_sync_wid;
1126 lower = v_sync_strt - v_disp;
1127 vslen = v_sync_wid;
1128 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1129 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1130 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1131
1132 switch (pix_width) {
1133#if 0
1134 case CRTC_PIX_WIDTH_4BPP:
1135 bpp = 4;
1136 var->red.offset = 0;
1137 var->red.length = 8;
1138 var->green.offset = 0;
1139 var->green.length = 8;
1140 var->blue.offset = 0;
1141 var->blue.length = 8;
1142 var->transp.offset = 0;
1143 var->transp.length = 0;
1144 break;
1145#endif
1146 case CRTC_PIX_WIDTH_8BPP:
1147 bpp = 8;
1148 var->red.offset = 0;
1149 var->red.length = 8;
1150 var->green.offset = 0;
1151 var->green.length = 8;
1152 var->blue.offset = 0;
1153 var->blue.length = 8;
1154 var->transp.offset = 0;
1155 var->transp.length = 0;
1156 break;
1157 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1158 bpp = 16;
1159 var->red.offset = 10;
1160 var->red.length = 5;
1161 var->green.offset = 5;
1162 var->green.length = 5;
1163 var->blue.offset = 0;
1164 var->blue.length = 5;
1165 var->transp.offset = 0;
1166 var->transp.length = 0;
1167 break;
1168 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1169 bpp = 16;
1170 var->red.offset = 11;
1171 var->red.length = 5;
1172 var->green.offset = 5;
1173 var->green.length = 6;
1174 var->blue.offset = 0;
1175 var->blue.length = 5;
1176 var->transp.offset = 0;
1177 var->transp.length = 0;
1178 break;
1179 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1180 bpp = 24;
1181 var->red.offset = 16;
1182 var->red.length = 8;
1183 var->green.offset = 8;
1184 var->green.length = 8;
1185 var->blue.offset = 0;
1186 var->blue.length = 8;
1187 var->transp.offset = 0;
1188 var->transp.length = 0;
1189 break;
1190 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1191 bpp = 32;
1192 var->red.offset = 16;
1193 var->red.length = 8;
1194 var->green.offset = 8;
1195 var->green.length = 8;
1196 var->blue.offset = 0;
1197 var->blue.length = 8;
1198 var->transp.offset = 24;
1199 var->transp.length = 8;
1200 break;
1201 default:
1202 FAIL("Invalid pixel width");
1203 }
1204
1205 /* output */
1206 var->xres = xres;
1207 var->yres = yres;
1208 var->xres_virtual = crtc->vxres;
1209 var->yres_virtual = crtc->vyres;
1210 var->bits_per_pixel = bpp;
1211 var->left_margin = left;
1212 var->right_margin = right;
1213 var->upper_margin = upper;
1214 var->lower_margin = lower;
1215 var->hsync_len = hslen;
1216 var->vsync_len = vslen;
1217 var->sync = sync;
1218 var->vmode = FB_VMODE_NONINTERLACED;
1219 /* In double scan mode, the vertical parameters are doubled, so we need to
1220 half them to get the right values.
1221 In interlaced mode the values are already correct, so no correction is
1222 necessary.
1223 */
1224 if (interlace)
1225 var->vmode = FB_VMODE_INTERLACED;
1226
1227 if (double_scan) {
1228 var->vmode = FB_VMODE_DOUBLE;
1229 var->yres>>=1;
1230 var->upper_margin>>=1;
1231 var->lower_margin>>=1;
1232 var->vsync_len>>=1;
1233 }
1234
1235 return 0;
1236}
1237
1238/* ------------------------------------------------------------------------- */
1239
1240static int atyfb_set_par(struct fb_info *info)
1241{
1242 struct atyfb_par *par = (struct atyfb_par *) info->par;
1243 struct fb_var_screeninfo *var = &info->var;
1244 u32 tmp, pixclock;
1245 int err;
1246#ifdef DEBUG
1247 struct fb_var_screeninfo debug;
1248 u32 pixclock_in_ps;
1249#endif
1250 if (par->asleep)
1251 return 0;
1252
1253 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1254 return err;
1255
1256 pixclock = atyfb_get_pixclock(var, par);
1257
1258 if (pixclock == 0) {
1259 FAIL("Invalid pixclock");
1260 } else {
1261 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1262 return err;
1263 }
1264
1265 par->accel_flags = var->accel_flags; /* hack */
1266
1267 if (par->blitter_may_be_busy)
1268 wait_for_idle(par);
1269
1270 aty_set_crtc(par, &par->crtc);
1271 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1272 par->pll_ops->set_pll(info, &par->pll);
1273
1274#ifdef DEBUG
1275 if(par->pll_ops && par->pll_ops->pll_to_var)
1276 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1277 else
1278 pixclock_in_ps = 0;
1279
1280 if(0 == pixclock_in_ps) {
1281 PRINTKE("ALERT ops->pll_to_var get 0\n");
1282 pixclock_in_ps = pixclock;
1283 }
1284
1285 memset(&debug, 0, sizeof(debug));
1286 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1287 u32 hSync, vRefresh;
1288 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1289 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1290
1291 h_disp = debug.xres;
1292 h_sync_strt = h_disp + debug.right_margin;
1293 h_sync_end = h_sync_strt + debug.hsync_len;
1294 h_total = h_sync_end + debug.left_margin;
1295 v_disp = debug.yres;
1296 v_sync_strt = v_disp + debug.lower_margin;
1297 v_sync_end = v_sync_strt + debug.vsync_len;
1298 v_total = v_sync_end + debug.upper_margin;
1299
1300 hSync = 1000000000 / (pixclock_in_ps * h_total);
1301 vRefresh = (hSync * 1000) / v_total;
1302 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1303 vRefresh *= 2;
1304 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1305 vRefresh /= 2;
1306
1307 DPRINTK("atyfb_set_par\n");
1308 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1309 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1310 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1311 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1312 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1313 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1314 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1315 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1316 h_disp, h_sync_strt, h_sync_end, h_total,
1317 v_disp, v_sync_strt, v_sync_end, v_total);
1318 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1319 pixclock_in_ps,
1320 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1321 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1322 }
1323#endif /* DEBUG */
1324
1325 if (!M64_HAS(INTEGRATED)) {
1326 /* Don't forget MEM_CNTL */
1327 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1328 switch (var->bits_per_pixel) {
1329 case 8:
1330 tmp |= 0x02000000;
1331 break;
1332 case 16:
1333 tmp |= 0x03000000;
1334 break;
1335 case 32:
1336 tmp |= 0x06000000;
1337 break;
1338 }
1339 aty_st_le32(MEM_CNTL, tmp, par);
1340 } else {
1341 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1342 if (!M64_HAS(MAGIC_POSTDIV))
1343 tmp |= par->mem_refresh_rate << 20;
1344 switch (var->bits_per_pixel) {
1345 case 8:
1346 case 24:
1347 tmp |= 0x00000000;
1348 break;
1349 case 16:
1350 tmp |= 0x04000000;
1351 break;
1352 case 32:
1353 tmp |= 0x08000000;
1354 break;
1355 }
1356 if (M64_HAS(CT_BUS)) {
1357 aty_st_le32(DAC_CNTL, 0x87010184, par);
1358 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1359 } else if (M64_HAS(VT_BUS)) {
1360 aty_st_le32(DAC_CNTL, 0x87010184, par);
1361 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1362 } else if (M64_HAS(MOBIL_BUS)) {
1363 aty_st_le32(DAC_CNTL, 0x80010102, par);
1364 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1365 } else {
1366 /* GT */
1367 aty_st_le32(DAC_CNTL, 0x86010102, par);
1368 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1369 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1370 }
1371 aty_st_le32(MEM_CNTL, tmp, par);
1372 }
1373 aty_st_8(DAC_MASK, 0xff, par);
1374
1375 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1376 info->fix.visual = var->bits_per_pixel <= 8 ?
1377 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1378
1379 /* Initialize the graphics engine */
1380 if (par->accel_flags & FB_ACCELF_TEXT)
1381 aty_init_engine(par, info);
1382
1383#ifdef CONFIG_BOOTX_TEXT
1384 btext_update_display(info->fix.smem_start,
1385 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1386 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1387 var->bits_per_pixel,
1388 par->crtc.vxres * var->bits_per_pixel / 8);
1389#endif /* CONFIG_BOOTX_TEXT */
1390#if 0
1391 /* switch to accelerator mode */
1392 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1393 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1394#endif
1395#ifdef DEBUG
1396{
1397 /* dump non shadow CRTC, pll, LCD registers */
1398 int i; u32 base;
1399
1400 /* CRTC registers */
1401 base = 0x2000;
1402 printk("debug atyfb: Mach64 non-shadow register values:");
1403 for (i = 0; i < 256; i = i+4) {
1404 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1405 printk(" %08X", aty_ld_le32(i, par));
1406 }
1407 printk("\n\n");
1408
1409#ifdef CONFIG_FB_ATY_CT
1410 /* PLL registers */
1411 base = 0x00;
1412 printk("debug atyfb: Mach64 PLL register values:");
1413 for (i = 0; i < 64; i++) {
1414 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1415 if(i%4 == 0) printk(" ");
1416 printk("%02X", aty_ld_pll_ct(i, par));
1417 }
1418 printk("\n\n");
1419#endif /* CONFIG_FB_ATY_CT */
1420
1421#ifdef CONFIG_FB_ATY_GENERIC_LCD
1422 if (par->lcd_table != 0) {
1423 /* LCD registers */
1424 base = 0x00;
1425 printk("debug atyfb: LCD register values:");
1426 if(M64_HAS(LT_LCD_REGS)) {
1427 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1428 if(i == EXT_VERT_STRETCH)
1429 continue;
1430 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1431 printk(" %08X", aty_ld_lcd(i, par));
1432 }
1433
1434 } else {
1435 for (i = 0; i < 64; i++) {
1436 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1437 printk(" %08X", aty_ld_lcd(i, par));
1438 }
1439 }
1440 printk("\n\n");
1441 }
1442#endif /* CONFIG_FB_ATY_GENERIC_LCD */
1443}
1444#endif /* DEBUG */
1445 return 0;
1446}
1447
1448static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1449{
1450 struct atyfb_par *par = (struct atyfb_par *) info->par;
1451 int err;
1452 struct crtc crtc;
1453 union aty_pll pll;
1454 u32 pixclock;
1455
1456 memcpy(&pll, &(par->pll), sizeof(pll));
1457
1458 if((err = aty_var_to_crtc(info, var, &crtc)))
1459 return err;
1460
1461 pixclock = atyfb_get_pixclock(var, par);
1462
1463 if (pixclock == 0) {
1464 FAIL("Invalid pixclock");
1465 } else {
1466 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1467 return err;
1468 }
1469
1470 if (var->accel_flags & FB_ACCELF_TEXT)
1471 info->var.accel_flags = FB_ACCELF_TEXT;
1472 else
1473 info->var.accel_flags = 0;
1474
1475#if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1476 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1477 return -EINVAL;
1478#endif
1479 aty_crtc_to_var(&crtc, var);
1480 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1481 return 0;
1482}
1483
1484static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1485{
1486 u32 xoffset = info->var.xoffset;
1487 u32 yoffset = info->var.yoffset;
1488 u32 vxres = par->crtc.vxres;
1489 u32 bpp = info->var.bits_per_pixel;
1490
1491 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1492}
1493
1494
1495 /*
1496 * Open/Release the frame buffer device
1497 */
1498
1499static int atyfb_open(struct fb_info *info, int user)
1500{
1501 struct atyfb_par *par = (struct atyfb_par *) info->par;
1502
1503 if (user) {
1504 par->open++;
1505#ifdef __sparc__
1506 par->mmaped = 0;
1507#endif
1508 }
1509 return (0);
1510}
1511
1512static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1513{
1514 struct atyfb_par *par = dev_id;
1515 int handled = 0;
1516 u32 int_cntl;
1517
1518 spin_lock(&par->int_lock);
1519
1520 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1521
1522 if (int_cntl & CRTC_VBLANK_INT) {
1523 /* clear interrupt */
1524 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1525 par->vblank.count++;
1526 if (par->vblank.pan_display) {
1527 par->vblank.pan_display = 0;
1528 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1529 }
1530 wake_up_interruptible(&par->vblank.wait);
1531 handled = 1;
1532 }
1533
1534 spin_unlock(&par->int_lock);
1535
1536 return IRQ_RETVAL(handled);
1537}
1538
1539static int aty_enable_irq(struct atyfb_par *par, int reenable)
1540{
1541 u32 int_cntl;
1542
1543 if (!test_and_set_bit(0, &par->irq_flags)) {
1544 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1545 clear_bit(0, &par->irq_flags);
1546 return -EINVAL;
1547 }
1548 spin_lock_irq(&par->int_lock);
1549 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1550 /* clear interrupt */
1551 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1552 /* enable interrupt */
1553 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1554 spin_unlock_irq(&par->int_lock);
1555 } else if (reenable) {
1556 spin_lock_irq(&par->int_lock);
1557 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1558 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1559 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1560 /* re-enable interrupt */
1561 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1562 }
1563 spin_unlock_irq(&par->int_lock);
1564 }
1565
1566 return 0;
1567}
1568
1569static int aty_disable_irq(struct atyfb_par *par)
1570{
1571 u32 int_cntl;
1572
1573 if (test_and_clear_bit(0, &par->irq_flags)) {
1574 if (par->vblank.pan_display) {
1575 par->vblank.pan_display = 0;
1576 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1577 }
1578 spin_lock_irq(&par->int_lock);
1579 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1580 /* disable interrupt */
1581 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1582 spin_unlock_irq(&par->int_lock);
1583 free_irq(par->irq, par);
1584 }
1585
1586 return 0;
1587}
1588
1589static int atyfb_release(struct fb_info *info, int user)
1590{
1591 struct atyfb_par *par = (struct atyfb_par *) info->par;
1592 if (user) {
1593 par->open--;
1594 mdelay(1);
1595 wait_for_idle(par);
1596 if (!par->open) {
1597#ifdef __sparc__
1598 int was_mmaped = par->mmaped;
1599
1600 par->mmaped = 0;
1601
1602 if (was_mmaped) {
1603 struct fb_var_screeninfo var;
1604
1605 /* Now reset the default display config, we have no
1606 * idea what the program(s) which mmap'd the chip did
1607 * to the configuration, nor whether it restored it
1608 * correctly.
1609 */
1610 var = default_var;
1611 if (noaccel)
1612 var.accel_flags &= ~FB_ACCELF_TEXT;
1613 else
1614 var.accel_flags |= FB_ACCELF_TEXT;
1615 if (var.yres == var.yres_virtual) {
1616 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1617 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1618 if (var.yres_virtual < var.yres)
1619 var.yres_virtual = var.yres;
1620 }
1621 }
1622#endif
1623 aty_disable_irq(par);
1624 }
1625 }
1626 return (0);
1627}
1628
1629 /*
1630 * Pan or Wrap the Display
1631 *
1632 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1633 */
1634
1635static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1636{
1637 struct atyfb_par *par = (struct atyfb_par *) info->par;
1638 u32 xres, yres, xoffset, yoffset;
1639
1640 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1641 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1642 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1643 yres >>= 1;
1644 xoffset = (var->xoffset + 7) & ~7;
1645 yoffset = var->yoffset;
1646 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1647 return -EINVAL;
1648 info->var.xoffset = xoffset;
1649 info->var.yoffset = yoffset;
1650 if (par->asleep)
1651 return 0;
1652
1653 set_off_pitch(par, info);
1654 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1655 par->vblank.pan_display = 1;
1656 } else {
1657 par->vblank.pan_display = 0;
1658 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1659 }
1660
1661 return 0;
1662}
1663
1664static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1665{
1666 struct aty_interrupt *vbl;
1667 unsigned int count;
1668 int ret;
1669
1670 switch (crtc) {
1671 case 0:
1672 vbl = &par->vblank;
1673 break;
1674 default:
1675 return -ENODEV;
1676 }
1677
1678 ret = aty_enable_irq(par, 0);
1679 if (ret)
1680 return ret;
1681
1682 count = vbl->count;
1683 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1684 if (ret < 0) {
1685 return ret;
1686 }
1687 if (ret == 0) {
1688 aty_enable_irq(par, 1);
1689 return -ETIMEDOUT;
1690 }
1691
1692 return 0;
1693}
1694
1695
1696#ifdef DEBUG
1697#define ATYIO_CLKR 0x41545900 /* ATY\00 */
1698#define ATYIO_CLKW 0x41545901 /* ATY\01 */
1699
1700struct atyclk {
1701 u32 ref_clk_per;
1702 u8 pll_ref_div;
1703 u8 mclk_fb_div;
1704 u8 mclk_post_div; /* 1,2,3,4,8 */
1705 u8 mclk_fb_mult; /* 2 or 4 */
1706 u8 xclk_post_div; /* 1,2,3,4,8 */
1707 u8 vclk_fb_div;
1708 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1709 u32 dsp_xclks_per_row; /* 0-16383 */
1710 u32 dsp_loop_latency; /* 0-15 */
1711 u32 dsp_precision; /* 0-7 */
1712 u32 dsp_on; /* 0-2047 */
1713 u32 dsp_off; /* 0-2047 */
1714};
1715
1716#define ATYIO_FEATR 0x41545902 /* ATY\02 */
1717#define ATYIO_FEATW 0x41545903 /* ATY\03 */
1718#endif
1719
1720#ifndef FBIO_WAITFORVSYNC
1721#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1722#endif
1723
1724static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1725 u_long arg, struct fb_info *info)
1726{
1727 struct atyfb_par *par = (struct atyfb_par *) info->par;
1728#ifdef __sparc__
1729 struct fbtype fbtyp;
1730#endif
1731
1732 switch (cmd) {
1733#ifdef __sparc__
1734 case FBIOGTYPE:
1735 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1736 fbtyp.fb_width = par->crtc.vxres;
1737 fbtyp.fb_height = par->crtc.vyres;
1738 fbtyp.fb_depth = info->var.bits_per_pixel;
1739 fbtyp.fb_cmsize = info->cmap.len;
1740 fbtyp.fb_size = info->fix.smem_len;
1741 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1742 return -EFAULT;
1743 break;
1744#endif /* __sparc__ */
1745
1746 case FBIO_WAITFORVSYNC:
1747 {
1748 u32 crtc;
1749
1750 if (get_user(crtc, (__u32 __user *) arg))
1751 return -EFAULT;
1752
1753 return aty_waitforvblank(par, crtc);
1754 }
1755 break;
1756
1757#if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1758 case ATYIO_CLKR:
1759 if (M64_HAS(INTEGRATED)) {
1760 struct atyclk clk;
1761 union aty_pll *pll = &(par->pll);
1762 u32 dsp_config = pll->ct.dsp_config;
1763 u32 dsp_on_off = pll->ct.dsp_on_off;
1764 clk.ref_clk_per = par->ref_clk_per;
1765 clk.pll_ref_div = pll->ct.pll_ref_div;
1766 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1767 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1768 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1769 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1770 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1771 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1772 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1773 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1774 clk.dsp_precision = (dsp_config >> 20) & 7;
1775 clk.dsp_off = dsp_on_off & 0x7ff;
1776 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1777 if (copy_to_user((struct atyclk __user *) arg, &clk,
1778 sizeof(clk)))
1779 return -EFAULT;
1780 } else
1781 return -EINVAL;
1782 break;
1783 case ATYIO_CLKW:
1784 if (M64_HAS(INTEGRATED)) {
1785 struct atyclk clk;
1786 union aty_pll *pll = &(par->pll);
1787 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1788 return -EFAULT;
1789 par->ref_clk_per = clk.ref_clk_per;
1790 pll->ct.pll_ref_div = clk.pll_ref_div;
1791 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1792 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1793 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1794 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1795 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1796 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1797 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1798 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1799 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1800 /*aty_calc_pll_ct(info, &pll->ct);*/
1801 aty_set_pll_ct(info, pll);
1802 } else
1803 return -EINVAL;
1804 break;
1805 case ATYIO_FEATR:
1806 if (get_user(par->features, (u32 __user *) arg))
1807 return -EFAULT;
1808 break;
1809 case ATYIO_FEATW:
1810 if (put_user(par->features, (u32 __user *) arg))
1811 return -EFAULT;
1812 break;
1813#endif /* DEBUG && CONFIG_FB_ATY_CT */
1814 default:
1815 return -EINVAL;
1816 }
1817 return 0;
1818}
1819
1820static int atyfb_sync(struct fb_info *info)
1821{
1822 struct atyfb_par *par = (struct atyfb_par *) info->par;
1823
1824 if (par->blitter_may_be_busy)
1825 wait_for_idle(par);
1826 return 0;
1827}
1828
1829#ifdef __sparc__
1830static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1831{
1832 struct atyfb_par *par = (struct atyfb_par *) info->par;
1833 unsigned int size, page, map_size = 0;
1834 unsigned long map_offset = 0;
1835 unsigned long off;
1836 int i;
1837
1838 if (!par->mmap_map)
1839 return -ENXIO;
1840
1841 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1842 return -EINVAL;
1843
1844 off = vma->vm_pgoff << PAGE_SHIFT;
1845 size = vma->vm_end - vma->vm_start;
1846
1847 /* To stop the swapper from even considering these pages. */
1848 vma->vm_flags |= (VM_IO | VM_RESERVED);
1849
1850 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1851 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1852 off += 0x8000000000000000UL;
1853
1854 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1855
1856 /* Each page, see which map applies */
1857 for (page = 0; page < size;) {
1858 map_size = 0;
1859 for (i = 0; par->mmap_map[i].size; i++) {
1860 unsigned long start = par->mmap_map[i].voff;
1861 unsigned long end = start + par->mmap_map[i].size;
1862 unsigned long offset = off + page;
1863
1864 if (start > offset)
1865 continue;
1866 if (offset >= end)
1867 continue;
1868
1869 map_size = par->mmap_map[i].size - (offset - start);
1870 map_offset =
1871 par->mmap_map[i].poff + (offset - start);
1872 break;
1873 }
1874 if (!map_size) {
1875 page += PAGE_SIZE;
1876 continue;
1877 }
1878 if (page + map_size > size)
1879 map_size = size - page;
1880
1881 pgprot_val(vma->vm_page_prot) &=
1882 ~(par->mmap_map[i].prot_mask);
1883 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1884
1885 if (remap_pfn_range(vma, vma->vm_start + page,
1886 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1887 return -EAGAIN;
1888
1889 page += map_size;
1890 }
1891
1892 if (!map_size)
1893 return -EINVAL;
1894
1895 if (!par->mmaped)
1896 par->mmaped = 1;
1897 return 0;
1898}
1899
1900static struct {
1901 u32 yoffset;
1902 u8 r[2][256];
1903 u8 g[2][256];
1904 u8 b[2][256];
1905} atyfb_save;
1906
1907static void atyfb_save_palette(struct atyfb_par *par, int enter)
1908{
1909 int i, tmp;
1910
1911 for (i = 0; i < 256; i++) {
1912 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1913 if (M64_HAS(EXTRA_BRIGHT))
1914 tmp |= 0x2;
1915 aty_st_8(DAC_CNTL, tmp, par);
1916 aty_st_8(DAC_MASK, 0xff, par);
1917
1918 writeb(i, &par->aty_cmap_regs->rindex);
1919 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1920 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1921 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1922 writeb(i, &par->aty_cmap_regs->windex);
1923 writeb(atyfb_save.r[1 - enter][i],
1924 &par->aty_cmap_regs->lut);
1925 writeb(atyfb_save.g[1 - enter][i],
1926 &par->aty_cmap_regs->lut);
1927 writeb(atyfb_save.b[1 - enter][i],
1928 &par->aty_cmap_regs->lut);
1929 }
1930}
1931
1932static void atyfb_palette(int enter)
1933{
1934 struct atyfb_par *par;
1935 struct fb_info *info;
1936 int i;
1937
1938 for (i = 0; i < FB_MAX; i++) {
1939 info = registered_fb[i];
1940 if (info && info->fbops == &atyfb_ops) {
1941 par = (struct atyfb_par *) info->par;
1942
1943 atyfb_save_palette(par, enter);
1944 if (enter) {
1945 atyfb_save.yoffset = info->var.yoffset;
1946 info->var.yoffset = 0;
1947 set_off_pitch(par, info);
1948 } else {
1949 info->var.yoffset = atyfb_save.yoffset;
1950 set_off_pitch(par, info);
1951 }
1952 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1953 break;
1954 }
1955 }
1956}
1957#endif /* __sparc__ */
1958
1959
1960
1961#if defined(CONFIG_PM) && defined(CONFIG_PCI)
1962
1963/* Power management routines. Those are used for PowerBook sleep.
1964 */
1965static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1966{
1967 u32 pm;
1968 int timeout;
1969
1970 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1971 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1972 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1973 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1974
1975 timeout = 2000;
1976 if (sleep) {
1977 /* Sleep */
1978 pm &= ~PWR_MGT_ON;
1979 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1980 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1981 udelay(10);
1982 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1983 pm |= SUSPEND_NOW;
1984 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1985 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1986 udelay(10);
1987 pm |= PWR_MGT_ON;
1988 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989 do {
1990 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1991 mdelay(1);
1992 if ((--timeout) == 0)
1993 break;
1994 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1995 } else {
1996 /* Wakeup */
1997 pm &= ~PWR_MGT_ON;
1998 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1999 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2000 udelay(10);
2001 pm &= ~SUSPEND_NOW;
2002 pm |= (PWR_BLON | AUTO_PWR_UP);
2003 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2004 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2005 udelay(10);
2006 pm |= PWR_MGT_ON;
2007 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2008 do {
2009 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2010 mdelay(1);
2011 if ((--timeout) == 0)
2012 break;
2013 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2014 }
2015 mdelay(500);
2016
2017 return timeout ? 0 : -EIO;
2018}
2019
2020static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2021{
2022 struct fb_info *info = pci_get_drvdata(pdev);
2023 struct atyfb_par *par = (struct atyfb_par *) info->par;
2024
2025#ifdef CONFIG_PPC_PMAC
2026 /* HACK ALERT ! Once I find a proper way to say to each driver
2027 * individually what will happen with it's PCI slot, I'll change
2028 * that. On laptops, the AGP slot is just unclocked, so D2 is
2029 * expected, while on desktops, the card is powered off
2030 */
2031 if (state >= 3)
2032 state = 2;
2033#endif /* CONFIG_PPC_PMAC */
2034
2035 if (state != 2 || state == pdev->dev.power.power_state)
2036 return 0;
2037
2038 acquire_console_sem();
2039
2040 fb_set_suspend(info, 1);
2041
2042 /* Idle & reset engine */
2043 wait_for_idle(par);
2044 aty_reset_engine(par);
2045
2046 /* Blank display and LCD */
2047 atyfb_blank(FB_BLANK_POWERDOWN, info);
2048
2049 par->asleep = 1;
2050 par->lock_blank = 1;
2051
2052 /* Set chip to "suspend" mode */
2053 if (aty_power_mgmt(1, par)) {
2054 par->asleep = 0;
2055 par->lock_blank = 0;
2056 atyfb_blank(FB_BLANK_UNBLANK, info);
2057 fb_set_suspend(info, 0);
2058 release_console_sem();
2059 return -EIO;
2060 }
2061
2062 release_console_sem();
2063
2064 pdev->dev.power.power_state = state;
2065
2066 return 0;
2067}
2068
2069static int atyfb_pci_resume(struct pci_dev *pdev)
2070{
2071 struct fb_info *info = pci_get_drvdata(pdev);
2072 struct atyfb_par *par = (struct atyfb_par *) info->par;
2073
2074 if (pdev->dev.power.power_state == 0)
2075 return 0;
2076
2077 acquire_console_sem();
2078
2079 if (pdev->dev.power.power_state == 2)
2080 aty_power_mgmt(0, par);
2081 par->asleep = 0;
2082
2083 /* Restore display */
2084 atyfb_set_par(info);
2085
2086 /* Refresh */
2087 fb_set_suspend(info, 0);
2088
2089 /* Unblank */
2090 par->lock_blank = 0;
2091 atyfb_blank(FB_BLANK_UNBLANK, info);
2092
2093 release_console_sem();
2094
2095 pdev->dev.power.power_state = PMSG_ON;
2096
2097 return 0;
2098}
2099
2100#endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2101
2102#ifdef CONFIG_PMAC_BACKLIGHT
2103
2104 /*
2105 * LCD backlight control
2106 */
2107
2108static int backlight_conv[] = {
2109 0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2110 0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2111};
2112
2113static int aty_set_backlight_enable(int on, int level, void *data)
2114{
2115 struct fb_info *info = (struct fb_info *) data;
2116 struct atyfb_par *par = (struct atyfb_par *) info->par;
2117 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2118
2119 reg |= (BLMOD_EN | BIASMOD_EN);
2120 if (on && level > BACKLIGHT_OFF) {
2121 reg &= ~BIAS_MOD_LEVEL_MASK;
2122 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2123 } else {
2124 reg &= ~BIAS_MOD_LEVEL_MASK;
2125 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2126 }
2127 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2128 return 0;
2129}
2130
2131static int aty_set_backlight_level(int level, void *data)
2132{
2133 return aty_set_backlight_enable(1, level, data);
2134}
2135
2136static struct backlight_controller aty_backlight_controller = {
2137 aty_set_backlight_enable,
2138 aty_set_backlight_level
2139};
2140#endif /* CONFIG_PMAC_BACKLIGHT */
2141
2142static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2143{
2144 const int ragepro_tbl[] = {
2145 44, 50, 55, 66, 75, 80, 100
2146 };
2147 const int ragexl_tbl[] = {
2148 50, 66, 75, 83, 90, 95, 100, 105,
2149 110, 115, 120, 125, 133, 143, 166
2150 };
2151 const int *refresh_tbl;
2152 int i, size;
2153
2154 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2155 refresh_tbl = ragexl_tbl;
2156 size = sizeof(ragexl_tbl)/sizeof(int);
2157 } else {
2158 refresh_tbl = ragepro_tbl;
2159 size = sizeof(ragepro_tbl)/sizeof(int);
2160 }
2161
2162 for (i=0; i < size; i++) {
2163 if (xclk < refresh_tbl[i])
2164 break;
2165 }
2166 par->mem_refresh_rate = i;
2167}
2168
2169 /*
2170 * Initialisation
2171 */
2172
2173static struct fb_info *fb_list = NULL;
2174
2175static int __init aty_init(struct fb_info *info, const char *name)
2176{
2177 struct atyfb_par *par = (struct atyfb_par *) info->par;
2178 const char *ramname = NULL, *xtal;
2179 int gtb_memsize;
2180 struct fb_var_screeninfo var;
2181 u8 pll_ref_div;
2182 u32 i;
2183#if defined(CONFIG_PPC)
2184 int sense;
2185#endif
2186
2187 init_waitqueue_head(&par->vblank.wait);
2188 spin_lock_init(&par->int_lock);
2189
2190 par->aty_cmap_regs =
2191 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2192
2193#ifdef CONFIG_PPC_PMAC
2194 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2195 * and set the frequency manually. */
2196 if (machine_is_compatible("PowerBook2,1")) {
2197 par->pll_limits.mclk = 70;
2198 par->pll_limits.xclk = 53;
2199 }
2200#endif
2201 if (pll)
2202 par->pll_limits.pll_max = pll;
2203 if (mclk)
2204 par->pll_limits.mclk = mclk;
2205 if (xclk)
2206 par->pll_limits.xclk = xclk;
2207
2208 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2209 par->pll_per = 1000000/par->pll_limits.pll_max;
2210 par->mclk_per = 1000000/par->pll_limits.mclk;
2211 par->xclk_per = 1000000/par->pll_limits.xclk;
2212
2213 par->ref_clk_per = 1000000000000ULL / 14318180;
2214 xtal = "14.31818";
2215
2216#ifdef CONFIG_FB_ATY_GX
2217 if (!M64_HAS(INTEGRATED)) {
2218 u32 stat0;
2219 u8 dac_type, dac_subtype, clk_type;
2220 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2221 par->bus_type = (stat0 >> 0) & 0x07;
2222 par->ram_type = (stat0 >> 3) & 0x07;
2223 ramname = aty_gx_ram[par->ram_type];
2224 /* FIXME: clockchip/RAMDAC probing? */
2225 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2226#ifdef CONFIG_ATARI
2227 clk_type = CLK_ATI18818_1;
2228 dac_type = (stat0 >> 9) & 0x07;
2229 if (dac_type == 0x07)
2230 dac_subtype = DAC_ATT20C408;
2231 else
2232 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2233#else
2234 dac_type = DAC_IBMRGB514;
2235 dac_subtype = DAC_IBMRGB514;
2236 clk_type = CLK_IBMRGB514;
2237#endif
2238 switch (dac_subtype) {
2239 case DAC_IBMRGB514:
2240 par->dac_ops = &aty_dac_ibm514;
2241 break;
2242 case DAC_ATI68860_B:
2243 case DAC_ATI68860_C:
2244 par->dac_ops = &aty_dac_ati68860b;
2245 break;
2246 case DAC_ATT20C408:
2247 case DAC_ATT21C498:
2248 par->dac_ops = &aty_dac_att21c498;
2249 break;
2250 default:
2251 PRINTKI("aty_init: DAC type not implemented yet!\n");
2252 par->dac_ops = &aty_dac_unsupported;
2253 break;
2254 }
2255 switch (clk_type) {
2256 case CLK_ATI18818_1:
2257 par->pll_ops = &aty_pll_ati18818_1;
2258 break;
2259 case CLK_STG1703:
2260 par->pll_ops = &aty_pll_stg1703;
2261 break;
2262 case CLK_CH8398:
2263 par->pll_ops = &aty_pll_ch8398;
2264 break;
2265 case CLK_ATT20C408:
2266 par->pll_ops = &aty_pll_att20c408;
2267 break;
2268 case CLK_IBMRGB514:
2269 par->pll_ops = &aty_pll_ibm514;
2270 break;
2271 default:
2272 PRINTKI("aty_init: CLK type not implemented yet!");
2273 par->pll_ops = &aty_pll_unsupported;
2274 break;
2275 }
2276 }
2277#endif /* CONFIG_FB_ATY_GX */
2278#ifdef CONFIG_FB_ATY_CT
2279 if (M64_HAS(INTEGRATED)) {
2280 par->dac_ops = &aty_dac_ct;
2281 par->pll_ops = &aty_pll_ct;
2282 par->bus_type = PCI;
2283#ifdef CONFIG_FB_ATY_XL_INIT
2284 if (IS_XL(par->pci_id))
2285 atyfb_xl_init(info);
2286#endif
2287 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2288 ramname = aty_ct_ram[par->ram_type];
2289 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2290 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2291 par->pll_limits.mclk = 63;
2292 }
2293
2294 if (M64_HAS(GTB_DSP)
2295 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2296 int diff1, diff2;
2297 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2298 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2299 if (diff1 < 0)
2300 diff1 = -diff1;
2301 if (diff2 < 0)
2302 diff2 = -diff2;
2303 if (diff2 < diff1) {
2304 par->ref_clk_per = 1000000000000ULL / 29498928;
2305 xtal = "29.498928";
2306 }
2307 }
2308#endif /* CONFIG_FB_ATY_CT */
2309
2310 /* save previous video mode */
2311 aty_get_crtc(par, &saved_crtc);
2312 if(par->pll_ops->get_pll)
2313 par->pll_ops->get_pll(info, &saved_pll);
2314
2315 i = aty_ld_le32(MEM_CNTL, par);
2316 gtb_memsize = M64_HAS(GTB_DSP);
2317 if (gtb_memsize)
2318 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2319 case MEM_SIZE_512K:
2320 info->fix.smem_len = 0x80000;
2321 break;
2322 case MEM_SIZE_1M:
2323 info->fix.smem_len = 0x100000;
2324 break;
2325 case MEM_SIZE_2M_GTB:
2326 info->fix.smem_len = 0x200000;
2327 break;
2328 case MEM_SIZE_4M_GTB:
2329 info->fix.smem_len = 0x400000;
2330 break;
2331 case MEM_SIZE_6M_GTB:
2332 info->fix.smem_len = 0x600000;
2333 break;
2334 case MEM_SIZE_8M_GTB:
2335 info->fix.smem_len = 0x800000;
2336 break;
2337 default:
2338 info->fix.smem_len = 0x80000;
2339 } else
2340 switch (i & MEM_SIZE_ALIAS) {
2341 case MEM_SIZE_512K:
2342 info->fix.smem_len = 0x80000;
2343 break;
2344 case MEM_SIZE_1M:
2345 info->fix.smem_len = 0x100000;
2346 break;
2347 case MEM_SIZE_2M:
2348 info->fix.smem_len = 0x200000;
2349 break;
2350 case MEM_SIZE_4M:
2351 info->fix.smem_len = 0x400000;
2352 break;
2353 case MEM_SIZE_6M:
2354 info->fix.smem_len = 0x600000;
2355 break;
2356 case MEM_SIZE_8M:
2357 info->fix.smem_len = 0x800000;
2358 break;
2359 default:
2360 info->fix.smem_len = 0x80000;
2361 }
2362
2363 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2364 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2365 info->fix.smem_len += 0x400000;
2366 }
2367
2368 if (vram) {
2369 info->fix.smem_len = vram * 1024;
2370 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2371 if (info->fix.smem_len <= 0x80000)
2372 i |= MEM_SIZE_512K;
2373 else if (info->fix.smem_len <= 0x100000)
2374 i |= MEM_SIZE_1M;
2375 else if (info->fix.smem_len <= 0x200000)
2376 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2377 else if (info->fix.smem_len <= 0x400000)
2378 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2379 else if (info->fix.smem_len <= 0x600000)
2380 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2381 else
2382 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2383 aty_st_le32(MEM_CNTL, i, par);
2384 }
2385
2386 /*
2387 * Reg Block 0 (CT-compatible block) is at mmio_start
2388 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2389 */
2390 if (M64_HAS(GX)) {
2391 info->fix.mmio_len = 0x400;
2392 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2393 } else if (M64_HAS(CT)) {
2394 info->fix.mmio_len = 0x400;
2395 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2396 } else if (M64_HAS(VT)) {
2397 info->fix.mmio_start -= 0x400;
2398 info->fix.mmio_len = 0x800;
2399 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2400 } else {/* GT */
2401 info->fix.mmio_start -= 0x400;
2402 info->fix.mmio_len = 0x800;
2403 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2404 }
2405
2406 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2407 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2408 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2409 par->pll_limits.mclk, par->pll_limits.xclk);
2410
2411#if defined(DEBUG) && defined(CONFIG_ATY_CT)
2412 if (M64_HAS(INTEGRATED)) {
2413 int i;
2414 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2415 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2416 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2417 "debug atyfb: PLL",
2418 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2419 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2420 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2421 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2422 for (i = 0; i < 40; i++)
2423 printk(" %02x", aty_ld_pll_ct(i, par));
2424 printk("\n");
2425 }
2426#endif
2427 if(par->pll_ops->init_pll)
2428 par->pll_ops->init_pll(info, &par->pll);
2429
2430 /*
2431 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2432 * FIXME: we should use the auxiliary aperture instead so we can access
2433 * the full 8 MB of video RAM on 8 MB boards
2434 */
2435
2436 if (!par->aux_start &&
2437 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2438 info->fix.smem_len -= GUI_RESERVE;
2439
2440 /*
2441 * Disable register access through the linear aperture
2442 * if the auxiliary aperture is used so we can access
2443 * the full 8 MB of video RAM on 8 MB boards.
2444 */
2445 if (par->aux_start)
2446 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2447
2448#ifdef CONFIG_MTRR
2449 par->mtrr_aper = -1;
2450 par->mtrr_reg = -1;
2451 if (!nomtrr) {
2452 /* Cover the whole resource. */
2453 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2454 if (par->mtrr_aper >= 0 && !par->aux_start) {
2455 /* Make a hole for mmio. */
2456 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2457 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2458 if (par->mtrr_reg < 0) {
2459 mtrr_del(par->mtrr_aper, 0, 0);
2460 par->mtrr_aper = -1;
2461 }
2462 }
2463 }
2464#endif
2465
2466 info->fbops = &atyfb_ops;
2467 info->pseudo_palette = pseudo_palette;
2468 info->flags = FBINFO_FLAG_DEFAULT;
2469
2470#ifdef CONFIG_PMAC_BACKLIGHT
2471 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2472 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2473 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2474 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2475 } else if (M64_HAS(MOBIL_BUS))
2476 register_backlight_controller(&aty_backlight_controller, info, "ati");
2477#endif /* CONFIG_PMAC_BACKLIGHT */
2478
2479 memset(&var, 0, sizeof(var));
2480#ifdef CONFIG_PPC
2481 if (_machine == _MACH_Pmac) {
2482 /*
2483 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2484 * applies to all Mac video cards
2485 */
2486 if (mode) {
2487 if (!mac_find_mode(&var, info, mode, 8))
2488 var = default_var;
2489 } else {
2490 if (default_vmode == VMODE_CHOOSE) {
2491 if (M64_HAS(G3_PB_1024x768))
2492 /* G3 PowerBook with 1024x768 LCD */
2493 default_vmode = VMODE_1024_768_60;
2494 else if (machine_is_compatible("iMac"))
2495 default_vmode = VMODE_1024_768_75;
2496 else if (machine_is_compatible
2497 ("PowerBook2,1"))
2498 /* iBook with 800x600 LCD */
2499 default_vmode = VMODE_800_600_60;
2500 else
2501 default_vmode = VMODE_640_480_67;
2502 sense = read_aty_sense(par);
2503 PRINTKI("monitor sense=%x, mode %d\n",
2504 sense, mac_map_monitor_sense(sense));
2505 }
2506 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2507 default_vmode = VMODE_640_480_60;
2508 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2509 default_cmode = CMODE_8;
2510 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
2511 var = default_var;
2512 }
2513 } else
2514#endif /* !CONFIG_PPC */
2515 if (
2516#if defined(CONFIG_SPARC32) || defined(CONFIG_SPARC64)
2517 /* On Sparc, unless the user gave a specific mode
2518 * specification, use the PROM probed values in
2519 * default_var.
2520 */
2521 !mode ||
2522#endif
2523 !fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2524 var = default_var;
2525
2526 if (noaccel)
2527 var.accel_flags &= ~FB_ACCELF_TEXT;
2528 else
2529 var.accel_flags |= FB_ACCELF_TEXT;
2530
2531 if (comp_sync != -1) {
2532 if (!comp_sync)
2533 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2534 else
2535 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2536 }
2537
2538 if (var.yres == var.yres_virtual) {
2539 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2540 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2541 if (var.yres_virtual < var.yres)
2542 var.yres_virtual = var.yres;
2543 }
2544
2545 if (atyfb_check_var(&var, info)) {
2546 PRINTKE("can't set default video mode\n");
2547 goto aty_init_exit;
2548 }
2549
2550#ifdef __sparc__
2551 atyfb_save_palette(par, 0);
2552#endif
2553
2554#ifdef CONFIG_FB_ATY_CT
2555 if (!noaccel && M64_HAS(INTEGRATED))
2556 aty_init_cursor(info);
2557#endif /* CONFIG_FB_ATY_CT */
2558 info->var = var;
2559
2560 fb_alloc_cmap(&info->cmap, 256, 0);
2561
2562 if (register_framebuffer(info) < 0)
2563 goto aty_init_exit;
2564
2565 fb_list = info;
2566
2567 PRINTKI("fb%d: %s frame buffer device on %s\n",
2568 info->node, info->fix.id, name);
2569 return 0;
2570
2571aty_init_exit:
2572 /* restore video mode */
2573 aty_set_crtc(par, &saved_crtc);
2574 par->pll_ops->set_pll(info, &saved_pll);
2575
2576#ifdef CONFIG_MTRR
2577 if (par->mtrr_reg >= 0) {
2578 mtrr_del(par->mtrr_reg, 0, 0);
2579 par->mtrr_reg = -1;
2580 }
2581 if (par->mtrr_aper >= 0) {
2582 mtrr_del(par->mtrr_aper, 0, 0);
2583 par->mtrr_aper = -1;
2584 }
2585#endif
2586 return -1;
2587}
2588
2589#ifdef CONFIG_ATARI
2590static int __init store_video_par(char *video_str, unsigned char m64_num)
2591{
2592 char *p;
2593 unsigned long vmembase, size, guiregbase;
2594
2595 PRINTKI("store_video_par() '%s' \n", video_str);
2596
2597 if (!(p = strsep(&video_str, ";")) || !*p)
2598 goto mach64_invalid;
2599 vmembase = simple_strtoul(p, NULL, 0);
2600 if (!(p = strsep(&video_str, ";")) || !*p)
2601 goto mach64_invalid;
2602 size = simple_strtoul(p, NULL, 0);
2603 if (!(p = strsep(&video_str, ";")) || !*p)
2604 goto mach64_invalid;
2605 guiregbase = simple_strtoul(p, NULL, 0);
2606
2607 phys_vmembase[m64_num] = vmembase;
2608 phys_size[m64_num] = size;
2609 phys_guiregbase[m64_num] = guiregbase;
2610 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2611 guiregbase);
2612 return 0;
2613
2614 mach64_invalid:
2615 phys_vmembase[m64_num] = 0;
2616 return -1;
2617}
2618#endif /* CONFIG_ATARI */
2619
2620 /*
2621 * Blank the display.
2622 */
2623
2624static int atyfb_blank(int blank, struct fb_info *info)
2625{
2626 struct atyfb_par *par = (struct atyfb_par *) info->par;
2627 u8 gen_cntl;
2628
2629 if (par->lock_blank || par->asleep)
2630 return 0;
2631
2632#ifdef CONFIG_PMAC_BACKLIGHT
2633 if ((_machine == _MACH_Pmac) && blank)
2634 set_backlight_enable(0);
2635#elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2636 if (par->lcd_table && blank &&
2637 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2638 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2639 pm &= ~PWR_BLON;
2640 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2641 }
2642#endif
2643
2644 gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par);
2645 switch (blank) {
2646 case FB_BLANK_UNBLANK:
2647 gen_cntl &= ~(0x4c);
2648 break;
2649 case FB_BLANK_NORMAL:
2650 gen_cntl |= 0x40;
2651 break;
2652 case FB_BLANK_VSYNC_SUSPEND:
2653 gen_cntl |= 0x8;
2654 break;
2655 case FB_BLANK_HSYNC_SUSPEND:
2656 gen_cntl |= 0x4;
2657 break;
2658 case FB_BLANK_POWERDOWN:
2659 gen_cntl |= 0x4c;
2660 break;
2661 }
2662 aty_st_8(CRTC_GEN_CNTL, gen_cntl, par);
2663
2664#ifdef CONFIG_PMAC_BACKLIGHT
2665 if ((_machine == _MACH_Pmac) && !blank)
2666 set_backlight_enable(1);
2667#elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2668 if (par->lcd_table && !blank &&
2669 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2670 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2671 pm |= PWR_BLON;
2672 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2673 }
2674#endif
2675
2676 return 0;
2677}
2678
2679static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2680 const struct atyfb_par *par)
2681{
2682#ifdef CONFIG_ATARI
2683 out_8(&par->aty_cmap_regs->windex, regno);
2684 out_8(&par->aty_cmap_regs->lut, red);
2685 out_8(&par->aty_cmap_regs->lut, green);
2686 out_8(&par->aty_cmap_regs->lut, blue);
2687#else
2688 writeb(regno, &par->aty_cmap_regs->windex);
2689 writeb(red, &par->aty_cmap_regs->lut);
2690 writeb(green, &par->aty_cmap_regs->lut);
2691 writeb(blue, &par->aty_cmap_regs->lut);
2692#endif
2693}
2694
2695 /*
2696 * Set a single color register. The values supplied are already
2697 * rounded down to the hardware's capabilities (according to the
2698 * entries in the var structure). Return != 0 for invalid regno.
2699 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2700 */
2701
2702static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2703 u_int transp, struct fb_info *info)
2704{
2705 struct atyfb_par *par = (struct atyfb_par *) info->par;
2706 int i, depth;
2707 u32 *pal = info->pseudo_palette;
2708
2709 depth = info->var.bits_per_pixel;
2710 if (depth == 16)
2711 depth = (info->var.green.length == 5) ? 15 : 16;
2712
2713 if (par->asleep)
2714 return 0;
2715
2716 if (regno > 255 ||
2717 (depth == 16 && regno > 63) ||
2718 (depth == 15 && regno > 31))
2719 return 1;
2720
2721 red >>= 8;
2722 green >>= 8;
2723 blue >>= 8;
2724
2725 par->palette[regno].red = red;
2726 par->palette[regno].green = green;
2727 par->palette[regno].blue = blue;
2728
2729 if (regno < 16) {
2730 switch (depth) {
2731 case 15:
2732 pal[regno] = (regno << 10) | (regno << 5) | regno;
2733 break;
2734 case 16:
2735 pal[regno] = (regno << 11) | (regno << 5) | regno;
2736 break;
2737 case 24:
2738 pal[regno] = (regno << 16) | (regno << 8) | regno;
2739 break;
2740 case 32:
2741 i = (regno << 8) | regno;
2742 pal[regno] = (i << 16) | i;
2743 break;
2744 }
2745 }
2746
2747 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2748 if (M64_HAS(EXTRA_BRIGHT))
2749 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2750 aty_st_8(DAC_CNTL, i, par);
2751 aty_st_8(DAC_MASK, 0xff, par);
2752
2753 if (M64_HAS(INTEGRATED)) {
2754 if (depth == 16) {
2755 if (regno < 32)
2756 aty_st_pal(regno << 3, red,
2757 par->palette[regno<<1].green,
2758 blue, par);
2759 red = par->palette[regno>>1].red;
2760 blue = par->palette[regno>>1].blue;
2761 regno <<= 2;
2762 } else if (depth == 15) {
2763 regno <<= 3;
2764 for(i = 0; i < 8; i++) {
2765 aty_st_pal(regno + i, red, green, blue, par);
2766 }
2767 }
2768 }
2769 aty_st_pal(regno, red, green, blue, par);
2770
2771 return 0;
2772}
2773
2774#ifdef CONFIG_PCI
2775
2776#ifdef __sparc__
2777
2778extern void (*prom_palette) (int);
2779
2780static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2781 struct fb_info *info, unsigned long addr)
2782{
2783 extern int con_is_present(void);
2784
2785 struct atyfb_par *par = info->par;
2786 struct pcidev_cookie *pcp;
2787 char prop[128];
2788 int node, len, i, j, ret;
2789 u32 mem, chip_id;
2790
2791 /* Do not attach when we have a serial console. */
2792 if (!con_is_present())
2793 return -ENXIO;
2794
2795 /*
2796 * Map memory-mapped registers.
2797 */
2798 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2799 info->fix.mmio_start = addr + 0x7ffc00UL;
2800
2801 /*
2802 * Map in big-endian aperture.
2803 */
2804 info->screen_base = (char *) (addr + 0x800000UL);
2805 info->fix.smem_start = addr + 0x800000UL;
2806
2807 /*
2808 * Figure mmap addresses from PCI config space.
2809 * Split Framebuffer in big- and little-endian halfs.
2810 */
2811 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2812 /* nothing */ ;
2813 j = i + 4;
2814
2815 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2816 if (!par->mmap_map) {
2817 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2818 return -ENOMEM;
2819 }
2820 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2821
2822 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2823 struct resource *rp = &pdev->resource[i];
2824 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2825 unsigned long base;
2826 u32 size, pbase;
2827
2828 base = rp->start;
2829
2830 io = (rp->flags & IORESOURCE_IO);
2831
2832 size = rp->end - base + 1;
2833
2834 pci_read_config_dword(pdev, breg, &pbase);
2835
2836 if (io)
2837 size &= ~1;
2838
2839 /*
2840 * Map the framebuffer a second time, this time without
2841 * the braindead _PAGE_IE setting. This is used by the
2842 * fixed Xserver, but we need to maintain the old mapping
2843 * to stay compatible with older ones...
2844 */
2845 if (base == addr) {
2846 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2847 par->mmap_map[j].poff = base & PAGE_MASK;
2848 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2849 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2850 par->mmap_map[j].prot_flag = _PAGE_E;
2851 j++;
2852 }
2853
2854 /*
2855 * Here comes the old framebuffer mapping with _PAGE_IE
2856 * set for the big endian half of the framebuffer...
2857 */
2858 if (base == addr) {
2859 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2860 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2861 par->mmap_map[j].size = 0x800000;
2862 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2863 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2864 size -= 0x800000;
2865 j++;
2866 }
2867
2868 par->mmap_map[j].voff = pbase & PAGE_MASK;
2869 par->mmap_map[j].poff = base & PAGE_MASK;
2870 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2871 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2872 par->mmap_map[j].prot_flag = _PAGE_E;
2873 j++;
2874 }
2875
2876 if((ret = correct_chipset(par)))
2877 return ret;
2878
2879 if (IS_XL(pdev->device)) {
2880 /*
2881 * Fix PROMs idea of MEM_CNTL settings...
2882 */
2883 mem = aty_ld_le32(MEM_CNTL, par);
2884 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2885 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2886 switch (mem & 0x0f) {
2887 case 3:
2888 mem = (mem & ~(0x0f)) | 2;
2889 break;
2890 case 7:
2891 mem = (mem & ~(0x0f)) | 3;
2892 break;
2893 case 9:
2894 mem = (mem & ~(0x0f)) | 4;
2895 break;
2896 case 11:
2897 mem = (mem & ~(0x0f)) | 5;
2898 break;
2899 default:
2900 break;
2901 }
2902 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2903 mem &= ~(0x00700000);
2904 }
2905 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2906 aty_st_le32(MEM_CNTL, mem, par);
2907 }
2908
2909 /*
2910 * If this is the console device, we will set default video
2911 * settings to what the PROM left us with.
2912 */
2913 node = prom_getchild(prom_root_node);
2914 node = prom_searchsiblings(node, "aliases");
2915 if (node) {
2916 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2917 if (len > 0) {
2918 prop[len] = '\0';
2919 node = prom_finddevice(prop);
2920 } else
2921 node = 0;
2922 }
2923
2924 pcp = pdev->sysdata;
2925 if (node == pcp->prom_node) {
2926 struct fb_var_screeninfo *var = &default_var;
2927 unsigned int N, P, Q, M, T, R;
2928 u32 v_total, h_total;
2929 struct crtc crtc;
2930 u8 pll_regs[16];
2931 u8 clock_cntl;
2932
2933 crtc.vxres = prom_getintdefault(node, "width", 1024);
2934 crtc.vyres = prom_getintdefault(node, "height", 768);
2935 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2936 var->xoffset = var->yoffset = 0;
2937 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2938 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2939 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2940 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2941 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2942 aty_crtc_to_var(&crtc, var);
2943
2944 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2945 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2946
2947 /*
2948 * Read the PLL to figure actual Refresh Rate.
2949 */
2950 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2951 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2952 for (i = 0; i < 16; i++)
2953 pll_regs[i] = aty_ld_pll_ct(i, par);
2954
2955 /*
2956 * PLL Reference Divider M:
2957 */
2958 M = pll_regs[2];
2959
2960 /*
2961 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
2962 */
2963 N = pll_regs[7 + (clock_cntl & 3)];
2964
2965 /*
2966 * PLL Post Divider P (Dependant on CLOCK_CNTL):
2967 */
2968 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
2969
2970 /*
2971 * PLL Divider Q:
2972 */
2973 Q = N / P;
2974
2975 /*
2976 * Target Frequency:
2977 *
2978 * T * M
2979 * Q = -------
2980 * 2 * R
2981 *
2982 * where R is XTALIN (= 14318 or 29498 kHz).
2983 */
2984 if (IS_XL(pdev->device))
2985 R = 29498;
2986 else
2987 R = 14318;
2988
2989 T = 2 * Q * R / M;
2990
2991 default_var.pixclock = 1000000000 / T;
2992 }
2993
2994 return 0;
2995}
2996
2997#else /* __sparc__ */
2998
2999#ifdef __i386__
3000#ifdef CONFIG_FB_ATY_GENERIC_LCD
3001static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3002{
3003 u32 driv_inf_tab, sig;
3004 u16 lcd_ofs;
3005
3006 /* To support an LCD panel, we should know it's dimensions and
3007 * it's desired pixel clock.
3008 * There are two ways to do it:
3009 * - Check the startup video mode and calculate the panel
3010 * size from it. This is unreliable.
3011 * - Read it from the driver information table in the video BIOS.
3012 */
3013 /* Address of driver information table is at offset 0x78. */
3014 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3015
3016 /* Check for the driver information table signature. */
3017 sig = (*(u32 *)driv_inf_tab);
3018 if ((sig == 0x54504c24) || /* Rage LT pro */
3019 (sig == 0x544d5224) || /* Rage mobility */
3020 (sig == 0x54435824) || /* Rage XC */
3021 (sig == 0x544c5824)) { /* Rage XL */
3022 PRINTKI("BIOS contains driver information table.\n");
3023 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3024 par->lcd_table = 0;
3025 if (lcd_ofs != 0) {
3026 par->lcd_table = bios_base + lcd_ofs;
3027 }
3028 }
3029
3030 if (par->lcd_table != 0) {
3031 char model[24];
3032 char strbuf[16];
3033 char refresh_rates_buf[100];
3034 int id, tech, f, i, m, default_refresh_rate;
3035 char *txtcolour;
3036 char *txtmonitor;
3037 char *txtdual;
3038 char *txtformat;
3039 u16 width, height, panel_type, refresh_rates;
3040 u16 *lcdmodeptr;
3041 u32 format;
3042 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3043 /* The most important information is the panel size at
3044 * offset 25 and 27, but there's some other nice information
3045 * which we print to the screen.
3046 */
3047 id = *(u8 *)par->lcd_table;
3048 strncpy(model,(char *)par->lcd_table+1,24);
3049 model[23]=0;
3050
3051 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3052 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3053 panel_type = *(u16 *)(par->lcd_table+29);
3054 if (panel_type & 1)
3055 txtcolour = "colour";
3056 else
3057 txtcolour = "monochrome";
3058 if (panel_type & 2)
3059 txtdual = "dual (split) ";
3060 else
3061 txtdual = "";
3062 tech = (panel_type>>2) & 63;
3063 switch (tech) {
3064 case 0:
3065 txtmonitor = "passive matrix";
3066 break;
3067 case 1:
3068 txtmonitor = "active matrix";
3069 break;
3070 case 2:
3071 txtmonitor = "active addressed STN";
3072 break;
3073 case 3:
3074 txtmonitor = "EL";
3075 break;
3076 case 4:
3077 txtmonitor = "plasma";
3078 break;
3079 default:
3080 txtmonitor = "unknown";
3081 }
3082 format = *(u32 *)(par->lcd_table+57);
3083 if (tech == 0 || tech == 2) {
3084 switch (format & 7) {
3085 case 0:
3086 txtformat = "12 bit interface";
3087 break;
3088 case 1:
3089 txtformat = "16 bit interface";
3090 break;
3091 case 2:
3092 txtformat = "24 bit interface";
3093 break;
3094 default:
3095 txtformat = "unkown format";
3096 }
3097 } else {
3098 switch (format & 7) {
3099 case 0:
3100 txtformat = "8 colours";
3101 break;
3102 case 1:
3103 txtformat = "512 colours";
3104 break;
3105 case 2:
3106 txtformat = "4096 colours";
3107 break;
3108 case 4:
3109 txtformat = "262144 colours (LT mode)";
3110 break;
3111 case 5:
3112 txtformat = "16777216 colours";
3113 break;
3114 case 6:
3115 txtformat = "262144 colours (FDPI-2 mode)";
3116 break;
3117 default:
3118 txtformat = "unkown format";
3119 }
3120 }
3121 PRINTKI("%s%s %s monitor detected: %s\n",
3122 txtdual ,txtcolour, txtmonitor, model);
3123 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3124 id, width, height, txtformat);
3125 refresh_rates_buf[0] = 0;
3126 refresh_rates = *(u16 *)(par->lcd_table+62);
3127 m = 1;
3128 f = 0;
3129 for (i=0;i<16;i++) {
3130 if (refresh_rates & m) {
3131 if (f == 0) {
3132 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3133 f++;
3134 } else {
3135 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3136 }
3137 strcat(refresh_rates_buf,strbuf);
3138 }
3139 m = m << 1;
3140 }
3141 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3142 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3143 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3144 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3145 /* We now need to determine the crtc parameters for the
3146 * lcd monitor. This is tricky, because they are not stored
3147 * individually in the BIOS. Instead, the BIOS contains a
3148 * table of display modes that work for this monitor.
3149 *
3150 * The idea is that we search for a mode of the same dimensions
3151 * as the dimensions of the lcd monitor. Say our lcd monitor
3152 * is 800x600 pixels, we search for a 800x600 monitor.
3153 * The CRTC parameters we find here are the ones that we need
3154 * to use to simulate other resolutions on the lcd screen.
3155 */
3156 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3157 while (*lcdmodeptr != 0) {
3158 u32 modeptr;
3159 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3160 modeptr = bios_base + *lcdmodeptr;
3161
3162 mwidth = *((u16 *)(modeptr+0));
3163 mheight = *((u16 *)(modeptr+2));
3164
3165 if (mwidth == width && mheight == height) {
3166 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3167 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3168 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3169 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3170 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3171 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3172
3173 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3174 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3175 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3176 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3177
3178 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3179 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3180 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3181 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3182
3183 par->lcd_vtotal++;
3184 par->lcd_vdisp++;
3185 lcd_vsync_start++;
3186
3187 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3188 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3189 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3190 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3191 break;
3192 }
3193
3194 lcdmodeptr++;
3195 }
3196 if (*lcdmodeptr == 0) {
3197 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3198 /* To do: Switch to CRT if possible. */
3199 } else {
3200 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3201 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3202 par->lcd_hdisp,
3203 par->lcd_hdisp + par->lcd_right_margin,
3204 par->lcd_hdisp + par->lcd_right_margin
3205 + par->lcd_hsync_dly + par->lcd_hsync_len,
3206 par->lcd_htotal,
3207 par->lcd_vdisp,
3208 par->lcd_vdisp + par->lcd_lower_margin,
3209 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3210 par->lcd_vtotal);
3211 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3212 par->lcd_pixclock,
3213 par->lcd_hblank_len - (par->lcd_right_margin +
3214 par->lcd_hsync_dly + par->lcd_hsync_len),
3215 par->lcd_hdisp,
3216 par->lcd_right_margin,
3217 par->lcd_hsync_len,
3218 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3219 par->lcd_vdisp,
3220 par->lcd_lower_margin,
3221 par->lcd_vsync_len);
3222 }
3223 }
3224}
3225#endif /* CONFIG_FB_ATY_GENERIC_LCD */
3226
3227static int __devinit init_from_bios(struct atyfb_par *par)
3228{
3229 u32 bios_base, rom_addr;
3230 int ret;
3231
3232 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3233 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3234
3235 /* The BIOS starts with 0xaa55. */
3236 if (*((u16 *)bios_base) == 0xaa55) {
3237
3238 u8 *bios_ptr;
3239 u16 rom_table_offset, freq_table_offset;
3240 PLL_BLOCK_MACH64 pll_block;
3241
3242 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3243
3244 /* check for frequncy table */
3245 bios_ptr = (u8*)bios_base;
3246 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3247 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3248 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3249
3250 PRINTKI("BIOS frequency table:\n");
3251 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3252 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3253 pll_block.ref_freq, pll_block.ref_divider);
3254 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3255 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3256 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3257
3258 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3259 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3260 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3261 par->pll_limits.ref_div = pll_block.ref_divider;
3262 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3263 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3264 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3265 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3266#ifdef CONFIG_FB_ATY_GENERIC_LCD
3267 aty_init_lcd(par, bios_base);
3268#endif
3269 ret = 0;
3270 } else {
3271 PRINTKE("no BIOS frequency table found, use parameters\n");
3272 ret = -ENXIO;
3273 }
3274 iounmap((void* __iomem )bios_base);
3275
3276 return ret;
3277}
3278#endif /* __i386__ */
3279
3280static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3281{
3282 struct atyfb_par *par = info->par;
3283 u16 tmp;
3284 unsigned long raddr;
3285 struct resource *rrp;
3286 int ret = 0;
3287
3288 raddr = addr + 0x7ff000UL;
3289 rrp = &pdev->resource[2];
3290 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3291 par->aux_start = rrp->start;
3292 par->aux_size = rrp->end - rrp->start + 1;
3293 raddr = rrp->start;
3294 PRINTKI("using auxiliary register aperture\n");
3295 }
3296
3297 info->fix.mmio_start = raddr;
3298 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3299 if (par->ati_regbase == 0)
3300 return -ENOMEM;
3301
3302 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3303 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3304
3305 /*
3306 * Enable memory-space accesses using config-space
3307 * command register.
3308 */
3309 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3310 if (!(tmp & PCI_COMMAND_MEMORY)) {
3311 tmp |= PCI_COMMAND_MEMORY;
3312 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3313 }
3314#ifdef __BIG_ENDIAN
3315 /* Use the big-endian aperture */
3316 addr += 0x800000;
3317#endif
3318
3319 /* Map in frame buffer */
3320 info->fix.smem_start = addr;
3321 info->screen_base = ioremap(addr, 0x800000);
3322 if (info->screen_base == NULL) {
3323 ret = -ENOMEM;
3324 goto atyfb_setup_generic_fail;
3325 }
3326
3327 if((ret = correct_chipset(par)))
3328 goto atyfb_setup_generic_fail;
3329#ifdef __i386__
3330 if((ret = init_from_bios(par)))
3331 goto atyfb_setup_generic_fail;
3332#endif
3333 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3334 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3335 else
3336 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3337
3338 /* according to ATI, we should use clock 3 for acelerated mode */
3339 par->clk_wr_offset = 3;
3340
3341 return 0;
3342
3343atyfb_setup_generic_fail:
3344 iounmap(par->ati_regbase);
3345 par->ati_regbase = NULL;
3346 return ret;
3347}
3348
3349#endif /* !__sparc__ */
3350
3351static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3352{
3353 unsigned long addr, res_start, res_size;
3354 struct fb_info *info;
3355 struct resource *rp;
3356 struct atyfb_par *par;
3357 int i, rc = -ENOMEM;
3358
3359 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3360 if (pdev->device == aty_chips[i].pci_id)
3361 break;
3362
3363 if (i < 0)
3364 return -ENODEV;
3365
3366 /* Enable device in PCI config */
3367 if (pci_enable_device(pdev)) {
3368 PRINTKE("Cannot enable PCI device\n");
3369 return -ENXIO;
3370 }
3371
3372 /* Find which resource to use */
3373 rp = &pdev->resource[0];
3374 if (rp->flags & IORESOURCE_IO)
3375 rp = &pdev->resource[1];
3376 addr = rp->start;
3377 if (!addr)
3378 return -ENXIO;
3379
3380 /* Reserve space */
3381 res_start = rp->start;
3382 res_size = rp->end - rp->start + 1;
3383 if (!request_mem_region (res_start, res_size, "atyfb"))
3384 return -EBUSY;
3385
3386 /* Allocate framebuffer */
3387 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3388 if (!info) {
3389 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3390 return -ENOMEM;
3391 }
3392 par = info->par;
3393 info->fix = atyfb_fix;
3394 info->device = &pdev->dev;
3395 par->pci_id = aty_chips[i].pci_id;
3396 par->res_start = res_start;
3397 par->res_size = res_size;
3398 par->irq = pdev->irq;
3399
3400 /* Setup "info" structure */
3401#ifdef __sparc__
3402 rc = atyfb_setup_sparc(pdev, info, addr);
3403#else
3404 rc = atyfb_setup_generic(pdev, info, addr);
3405#endif
3406 if (rc)
3407 goto err_release_mem;
3408
3409 pci_set_drvdata(pdev, info);
3410
3411 /* Init chip & register framebuffer */
3412 if (aty_init(info, "PCI"))
3413 goto err_release_io;
3414
3415#ifdef __sparc__
3416 if (!prom_palette)
3417 prom_palette = atyfb_palette;
3418
3419 /*
3420 * Add /dev/fb mmap values.
3421 */
3422 par->mmap_map[0].voff = 0x8000000000000000UL;
3423 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3424 par->mmap_map[0].size = info->fix.smem_len;
3425 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3426 par->mmap_map[0].prot_flag = _PAGE_E;
3427 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3428 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3429 par->mmap_map[1].size = PAGE_SIZE;
3430 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3431 par->mmap_map[1].prot_flag = _PAGE_E;
3432#endif /* __sparc__ */
3433
3434 return 0;
3435
3436err_release_io:
3437#ifdef __sparc__
3438 kfree(par->mmap_map);
3439#else
3440 if (par->ati_regbase)
3441 iounmap(par->ati_regbase);
3442 if (info->screen_base)
3443 iounmap(info->screen_base);
3444#endif
3445err_release_mem:
3446 if (par->aux_start)
3447 release_mem_region(par->aux_start, par->aux_size);
3448
3449 release_mem_region(par->res_start, par->res_size);
3450 framebuffer_release(info);
3451
3452 return rc;
3453}
3454
3455#endif /* CONFIG_PCI */
3456
3457#ifdef CONFIG_ATARI
3458
3459static int __devinit atyfb_atari_probe(void)
3460{
3461 struct aty_par *par;
3462 struct fb_info *info;
3463 int m64_num;
3464 u32 clock_r;
3465
3466 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3467 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3468 !phys_guiregbase[m64_num]) {
3469 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3470 continue;
3471 }
3472
3473 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3474 if (!info) {
3475 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3476 return -ENOMEM;
3477 }
3478 par = info->par;
3479
3480 info->fix = atyfb_fix;
3481
3482 par->irq = (unsigned int) -1; /* something invalid */
3483
3484 /*
3485 * Map the video memory (physical address given) to somewhere in the
3486 * kernel address space.
3487 */
3488 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3489 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3490 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3491 0xFC00ul;
3492 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3493
3494 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3495 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3496
3497 switch (clock_r & 0x003F) {
3498 case 0x12:
3499 par->clk_wr_offset = 3; /* */
3500 break;
3501 case 0x34:
3502 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3503 break;
3504 case 0x16:
3505 par->clk_wr_offset = 1; /* */
3506 break;
3507 case 0x38:
3508 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3509 break;
3510 }
3511
3512 if (aty_init(info, "ISA bus")) {
3513 framebuffer_release(info);
3514 /* This is insufficient! kernel_map has added two large chunks!! */
3515 return -ENXIO;
3516 }
3517 }
3518}
3519
3520#endif /* CONFIG_ATARI */
3521
3522static void __devexit atyfb_remove(struct fb_info *info)
3523{
3524 struct atyfb_par *par = (struct atyfb_par *) info->par;
3525
3526 /* restore video mode */
3527 aty_set_crtc(par, &saved_crtc);
3528 par->pll_ops->set_pll(info, &saved_pll);
3529
3530 unregister_framebuffer(info);
3531
3532#ifdef CONFIG_MTRR
3533 if (par->mtrr_reg >= 0) {
3534 mtrr_del(par->mtrr_reg, 0, 0);
3535 par->mtrr_reg = -1;
3536 }
3537 if (par->mtrr_aper >= 0) {
3538 mtrr_del(par->mtrr_aper, 0, 0);
3539 par->mtrr_aper = -1;
3540 }
3541#endif
3542#ifndef __sparc__
3543 if (par->ati_regbase)
3544 iounmap(par->ati_regbase);
3545 if (info->screen_base)
3546 iounmap(info->screen_base);
3547#ifdef __BIG_ENDIAN
3548 if (info->sprite.addr)
3549 iounmap(info->sprite.addr);
3550#endif
3551#endif
3552#ifdef __sparc__
3553 kfree(par->mmap_map);
3554#endif
3555 if (par->aux_start)
3556 release_mem_region(par->aux_start, par->aux_size);
3557
3558 if (par->res_start)
3559 release_mem_region(par->res_start, par->res_size);
3560
3561 framebuffer_release(info);
3562}
3563
3564#ifdef CONFIG_PCI
3565
3566static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3567{
3568 struct fb_info *info = pci_get_drvdata(pdev);
3569
3570 atyfb_remove(info);
3571}
3572
3573/*
3574 * This driver uses its own matching table. That will be more difficult
3575 * to fix, so for now, we just match against any ATI ID and let the
3576 * probe() function find out what's up. That also mean we don't have
3577 * a module ID table though.
3578 */
3579static struct pci_device_id atyfb_pci_tbl[] = {
3580 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3581 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3582 { 0, }
3583};
3584
3585static struct pci_driver atyfb_driver = {
3586 .name = "atyfb",
3587 .id_table = atyfb_pci_tbl,
3588 .probe = atyfb_pci_probe,
3589 .remove = __devexit_p(atyfb_pci_remove),
3590#ifdef CONFIG_PM
3591 .suspend = atyfb_pci_suspend,
3592 .resume = atyfb_pci_resume,
3593#endif /* CONFIG_PM */
3594};
3595
3596#endif /* CONFIG_PCI */
3597
3598#ifndef MODULE
3599static int __init atyfb_setup(char *options)
3600{
3601 char *this_opt;
3602
3603 if (!options || !*options)
3604 return 0;
3605
3606 while ((this_opt = strsep(&options, ",")) != NULL) {
3607 if (!strncmp(this_opt, "noaccel", 7)) {
3608 noaccel = 1;
3609#ifdef CONFIG_MTRR
3610 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3611 nomtrr = 1;
3612#endif
3613 } else if (!strncmp(this_opt, "vram:", 5))
3614 vram = simple_strtoul(this_opt + 5, NULL, 0);
3615 else if (!strncmp(this_opt, "pll:", 4))
3616 pll = simple_strtoul(this_opt + 4, NULL, 0);
3617 else if (!strncmp(this_opt, "mclk:", 5))
3618 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3619 else if (!strncmp(this_opt, "xclk:", 5))
3620 xclk = simple_strtoul(this_opt+5, NULL, 0);
3621 else if (!strncmp(this_opt, "comp_sync:", 10))
3622 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3623#ifdef CONFIG_PPC
3624 else if (!strncmp(this_opt, "vmode:", 6)) {
3625 unsigned int vmode =
3626 simple_strtoul(this_opt + 6, NULL, 0);
3627 if (vmode > 0 && vmode <= VMODE_MAX)
3628 default_vmode = vmode;
3629 } else if (!strncmp(this_opt, "cmode:", 6)) {
3630 unsigned int cmode =
3631 simple_strtoul(this_opt + 6, NULL, 0);
3632 switch (cmode) {
3633 case 0:
3634 case 8:
3635 default_cmode = CMODE_8;
3636 break;
3637 case 15:
3638 case 16:
3639 default_cmode = CMODE_16;
3640 break;
3641 case 24:
3642 case 32:
3643 default_cmode = CMODE_32;
3644 break;
3645 }
3646 }
3647#endif
3648#ifdef CONFIG_ATARI
3649 /*
3650 * Why do we need this silly Mach64 argument?
3651 * We are already here because of mach64= so its redundant.
3652 */
3653 else if (MACH_IS_ATARI
3654 && (!strncmp(this_opt, "Mach64:", 7))) {
3655 static unsigned char m64_num;
3656 static char mach64_str[80];
3657 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3658 if (!store_video_par(mach64_str, m64_num)) {
3659 m64_num++;
3660 mach64_count = m64_num;
3661 }
3662 }
3663#endif
3664 else
3665 mode = this_opt;
3666 }
3667 return 0;
3668}
3669#endif /* MODULE */
3670
3671static int __init atyfb_init(void)
3672{
3673#ifndef MODULE
3674 char *option = NULL;
3675
3676 if (fb_get_options("atyfb", &option))
3677 return -ENODEV;
3678 atyfb_setup(option);
3679#endif
3680
3681#ifdef CONFIG_PCI
3682 pci_register_driver(&atyfb_driver);
3683#endif
3684#ifdef CONFIG_ATARI
3685 atyfb_atari_probe();
3686#endif
3687 return 0;
3688}
3689
3690static void __exit atyfb_exit(void)
3691{
3692#ifdef CONFIG_PCI
3693 pci_unregister_driver(&atyfb_driver);
3694#endif
3695}
3696
3697module_init(atyfb_init);
3698module_exit(atyfb_exit);
3699
3700MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3701MODULE_LICENSE("GPL");
3702module_param(noaccel, bool, 0);
3703MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3704module_param(vram, int, 0);
3705MODULE_PARM_DESC(vram, "int: override size of video ram");
3706module_param(pll, int, 0);
3707MODULE_PARM_DESC(pll, "int: override video clock");
3708module_param(mclk, int, 0);
3709MODULE_PARM_DESC(mclk, "int: override memory clock");
3710module_param(xclk, int, 0);
3711MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3712module_param(comp_sync, int, 0);
3713MODULE_PARM_DESC(comp_sync,
3714 "Set composite sync signal to low (0) or high (1)");
3715module_param(mode, charp, 0);
3716MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3717#ifdef CONFIG_MTRR
3718module_param(nomtrr, bool, 0);
3719MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3720#endif
diff --git a/drivers/video/aty/mach64_accel.c b/drivers/video/aty/mach64_accel.c
new file mode 100644
index 000000000000..c98f4a442134
--- /dev/null
+++ b/drivers/video/aty/mach64_accel.c
@@ -0,0 +1,433 @@
1
2/*
3 * ATI Mach64 Hardware Acceleration
4 */
5
6#include <linux/sched.h>
7#include <linux/delay.h>
8#include <linux/fb.h>
9#include <video/mach64.h>
10#include "atyfb.h"
11
12 /*
13 * Generic Mach64 routines
14 */
15
16/* this is for DMA GUI engine! work in progress */
17typedef struct {
18 u32 frame_buf_offset;
19 u32 system_mem_addr;
20 u32 command;
21 u32 reserved;
22} BM_DESCRIPTOR_ENTRY;
23
24#define LAST_DESCRIPTOR (1 << 31)
25#define SYSTEM_TO_FRAME_BUFFER 0
26
27static u32 rotation24bpp(u32 dx, u32 direction)
28{
29 u32 rotation;
30 if (direction & DST_X_LEFT_TO_RIGHT) {
31 rotation = (dx / 4) % 6;
32 } else {
33 rotation = ((dx + 2) / 4) % 6;
34 }
35
36 return ((rotation << 8) | DST_24_ROTATION_ENABLE);
37}
38
39void aty_reset_engine(const struct atyfb_par *par)
40{
41 /* reset engine */
42 aty_st_le32(GEN_TEST_CNTL,
43 aty_ld_le32(GEN_TEST_CNTL, par) & ~GUI_ENGINE_ENABLE, par);
44 /* enable engine */
45 aty_st_le32(GEN_TEST_CNTL,
46 aty_ld_le32(GEN_TEST_CNTL, par) | GUI_ENGINE_ENABLE, par);
47 /* ensure engine is not locked up by clearing any FIFO or */
48 /* HOST errors */
49 aty_st_le32(BUS_CNTL,
50 aty_ld_le32(BUS_CNTL, par) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK, par);
51}
52
53static void reset_GTC_3D_engine(const struct atyfb_par *par)
54{
55 aty_st_le32(SCALE_3D_CNTL, 0xc0, par);
56 mdelay(GTC_3D_RESET_DELAY);
57 aty_st_le32(SETUP_CNTL, 0x00, par);
58 mdelay(GTC_3D_RESET_DELAY);
59 aty_st_le32(SCALE_3D_CNTL, 0x00, par);
60 mdelay(GTC_3D_RESET_DELAY);
61}
62
63void aty_init_engine(struct atyfb_par *par, struct fb_info *info)
64{
65 u32 pitch_value;
66
67 /* determine modal information from global mode structure */
68 pitch_value = info->var.xres_virtual;
69
70 if (info->var.bits_per_pixel == 24) {
71 /* In 24 bpp, the engine is in 8 bpp - this requires that all */
72 /* horizontal coordinates and widths must be adjusted */
73 pitch_value *= 3;
74 }
75
76 /* On GTC (RagePro), we need to reset the 3D engine before */
77 if (M64_HAS(RESET_3D))
78 reset_GTC_3D_engine(par);
79
80 /* Reset engine, enable, and clear any engine errors */
81 aty_reset_engine(par);
82 /* Ensure that vga page pointers are set to zero - the upper */
83 /* page pointers are set to 1 to handle overflows in the */
84 /* lower page */
85 aty_st_le32(MEM_VGA_WP_SEL, 0x00010000, par);
86 aty_st_le32(MEM_VGA_RP_SEL, 0x00010000, par);
87
88 /* ---- Setup standard engine context ---- */
89
90 /* All GUI registers here are FIFOed - therefore, wait for */
91 /* the appropriate number of empty FIFO entries */
92 wait_for_fifo(14, par);
93
94 /* enable all registers to be loaded for context loads */
95 aty_st_le32(CONTEXT_MASK, 0xFFFFFFFF, par);
96
97 /* set destination pitch to modal pitch, set offset to zero */
98 aty_st_le32(DST_OFF_PITCH, (pitch_value / 8) << 22, par);
99
100 /* zero these registers (set them to a known state) */
101 aty_st_le32(DST_Y_X, 0, par);
102 aty_st_le32(DST_HEIGHT, 0, par);
103 aty_st_le32(DST_BRES_ERR, 0, par);
104 aty_st_le32(DST_BRES_INC, 0, par);
105 aty_st_le32(DST_BRES_DEC, 0, par);
106
107 /* set destination drawing attributes */
108 aty_st_le32(DST_CNTL, DST_LAST_PEL | DST_Y_TOP_TO_BOTTOM |
109 DST_X_LEFT_TO_RIGHT, par);
110
111 /* set source pitch to modal pitch, set offset to zero */
112 aty_st_le32(SRC_OFF_PITCH, (pitch_value / 8) << 22, par);
113
114 /* set these registers to a known state */
115 aty_st_le32(SRC_Y_X, 0, par);
116 aty_st_le32(SRC_HEIGHT1_WIDTH1, 1, par);
117 aty_st_le32(SRC_Y_X_START, 0, par);
118 aty_st_le32(SRC_HEIGHT2_WIDTH2, 1, par);
119
120 /* set source pixel retrieving attributes */
121 aty_st_le32(SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT, par);
122
123 /* set host attributes */
124 wait_for_fifo(13, par);
125 aty_st_le32(HOST_CNTL, 0, par);
126
127 /* set pattern attributes */
128 aty_st_le32(PAT_REG0, 0, par);
129 aty_st_le32(PAT_REG1, 0, par);
130 aty_st_le32(PAT_CNTL, 0, par);
131
132 /* set scissors to modal size */
133 aty_st_le32(SC_LEFT, 0, par);
134 aty_st_le32(SC_TOP, 0, par);
135 aty_st_le32(SC_BOTTOM, par->crtc.vyres - 1, par);
136 aty_st_le32(SC_RIGHT, pitch_value - 1, par);
137
138 /* set background color to minimum value (usually BLACK) */
139 aty_st_le32(DP_BKGD_CLR, 0, par);
140
141 /* set foreground color to maximum value (usually WHITE) */
142 aty_st_le32(DP_FRGD_CLR, 0xFFFFFFFF, par);
143
144 /* set write mask to effect all pixel bits */
145 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF, par);
146
147 /* set foreground mix to overpaint and background mix to */
148 /* no-effect */
149 aty_st_le32(DP_MIX, FRGD_MIX_S | BKGD_MIX_D, par);
150
151 /* set primary source pixel channel to foreground color */
152 /* register */
153 aty_st_le32(DP_SRC, FRGD_SRC_FRGD_CLR, par);
154
155 /* set compare functionality to false (no-effect on */
156 /* destination) */
157 wait_for_fifo(3, par);
158 aty_st_le32(CLR_CMP_CLR, 0, par);
159 aty_st_le32(CLR_CMP_MASK, 0xFFFFFFFF, par);
160 aty_st_le32(CLR_CMP_CNTL, 0, par);
161
162 /* set pixel depth */
163 wait_for_fifo(2, par);
164 aty_st_le32(DP_PIX_WIDTH, par->crtc.dp_pix_width, par);
165 aty_st_le32(DP_CHAIN_MASK, par->crtc.dp_chain_mask, par);
166
167 wait_for_fifo(5, par);
168 aty_st_le32(SCALE_3D_CNTL, 0, par);
169 aty_st_le32(Z_CNTL, 0, par);
170 aty_st_le32(CRTC_INT_CNTL, aty_ld_le32(CRTC_INT_CNTL, par) & ~0x20,
171 par);
172 aty_st_le32(GUI_TRAJ_CNTL, 0x100023, par);
173
174 /* insure engine is idle before leaving */
175 wait_for_idle(par);
176}
177
178 /*
179 * Accelerated functions
180 */
181
182static inline void draw_rect(s16 x, s16 y, u16 width, u16 height,
183 struct atyfb_par *par)
184{
185 /* perform rectangle fill */
186 wait_for_fifo(2, par);
187 aty_st_le32(DST_Y_X, (x << 16) | y, par);
188 aty_st_le32(DST_HEIGHT_WIDTH, (width << 16) | height, par);
189 par->blitter_may_be_busy = 1;
190}
191
192void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
193{
194 struct atyfb_par *par = (struct atyfb_par *) info->par;
195 u32 dy = area->dy, sy = area->sy, direction = DST_LAST_PEL;
196 u32 sx = area->sx, dx = area->dx, width = area->width, rotation = 0;
197
198 if (par->asleep)
199 return;
200 if (!area->width || !area->height)
201 return;
202 if (!par->accel_flags) {
203 if (par->blitter_may_be_busy)
204 wait_for_idle(par);
205 cfb_copyarea(info, area);
206 return;
207 }
208
209 if (info->var.bits_per_pixel == 24) {
210 /* In 24 bpp, the engine is in 8 bpp - this requires that all */
211 /* horizontal coordinates and widths must be adjusted */
212 sx *= 3;
213 dx *= 3;
214 width *= 3;
215 }
216
217 if (area->sy < area->dy) {
218 dy += area->height - 1;
219 sy += area->height - 1;
220 } else
221 direction |= DST_Y_TOP_TO_BOTTOM;
222
223 if (sx < dx) {
224 dx += width - 1;
225 sx += width - 1;
226 } else
227 direction |= DST_X_LEFT_TO_RIGHT;
228
229 if (info->var.bits_per_pixel == 24) {
230 rotation = rotation24bpp(dx, direction);
231 }
232
233 wait_for_fifo(4, par);
234 aty_st_le32(DP_SRC, FRGD_SRC_BLIT, par);
235 aty_st_le32(SRC_Y_X, (sx << 16) | sy, par);
236 aty_st_le32(SRC_HEIGHT1_WIDTH1, (width << 16) | area->height, par);
237 aty_st_le32(DST_CNTL, direction | rotation, par);
238 draw_rect(dx, dy, width, area->height, par);
239}
240
241void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
242{
243 struct atyfb_par *par = (struct atyfb_par *) info->par;
244 u32 color = rect->color, dx = rect->dx, width = rect->width, rotation = 0;
245
246 if (par->asleep)
247 return;
248 if (!rect->width || !rect->height)
249 return;
250 if (!par->accel_flags) {
251 if (par->blitter_may_be_busy)
252 wait_for_idle(par);
253 cfb_fillrect(info, rect);
254 return;
255 }
256
257 color |= (rect->color << 8);
258 color |= (rect->color << 16);
259
260 if (info->var.bits_per_pixel == 24) {
261 /* In 24 bpp, the engine is in 8 bpp - this requires that all */
262 /* horizontal coordinates and widths must be adjusted */
263 dx *= 3;
264 width *= 3;
265 rotation = rotation24bpp(dx, DST_X_LEFT_TO_RIGHT);
266 }
267
268 wait_for_fifo(3, par);
269 aty_st_le32(DP_FRGD_CLR, color, par);
270 aty_st_le32(DP_SRC,
271 BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR | MONO_SRC_ONE,
272 par);
273 aty_st_le32(DST_CNTL,
274 DST_LAST_PEL | DST_Y_TOP_TO_BOTTOM |
275 DST_X_LEFT_TO_RIGHT | rotation, par);
276 draw_rect(dx, rect->dy, width, rect->height, par);
277}
278
279void atyfb_imageblit(struct fb_info *info, const struct fb_image *image)
280{
281 struct atyfb_par *par = (struct atyfb_par *) info->par;
282 u32 src_bytes, dx = image->dx, dy = image->dy, width = image->width;
283 u32 pix_width_save, pix_width, host_cntl, rotation = 0, src, mix;
284
285 if (par->asleep)
286 return;
287 if (!image->width || !image->height)
288 return;
289 if (!par->accel_flags ||
290 (image->depth != 1 && info->var.bits_per_pixel != image->depth)) {
291 if (par->blitter_may_be_busy)
292 wait_for_idle(par);
293
294 cfb_imageblit(info, image);
295 return;
296 }
297
298 wait_for_idle(par);
299 pix_width = pix_width_save = aty_ld_le32(DP_PIX_WIDTH, par);
300 host_cntl = aty_ld_le32(HOST_CNTL, par) | HOST_BYTE_ALIGN;
301
302 switch (image->depth) {
303 case 1:
304 pix_width &= ~(BYTE_ORDER_MASK | HOST_MASK);
305 pix_width |= (BYTE_ORDER_MSB_TO_LSB | HOST_1BPP);
306 break;
307 case 4:
308 pix_width &= ~(BYTE_ORDER_MASK | HOST_MASK);
309 pix_width |= (BYTE_ORDER_MSB_TO_LSB | HOST_4BPP);
310 break;
311 case 8:
312 pix_width &= ~HOST_MASK;
313 pix_width |= HOST_8BPP;
314 break;
315 case 15:
316 pix_width &= ~HOST_MASK;
317 pix_width |= HOST_15BPP;
318 break;
319 case 16:
320 pix_width &= ~HOST_MASK;
321 pix_width |= HOST_16BPP;
322 break;
323 case 24:
324 pix_width &= ~HOST_MASK;
325 pix_width |= HOST_24BPP;
326 break;
327 case 32:
328 pix_width &= ~HOST_MASK;
329 pix_width |= HOST_32BPP;
330 break;
331 }
332
333 if (info->var.bits_per_pixel == 24) {
334 /* In 24 bpp, the engine is in 8 bpp - this requires that all */
335 /* horizontal coordinates and widths must be adjusted */
336 dx *= 3;
337 width *= 3;
338
339 rotation = rotation24bpp(dx, DST_X_LEFT_TO_RIGHT);
340
341 pix_width &= ~DST_MASK;
342 pix_width |= DST_8BPP;
343
344 /*
345 * since Rage 3D IIc we have DP_HOST_TRIPLE_EN bit
346 * this hwaccelerated triple has an issue with not aligned data
347 */
348 if (M64_HAS(HW_TRIPLE) && image->width % 8 == 0)
349 pix_width |= DP_HOST_TRIPLE_EN;
350 }
351
352 if (image->depth == 1) {
353 u32 fg, bg;
354 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
355 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
356 fg = ((u32*)(info->pseudo_palette))[image->fg_color];
357 bg = ((u32*)(info->pseudo_palette))[image->bg_color];
358 } else {
359 fg = image->fg_color;
360 bg = image->bg_color;
361 }
362
363 wait_for_fifo(2, par);
364 aty_st_le32(DP_BKGD_CLR, bg, par);
365 aty_st_le32(DP_FRGD_CLR, fg, par);
366 src = MONO_SRC_HOST | FRGD_SRC_FRGD_CLR | BKGD_SRC_BKGD_CLR;
367 mix = FRGD_MIX_S | BKGD_MIX_S;
368 } else {
369 src = MONO_SRC_ONE | FRGD_SRC_HOST;
370 mix = FRGD_MIX_D_XOR_S | BKGD_MIX_D;
371 }
372
373 wait_for_fifo(6, par);
374 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF, par);
375 aty_st_le32(DP_PIX_WIDTH, pix_width, par);
376 aty_st_le32(DP_MIX, mix, par);
377 aty_st_le32(DP_SRC, src, par);
378 aty_st_le32(HOST_CNTL, host_cntl, par);
379 aty_st_le32(DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT | rotation, par);
380
381 draw_rect(dx, dy, width, image->height, par);
382 src_bytes = (((image->width * image->depth) + 7) / 8) * image->height;
383
384 /* manual triple each pixel */
385 if (info->var.bits_per_pixel == 24 && !(pix_width & DP_HOST_TRIPLE_EN)) {
386 int inbit, outbit, mult24, byte_id_in_dword, width;
387 u8 *pbitmapin = (u8*)image->data, *pbitmapout;
388 u32 hostdword;
389
390 for (width = image->width, inbit = 7, mult24 = 0; src_bytes; ) {
391 for (hostdword = 0, pbitmapout = (u8*)&hostdword, byte_id_in_dword = 0;
392 byte_id_in_dword < 4 && src_bytes;
393 byte_id_in_dword++, pbitmapout++) {
394 for (outbit = 7; outbit >= 0; outbit--) {
395 *pbitmapout |= (((*pbitmapin >> inbit) & 1) << outbit);
396 mult24++;
397 /* next bit */
398 if (mult24 == 3) {
399 mult24 = 0;
400 inbit--;
401 width--;
402 }
403
404 /* next byte */
405 if (inbit < 0 || width == 0) {
406 src_bytes--;
407 pbitmapin++;
408 inbit = 7;
409
410 if (width == 0) {
411 width = image->width;
412 outbit = 0;
413 }
414 }
415 }
416 }
417 wait_for_fifo(1, par);
418 aty_st_le32(HOST_DATA0, hostdword, par);
419 }
420 } else {
421 u32 *pbitmap, dwords = (src_bytes + 3) / 4;
422 for (pbitmap = (u32*)(image->data); dwords; dwords--, pbitmap++) {
423 wait_for_fifo(1, par);
424 aty_st_le32(HOST_DATA0, le32_to_cpup(pbitmap), par);
425 }
426 }
427
428 wait_for_idle(par);
429
430 /* restore pix_width */
431 wait_for_fifo(1, par);
432 aty_st_le32(DP_PIX_WIDTH, pix_width_save, par);
433}
diff --git a/drivers/video/aty/mach64_ct.c b/drivers/video/aty/mach64_ct.c
new file mode 100644
index 000000000000..9bdb2aab01aa
--- /dev/null
+++ b/drivers/video/aty/mach64_ct.c
@@ -0,0 +1,619 @@
1
2/*
3 * ATI Mach64 CT/VT/GT/LT Support
4 */
5
6#include <linux/fb.h>
7#include <linux/delay.h>
8#include <asm/io.h>
9#include <video/mach64.h>
10#include "atyfb.h"
11
12#undef DEBUG
13
14static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
15static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
16static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
17static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
18
19u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par)
20{
21 u8 res;
22
23 /* write addr byte */
24 aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par);
25 /* read the register value */
26 res = aty_ld_8(CLOCK_CNTL_DATA, par);
27 return res;
28}
29
30void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
31{
32 /* write addr byte */
33 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
34 /* write the register value */
35 aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par);
36 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
37}
38
39/*
40 * by Daniel Mantione
41 * <daniel.mantione@freepascal.org>
42 *
43 *
44 * ATI Mach64 CT clock synthesis description.
45 *
46 * All clocks on the Mach64 can be calculated using the same principle:
47 *
48 * XTALIN * x * FB_DIV
49 * CLK = ----------------------
50 * PLL_REF_DIV * POST_DIV
51 *
52 * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz.
53 * PLL_REF_DIV can be set by the user, but is the same for all clocks.
54 * FB_DIV can be set by the user for each clock individually, it should be set
55 * between 128 and 255, the chip will generate a bad clock signal for too low
56 * values.
57 * x depends on the type of clock; usually it is 2, but for the MCLK it can also
58 * be set to 4.
59 * POST_DIV can be set by the user for each clock individually, Possible values
60 * are 1,2,4,8 and for some clocks other values are available too.
61 * CLK is of course the clock speed that is generated.
62 *
63 * The Mach64 has these clocks:
64 *
65 * MCLK The clock rate of the chip
66 * XCLK The clock rate of the on-chip memory
67 * VCLK0 First pixel clock of first CRT controller
68 * VCLK1 Second pixel clock of first CRT controller
69 * VCLK2 Third pixel clock of first CRT controller
70 * VCLK3 Fourth pixel clock of first CRT controller
71 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
72 * V2CLK Pixel clock of the second CRT controller.
73 * SCLK Multi-purpose clock
74 *
75 * - MCLK and XCLK use the same FB_DIV
76 * - VCLK0 .. VCLK3 use the same FB_DIV
77 * - V2CLK is needed when the second CRTC is used (can be used for dualhead);
78 * i.e. CRT monitor connected to laptop has different resolution than built
79 * in LCD monitor.
80 * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO,
81 * Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT.
82 * - V2CLK is not available on all cards, most likely only the Rage LT-PRO,
83 * the Rage XL and the Rage Mobility
84 *
85 * SCLK can be used to:
86 * - Clock the chip instead of MCLK
87 * - Replace XTALIN with a user defined frequency
88 * - Generate the pixel clock for the LCD monitor (instead of VCLK)
89 */
90
91 /*
92 * It can be quite hard to calculate XCLK and MCLK if they don't run at the
93 * same frequency. Luckily, until now all cards that need asynchrone clock
94 * speeds seem to have SCLK.
95 * So this driver uses SCLK to clock the chip and XCLK to clock the memory.
96 */
97
98/* ------------------------------------------------------------------------- */
99
100/*
101 * PLL programming (Mach64 CT family)
102 *
103 *
104 * This procedure sets the display fifo. The display fifo is a buffer that
105 * contains data read from the video memory that waits to be processed by
106 * the CRT controller.
107 *
108 * On the more modern Mach64 variants, the chip doesn't calculate the
109 * interval after which the display fifo has to be reloaded from memory
110 * automatically, the driver has to do it instead.
111 */
112
113#define Maximum_DSP_PRECISION 7
114static u8 postdividers[] = {1,2,4,8,3};
115
116static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
117{
118 u32 dsp_off, dsp_on, dsp_xclks;
119 u32 multiplier, divider, ras_multiplier, ras_divider, tmp;
120 u8 vshift, xshift;
121 s8 dsp_precision;
122
123 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
124 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
125
126 ras_multiplier = pll->xclkmaxrasdelay;
127 ras_divider = 1;
128
129 if (bpp>=8)
130 divider = divider * (bpp >> 2);
131
132 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */
133
134 if (bpp == 0)
135 vshift--; /* ... but only 32 bits in VGA mode. */
136
137#ifdef CONFIG_FB_ATY_GENERIC_LCD
138 if (pll->xres != 0) {
139 struct atyfb_par *par = (struct atyfb_par *) info->par;
140
141 multiplier = multiplier * par->lcd_width;
142 divider = divider * pll->xres & ~7;
143
144 ras_multiplier = ras_multiplier * par->lcd_width;
145 ras_divider = ras_divider * pll->xres & ~7;
146 }
147#endif
148 /* If we don't do this, 32 bits for multiplier & divider won't be
149 enough in certain situations! */
150 while (((multiplier | divider) & 1) == 0) {
151 multiplier = multiplier >> 1;
152 divider = divider >> 1;
153 }
154
155 /* Determine DSP precision first */
156 tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
157
158 for (dsp_precision = -5; tmp; dsp_precision++)
159 tmp >>= 1;
160 if (dsp_precision < 0)
161 dsp_precision = 0;
162 else if (dsp_precision > Maximum_DSP_PRECISION)
163 dsp_precision = Maximum_DSP_PRECISION;
164
165 xshift = 6 - dsp_precision;
166 vshift += xshift;
167
168 /* Move on to dsp_off */
169 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
170 (1 << (vshift - xshift));
171
172/* if (bpp == 0)
173 dsp_on = ((multiplier * 20 << vshift) + divider) / divider;
174 else */
175 {
176 dsp_on = ((multiplier << vshift) + divider) / divider;
177 tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider;
178 if (dsp_on < tmp)
179 dsp_on = tmp;
180 dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
181 }
182
183 /* Calculate rounding factor and apply it to dsp_on */
184 tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1;
185 dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1);
186
187 if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) {
188 dsp_on = dsp_off - (multiplier << vshift) / divider;
189 dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1);
190 }
191
192 /* Last but not least: dsp_xclks */
193 dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider;
194
195 /* Get register values. */
196 pll->dsp_on_off = (dsp_on << 16) + dsp_off;
197 pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
198#ifdef DEBUG
199 printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n",
200 __FUNCTION__, pll->dsp_config, pll->dsp_on_off);
201#endif
202 return 0;
203}
204
205static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
206{
207 u32 q;
208 struct atyfb_par *par = (struct atyfb_par *) info->par;
209#ifdef DEBUG
210 int pllvclk;
211#endif
212
213 /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
214 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
215 if (q < 16*8 || q > 255*8) {
216 printk(KERN_CRIT "atyfb: vclk out of range\n");
217 return -EINVAL;
218 } else {
219 pll->vclk_post_div = (q < 128*8);
220 pll->vclk_post_div += (q < 64*8);
221 pll->vclk_post_div += (q < 32*8);
222 }
223 pll->vclk_post_div_real = postdividers[pll->vclk_post_div];
224 // pll->vclk_post_div <<= 6;
225 pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
226#ifdef DEBUG
227 pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
228 (par->ref_clk_per * pll->pll_ref_div);
229 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n",
230 __FUNCTION__, pllvclk, pllvclk / pll->vclk_post_div_real);
231#endif
232 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
233 return 0;
234}
235
236static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
237{
238 struct atyfb_par *par = (struct atyfb_par *) info->par;
239 int err;
240
241 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
242 return err;
243 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
244 return err;
245 /*aty_calc_pll_ct(info, &pll->ct);*/
246 return 0;
247}
248
249static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
250{
251 struct atyfb_par *par = (struct atyfb_par *) info->par;
252 u32 ret;
253 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
254#ifdef CONFIG_FB_ATY_GENERIC_LCD
255 if(pll->ct.xres > 0) {
256 ret *= par->lcd_width;
257 ret /= pll->ct.xres;
258 }
259#endif
260#ifdef DEBUG
261 printk("atyfb(%s): calculated 0x%08X(%i)\n", __FUNCTION__, ret, ret);
262#endif
263 return ret;
264}
265
266void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
267{
268 struct atyfb_par *par = (struct atyfb_par *) info->par;
269 u32 crtc_gen_cntl, lcd_gen_cntrl;
270 u8 tmp, tmp2;
271
272 lcd_gen_cntrl = 0;
273#ifdef DEBUG
274 printk("atyfb(%s): about to program:\n"
275 "pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n",
276 __FUNCTION__,
277 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
278
279 printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n",
280 __FUNCTION__,
281 par->clk_wr_offset, pll->ct.vclk_fb_div,
282 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
283#endif
284#ifdef CONFIG_FB_ATY_GENERIC_LCD
285 if (par->lcd_table != 0) {
286 /* turn off LCD */
287 lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par);
288 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par);
289 }
290#endif
291 aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par);
292
293 /* Temporarily switch to accelerator mode */
294 crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
295 if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
296 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par);
297
298 /* Reset VCLK generator */
299 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
300
301 /* Set post-divider */
302 tmp2 = par->clk_wr_offset << 1;
303 tmp = aty_ld_pll_ct(VCLK_POST_DIV, par);
304 tmp &= ~(0x03U << tmp2);
305 tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
306 aty_st_pll_ct(VCLK_POST_DIV, tmp, par);
307
308 /* Set extended post-divider */
309 tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par);
310 tmp &= ~(0x10U << par->clk_wr_offset);
311 tmp &= 0xF0U;
312 tmp |= pll->ct.pll_ext_cntl;
313 aty_st_pll_ct(PLL_EXT_CNTL, tmp, par);
314
315 /* Set feedback divider */
316 tmp = VCLK0_FB_DIV + par->clk_wr_offset;
317 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
318
319 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
320
321 /* End VCLK generator reset */
322 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
323 mdelay(5);
324
325 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
326 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
327 mdelay(1);
328
329 /* Restore mode register */
330 if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
331 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par);
332
333 if (M64_HAS(GTB_DSP)) {
334 u8 dll_cntl;
335
336 if (M64_HAS(XL_DLL))
337 dll_cntl = 0x80;
338 else if (par->ram_type >= SDRAM)
339 dll_cntl = 0xa6;
340 else
341 dll_cntl = 0xa0;
342 aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
343 aty_st_pll_ct(VFC_CNTL, 0x1b, par);
344 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
345 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
346
347 mdelay(10);
348 aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
349 mdelay(10);
350 aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par);
351 mdelay(10);
352 aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par);
353 }
354#ifdef CONFIG_FB_ATY_GENERIC_LCD
355 if (par->lcd_table != 0) {
356 /* restore LCD */
357 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par);
358 }
359#endif
360}
361
362static void __init aty_get_pll_ct(const struct fb_info *info,
363 union aty_pll *pll)
364{
365 struct atyfb_par *par = (struct atyfb_par *) info->par;
366 u8 tmp, clock;
367
368 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
369 tmp = clock << 1;
370 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
371
372 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
373 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
374 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
375 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
376
377 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
378 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
379
380 if (M64_HAS(GTB_DSP)) {
381 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
382 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
383 }
384}
385
386static int __init aty_init_pll_ct(const struct fb_info *info,
387 union aty_pll *pll)
388{
389 struct atyfb_par *par = (struct atyfb_par *) info->par;
390 u8 mpost_div, xpost_div, sclk_post_div_real, sclk_fb_div, spll_cntl2;
391 u32 q, i, memcntl, trp;
392 u32 dsp_config, dsp_on_off, vga_dsp_config, vga_dsp_on_off;
393#ifdef DEBUG
394 int pllmclk, pllsclk;
395#endif
396 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
397 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
398 pll->ct.xclk_ref_div = 1;
399 switch (pll->ct.xclk_post_div) {
400 case 0: case 1: case 2: case 3:
401 break;
402
403 case 4:
404 pll->ct.xclk_ref_div = 3;
405 pll->ct.xclk_post_div = 0;
406 break;
407
408 default:
409 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
410 return -EINVAL;
411 }
412 pll->ct.mclk_fb_mult = 2;
413 if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
414 pll->ct.mclk_fb_mult = 4;
415 pll->ct.xclk_post_div -= 1;
416 }
417
418#ifdef DEBUG
419 printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n",
420 __FUNCTION__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
421#endif
422
423 memcntl = aty_ld_le32(MEM_CNTL, par);
424 trp = (memcntl & 0x300) >> 8;
425
426 pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
427 pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
428
429 if (M64_HAS(FIFO_32)) {
430 pll->ct.fifo_size = 32;
431 } else {
432 pll->ct.fifo_size = 24;
433 pll->ct.xclkpagefaultdelay += 2;
434 pll->ct.xclkmaxrasdelay += 3;
435 }
436
437 switch (par->ram_type) {
438 case DRAM:
439 if (info->fix.smem_len<=ONE_MB) {
440 pll->ct.dsp_loop_latency = 10;
441 } else {
442 pll->ct.dsp_loop_latency = 8;
443 pll->ct.xclkpagefaultdelay += 2;
444 }
445 break;
446 case EDO:
447 case PSEUDO_EDO:
448 if (info->fix.smem_len<=ONE_MB) {
449 pll->ct.dsp_loop_latency = 9;
450 } else {
451 pll->ct.dsp_loop_latency = 8;
452 pll->ct.xclkpagefaultdelay += 1;
453 }
454 break;
455 case SDRAM:
456 if (info->fix.smem_len<=ONE_MB) {
457 pll->ct.dsp_loop_latency = 11;
458 } else {
459 pll->ct.dsp_loop_latency = 10;
460 pll->ct.xclkpagefaultdelay += 1;
461 }
462 break;
463 case SGRAM:
464 pll->ct.dsp_loop_latency = 8;
465 pll->ct.xclkpagefaultdelay += 3;
466 break;
467 default:
468 pll->ct.dsp_loop_latency = 11;
469 pll->ct.xclkpagefaultdelay += 3;
470 break;
471 }
472
473 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
474 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
475
476 /* Allow BIOS to override */
477 dsp_config = aty_ld_le32(DSP_CONFIG, par);
478 dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
479 vga_dsp_config = aty_ld_le32(VGA_DSP_CONFIG, par);
480 vga_dsp_on_off = aty_ld_le32(VGA_DSP_ON_OFF, par);
481
482 if (dsp_config)
483 pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
484#if 0
485 FIXME: is it relevant for us?
486 if ((!dsp_on_off && !M64_HAS(RESET_3D)) ||
487 ((dsp_on_off == vga_dsp_on_off) &&
488 (!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW)))) {
489 vga_dsp_on_off &= VGA_DSP_OFF;
490 vga_dsp_config &= VGA_DSP_XCLKS_PER_QW;
491 if (ATIDivide(vga_dsp_on_off, vga_dsp_config, 5, 1) > 24)
492 pll->ct.fifo_size = 32;
493 else
494 pll->ct.fifo_size = 24;
495 }
496#endif
497 /* Exit if the user does not want us to tamper with the clock
498 rates of her chip. */
499 if (par->mclk_per == 0) {
500 u8 mclk_fb_div, pll_ext_cntl;
501 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
502 pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
503 pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07];
504 mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
505 if (pll_ext_cntl & PLL_MFB_TIMES_4_2B)
506 mclk_fb_div <<= 1;
507 pll->ct.mclk_fb_div = mclk_fb_div;
508 return 0;
509 }
510
511 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
512
513 /* FIXME: use the VTB/GTB /3 post divider if it's better suited */
514 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
515 (pll->ct.mclk_fb_mult * par->xclk_per);
516
517 if (q < 16*8 || q > 255*8) {
518 printk(KERN_CRIT "atxfb: xclk out of range\n");
519 return -EINVAL;
520 } else {
521 xpost_div = (q < 128*8);
522 xpost_div += (q < 64*8);
523 xpost_div += (q < 32*8);
524 }
525 pll->ct.xclk_post_div_real = postdividers[xpost_div];
526 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
527
528#ifdef DEBUG
529 pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
530 (par->ref_clk_per * pll->ct.pll_ref_div);
531 printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n",
532 __FUNCTION__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
533#endif
534
535 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
536 pll->ct.pll_gen_cntl = OSC_EN;
537 else
538 pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
539
540 if (M64_HAS(MAGIC_POSTDIV))
541 pll->ct.pll_ext_cntl = 0;
542 else
543 pll->ct.pll_ext_cntl = xpost_div;
544
545 if (pll->ct.mclk_fb_mult == 4)
546 pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
547
548 if (par->mclk_per == par->xclk_per) {
549 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
550 } else {
551 /*
552 * The chip clock is not equal to the memory clock.
553 * Therefore we will use sclk to clock the chip.
554 */
555 pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
556
557 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
558 if (q < 16*8 || q > 255*8) {
559 printk(KERN_CRIT "atyfb: mclk out of range\n");
560 return -EINVAL;
561 } else {
562 mpost_div = (q < 128*8);
563 mpost_div += (q < 64*8);
564 mpost_div += (q < 32*8);
565 }
566 sclk_post_div_real = postdividers[mpost_div];
567 sclk_fb_div = q * sclk_post_div_real / 8;
568 spll_cntl2 = mpost_div << 4;
569#ifdef DEBUG
570 pllsclk = (1000000 * 2 * sclk_fb_div) /
571 (par->ref_clk_per * pll->ct.pll_ref_div);
572 printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n",
573 __FUNCTION__, pllsclk, pllsclk / sclk_post_div_real);
574#endif
575 /*
576 * This disables the sclk, crashes the computer as reported:
577 * aty_st_pll_ct(SPLL_CNTL2, 3, info);
578 *
579 * So it seems the sclk must be enabled before it is used;
580 * so PLL_GEN_CNTL must be programmed *after* the sclk.
581 */
582 aty_st_pll_ct(SCLK_FB_DIV, sclk_fb_div, par);
583 aty_st_pll_ct(SPLL_CNTL2, spll_cntl2, par);
584 /*
585 * The sclk has been started. However, I believe the first clock
586 * ticks it generates are not very stable. Hope this primitive loop
587 * helps for Rage Mobilities that sometimes crash when
588 * we switch to sclk. (Daniel Mantione, 13-05-2003)
589 */
590 for (i=0;i<=0x1ffff;i++);
591 }
592
593 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
594 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
595 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
596 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
597 /* Disable the extra precision pixel clock controls since we do not use them. */
598 aty_st_pll_ct(EXT_VPLL_CNTL, aty_ld_pll_ct(EXT_VPLL_CNTL, par) &
599 ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC), par);
600
601 return 0;
602}
603
604static int dummy(void)
605{
606 return 0;
607}
608
609const struct aty_dac_ops aty_dac_ct = {
610 .set_dac = (void *) dummy,
611};
612
613const struct aty_pll_ops aty_pll_ct = {
614 .var_to_pll = aty_var_to_pll_ct,
615 .pll_to_var = aty_pll_to_var_ct,
616 .set_pll = aty_set_pll_ct,
617 .get_pll = aty_get_pll_ct,
618 .init_pll = aty_init_pll_ct
619};
diff --git a/drivers/video/aty/mach64_cursor.c b/drivers/video/aty/mach64_cursor.c
new file mode 100644
index 000000000000..ad8b7496f853
--- /dev/null
+++ b/drivers/video/aty/mach64_cursor.c
@@ -0,0 +1,226 @@
1/*
2 * ATI Mach64 CT/VT/GT/LT Cursor Support
3 */
4
5#include <linux/slab.h>
6#include <linux/fb.h>
7#include <linux/init.h>
8#include <linux/string.h>
9
10#include <asm/io.h>
11#include <asm/uaccess.h>
12
13#ifdef __sparc__
14#include <asm/pbm.h>
15#include <asm/fbio.h>
16#endif
17
18#include <video/mach64.h>
19#include "atyfb.h"
20
21/*
22 * The hardware cursor definition requires 2 bits per pixel. The
23 * Cursor size reguardless of the visible cursor size is 64 pixels
24 * by 64 lines. The total memory required to define the cursor is
25 * 16 bytes / line for 64 lines or 1024 bytes of data. The data
26 * must be in a contigiuos format. The 2 bit cursor code values are
27 * as follows:
28 *
29 * 00 - pixel colour = CURSOR_CLR_0
30 * 01 - pixel colour = CURSOR_CLR_1
31 * 10 - pixel colour = transparent (current display pixel)
32 * 11 - pixel colour = 1's complement of current display pixel
33 *
34 * Cursor Offset 64 pixels Actual Displayed Area
35 * \_________________________/
36 * | | | |
37 * |<--------------->| | |
38 * | CURS_HORZ_OFFSET| | |
39 * | |_______| | 64 Lines
40 * | ^ | |
41 * | | | |
42 * | CURS_VERT_OFFSET| |
43 * | | | |
44 * |____________________|____| |
45 *
46 *
47 * The Screen position of the top left corner of the displayed
48 * cursor is specificed by CURS_HORZ_VERT_POSN. Care must be taken
49 * when the cursor hot spot is not the top left corner and the
50 * physical cursor position becomes negative. It will be be displayed
51 * if either the horizontal or vertical cursor position is negative
52 *
53 * If x becomes negative the cursor manager must adjust the CURS_HORZ_OFFSET
54 * to a larger number and saturate CUR_HORZ_POSN to zero.
55 *
56 * if Y becomes negative, CUR_VERT_OFFSET must be adjusted to a larger number,
57 * CUR_OFFSET must be adjusted to a point to the appropraite line in the cursor
58 * definitation and CUR_VERT_POSN must be saturated to zero.
59 */
60
61 /*
62 * Hardware Cursor support.
63 */
64static const u8 cursor_bits_lookup[16] = {
65 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
66 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
67};
68
69static const u8 cursor_mask_lookup[16] = {
70 0xaa, 0x2a, 0x8a, 0x0a, 0xa2, 0x22, 0x82, 0x02,
71 0xa8, 0x28, 0x88, 0x08, 0xa0, 0x20, 0x80, 0x00
72};
73
74static int atyfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
75{
76 struct atyfb_par *par = (struct atyfb_par *) info->par;
77 u16 xoff, yoff;
78 int x, y, h;
79
80#ifdef __sparc__
81 if (par->mmaped)
82 return -EPERM;
83#endif
84 if (par->asleep)
85 return -EPERM;
86
87 /* Hide cursor */
88 wait_for_fifo(1, par);
89 aty_st_le32(GEN_TEST_CNTL, aty_ld_le32(GEN_TEST_CNTL, par) & ~HWCURSOR_ENABLE, par);
90
91 /* set position */
92 if (cursor->set & FB_CUR_SETPOS) {
93 x = cursor->image.dx - cursor->hot.x - info->var.xoffset;
94 if (x < 0) {
95 xoff = -x;
96 x = 0;
97 } else {
98 xoff = 0;
99 }
100
101 y = cursor->image.dy - cursor->hot.y - info->var.yoffset;
102 if (y < 0) {
103 yoff = -y;
104 y = 0;
105 } else {
106 yoff = 0;
107 }
108
109 h = cursor->image.height;
110
111 /*
112 * In doublescan mode, the cursor location
113 * and heigh also needs to be doubled.
114 */
115 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN) {
116 y<<=1;
117 h<<=1;
118 }
119 wait_for_fifo(4, par);
120 aty_st_le32(CUR_OFFSET, (info->fix.smem_len >> 3) + (yoff << 1), par);
121 aty_st_le32(CUR_HORZ_VERT_OFF,
122 ((u32) (64 - h + yoff) << 16) | xoff, par);
123 aty_st_le32(CUR_HORZ_VERT_POSN, ((u32) y << 16) | x, par);
124 }
125
126 /* Set color map */
127 if (cursor->set & FB_CUR_SETCMAP) {
128 u32 fg_idx, bg_idx, fg, bg;
129
130 fg_idx = cursor->image.fg_color;
131 bg_idx = cursor->image.bg_color;
132
133 fg = (info->cmap.red[fg_idx] << 24) |
134 (info->cmap.green[fg_idx] << 16) |
135 (info->cmap.blue[fg_idx] << 8) | 15;
136
137 bg = (info->cmap.red[bg_idx] << 24) |
138 (info->cmap.green[bg_idx] << 16) |
139 (info->cmap.blue[bg_idx] << 8);
140
141 wait_for_fifo(2, par);
142 aty_st_le32(CUR_CLR0, bg, par);
143 aty_st_le32(CUR_CLR1, fg, par);
144 }
145
146 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
147 u8 *src = (u8 *)cursor->image.data;
148 u8 *msk = (u8 *)cursor->mask;
149 u8 __iomem *dst = (u8 __iomem *)info->sprite.addr;
150 unsigned int width = (cursor->image.width + 7) >> 3;
151 unsigned int height = cursor->image.height;
152 unsigned int align = info->sprite.scan_align;
153
154 unsigned int i, j, offset;
155 u8 m, b;
156
157 // Clear cursor image with 1010101010...
158 fb_memset(dst, 0xaa, 1024);
159
160 offset = align - width*2;
161
162 for (i = 0; i < height; i++) {
163 for (j = 0; j < width; j++) {
164 b = *src++;
165 m = *msk++;
166 switch (cursor->rop) {
167 case ROP_XOR:
168 // Upper 4 bits of mask data
169 fb_writeb(cursor_mask_lookup[m >> 4 ] |
170 cursor_bits_lookup[(b ^ m) >> 4], dst++);
171 // Lower 4 bits of mask
172 fb_writeb(cursor_mask_lookup[m & 0x0f ] |
173 cursor_bits_lookup[(b ^ m) & 0x0f], dst++);
174 break;
175 case ROP_COPY:
176 // Upper 4 bits of mask data
177 fb_writeb(cursor_mask_lookup[m >> 4 ] |
178 cursor_bits_lookup[(b & m) >> 4], dst++);
179 // Lower 4 bits of mask
180 fb_writeb(cursor_mask_lookup[m & 0x0f ] |
181 cursor_bits_lookup[(b & m) & 0x0f], dst++);
182 break;
183 }
184 }
185 dst += offset;
186 }
187 }
188
189 if (cursor->enable) {
190 wait_for_fifo(1, par);
191 aty_st_le32(GEN_TEST_CNTL, aty_ld_le32(GEN_TEST_CNTL, par)
192 | HWCURSOR_ENABLE, par);
193 }
194 return 0;
195}
196
197int __init aty_init_cursor(struct fb_info *info)
198{
199 unsigned long addr;
200
201 info->fix.smem_len -= PAGE_SIZE;
202
203#ifdef __sparc__
204 addr = (unsigned long) info->screen_base - 0x800000 + info->fix.smem_len;
205 info->sprite.addr = (u8 *) addr;
206#else
207#ifdef __BIG_ENDIAN
208 addr = info->fix.smem_start - 0x800000 + info->fix.smem_len;
209 info->sprite.addr = (u8 *) ioremap(addr, 1024);
210#else
211 addr = (unsigned long) info->screen_base + info->fix.smem_len;
212 info->sprite.addr = (u8 *) addr;
213#endif
214#endif
215 if (!info->sprite.addr)
216 return -ENXIO;
217 info->sprite.size = PAGE_SIZE;
218 info->sprite.scan_align = 16; /* Scratch pad 64 bytes wide */
219 info->sprite.buf_align = 16; /* and 64 lines tall. */
220 info->sprite.flags = FB_PIXMAP_IO;
221
222 info->fbops->fb_cursor = atyfb_cursor;
223
224 return 0;
225}
226
diff --git a/drivers/video/aty/mach64_gx.c b/drivers/video/aty/mach64_gx.c
new file mode 100644
index 000000000000..01fdff79483b
--- /dev/null
+++ b/drivers/video/aty/mach64_gx.c
@@ -0,0 +1,912 @@
1
2/*
3 * ATI Mach64 GX Support
4 */
5
6#include <linux/delay.h>
7#include <linux/fb.h>
8#include <linux/sched.h>
9
10#include <asm/io.h>
11
12#include <video/mach64.h>
13#include "atyfb.h"
14
15/* Definitions for the ICS 2595 == ATI 18818_1 Clockchip */
16
17#define REF_FREQ_2595 1432 /* 14.33 MHz (exact 14.31818) */
18#define REF_DIV_2595 46 /* really 43 on ICS 2595 !!! */
19 /* ohne Prescaler */
20#define MAX_FREQ_2595 15938 /* 159.38 MHz (really 170.486) */
21#define MIN_FREQ_2595 8000 /* 80.00 MHz ( 85.565) */
22 /* mit Prescaler 2, 4, 8 */
23#define ABS_MIN_FREQ_2595 1000 /* 10.00 MHz (really 10.697) */
24#define N_ADJ_2595 257
25
26#define STOP_BITS_2595 0x1800
27
28
29#define MIN_N_408 2
30
31#define MIN_N_1703 6
32
33#define MIN_M 2
34#define MAX_M 30
35#define MIN_N 35
36#define MAX_N 255-8
37
38
39 /*
40 * Support Functions
41 */
42
43static void aty_dac_waste4(const struct atyfb_par *par)
44{
45 (void) aty_ld_8(DAC_REGS, par);
46
47 (void) aty_ld_8(DAC_REGS + 2, par);
48 (void) aty_ld_8(DAC_REGS + 2, par);
49 (void) aty_ld_8(DAC_REGS + 2, par);
50 (void) aty_ld_8(DAC_REGS + 2, par);
51}
52
53static void aty_StrobeClock(const struct atyfb_par *par)
54{
55 u8 tmp;
56
57 udelay(26);
58
59 tmp = aty_ld_8(CLOCK_CNTL, par);
60 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par);
61 return;
62}
63
64
65 /*
66 * IBM RGB514 DAC and Clock Chip
67 */
68
69static void aty_st_514(int offset, u8 val, const struct atyfb_par *par)
70{
71 aty_st_8(DAC_CNTL, 1, par);
72 /* right addr byte */
73 aty_st_8(DAC_W_INDEX, offset & 0xff, par);
74 /* left addr byte */
75 aty_st_8(DAC_DATA, (offset >> 8) & 0xff, par);
76 aty_st_8(DAC_MASK, val, par);
77 aty_st_8(DAC_CNTL, 0, par);
78}
79
80static int aty_set_dac_514(const struct fb_info *info,
81 const union aty_pll *pll, u32 bpp, u32 accel)
82{
83 struct atyfb_par *par = (struct atyfb_par *) info->par;
84 static struct {
85 u8 pixel_dly;
86 u8 misc2_cntl;
87 u8 pixel_rep;
88 u8 pixel_cntl_index;
89 u8 pixel_cntl_v1;
90 } tab[3] = {
91 {
92 0, 0x41, 0x03, 0x71, 0x45}, /* 8 bpp */
93 {
94 0, 0x45, 0x04, 0x0c, 0x01}, /* 555 */
95 {
96 0, 0x45, 0x06, 0x0e, 0x00}, /* XRGB */
97 };
98 int i;
99
100 switch (bpp) {
101 case 8:
102 default:
103 i = 0;
104 break;
105 case 16:
106 i = 1;
107 break;
108 case 32:
109 i = 2;
110 break;
111 }
112 aty_st_514(0x90, 0x00, par); /* VRAM Mask Low */
113 aty_st_514(0x04, tab[i].pixel_dly, par); /* Horizontal Sync Control */
114 aty_st_514(0x05, 0x00, par); /* Power Management */
115 aty_st_514(0x02, 0x01, par); /* Misc Clock Control */
116 aty_st_514(0x71, tab[i].misc2_cntl, par); /* Misc Control 2 */
117 aty_st_514(0x0a, tab[i].pixel_rep, par); /* Pixel Format */
118 aty_st_514(tab[i].pixel_cntl_index, tab[i].pixel_cntl_v1, par);
119 /* Misc Control 2 / 16 BPP Control / 32 BPP Control */
120 return 0;
121}
122
123static int aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per,
124 u32 bpp, union aty_pll *pll)
125{
126 /*
127 * FIXME: use real calculations instead of using fixed values from the old
128 * driver
129 */
130 static struct {
131 u32 limit; /* pixlock rounding limit (arbitrary) */
132 u8 m; /* (df<<6) | vco_div_count */
133 u8 n; /* ref_div_count */
134 } RGB514_clocks[7] = {
135 {
136 8000, (3 << 6) | 20, 9}, /* 7395 ps / 135.2273 MHz */
137 {
138 10000, (1 << 6) | 19, 3}, /* 9977 ps / 100.2273 MHz */
139 {
140 13000, (1 << 6) | 2, 3}, /* 12509 ps / 79.9432 MHz */
141 {
142 14000, (2 << 6) | 8, 7}, /* 13394 ps / 74.6591 MHz */
143 {
144 16000, (1 << 6) | 44, 6}, /* 15378 ps / 65.0284 MHz */
145 {
146 25000, (1 << 6) | 15, 5}, /* 17460 ps / 57.2727 MHz */
147 {
148 50000, (0 << 6) | 53, 7}, /* 33145 ps / 30.1705 MHz */
149 };
150 int i;
151
152 for (i = 0; i < sizeof(RGB514_clocks) / sizeof(*RGB514_clocks);
153 i++)
154 if (vclk_per <= RGB514_clocks[i].limit) {
155 pll->ibm514.m = RGB514_clocks[i].m;
156 pll->ibm514.n = RGB514_clocks[i].n;
157 return 0;
158 }
159 return -EINVAL;
160}
161
162static u32 aty_pll_514_to_var(const struct fb_info *info,
163 const union aty_pll *pll)
164{
165 struct atyfb_par *par = (struct atyfb_par *) info->par;
166 u8 df, vco_div_count, ref_div_count;
167
168 df = pll->ibm514.m >> 6;
169 vco_div_count = pll->ibm514.m & 0x3f;
170 ref_div_count = pll->ibm514.n;
171
172 return ((par->ref_clk_per * ref_div_count) << (3 - df))/
173 (vco_div_count + 65);
174}
175
176static void aty_set_pll_514(const struct fb_info *info,
177 const union aty_pll *pll)
178{
179 struct atyfb_par *par = (struct atyfb_par *) info->par;
180
181 aty_st_514(0x06, 0x02, par); /* DAC Operation */
182 aty_st_514(0x10, 0x01, par); /* PLL Control 1 */
183 aty_st_514(0x70, 0x01, par); /* Misc Control 1 */
184 aty_st_514(0x8f, 0x1f, par); /* PLL Ref. Divider Input */
185 aty_st_514(0x03, 0x00, par); /* Sync Control */
186 aty_st_514(0x05, 0x00, par); /* Power Management */
187 aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */
188 aty_st_514(0x21, pll->ibm514.n, par); /* F1 / N0 */
189}
190
191const struct aty_dac_ops aty_dac_ibm514 = {
192 .set_dac = aty_set_dac_514,
193};
194
195const struct aty_pll_ops aty_pll_ibm514 = {
196 .var_to_pll = aty_var_to_pll_514,
197 .pll_to_var = aty_pll_514_to_var,
198 .set_pll = aty_set_pll_514,
199};
200
201
202 /*
203 * ATI 68860-B DAC
204 */
205
206static int aty_set_dac_ATI68860_B(const struct fb_info *info,
207 const union aty_pll *pll, u32 bpp,
208 u32 accel)
209{
210 struct atyfb_par *par = (struct atyfb_par *) info->par;
211 u32 gModeReg, devSetupRegA, temp, mask;
212
213 gModeReg = 0;
214 devSetupRegA = 0;
215
216 switch (bpp) {
217 case 8:
218 gModeReg = 0x83;
219 devSetupRegA =
220 0x60 | 0x00 /*(info->mach64DAC8Bit ? 0x00 : 0x01) */ ;
221 break;
222 case 15:
223 gModeReg = 0xA0;
224 devSetupRegA = 0x60;
225 break;
226 case 16:
227 gModeReg = 0xA1;
228 devSetupRegA = 0x60;
229 break;
230 case 24:
231 gModeReg = 0xC0;
232 devSetupRegA = 0x60;
233 break;
234 case 32:
235 gModeReg = 0xE3;
236 devSetupRegA = 0x60;
237 break;
238 }
239
240 if (!accel) {
241 gModeReg = 0x80;
242 devSetupRegA = 0x61;
243 }
244
245 temp = aty_ld_8(DAC_CNTL, par);
246 aty_st_8(DAC_CNTL, (temp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3,
247 par);
248
249 aty_st_8(DAC_REGS + 2, 0x1D, par);
250 aty_st_8(DAC_REGS + 3, gModeReg, par);
251 aty_st_8(DAC_REGS, 0x02, par);
252
253 temp = aty_ld_8(DAC_CNTL, par);
254 aty_st_8(DAC_CNTL, temp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par);
255
256 if (info->fix.smem_len < ONE_MB)
257 mask = 0x04;
258 else if (info->fix.smem_len == ONE_MB)
259 mask = 0x08;
260 else
261 mask = 0x0C;
262
263 /* The following assumes that the BIOS has correctly set R7 of the
264 * Device Setup Register A at boot time.
265 */
266#define A860_DELAY_L 0x80
267
268 temp = aty_ld_8(DAC_REGS, par);
269 aty_st_8(DAC_REGS, (devSetupRegA | mask) | (temp & A860_DELAY_L),
270 par);
271 temp = aty_ld_8(DAC_CNTL, par);
272 aty_st_8(DAC_CNTL, (temp & ~(DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3)),
273 par);
274
275 aty_st_le32(BUS_CNTL, 0x890e20f1, par);
276 aty_st_le32(DAC_CNTL, 0x47052100, par);
277 return 0;
278}
279
280const struct aty_dac_ops aty_dac_ati68860b = {
281 .set_dac = aty_set_dac_ATI68860_B,
282};
283
284
285 /*
286 * AT&T 21C498 DAC
287 */
288
289static int aty_set_dac_ATT21C498(const struct fb_info *info,
290 const union aty_pll *pll, u32 bpp,
291 u32 accel)
292{
293 struct atyfb_par *par = (struct atyfb_par *) info->par;
294 u32 dotClock;
295 int muxmode = 0;
296 int DACMask = 0;
297
298 dotClock = 100000000 / pll->ics2595.period_in_ps;
299
300 switch (bpp) {
301 case 8:
302 if (dotClock > 8000) {
303 DACMask = 0x24;
304 muxmode = 1;
305 } else
306 DACMask = 0x04;
307 break;
308 case 15:
309 DACMask = 0x16;
310 break;
311 case 16:
312 DACMask = 0x36;
313 break;
314 case 24:
315 DACMask = 0xE6;
316 break;
317 case 32:
318 DACMask = 0xE6;
319 break;
320 }
321
322 if (1 /* info->mach64DAC8Bit */ )
323 DACMask |= 0x02;
324
325 aty_dac_waste4(par);
326 aty_st_8(DAC_REGS + 2, DACMask, par);
327
328 aty_st_le32(BUS_CNTL, 0x890e20f1, par);
329 aty_st_le32(DAC_CNTL, 0x00072000, par);
330 return muxmode;
331}
332
333const struct aty_dac_ops aty_dac_att21c498 = {
334 .set_dac = aty_set_dac_ATT21C498,
335};
336
337
338 /*
339 * ATI 18818 / ICS 2595 Clock Chip
340 */
341
342static int aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per,
343 u32 bpp, union aty_pll *pll)
344{
345 u32 MHz100; /* in 0.01 MHz */
346 u32 program_bits;
347 u32 post_divider;
348
349 /* Calculate the programming word */
350 MHz100 = 100000000 / vclk_per;
351
352 program_bits = -1;
353 post_divider = 1;
354
355 if (MHz100 > MAX_FREQ_2595) {
356 MHz100 = MAX_FREQ_2595;
357 return -EINVAL;
358 } else if (MHz100 < ABS_MIN_FREQ_2595) {
359 program_bits = 0; /* MHz100 = 257 */
360 return -EINVAL;
361 } else {
362 while (MHz100 < MIN_FREQ_2595) {
363 MHz100 *= 2;
364 post_divider *= 2;
365 }
366 }
367 MHz100 *= 1000;
368 MHz100 = (REF_DIV_2595 * MHz100) / REF_FREQ_2595;
369
370 MHz100 += 500; /* + 0.5 round */
371 MHz100 /= 1000;
372
373 if (program_bits == -1) {
374 program_bits = MHz100 - N_ADJ_2595;
375 switch (post_divider) {
376 case 1:
377 program_bits |= 0x0600;
378 break;
379 case 2:
380 program_bits |= 0x0400;
381 break;
382 case 4:
383 program_bits |= 0x0200;
384 break;
385 case 8:
386 default:
387 break;
388 }
389 }
390
391 program_bits |= STOP_BITS_2595;
392
393 pll->ics2595.program_bits = program_bits;
394 pll->ics2595.locationAddr = 0;
395 pll->ics2595.post_divider = post_divider;
396 pll->ics2595.period_in_ps = vclk_per;
397
398 return 0;
399}
400
401static u32 aty_pll_18818_to_var(const struct fb_info *info,
402 const union aty_pll *pll)
403{
404 return (pll->ics2595.period_in_ps); /* default for now */
405}
406
407static void aty_ICS2595_put1bit(u8 data, const struct atyfb_par *par)
408{
409 u8 tmp;
410
411 data &= 0x01;
412 tmp = aty_ld_8(CLOCK_CNTL, par);
413 aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
414 (tmp & ~0x04) | (data << 2), par);
415
416 tmp = aty_ld_8(CLOCK_CNTL, par);
417 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (0 << 3),
418 par);
419
420 aty_StrobeClock(par);
421
422 tmp = aty_ld_8(CLOCK_CNTL, par);
423 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (1 << 3),
424 par);
425
426 aty_StrobeClock(par);
427 return;
428}
429
430static void aty_set_pll18818(const struct fb_info *info,
431 const union aty_pll *pll)
432{
433 struct atyfb_par *par = (struct atyfb_par *) info->par;
434 u32 program_bits;
435 u32 locationAddr;
436
437 u32 i;
438
439 u8 old_clock_cntl;
440 u8 old_crtc_ext_disp;
441
442 old_clock_cntl = aty_ld_8(CLOCK_CNTL, par);
443 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par);
444
445 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
446 aty_st_8(CRTC_GEN_CNTL + 3,
447 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
448
449 mdelay(15); /* delay for 50 (15) ms */
450
451 program_bits = pll->ics2595.program_bits;
452 locationAddr = pll->ics2595.locationAddr;
453
454 /* Program the clock chip */
455 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par); /* Strobe = 0 */
456 aty_StrobeClock(par);
457 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 1, par); /* Strobe = 0 */
458 aty_StrobeClock(par);
459
460 aty_ICS2595_put1bit(1, par); /* Send start bits */
461 aty_ICS2595_put1bit(0, par); /* Start bit */
462 aty_ICS2595_put1bit(0, par); /* Read / ~Write */
463
464 for (i = 0; i < 5; i++) { /* Location 0..4 */
465 aty_ICS2595_put1bit(locationAddr & 1, par);
466 locationAddr >>= 1;
467 }
468
469 for (i = 0; i < 8 + 1 + 2 + 2; i++) {
470 aty_ICS2595_put1bit(program_bits & 1, par);
471 program_bits >>= 1;
472 }
473
474 mdelay(1); /* delay for 1 ms */
475
476 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
477 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
478 aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
479 old_clock_cntl | CLOCK_STROBE, par);
480
481 mdelay(50); /* delay for 50 (15) ms */
482 aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
483 ((pll->ics2595.locationAddr & 0x0F) | CLOCK_STROBE), par);
484 return;
485}
486
487const struct aty_pll_ops aty_pll_ati18818_1 = {
488 .var_to_pll = aty_var_to_pll_18818,
489 .pll_to_var = aty_pll_18818_to_var,
490 .set_pll = aty_set_pll18818,
491};
492
493
494 /*
495 * STG 1703 Clock Chip
496 */
497
498static int aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per,
499 u32 bpp, union aty_pll *pll)
500{
501 u32 mhz100; /* in 0.01 MHz */
502 u32 program_bits;
503 /* u32 post_divider; */
504 u32 mach64MinFreq, mach64MaxFreq, mach64RefFreq;
505 u32 temp, tempB;
506 u16 remainder, preRemainder;
507 short divider = 0, tempA;
508
509 /* Calculate the programming word */
510 mhz100 = 100000000 / vclk_per;
511 mach64MinFreq = MIN_FREQ_2595;
512 mach64MaxFreq = MAX_FREQ_2595;
513 mach64RefFreq = REF_FREQ_2595; /* 14.32 MHz */
514
515 /* Calculate program word */
516 if (mhz100 == 0)
517 program_bits = 0xE0;
518 else {
519 if (mhz100 < mach64MinFreq)
520 mhz100 = mach64MinFreq;
521 if (mhz100 > mach64MaxFreq)
522 mhz100 = mach64MaxFreq;
523
524 divider = 0;
525 while (mhz100 < (mach64MinFreq << 3)) {
526 mhz100 <<= 1;
527 divider += 0x20;
528 }
529
530 temp = (unsigned int) (mhz100);
531 temp = (unsigned int) (temp * (MIN_N_1703 + 2));
532 temp -= (short) (mach64RefFreq << 1);
533
534 tempA = MIN_N_1703;
535 preRemainder = 0xffff;
536
537 do {
538 tempB = temp;
539 remainder = tempB % mach64RefFreq;
540 tempB = tempB / mach64RefFreq;
541
542 if ((tempB & 0xffff) <= 127
543 && (remainder <= preRemainder)) {
544 preRemainder = remainder;
545 divider &= ~0x1f;
546 divider |= tempA;
547 divider =
548 (divider & 0x00ff) +
549 ((tempB & 0xff) << 8);
550 }
551
552 temp += mhz100;
553 tempA++;
554 } while (tempA <= (MIN_N_1703 << 1));
555
556 program_bits = divider;
557 }
558
559 pll->ics2595.program_bits = program_bits;
560 pll->ics2595.locationAddr = 0;
561 pll->ics2595.post_divider = divider; /* fuer nix */
562 pll->ics2595.period_in_ps = vclk_per;
563
564 return 0;
565}
566
567static u32 aty_pll_1703_to_var(const struct fb_info *info,
568 const union aty_pll *pll)
569{
570 return (pll->ics2595.period_in_ps); /* default for now */
571}
572
573static void aty_set_pll_1703(const struct fb_info *info,
574 const union aty_pll *pll)
575{
576 struct atyfb_par *par = (struct atyfb_par *) info->par;
577 u32 program_bits;
578 u32 locationAddr;
579
580 char old_crtc_ext_disp;
581
582 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
583 aty_st_8(CRTC_GEN_CNTL + 3,
584 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
585
586 program_bits = pll->ics2595.program_bits;
587 locationAddr = pll->ics2595.locationAddr;
588
589 /* Program clock */
590 aty_dac_waste4(par);
591
592 (void) aty_ld_8(DAC_REGS + 2, par);
593 aty_st_8(DAC_REGS + 2, (locationAddr << 1) + 0x20, par);
594 aty_st_8(DAC_REGS + 2, 0, par);
595 aty_st_8(DAC_REGS + 2, (program_bits & 0xFF00) >> 8, par);
596 aty_st_8(DAC_REGS + 2, (program_bits & 0xFF), par);
597
598 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
599 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
600 return;
601}
602
603const struct aty_pll_ops aty_pll_stg1703 = {
604 .var_to_pll = aty_var_to_pll_1703,
605 .pll_to_var = aty_pll_1703_to_var,
606 .set_pll = aty_set_pll_1703,
607};
608
609
610 /*
611 * Chrontel 8398 Clock Chip
612 */
613
614static int aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per,
615 u32 bpp, union aty_pll *pll)
616{
617 u32 tempA, tempB, fOut, longMHz100, diff, preDiff;
618
619 u32 mhz100; /* in 0.01 MHz */
620 u32 program_bits;
621 /* u32 post_divider; */
622 u32 mach64MinFreq, mach64MaxFreq, mach64RefFreq;
623 u16 m, n, k = 0, save_m, save_n, twoToKth;
624
625 /* Calculate the programming word */
626 mhz100 = 100000000 / vclk_per;
627 mach64MinFreq = MIN_FREQ_2595;
628 mach64MaxFreq = MAX_FREQ_2595;
629 mach64RefFreq = REF_FREQ_2595; /* 14.32 MHz */
630
631 save_m = 0;
632 save_n = 0;
633
634 /* Calculate program word */
635 if (mhz100 == 0)
636 program_bits = 0xE0;
637 else {
638 if (mhz100 < mach64MinFreq)
639 mhz100 = mach64MinFreq;
640 if (mhz100 > mach64MaxFreq)
641 mhz100 = mach64MaxFreq;
642
643 longMHz100 = mhz100 * 256 / 100; /* 8 bit scale this */
644
645 while (mhz100 < (mach64MinFreq << 3)) {
646 mhz100 <<= 1;
647 k++;
648 }
649
650 twoToKth = 1 << k;
651 diff = 0;
652 preDiff = 0xFFFFFFFF;
653
654 for (m = MIN_M; m <= MAX_M; m++) {
655 for (n = MIN_N; n <= MAX_N; n++) {
656 tempA = 938356; /* 14.31818 * 65536 */
657 tempA *= (n + 8); /* 43..256 */
658 tempB = twoToKth * 256;
659 tempB *= (m + 2); /* 4..32 */
660 fOut = tempA / tempB; /* 8 bit scale */
661
662 if (longMHz100 > fOut)
663 diff = longMHz100 - fOut;
664 else
665 diff = fOut - longMHz100;
666
667 if (diff < preDiff) {
668 save_m = m;
669 save_n = n;
670 preDiff = diff;
671 }
672 }
673 }
674
675 program_bits = (k << 6) + (save_m) + (save_n << 8);
676 }
677
678 pll->ics2595.program_bits = program_bits;
679 pll->ics2595.locationAddr = 0;
680 pll->ics2595.post_divider = 0;
681 pll->ics2595.period_in_ps = vclk_per;
682
683 return 0;
684}
685
686static u32 aty_pll_8398_to_var(const struct fb_info *info,
687 const union aty_pll *pll)
688{
689 return (pll->ics2595.period_in_ps); /* default for now */
690}
691
692static void aty_set_pll_8398(const struct fb_info *info,
693 const union aty_pll *pll)
694{
695 struct atyfb_par *par = (struct atyfb_par *) info->par;
696 u32 program_bits;
697 u32 locationAddr;
698
699 char old_crtc_ext_disp;
700 char tmp;
701
702 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
703 aty_st_8(CRTC_GEN_CNTL + 3,
704 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
705
706 program_bits = pll->ics2595.program_bits;
707 locationAddr = pll->ics2595.locationAddr;
708
709 /* Program clock */
710 tmp = aty_ld_8(DAC_CNTL, par);
711 aty_st_8(DAC_CNTL, tmp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par);
712
713 aty_st_8(DAC_REGS, locationAddr, par);
714 aty_st_8(DAC_REGS + 1, (program_bits & 0xff00) >> 8, par);
715 aty_st_8(DAC_REGS + 1, (program_bits & 0xff), par);
716
717 tmp = aty_ld_8(DAC_CNTL, par);
718 aty_st_8(DAC_CNTL, (tmp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3,
719 par);
720
721 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
722 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
723
724 return;
725}
726
727const struct aty_pll_ops aty_pll_ch8398 = {
728 .var_to_pll = aty_var_to_pll_8398,
729 .pll_to_var = aty_pll_8398_to_var,
730 .set_pll = aty_set_pll_8398,
731};
732
733
734 /*
735 * AT&T 20C408 Clock Chip
736 */
737
738static int aty_var_to_pll_408(const struct fb_info *info, u32 vclk_per,
739 u32 bpp, union aty_pll *pll)
740{
741 u32 mhz100; /* in 0.01 MHz */
742 u32 program_bits;
743 /* u32 post_divider; */
744 u32 mach64MinFreq, mach64MaxFreq, mach64RefFreq;
745 u32 temp, tempB;
746 u16 remainder, preRemainder;
747 short divider = 0, tempA;
748
749 /* Calculate the programming word */
750 mhz100 = 100000000 / vclk_per;
751 mach64MinFreq = MIN_FREQ_2595;
752 mach64MaxFreq = MAX_FREQ_2595;
753 mach64RefFreq = REF_FREQ_2595; /* 14.32 MHz */
754
755 /* Calculate program word */
756 if (mhz100 == 0)
757 program_bits = 0xFF;
758 else {
759 if (mhz100 < mach64MinFreq)
760 mhz100 = mach64MinFreq;
761 if (mhz100 > mach64MaxFreq)
762 mhz100 = mach64MaxFreq;
763
764 while (mhz100 < (mach64MinFreq << 3)) {
765 mhz100 <<= 1;
766 divider += 0x40;
767 }
768
769 temp = (unsigned int) mhz100;
770 temp = (unsigned int) (temp * (MIN_N_408 + 2));
771 temp -= ((short) (mach64RefFreq << 1));
772
773 tempA = MIN_N_408;
774 preRemainder = 0xFFFF;
775
776 do {
777 tempB = temp;
778 remainder = tempB % mach64RefFreq;
779 tempB = tempB / mach64RefFreq;
780 if (((tempB & 0xFFFF) <= 255)
781 && (remainder <= preRemainder)) {
782 preRemainder = remainder;
783 divider &= ~0x3f;
784 divider |= tempA;
785 divider =
786 (divider & 0x00FF) +
787 ((tempB & 0xFF) << 8);
788 }
789 temp += mhz100;
790 tempA++;
791 } while (tempA <= 32);
792
793 program_bits = divider;
794 }
795
796 pll->ics2595.program_bits = program_bits;
797 pll->ics2595.locationAddr = 0;
798 pll->ics2595.post_divider = divider; /* fuer nix */
799 pll->ics2595.period_in_ps = vclk_per;
800
801 return 0;
802}
803
804static u32 aty_pll_408_to_var(const struct fb_info *info,
805 const union aty_pll *pll)
806{
807 return (pll->ics2595.period_in_ps); /* default for now */
808}
809
810static void aty_set_pll_408(const struct fb_info *info,
811 const union aty_pll *pll)
812{
813 struct atyfb_par *par = (struct atyfb_par *) info->par;
814 u32 program_bits;
815 u32 locationAddr;
816
817 u8 tmpA, tmpB, tmpC;
818 char old_crtc_ext_disp;
819
820 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
821 aty_st_8(CRTC_GEN_CNTL + 3,
822 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
823
824 program_bits = pll->ics2595.program_bits;
825 locationAddr = pll->ics2595.locationAddr;
826
827 /* Program clock */
828 aty_dac_waste4(par);
829 tmpB = aty_ld_8(DAC_REGS + 2, par) | 1;
830 aty_dac_waste4(par);
831 aty_st_8(DAC_REGS + 2, tmpB, par);
832
833 tmpA = tmpB;
834 tmpC = tmpA;
835 tmpA |= 8;
836 tmpB = 1;
837
838 aty_st_8(DAC_REGS, tmpB, par);
839 aty_st_8(DAC_REGS + 2, tmpA, par);
840
841 udelay(400); /* delay for 400 us */
842
843 locationAddr = (locationAddr << 2) + 0x40;
844 tmpB = locationAddr;
845 tmpA = program_bits >> 8;
846
847 aty_st_8(DAC_REGS, tmpB, par);
848 aty_st_8(DAC_REGS + 2, tmpA, par);
849
850 tmpB = locationAddr + 1;
851 tmpA = (u8) program_bits;
852
853 aty_st_8(DAC_REGS, tmpB, par);
854 aty_st_8(DAC_REGS + 2, tmpA, par);
855
856 tmpB = locationAddr + 2;
857 tmpA = 0x77;
858
859 aty_st_8(DAC_REGS, tmpB, par);
860 aty_st_8(DAC_REGS + 2, tmpA, par);
861
862 udelay(400); /* delay for 400 us */
863 tmpA = tmpC & (~(1 | 8));
864 tmpB = 1;
865
866 aty_st_8(DAC_REGS, tmpB, par);
867 aty_st_8(DAC_REGS + 2, tmpA, par);
868
869 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
870 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
871 return;
872}
873
874const struct aty_pll_ops aty_pll_att20c408 = {
875 .var_to_pll = aty_var_to_pll_408,
876 .pll_to_var = aty_pll_408_to_var,
877 .set_pll = aty_set_pll_408,
878};
879
880
881 /*
882 * Unsupported DAC and Clock Chip
883 */
884
885static int aty_set_dac_unsupported(const struct fb_info *info,
886 const union aty_pll *pll, u32 bpp,
887 u32 accel)
888{
889 struct atyfb_par *par = (struct atyfb_par *) info->par;
890
891 aty_st_le32(BUS_CNTL, 0x890e20f1, par);
892 aty_st_le32(DAC_CNTL, 0x47052100, par);
893 /* new in 2.2.3p1 from Geert. ???????? */
894 aty_st_le32(BUS_CNTL, 0x590e10ff, par);
895 aty_st_le32(DAC_CNTL, 0x47012100, par);
896 return 0;
897}
898
899static int dummy(void)
900{
901 return 0;
902}
903
904const struct aty_dac_ops aty_dac_unsupported = {
905 .set_dac = aty_set_dac_unsupported,
906};
907
908const struct aty_pll_ops aty_pll_unsupported = {
909 .var_to_pll = (void *) dummy,
910 .pll_to_var = (void *) dummy,
911 .set_pll = (void *) dummy,
912};
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
new file mode 100644
index 000000000000..3ca27cb13caa
--- /dev/null
+++ b/drivers/video/aty/radeon_accel.c
@@ -0,0 +1,316 @@
1#include "radeonfb.h"
2
3/* the accelerated functions here are patterned after the
4 * "ACCEL_MMIO" ifdef branches in XFree86
5 * --dte
6 */
7
8static void radeon_fixup_offset(struct radeonfb_info *rinfo)
9{
10 u32 local_base;
11
12 /* *** Ugly workaround *** */
13 /*
14 * On some platforms, the video memory is mapped at 0 in radeon chip space
15 * (like PPCs) by the firmware. X will always move it up so that it's seen
16 * by the chip to be at the same address as the PCI BAR.
17 * That means that when switching back from X, there is a mismatch between
18 * the offsets programmed into the engine. This means that potentially,
19 * accel operations done before radeonfb has a chance to re-init the engine
20 * will have incorrect offsets, and potentially trash system memory !
21 *
22 * The correct fix is for fbcon to never call any accel op before the engine
23 * has properly been re-initialized (by a call to set_var), but this is a
24 * complex fix. This workaround in the meantime, called before every accel
25 * operation, makes sure the offsets are in sync.
26 */
27
28 radeon_fifo_wait (1);
29 local_base = INREG(MC_FB_LOCATION) << 16;
30 if (local_base == rinfo->fb_local_base)
31 return;
32
33 rinfo->fb_local_base = local_base;
34
35 radeon_fifo_wait (3);
36 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
37 (rinfo->fb_local_base >> 10));
38 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
39 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
40}
41
42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
43 const struct fb_fillrect *region)
44{
45 radeon_fifo_wait(4);
46
47 OUTREG(DP_GUI_MASTER_CNTL,
48 rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */
49 | GMC_BRUSH_SOLID_COLOR
50 | ROP3_P);
51 if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
52 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
53 else
54 OUTREG(DP_BRUSH_FRGD_CLR, region->color);
55 OUTREG(DP_WRITE_MSK, 0xffffffff);
56 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
57
58 radeon_fifo_wait(2);
59 OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
60 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
61}
62
63void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
64{
65 struct radeonfb_info *rinfo = info->par;
66 struct fb_fillrect modded;
67 int vxres, vyres;
68
69 if (info->state != FBINFO_STATE_RUNNING)
70 return;
71 if (info->flags & FBINFO_HWACCEL_DISABLED) {
72 cfb_fillrect(info, region);
73 return;
74 }
75
76 radeon_fixup_offset(rinfo);
77
78 vxres = info->var.xres_virtual;
79 vyres = info->var.yres_virtual;
80
81 memcpy(&modded, region, sizeof(struct fb_fillrect));
82
83 if(!modded.width || !modded.height ||
84 modded.dx >= vxres || modded.dy >= vyres)
85 return;
86
87 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
88 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
89
90 radeonfb_prim_fillrect(rinfo, &modded);
91}
92
93static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
94 const struct fb_copyarea *area)
95{
96 int xdir, ydir;
97 u32 sx, sy, dx, dy, w, h;
98
99 w = area->width; h = area->height;
100 dx = area->dx; dy = area->dy;
101 sx = area->sx; sy = area->sy;
102 xdir = sx - dx;
103 ydir = sy - dy;
104
105 if ( xdir < 0 ) { sx += w-1; dx += w-1; }
106 if ( ydir < 0 ) { sy += h-1; dy += h-1; }
107
108 radeon_fifo_wait(3);
109 OUTREG(DP_GUI_MASTER_CNTL,
110 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
111 | GMC_BRUSH_NONE
112 | GMC_SRC_DSTCOLOR
113 | ROP3_S
114 | DP_SRC_SOURCE_MEMORY );
115 OUTREG(DP_WRITE_MSK, 0xffffffff);
116 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
117 | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
118
119 radeon_fifo_wait(3);
120 OUTREG(SRC_Y_X, (sy << 16) | sx);
121 OUTREG(DST_Y_X, (dy << 16) | dx);
122 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
123}
124
125
126void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
127{
128 struct radeonfb_info *rinfo = info->par;
129 struct fb_copyarea modded;
130 u32 vxres, vyres;
131 modded.sx = area->sx;
132 modded.sy = area->sy;
133 modded.dx = area->dx;
134 modded.dy = area->dy;
135 modded.width = area->width;
136 modded.height = area->height;
137
138 if (info->state != FBINFO_STATE_RUNNING)
139 return;
140 if (info->flags & FBINFO_HWACCEL_DISABLED) {
141 cfb_copyarea(info, area);
142 return;
143 }
144
145 radeon_fixup_offset(rinfo);
146
147 vxres = info->var.xres_virtual;
148 vyres = info->var.yres_virtual;
149
150 if(!modded.width || !modded.height ||
151 modded.sx >= vxres || modded.sy >= vyres ||
152 modded.dx >= vxres || modded.dy >= vyres)
153 return;
154
155 if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx;
156 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
157 if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
158 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
159
160 radeonfb_prim_copyarea(rinfo, &modded);
161}
162
163void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
164{
165 struct radeonfb_info *rinfo = info->par;
166
167 if (info->state != FBINFO_STATE_RUNNING)
168 return;
169 radeon_engine_idle();
170
171 cfb_imageblit(info, image);
172}
173
174int radeonfb_sync(struct fb_info *info)
175{
176 struct radeonfb_info *rinfo = info->par;
177
178 if (info->state != FBINFO_STATE_RUNNING)
179 return 0;
180 radeon_engine_idle();
181
182 return 0;
183}
184
185void radeonfb_engine_reset(struct radeonfb_info *rinfo)
186{
187 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
188 u32 host_path_cntl;
189
190 radeon_engine_flush (rinfo);
191
192 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
193 mclk_cntl = INPLL(MCLK_CNTL);
194
195 OUTPLL(MCLK_CNTL, (mclk_cntl |
196 FORCEON_MCLKA |
197 FORCEON_MCLKB |
198 FORCEON_YCLKA |
199 FORCEON_YCLKB |
200 FORCEON_MC |
201 FORCEON_AIC));
202
203 host_path_cntl = INREG(HOST_PATH_CNTL);
204 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
205
206 if (rinfo->family == CHIP_FAMILY_R300 ||
207 rinfo->family == CHIP_FAMILY_R350 ||
208 rinfo->family == CHIP_FAMILY_RV350) {
209 u32 tmp;
210
211 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
212 SOFT_RESET_CP |
213 SOFT_RESET_HI |
214 SOFT_RESET_E2));
215 INREG(RBBM_SOFT_RESET);
216 OUTREG(RBBM_SOFT_RESET, 0);
217 tmp = INREG(RB2D_DSTCACHE_MODE);
218 OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
219 } else {
220 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
221 SOFT_RESET_CP |
222 SOFT_RESET_HI |
223 SOFT_RESET_SE |
224 SOFT_RESET_RE |
225 SOFT_RESET_PP |
226 SOFT_RESET_E2 |
227 SOFT_RESET_RB);
228 INREG(RBBM_SOFT_RESET);
229 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
230 ~(SOFT_RESET_CP |
231 SOFT_RESET_HI |
232 SOFT_RESET_SE |
233 SOFT_RESET_RE |
234 SOFT_RESET_PP |
235 SOFT_RESET_E2 |
236 SOFT_RESET_RB));
237 INREG(RBBM_SOFT_RESET);
238 }
239
240 OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
241 INREG(HOST_PATH_CNTL);
242 OUTREG(HOST_PATH_CNTL, host_path_cntl);
243
244 if (rinfo->family != CHIP_FAMILY_R300 ||
245 rinfo->family != CHIP_FAMILY_R350 ||
246 rinfo->family != CHIP_FAMILY_RV350)
247 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
248
249 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
250 OUTPLL(MCLK_CNTL, mclk_cntl);
251}
252
253void radeonfb_engine_init (struct radeonfb_info *rinfo)
254{
255 unsigned long temp;
256
257 /* disable 3D engine */
258 OUTREG(RB3D_CNTL, 0);
259
260 radeonfb_engine_reset(rinfo);
261
262 radeon_fifo_wait (1);
263 if ((rinfo->family != CHIP_FAMILY_R300) &&
264 (rinfo->family != CHIP_FAMILY_R350) &&
265 (rinfo->family != CHIP_FAMILY_RV350))
266 OUTREG(RB2D_DSTCACHE_MODE, 0);
267
268 radeon_fifo_wait (3);
269 /* We re-read MC_FB_LOCATION from card as it can have been
270 * modified by XFree drivers (ouch !)
271 */
272 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
273
274 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
275 (rinfo->fb_local_base >> 10));
276 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
277 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
278
279 radeon_fifo_wait (1);
280#if defined(__BIG_ENDIAN)
281 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
282#else
283 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
284#endif
285 radeon_fifo_wait (2);
286 OUTREG(DEFAULT_SC_TOP_LEFT, 0);
287 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
288 DEFAULT_SC_BOTTOM_MAX));
289
290 temp = radeon_get_dstbpp(rinfo->depth);
291 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
292
293 radeon_fifo_wait (1);
294 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
295 GMC_BRUSH_SOLID_COLOR |
296 GMC_SRC_DATATYPE_COLOR));
297
298 radeon_fifo_wait (7);
299
300 /* clear line drawing regs */
301 OUTREG(DST_LINE_START, 0);
302 OUTREG(DST_LINE_END, 0);
303
304 /* set brush color regs */
305 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
306 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
307
308 /* set source color regs */
309 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
310 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
311
312 /* default write mask */
313 OUTREG(DP_WRITE_MSK, 0xffffffff);
314
315 radeon_engine_idle ();
316}
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
new file mode 100644
index 000000000000..e8eb124754b1
--- /dev/null
+++ b/drivers/video/aty/radeon_base.c
@@ -0,0 +1,2587 @@
1/*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53#define RADEON_VERSION "0.2.0"
54
55#include <linux/config.h>
56#include <linux/module.h>
57#include <linux/moduleparam.h>
58#include <linux/kernel.h>
59#include <linux/errno.h>
60#include <linux/string.h>
61#include <linux/mm.h>
62#include <linux/tty.h>
63#include <linux/slab.h>
64#include <linux/delay.h>
65#include <linux/time.h>
66#include <linux/fb.h>
67#include <linux/ioport.h>
68#include <linux/init.h>
69#include <linux/pci.h>
70#include <linux/vmalloc.h>
71#include <linux/device.h>
72#include <linux/i2c.h>
73
74#include <asm/io.h>
75#include <asm/uaccess.h>
76
77#ifdef CONFIG_PPC_OF
78
79#include <asm/pci-bridge.h>
80#include "../macmodes.h"
81
82#ifdef CONFIG_PMAC_BACKLIGHT
83#include <asm/backlight.h>
84#endif
85
86#ifdef CONFIG_BOOTX_TEXT
87#include <asm/btext.h>
88#endif
89
90#endif /* CONFIG_PPC_OF */
91
92#ifdef CONFIG_MTRR
93#include <asm/mtrr.h>
94#endif
95
96#include <video/radeon.h>
97#include <linux/radeonfb.h>
98
99#include "../edid.h" // MOVE THAT TO include/video
100#include "ati_ids.h"
101#include "radeonfb.h"
102
103#define MAX_MAPPED_VRAM (2048*2048*4)
104#define MIN_MAPPED_VRAM (1024*768*1)
105
106#define CHIP_DEF(id, family, flags) \
107 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
108
109static struct pci_device_id radeonfb_pci_table[] = {
110 /* Mobility M6 */
111 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
112 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
113 /* Radeon VE/7000 */
114 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
115 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
116 /* Radeon IGP320M (U1) */
117 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
118 /* Radeon IGP320 (A3) */
119 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
120 /* IGP330M/340M/350M (U2) */
121 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122 /* IGP330/340/350 (A4) */
123 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124 /* Mobility 7000 IGP */
125 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
126 /* 7000 IGP (A4+) */
127 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
128 /* 8500 AIW */
129 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
130 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
131 /* 8700/8800 */
132 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
133 /* 8500 */
134 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
135 /* 9100 */
136 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
137 /* Mobility M7 */
138 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 /* 7500 */
141 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
142 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
143 /* Mobility M9 */
144 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
148 /* 9000/Pro */
149 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
150 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
151 /* Mobility 9100 IGP (U3) */
152 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
153 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 /* 9100 IGP (A5) */
155 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
156 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 /* Mobility 9200 (M9+) */
158 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
159 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 /* 9200 */
161 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
162 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
165 /* 9500 */
166 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
168 /* 9600TX / FireGL Z1 */
169 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
171 /* 9700/9500/Pro/FireGL X1 */
172 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
173 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
176 /* Mobility M10/M11 */
177 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 /* 9600/FireGL T2 */
184 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
190 /* 9800/Pro/FileGL X2 */
191 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
199 /* Newer stuff */
200 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
209 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
210 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
217 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
226 /* Original Radeon/7200 */
227 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
229 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
231 { 0, }
232};
233MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
234
235
236typedef struct {
237 u16 reg;
238 u32 val;
239} reg_val;
240
241
242/* these common regs are cleared before mode setting so they do not
243 * interfere with anything
244 */
245static reg_val common_regs[] = {
246 { OVR_CLR, 0 },
247 { OVR_WID_LEFT_RIGHT, 0 },
248 { OVR_WID_TOP_BOTTOM, 0 },
249 { OV0_SCALE_CNTL, 0 },
250 { SUBPIC_CNTL, 0 },
251 { VIPH_CONTROL, 0 },
252 { I2C_CNTL_1, 0 },
253 { GEN_INT_CNTL, 0 },
254 { CAP0_TRIG_CNTL, 0 },
255 { CAP1_TRIG_CNTL, 0 },
256};
257
258/*
259 * globals
260 */
261
262static char *mode_option;
263static char *monitor_layout;
264static int noaccel = 0;
265static int default_dynclk = -2;
266static int nomodeset = 0;
267static int ignore_edid = 0;
268static int mirror = 0;
269static int panel_yres = 0;
270static int force_dfp = 0;
271static int force_measure_pll = 0;
272#ifdef CONFIG_MTRR
273static int nomtrr = 0;
274#endif
275
276/*
277 * prototypes
278 */
279
280
281#ifdef CONFIG_PPC_OF
282
283#ifdef CONFIG_PMAC_BACKLIGHT
284static int radeon_set_backlight_enable(int on, int level, void *data);
285static int radeon_set_backlight_level(int level, void *data);
286static struct backlight_controller radeon_backlight_controller = {
287 radeon_set_backlight_enable,
288 radeon_set_backlight_level
289};
290#endif /* CONFIG_PMAC_BACKLIGHT */
291
292#endif /* CONFIG_PPC_OF */
293
294static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
295{
296 if (!rinfo->bios_seg)
297 return;
298 pci_unmap_rom(dev, rinfo->bios_seg);
299}
300
301static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
302{
303 void __iomem *rom;
304 u16 dptr;
305 u8 rom_type;
306 size_t rom_size;
307
308 /* If this is a primary card, there is a shadow copy of the
309 * ROM somewhere in the first meg. We will just ignore the copy
310 * and use the ROM directly.
311 */
312
313 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
314 unsigned int temp;
315 temp = INREG(MPP_TB_CONFIG);
316 temp &= 0x00ffffffu;
317 temp |= 0x04 << 24;
318 OUTREG(MPP_TB_CONFIG, temp);
319 temp = INREG(MPP_TB_CONFIG);
320
321 rom = pci_map_rom(dev, &rom_size);
322 if (!rom) {
323 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
324 pci_name(rinfo->pdev));
325 return -ENOMEM;
326 }
327
328 rinfo->bios_seg = rom;
329
330 /* Very simple test to make sure it appeared */
331 if (BIOS_IN16(0) != 0xaa55) {
332 printk(KERN_ERR "radeonfb (%s): Invalid ROM signature %x should be"
333 "0xaa55\n", pci_name(rinfo->pdev), BIOS_IN16(0));
334 goto failed;
335 }
336 /* Look for the PCI data to check the ROM type */
337 dptr = BIOS_IN16(0x18);
338
339 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
340 * for now, until I've verified this works everywhere. The goal here is more
341 * to phase out Open Firmware images.
342 *
343 * Currently, we only look at the first PCI data, we could iteratre and deal with
344 * them all, and we should use fb_bios_start relative to start of image and not
345 * relative start of ROM, but so far, I never found a dual-image ATI card
346 *
347 * typedef struct {
348 * u32 signature; + 0x00
349 * u16 vendor; + 0x04
350 * u16 device; + 0x06
351 * u16 reserved_1; + 0x08
352 * u16 dlen; + 0x0a
353 * u8 drevision; + 0x0c
354 * u8 class_hi; + 0x0d
355 * u16 class_lo; + 0x0e
356 * u16 ilen; + 0x10
357 * u16 irevision; + 0x12
358 * u8 type; + 0x14
359 * u8 indicator; + 0x15
360 * u16 reserved_2; + 0x16
361 * } pci_data_t;
362 */
363 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
364 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
365 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
366 goto anyway;
367 }
368 rom_type = BIOS_IN8(dptr + 0x14);
369 switch(rom_type) {
370 case 0:
371 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
372 break;
373 case 1:
374 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
375 goto failed;
376 case 2:
377 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
378 goto failed;
379 default:
380 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
381 goto failed;
382 }
383 anyway:
384 /* Locate the flat panel infos, do some sanity checking !!! */
385 rinfo->fp_bios_start = BIOS_IN16(0x48);
386 return 0;
387
388 failed:
389 rinfo->bios_seg = NULL;
390 radeon_unmap_ROM(rinfo, dev);
391 return -ENXIO;
392}
393
394#ifdef CONFIG_X86
395static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
396{
397 /* I simplified this code as we used to miss the signatures in
398 * a lot of case. It's now closer to XFree, we just don't check
399 * for signatures at all... Something better will have to be done
400 * if we end up having conflicts
401 */
402 u32 segstart;
403 void __iomem *rom_base = NULL;
404
405 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
406 rom_base = ioremap(segstart, 0x10000);
407 if (rom_base == NULL)
408 return -ENOMEM;
409 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
410 break;
411 iounmap(rom_base);
412 rom_base = NULL;
413 }
414 if (rom_base == NULL)
415 return -ENXIO;
416
417 /* Locate the flat panel infos, do some sanity checking !!! */
418 rinfo->bios_seg = rom_base;
419 rinfo->fp_bios_start = BIOS_IN16(0x48);
420
421 return 0;
422}
423#endif
424
425#ifdef CONFIG_PPC_OF
426/*
427 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
428 * tree. Hopefully, ATI OF driver is kind enough to fill these
429 */
430static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
431{
432 struct device_node *dp = rinfo->of_node;
433 u32 *val;
434
435 if (dp == NULL)
436 return -ENODEV;
437 val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
438 if (!val || !*val) {
439 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
440 return -EINVAL;
441 }
442
443 rinfo->pll.ref_clk = (*val) / 10;
444
445 val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
446 if (val && *val)
447 rinfo->pll.sclk = (*val) / 10;
448
449 val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
450 if (val && *val)
451 rinfo->pll.mclk = (*val) / 10;
452
453 return 0;
454}
455#endif /* CONFIG_PPC_OF */
456
457/*
458 * Read PLL infos from chip registers
459 */
460static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
461{
462 unsigned char ppll_div_sel;
463 unsigned Ns, Nm, M;
464 unsigned sclk, mclk, tmp, ref_div;
465 int hTotal, vTotal, num, denom, m, n;
466 unsigned long long hz, vclk;
467 long xtal;
468 struct timeval start_tv, stop_tv;
469 long total_secs, total_usecs;
470 int i;
471
472 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
473 * here, so... --BenH
474 */
475
476 /* Flush PCI buffers ? */
477 tmp = INREG(DEVICE_ID);
478
479 local_irq_disable();
480
481 for(i=0; i<1000000; i++)
482 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
483 break;
484
485 do_gettimeofday(&start_tv);
486
487 for(i=0; i<1000000; i++)
488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
489 break;
490
491 for(i=0; i<1000000; i++)
492 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
493 break;
494
495 do_gettimeofday(&stop_tv);
496
497 local_irq_enable();
498
499 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
500 if (total_secs > 10)
501 return -1;
502 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
503 total_usecs += total_secs * 1000000;
504 if (total_usecs < 0)
505 total_usecs = -total_usecs;
506 hz = 1000000/total_usecs;
507
508 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
509 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
510 vclk = (long long)hTotal * (long long)vTotal * hz;
511
512 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
513 case 0:
514 default:
515 num = 1;
516 denom = 1;
517 break;
518 case 1:
519 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
520 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
521 num = 2*n;
522 denom = 2*m;
523 break;
524 case 2:
525 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
526 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
527 num = 2*n;
528 denom = 2*m;
529 break;
530 }
531
532 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
533 radeon_pll_errata_after_index(rinfo);
534
535 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
536 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
537
538 num *= n;
539 denom *= m;
540
541 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
542 case 1:
543 denom *= 2;
544 break;
545 case 2:
546 denom *= 4;
547 break;
548 case 3:
549 denom *= 8;
550 break;
551 case 4:
552 denom *= 3;
553 break;
554 case 6:
555 denom *= 6;
556 break;
557 case 7:
558 denom *= 12;
559 break;
560 }
561
562 vclk *= denom;
563 do_div(vclk, 1000 * num);
564 xtal = vclk;
565
566 if ((xtal > 26900) && (xtal < 27100))
567 xtal = 2700;
568 else if ((xtal > 14200) && (xtal < 14400))
569 xtal = 1432;
570 else if ((xtal > 29400) && (xtal < 29600))
571 xtal = 2950;
572 else {
573 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
574 return -1;
575 }
576
577 tmp = INPLL(M_SPLL_REF_FB_DIV);
578 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
579
580 Ns = (tmp & 0xff0000) >> 16;
581 Nm = (tmp & 0xff00) >> 8;
582 M = (tmp & 0xff);
583 sclk = round_div((2 * Ns * xtal), (2 * M));
584 mclk = round_div((2 * Nm * xtal), (2 * M));
585
586 /* we're done, hopefully these are sane values */
587 rinfo->pll.ref_clk = xtal;
588 rinfo->pll.ref_div = ref_div;
589 rinfo->pll.sclk = sclk;
590 rinfo->pll.mclk = mclk;
591
592 return 0;
593}
594
595/*
596 * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
597 */
598static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
599{
600 /*
601 * In the case nothing works, these are defaults; they are mostly
602 * incomplete, however. It does provide ppll_max and _min values
603 * even for most other methods, however.
604 */
605 switch (rinfo->chipset) {
606 case PCI_DEVICE_ID_ATI_RADEON_QW:
607 case PCI_DEVICE_ID_ATI_RADEON_QX:
608 rinfo->pll.ppll_max = 35000;
609 rinfo->pll.ppll_min = 12000;
610 rinfo->pll.mclk = 23000;
611 rinfo->pll.sclk = 23000;
612 rinfo->pll.ref_clk = 2700;
613 break;
614 case PCI_DEVICE_ID_ATI_RADEON_QL:
615 case PCI_DEVICE_ID_ATI_RADEON_QN:
616 case PCI_DEVICE_ID_ATI_RADEON_QO:
617 case PCI_DEVICE_ID_ATI_RADEON_Ql:
618 case PCI_DEVICE_ID_ATI_RADEON_BB:
619 rinfo->pll.ppll_max = 35000;
620 rinfo->pll.ppll_min = 12000;
621 rinfo->pll.mclk = 27500;
622 rinfo->pll.sclk = 27500;
623 rinfo->pll.ref_clk = 2700;
624 break;
625 case PCI_DEVICE_ID_ATI_RADEON_Id:
626 case PCI_DEVICE_ID_ATI_RADEON_Ie:
627 case PCI_DEVICE_ID_ATI_RADEON_If:
628 case PCI_DEVICE_ID_ATI_RADEON_Ig:
629 rinfo->pll.ppll_max = 35000;
630 rinfo->pll.ppll_min = 12000;
631 rinfo->pll.mclk = 25000;
632 rinfo->pll.sclk = 25000;
633 rinfo->pll.ref_clk = 2700;
634 break;
635 case PCI_DEVICE_ID_ATI_RADEON_ND:
636 case PCI_DEVICE_ID_ATI_RADEON_NE:
637 case PCI_DEVICE_ID_ATI_RADEON_NF:
638 case PCI_DEVICE_ID_ATI_RADEON_NG:
639 rinfo->pll.ppll_max = 40000;
640 rinfo->pll.ppll_min = 20000;
641 rinfo->pll.mclk = 27000;
642 rinfo->pll.sclk = 27000;
643 rinfo->pll.ref_clk = 2700;
644 break;
645 case PCI_DEVICE_ID_ATI_RADEON_QD:
646 case PCI_DEVICE_ID_ATI_RADEON_QE:
647 case PCI_DEVICE_ID_ATI_RADEON_QF:
648 case PCI_DEVICE_ID_ATI_RADEON_QG:
649 default:
650 rinfo->pll.ppll_max = 35000;
651 rinfo->pll.ppll_min = 12000;
652 rinfo->pll.mclk = 16600;
653 rinfo->pll.sclk = 16600;
654 rinfo->pll.ref_clk = 2700;
655 break;
656 }
657 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
658
659
660#ifdef CONFIG_PPC_OF
661 /*
662 * Retreive PLL infos from Open Firmware first
663 */
664 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
665 printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
666 goto found;
667 }
668#endif /* CONFIG_PPC_OF */
669
670 /*
671 * Check out if we have an X86 which gave us some PLL informations
672 * and if yes, retreive them
673 */
674 if (!force_measure_pll && rinfo->bios_seg) {
675 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
676
677 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
678 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
679 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
680 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
681 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
682 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
683
684 printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
685 goto found;
686 }
687
688 /*
689 * We didn't get PLL parameters from either OF or BIOS, we try to
690 * probe them
691 */
692 if (radeon_probe_pll_params(rinfo) == 0) {
693 printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
694 goto found;
695 }
696
697 /*
698 * Fall back to already-set defaults...
699 */
700 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
701
702found:
703 /*
704 * Some methods fail to retreive SCLK and MCLK values, we apply default
705 * settings in this case (200Mhz). If that really happne often, we could
706 * fetch from registers instead...
707 */
708 if (rinfo->pll.mclk == 0)
709 rinfo->pll.mclk = 20000;
710 if (rinfo->pll.sclk == 0)
711 rinfo->pll.sclk = 20000;
712
713 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
714 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
715 rinfo->pll.ref_div,
716 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
717 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
718 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
719}
720
721static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
722{
723 struct radeonfb_info *rinfo = info->par;
724 struct fb_var_screeninfo v;
725 int nom, den;
726 unsigned int pitch;
727
728 if (radeon_match_mode(rinfo, &v, var))
729 return -EINVAL;
730
731 switch (v.bits_per_pixel) {
732 case 0 ... 8:
733 v.bits_per_pixel = 8;
734 break;
735 case 9 ... 16:
736 v.bits_per_pixel = 16;
737 break;
738 case 17 ... 24:
739#if 0 /* Doesn't seem to work */
740 v.bits_per_pixel = 24;
741 break;
742#endif
743 return -EINVAL;
744 case 25 ... 32:
745 v.bits_per_pixel = 32;
746 break;
747 default:
748 return -EINVAL;
749 }
750
751 switch (var_to_depth(&v)) {
752 case 8:
753 nom = den = 1;
754 v.red.offset = v.green.offset = v.blue.offset = 0;
755 v.red.length = v.green.length = v.blue.length = 8;
756 v.transp.offset = v.transp.length = 0;
757 break;
758 case 15:
759 nom = 2;
760 den = 1;
761 v.red.offset = 10;
762 v.green.offset = 5;
763 v.blue.offset = 0;
764 v.red.length = v.green.length = v.blue.length = 5;
765 v.transp.offset = v.transp.length = 0;
766 break;
767 case 16:
768 nom = 2;
769 den = 1;
770 v.red.offset = 11;
771 v.green.offset = 5;
772 v.blue.offset = 0;
773 v.red.length = 5;
774 v.green.length = 6;
775 v.blue.length = 5;
776 v.transp.offset = v.transp.length = 0;
777 break;
778 case 24:
779 nom = 4;
780 den = 1;
781 v.red.offset = 16;
782 v.green.offset = 8;
783 v.blue.offset = 0;
784 v.red.length = v.blue.length = v.green.length = 8;
785 v.transp.offset = v.transp.length = 0;
786 break;
787 case 32:
788 nom = 4;
789 den = 1;
790 v.red.offset = 16;
791 v.green.offset = 8;
792 v.blue.offset = 0;
793 v.red.length = v.blue.length = v.green.length = 8;
794 v.transp.offset = 24;
795 v.transp.length = 8;
796 break;
797 default:
798 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
799 var->xres, var->yres, var->bits_per_pixel);
800 return -EINVAL;
801 }
802
803 if (v.yres_virtual < v.yres)
804 v.yres_virtual = v.yres;
805 if (v.xres_virtual < v.xres)
806 v.xres_virtual = v.xres;
807
808
809 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
810 * with some panels, though I don't quite like this solution
811 */
812 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
813 v.xres_virtual = v.xres_virtual & ~7ul;
814 } else {
815 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
816 & ~(0x3f)) >> 6;
817 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
818 }
819
820 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
821 return -EINVAL;
822
823 if (v.xres_virtual < v.xres)
824 v.xres = v.xres_virtual;
825
826 if (v.xoffset < 0)
827 v.xoffset = 0;
828 if (v.yoffset < 0)
829 v.yoffset = 0;
830
831 if (v.xoffset > v.xres_virtual - v.xres)
832 v.xoffset = v.xres_virtual - v.xres - 1;
833
834 if (v.yoffset > v.yres_virtual - v.yres)
835 v.yoffset = v.yres_virtual - v.yres - 1;
836
837 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
838 v.transp.offset = v.transp.length =
839 v.transp.msb_right = 0;
840
841 memcpy(var, &v, sizeof(v));
842
843 return 0;
844}
845
846
847static int radeonfb_pan_display (struct fb_var_screeninfo *var,
848 struct fb_info *info)
849{
850 struct radeonfb_info *rinfo = info->par;
851
852 if ((var->xoffset + var->xres > var->xres_virtual)
853 || (var->yoffset + var->yres > var->yres_virtual))
854 return -EINVAL;
855
856 if (rinfo->asleep)
857 return 0;
858
859 radeon_fifo_wait(2);
860 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
861 * var->bits_per_pixel / 8) & ~7);
862 return 0;
863}
864
865
866static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
867 unsigned long arg, struct fb_info *info)
868{
869 struct radeonfb_info *rinfo = info->par;
870 unsigned int tmp;
871 u32 value = 0;
872 int rc;
873
874 switch (cmd) {
875 /*
876 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
877 * and do something better using 2nd CRTC instead of just hackish
878 * routing to second output
879 */
880 case FBIO_RADEON_SET_MIRROR:
881 if (!rinfo->is_mobility)
882 return -EINVAL;
883
884 rc = get_user(value, (__u32 __user *)arg);
885
886 if (rc)
887 return rc;
888
889 radeon_fifo_wait(2);
890 if (value & 0x01) {
891 tmp = INREG(LVDS_GEN_CNTL);
892
893 tmp |= (LVDS_ON | LVDS_BLON);
894 } else {
895 tmp = INREG(LVDS_GEN_CNTL);
896
897 tmp &= ~(LVDS_ON | LVDS_BLON);
898 }
899
900 OUTREG(LVDS_GEN_CNTL, tmp);
901
902 if (value & 0x02) {
903 tmp = INREG(CRTC_EXT_CNTL);
904 tmp |= CRTC_CRT_ON;
905
906 mirror = 1;
907 } else {
908 tmp = INREG(CRTC_EXT_CNTL);
909 tmp &= ~CRTC_CRT_ON;
910
911 mirror = 0;
912 }
913
914 OUTREG(CRTC_EXT_CNTL, tmp);
915
916 return 0;
917 case FBIO_RADEON_GET_MIRROR:
918 if (!rinfo->is_mobility)
919 return -EINVAL;
920
921 tmp = INREG(LVDS_GEN_CNTL);
922 if ((LVDS_ON | LVDS_BLON) & tmp)
923 value |= 0x01;
924
925 tmp = INREG(CRTC_EXT_CNTL);
926 if (CRTC_CRT_ON & tmp)
927 value |= 0x02;
928
929 return put_user(value, (__u32 __user *)arg);
930 default:
931 return -EINVAL;
932 }
933
934 return -EINVAL;
935}
936
937
938int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
939{
940 u32 val;
941 u32 tmp_pix_clks;
942 int unblank = 0;
943
944 if (rinfo->lock_blank)
945 return 0;
946
947 radeon_engine_idle();
948
949 val = INREG(CRTC_EXT_CNTL);
950 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
951 CRTC_VSYNC_DIS);
952 switch (blank) {
953 case FB_BLANK_VSYNC_SUSPEND:
954 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
955 break;
956 case FB_BLANK_HSYNC_SUSPEND:
957 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
958 break;
959 case FB_BLANK_POWERDOWN:
960 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
961 CRTC_HSYNC_DIS);
962 break;
963 case FB_BLANK_NORMAL:
964 val |= CRTC_DISPLAY_DIS;
965 break;
966 case FB_BLANK_UNBLANK:
967 default:
968 unblank = 1;
969 }
970 OUTREG(CRTC_EXT_CNTL, val);
971
972
973 switch (rinfo->mon1_type) {
974 case MT_DFP:
975 if (unblank)
976 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
977 ~(FP_FPON | FP_TMDS_EN));
978 else {
979 if (mode_switch || blank == FB_BLANK_NORMAL)
980 break;
981 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
982 }
983 break;
984 case MT_LCD:
985 del_timer_sync(&rinfo->lvds_timer);
986 val = INREG(LVDS_GEN_CNTL);
987 if (unblank) {
988 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
989 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
990 & (LVDS_DIGON | LVDS_BL_MOD_EN));
991 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
992 OUTREG(LVDS_GEN_CNTL, target_val);
993 else if ((val ^ target_val) != 0) {
994 OUTREG(LVDS_GEN_CNTL, target_val
995 & ~(LVDS_ON | LVDS_BL_MOD_EN));
996 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
997 rinfo->init_state.lvds_gen_cntl |=
998 target_val & LVDS_STATE_MASK;
999 if (mode_switch) {
1000 radeon_msleep(rinfo->panel_info.pwr_delay);
1001 OUTREG(LVDS_GEN_CNTL, target_val);
1002 }
1003 else {
1004 rinfo->pending_lvds_gen_cntl = target_val;
1005 mod_timer(&rinfo->lvds_timer,
1006 jiffies +
1007 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1008 }
1009 }
1010 } else {
1011 val |= LVDS_DISPLAY_DIS;
1012 OUTREG(LVDS_GEN_CNTL, val);
1013
1014 /* We don't do a full switch-off on a simple mode switch */
1015 if (mode_switch || blank == FB_BLANK_NORMAL)
1016 break;
1017
1018 /* Asic bug, when turning off LVDS_ON, we have to make sure
1019 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1020 */
1021 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1022 if (rinfo->is_mobility || rinfo->is_IGP)
1023 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1024 val &= ~(LVDS_BL_MOD_EN);
1025 OUTREG(LVDS_GEN_CNTL, val);
1026 udelay(100);
1027 val &= ~(LVDS_ON | LVDS_EN);
1028 OUTREG(LVDS_GEN_CNTL, val);
1029 val &= ~LVDS_DIGON;
1030 rinfo->pending_lvds_gen_cntl = val;
1031 mod_timer(&rinfo->lvds_timer,
1032 jiffies +
1033 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1034 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1035 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1036 if (rinfo->is_mobility || rinfo->is_IGP)
1037 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1038 }
1039 break;
1040 case MT_CRT:
1041 // todo: powerdown DAC
1042 default:
1043 break;
1044 }
1045
1046 /* let fbcon do a soft blank for us */
1047 return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
1048}
1049
1050static int radeonfb_blank (int blank, struct fb_info *info)
1051{
1052 struct radeonfb_info *rinfo = info->par;
1053
1054 if (rinfo->asleep)
1055 return 0;
1056
1057 return radeon_screen_blank(rinfo, blank, 0);
1058}
1059
1060static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1061 unsigned blue, unsigned transp, struct fb_info *info)
1062{
1063 struct radeonfb_info *rinfo = info->par;
1064 u32 pindex;
1065 unsigned int i;
1066
1067 if (regno > 255)
1068 return 1;
1069
1070 red >>= 8;
1071 green >>= 8;
1072 blue >>= 8;
1073 rinfo->palette[regno].red = red;
1074 rinfo->palette[regno].green = green;
1075 rinfo->palette[regno].blue = blue;
1076
1077 /* default */
1078 pindex = regno;
1079
1080 if (!rinfo->asleep) {
1081 u32 dac_cntl2, vclk_cntl = 0;
1082
1083 radeon_fifo_wait(9);
1084 if (rinfo->is_mobility) {
1085 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1086 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1087 }
1088
1089 /* Make sure we are on first palette */
1090 if (rinfo->has_CRTC2) {
1091 dac_cntl2 = INREG(DAC_CNTL2);
1092 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1093 OUTREG(DAC_CNTL2, dac_cntl2);
1094 }
1095
1096 if (rinfo->bpp == 16) {
1097 pindex = regno * 8;
1098
1099 if (rinfo->depth == 16 && regno > 63)
1100 return 1;
1101 if (rinfo->depth == 15 && regno > 31)
1102 return 1;
1103
1104 /* For 565, the green component is mixed one order below */
1105 if (rinfo->depth == 16) {
1106 OUTREG(PALETTE_INDEX, pindex>>1);
1107 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1108 (green << 8) | (rinfo->palette[regno>>1].blue));
1109 green = rinfo->palette[regno<<1].green;
1110 }
1111 }
1112
1113 if (rinfo->depth != 16 || regno < 32) {
1114 OUTREG(PALETTE_INDEX, pindex);
1115 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1116 }
1117 if (rinfo->is_mobility)
1118 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1119 }
1120 if (regno < 16) {
1121 u32 *pal = info->pseudo_palette;
1122 switch (rinfo->depth) {
1123 case 15:
1124 pal[regno] = (regno << 10) | (regno << 5) | regno;
1125 break;
1126 case 16:
1127 pal[regno] = (regno << 11) | (regno << 5) | regno;
1128 break;
1129 case 24:
1130 pal[regno] = (regno << 16) | (regno << 8) | regno;
1131 break;
1132 case 32:
1133 i = (regno << 8) | regno;
1134 pal[regno] = (i << 16) | i;
1135 break;
1136 }
1137 }
1138 return 0;
1139}
1140
1141
1142static void radeon_save_state (struct radeonfb_info *rinfo,
1143 struct radeon_regs *save)
1144{
1145 /* CRTC regs */
1146 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1147 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1148 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1149 save->dac_cntl = INREG(DAC_CNTL);
1150 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1151 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1152 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1153 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1154 save->crtc_pitch = INREG(CRTC_PITCH);
1155 save->surface_cntl = INREG(SURFACE_CNTL);
1156
1157 /* FP regs */
1158 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1159 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1160 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1161 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1162 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1163 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1164 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1165 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1166 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1167 save->tmds_crc = INREG(TMDS_CRC);
1168 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1169 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1170
1171 /* PLL regs */
1172 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1173 radeon_pll_errata_after_index(rinfo);
1174 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1175 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1176}
1177
1178
1179static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1180{
1181 int i;
1182
1183 radeon_fifo_wait(20);
1184
1185 /* Workaround from XFree */
1186 if (rinfo->is_mobility) {
1187 /* A temporal workaround for the occational blanking on certain laptop
1188 * panels. This appears to related to the PLL divider registers
1189 * (fail to lock?). It occurs even when all dividers are the same
1190 * with their old settings. In this case we really don't need to
1191 * fiddle with PLL registers. By doing this we can avoid the blanking
1192 * problem with some panels.
1193 */
1194 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1195 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1196 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1197 /* We still have to force a switch to selected PPLL div thanks to
1198 * an XFree86 driver bug which will switch it away in some cases
1199 * even when using UseFDev */
1200 OUTREGP(CLOCK_CNTL_INDEX,
1201 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1202 ~PPLL_DIV_SEL_MASK);
1203 radeon_pll_errata_after_index(rinfo);
1204 radeon_pll_errata_after_data(rinfo);
1205 return;
1206 }
1207 }
1208
1209 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1210 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1211
1212 /* Reset PPLL & enable atomic update */
1213 OUTPLLP(PPLL_CNTL,
1214 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1215 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1216
1217 /* Switch to selected PPLL divider */
1218 OUTREGP(CLOCK_CNTL_INDEX,
1219 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1220 ~PPLL_DIV_SEL_MASK);
1221 radeon_pll_errata_after_index(rinfo);
1222 radeon_pll_errata_after_data(rinfo);
1223
1224 /* Set PPLL ref. div */
1225 if (rinfo->family == CHIP_FAMILY_R300 ||
1226 rinfo->family == CHIP_FAMILY_RS300 ||
1227 rinfo->family == CHIP_FAMILY_R350 ||
1228 rinfo->family == CHIP_FAMILY_RV350) {
1229 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1230 /* When restoring console mode, use saved PPLL_REF_DIV
1231 * setting.
1232 */
1233 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1234 } else {
1235 /* R300 uses ref_div_acc field as real ref divider */
1236 OUTPLLP(PPLL_REF_DIV,
1237 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1238 ~R300_PPLL_REF_DIV_ACC_MASK);
1239 }
1240 } else
1241 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1242
1243 /* Set PPLL divider 3 & post divider*/
1244 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1245 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1246
1247 /* Write update */
1248 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1249 ;
1250 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1251
1252 /* Wait read update complete */
1253 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1254 the cause yet, but this workaround will mask the problem for now.
1255 Other chips usually will pass at the very first test, so the
1256 workaround shouldn't have any effect on them. */
1257 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1258 ;
1259
1260 OUTPLL(HTOTAL_CNTL, 0);
1261
1262 /* Clear reset & atomic update */
1263 OUTPLLP(PPLL_CNTL, 0,
1264 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1265
1266 /* We may want some locking ... oh well */
1267 radeon_msleep(5);
1268
1269 /* Switch back VCLK source to PPLL */
1270 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1271}
1272
1273/*
1274 * Timer function for delayed LVDS panel power up/down
1275 */
1276static void radeon_lvds_timer_func(unsigned long data)
1277{
1278 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1279
1280 radeon_engine_idle();
1281
1282 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1283}
1284
1285/*
1286 * Apply a video mode. This will apply the whole register set, including
1287 * the PLL registers, to the card
1288 */
1289void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1290 int regs_only)
1291{
1292 int i;
1293 int primary_mon = PRIMARY_MONITOR(rinfo);
1294
1295 if (nomodeset)
1296 return;
1297
1298 if (!regs_only)
1299 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1300
1301 radeon_fifo_wait(31);
1302 for (i=0; i<10; i++)
1303 OUTREG(common_regs[i].reg, common_regs[i].val);
1304
1305 /* Apply surface registers */
1306 for (i=0; i<8; i++) {
1307 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1308 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1309 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1310 }
1311
1312 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1313 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1314 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1315 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1316 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1317 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1318 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1319 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1320 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1321 OUTREG(CRTC_OFFSET, 0);
1322 OUTREG(CRTC_OFFSET_CNTL, 0);
1323 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1324 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1325
1326 radeon_write_pll_regs(rinfo, mode);
1327
1328 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1329 radeon_fifo_wait(10);
1330 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1331 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1332 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1333 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1334 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1335 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1336 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1337 OUTREG(TMDS_CRC, mode->tmds_crc);
1338 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1339 }
1340
1341 if (!regs_only)
1342 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1343
1344 radeon_fifo_wait(2);
1345 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1346
1347 return;
1348}
1349
1350/*
1351 * Calculate the PLL values for a given mode
1352 */
1353static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1354 unsigned long freq)
1355{
1356 const struct {
1357 int divider;
1358 int bitvalue;
1359 } *post_div,
1360 post_divs[] = {
1361 { 1, 0 },
1362 { 2, 1 },
1363 { 4, 2 },
1364 { 8, 3 },
1365 { 3, 4 },
1366 { 16, 5 },
1367 { 6, 6 },
1368 { 12, 7 },
1369 { 0, 0 },
1370 };
1371 int fb_div, pll_output_freq = 0;
1372 int uses_dvo = 0;
1373
1374 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1375 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1376 * recent than an r(v)100...
1377 */
1378#if 1
1379 /* XXX I had reports of flicker happening with the cinema display
1380 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1381 * this case. This could just be a bandwidth calculation issue, I
1382 * haven't implemented the bandwidth code yet, but in the meantime,
1383 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1384 * I haven't seen a case were were absolutely needed an odd PLL
1385 * divider. I'll find a better fix once I have more infos on the
1386 * real cause of the problem.
1387 */
1388 while (rinfo->has_CRTC2) {
1389 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1390 u32 disp_output_cntl;
1391 int source;
1392
1393 /* FP2 path not enabled */
1394 if ((fp2_gen_cntl & FP2_ON) == 0)
1395 break;
1396 /* Not all chip revs have the same format for this register,
1397 * extract the source selection
1398 */
1399 if (rinfo->family == CHIP_FAMILY_R200 ||
1400 rinfo->family == CHIP_FAMILY_R300 ||
1401 rinfo->family == CHIP_FAMILY_R350 ||
1402 rinfo->family == CHIP_FAMILY_RV350) {
1403 source = (fp2_gen_cntl >> 10) & 0x3;
1404 /* sourced from transform unit, check for transform unit
1405 * own source
1406 */
1407 if (source == 3) {
1408 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1409 source = (disp_output_cntl >> 12) & 0x3;
1410 }
1411 } else
1412 source = (fp2_gen_cntl >> 13) & 0x1;
1413 /* sourced from CRTC2 -> exit */
1414 if (source == 1)
1415 break;
1416
1417 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1418 uses_dvo = 1;
1419 break;
1420 }
1421#else
1422 uses_dvo = 1;
1423#endif
1424 if (freq > rinfo->pll.ppll_max)
1425 freq = rinfo->pll.ppll_max;
1426 if (freq*12 < rinfo->pll.ppll_min)
1427 freq = rinfo->pll.ppll_min / 12;
1428 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1429 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1430
1431 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1432 pll_output_freq = post_div->divider * freq;
1433 /* If we output to the DVO port (external TMDS), we don't allow an
1434 * odd PLL divider as those aren't supported on this path
1435 */
1436 if (uses_dvo && (post_div->divider & 1))
1437 continue;
1438 if (pll_output_freq >= rinfo->pll.ppll_min &&
1439 pll_output_freq <= rinfo->pll.ppll_max)
1440 break;
1441 }
1442
1443 /* If we fall through the bottom, try the "default value"
1444 given by the terminal post_div->bitvalue */
1445 if ( !post_div->divider ) {
1446 post_div = &post_divs[post_div->bitvalue];
1447 pll_output_freq = post_div->divider * freq;
1448 }
1449 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1450 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1451 pll_output_freq);
1452
1453 /* If we fall through the bottom, try the "default value"
1454 given by the terminal post_div->bitvalue */
1455 if ( !post_div->divider ) {
1456 post_div = &post_divs[post_div->bitvalue];
1457 pll_output_freq = post_div->divider * freq;
1458 }
1459 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1460 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1461 pll_output_freq);
1462
1463 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1464 rinfo->pll.ref_clk);
1465 regs->ppll_ref_div = rinfo->pll.ref_div;
1466 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1467
1468 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1469 RTRACE("fb_div = 0x%x\n", fb_div);
1470 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1471}
1472
1473static int radeonfb_set_par(struct fb_info *info)
1474{
1475 struct radeonfb_info *rinfo = info->par;
1476 struct fb_var_screeninfo *mode = &info->var;
1477 struct radeon_regs *newmode;
1478 int hTotal, vTotal, hSyncStart, hSyncEnd,
1479 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1480 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1481 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1482 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1483 int i, freq;
1484 int format = 0;
1485 int nopllcalc = 0;
1486 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1487 int primary_mon = PRIMARY_MONITOR(rinfo);
1488 int depth = var_to_depth(mode);
1489 int use_rmx = 0;
1490
1491 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1492 if (!newmode)
1493 return -ENOMEM;
1494
1495 /* We always want engine to be idle on a mode switch, even
1496 * if we won't actually change the mode
1497 */
1498 radeon_engine_idle();
1499
1500 hSyncStart = mode->xres + mode->right_margin;
1501 hSyncEnd = hSyncStart + mode->hsync_len;
1502 hTotal = hSyncEnd + mode->left_margin;
1503
1504 vSyncStart = mode->yres + mode->lower_margin;
1505 vSyncEnd = vSyncStart + mode->vsync_len;
1506 vTotal = vSyncEnd + mode->upper_margin;
1507 pixClock = mode->pixclock;
1508
1509 sync = mode->sync;
1510 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1511 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1512
1513 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1514 if (rinfo->panel_info.xres < mode->xres)
1515 mode->xres = rinfo->panel_info.xres;
1516 if (rinfo->panel_info.yres < mode->yres)
1517 mode->yres = rinfo->panel_info.yres;
1518
1519 hTotal = mode->xres + rinfo->panel_info.hblank;
1520 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1521 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1522
1523 vTotal = mode->yres + rinfo->panel_info.vblank;
1524 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1525 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1526
1527 h_sync_pol = !rinfo->panel_info.hAct_high;
1528 v_sync_pol = !rinfo->panel_info.vAct_high;
1529
1530 pixClock = 100000000 / rinfo->panel_info.clock;
1531
1532 if (rinfo->panel_info.use_bios_dividers) {
1533 nopllcalc = 1;
1534 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1535 (rinfo->panel_info.post_divider << 16);
1536 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1537 }
1538 }
1539 dotClock = 1000000000 / pixClock;
1540 freq = dotClock / 10; /* x100 */
1541
1542 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1543 hSyncStart, hSyncEnd, hTotal);
1544 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1545 vSyncStart, vSyncEnd, vTotal);
1546
1547 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1548 vsync_wid = vSyncEnd - vSyncStart;
1549 if (hsync_wid == 0)
1550 hsync_wid = 1;
1551 else if (hsync_wid > 0x3f) /* max */
1552 hsync_wid = 0x3f;
1553
1554 if (vsync_wid == 0)
1555 vsync_wid = 1;
1556 else if (vsync_wid > 0x1f) /* max */
1557 vsync_wid = 0x1f;
1558
1559 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1560 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1561
1562 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1563
1564 format = radeon_get_dstbpp(depth);
1565 bytpp = mode->bits_per_pixel >> 3;
1566
1567 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1568 hsync_fudge = hsync_fudge_fp[format-1];
1569 else
1570 hsync_fudge = hsync_adj_tab[format-1];
1571
1572 hsync_start = hSyncStart - 8 + hsync_fudge;
1573
1574 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1575 (format << 8);
1576
1577 /* Clear auto-center etc... */
1578 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1579 newmode->crtc_more_cntl &= 0xfffffff0;
1580
1581 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1582 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1583 if (mirror)
1584 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1585
1586 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1587 CRTC_INTERLACE_EN);
1588 } else {
1589 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1590 CRTC_CRT_ON;
1591 }
1592
1593 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1594 DAC_8BIT_EN;
1595
1596 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1597 (((mode->xres / 8) - 1) << 16));
1598
1599 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1600 (hsync_wid << 16) | (h_sync_pol << 23));
1601
1602 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1603 ((mode->yres - 1) << 16);
1604
1605 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1606 (vsync_wid << 16) | (v_sync_pol << 23));
1607
1608 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1609 /* We first calculate the engine pitch */
1610 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1611 & ~(0x3f)) >> 6;
1612
1613 /* Then, re-multiply it to get the CRTC pitch */
1614 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1615 } else
1616 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1617
1618 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1619
1620 /*
1621 * It looks like recent chips have a problem with SURFACE_CNTL,
1622 * setting SURF_TRANSLATION_DIS completely disables the
1623 * swapper as well, so we leave it unset now.
1624 */
1625 newmode->surface_cntl = 0;
1626
1627#if defined(__BIG_ENDIAN)
1628
1629 /* Setup swapping on both apertures, though we currently
1630 * only use aperture 0, enabling swapper on aperture 1
1631 * won't harm
1632 */
1633 switch (mode->bits_per_pixel) {
1634 case 16:
1635 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1636 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1637 break;
1638 case 24:
1639 case 32:
1640 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1641 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1642 break;
1643 }
1644#endif
1645
1646 /* Clear surface registers */
1647 for (i=0; i<8; i++) {
1648 newmode->surf_lower_bound[i] = 0;
1649 newmode->surf_upper_bound[i] = 0x1f;
1650 newmode->surf_info[i] = 0;
1651 }
1652
1653 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1654 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1655 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1656 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1657
1658 rinfo->bpp = mode->bits_per_pixel;
1659 rinfo->depth = depth;
1660
1661 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1662 RTRACE("freq = %lu\n", (unsigned long)freq);
1663
1664 /* We use PPLL_DIV_3 */
1665 newmode->clk_cntl_index = 0x300;
1666
1667 /* Calculate PPLL value if necessary */
1668 if (!nopllcalc)
1669 radeon_calc_pll_regs(rinfo, newmode, freq);
1670
1671 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1672
1673 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1674 unsigned int hRatio, vRatio;
1675
1676 if (mode->xres > rinfo->panel_info.xres)
1677 mode->xres = rinfo->panel_info.xres;
1678 if (mode->yres > rinfo->panel_info.yres)
1679 mode->yres = rinfo->panel_info.yres;
1680
1681 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1682 << HORZ_PANEL_SHIFT);
1683 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1684 << VERT_PANEL_SHIFT);
1685
1686 if (mode->xres != rinfo->panel_info.xres) {
1687 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1688 rinfo->panel_info.xres);
1689 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1690 (newmode->fp_horz_stretch &
1691 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1692 HORZ_AUTO_RATIO_INC)));
1693 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1694 HORZ_STRETCH_ENABLE);
1695 use_rmx = 1;
1696 }
1697 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1698
1699 if (mode->yres != rinfo->panel_info.yres) {
1700 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1701 rinfo->panel_info.yres);
1702 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1703 (newmode->fp_vert_stretch &
1704 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1705 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1706 VERT_STRETCH_ENABLE);
1707 use_rmx = 1;
1708 }
1709 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1710
1711 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1712 ~(FP_SEL_CRTC2 |
1713 FP_RMX_HVSYNC_CONTROL_EN |
1714 FP_DFP_SYNC_SEL |
1715 FP_CRT_SYNC_SEL |
1716 FP_CRTC_LOCK_8DOT |
1717 FP_USE_SHADOW_EN |
1718 FP_CRTC_USE_SHADOW_VEND |
1719 FP_CRT_SYNC_ALT));
1720
1721 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1722 FP_CRTC_DONT_SHADOW_HEND |
1723 FP_PANEL_FORMAT);
1724
1725 if (IS_R300_VARIANT(rinfo) ||
1726 (rinfo->family == CHIP_FAMILY_R200)) {
1727 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1728 if (use_rmx)
1729 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1730 else
1731 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1732 } else
1733 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1734
1735 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1736 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1737 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1738 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1739
1740 if (primary_mon == MT_LCD) {
1741 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1742 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1743 } else {
1744 /* DFP */
1745 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1746 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1747 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1748 if (IS_R300_VARIANT(rinfo) ||
1749 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1750 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1751 else
1752 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1753 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1754 }
1755
1756 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1757 (((mode->xres / 8) - 1) << 16));
1758 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1759 ((mode->yres - 1) << 16);
1760 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1761 (hsync_wid << 16) | (h_sync_pol << 23));
1762 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1763 (vsync_wid << 16) | (v_sync_pol << 23));
1764 }
1765
1766 /* do it! */
1767 if (!rinfo->asleep) {
1768 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1769 radeon_write_mode (rinfo, newmode, 0);
1770 /* (re)initialize the engine */
1771 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1772 radeonfb_engine_init (rinfo);
1773 }
1774 /* Update fix */
1775 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1776 info->fix.line_length = rinfo->pitch*64;
1777 else
1778 info->fix.line_length = mode->xres_virtual
1779 * ((mode->bits_per_pixel + 1) / 8);
1780 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1781 : FB_VISUAL_DIRECTCOLOR;
1782
1783#ifdef CONFIG_BOOTX_TEXT
1784 /* Update debug text engine */
1785 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1786 rinfo->depth, info->fix.line_length);
1787#endif
1788
1789 kfree(newmode);
1790 return 0;
1791}
1792
1793
1794static struct fb_ops radeonfb_ops = {
1795 .owner = THIS_MODULE,
1796 .fb_check_var = radeonfb_check_var,
1797 .fb_set_par = radeonfb_set_par,
1798 .fb_setcolreg = radeonfb_setcolreg,
1799 .fb_pan_display = radeonfb_pan_display,
1800 .fb_blank = radeonfb_blank,
1801 .fb_ioctl = radeonfb_ioctl,
1802 .fb_sync = radeonfb_sync,
1803 .fb_fillrect = radeonfb_fillrect,
1804 .fb_copyarea = radeonfb_copyarea,
1805 .fb_imageblit = radeonfb_imageblit,
1806 .fb_cursor = soft_cursor,
1807};
1808
1809
1810static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1811{
1812 struct fb_info *info = rinfo->info;
1813
1814 info->par = rinfo;
1815 info->pseudo_palette = rinfo->pseudo_palette;
1816 info->flags = FBINFO_DEFAULT
1817 | FBINFO_HWACCEL_COPYAREA
1818 | FBINFO_HWACCEL_FILLRECT
1819 | FBINFO_HWACCEL_XPAN
1820 | FBINFO_HWACCEL_YPAN;
1821 info->fbops = &radeonfb_ops;
1822 info->screen_base = rinfo->fb_base;
1823 info->screen_size = rinfo->mapped_vram;
1824 /* Fill fix common fields */
1825 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1826 info->fix.smem_start = rinfo->fb_base_phys;
1827 info->fix.smem_len = rinfo->video_ram;
1828 info->fix.type = FB_TYPE_PACKED_PIXELS;
1829 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1830 info->fix.xpanstep = 8;
1831 info->fix.ypanstep = 1;
1832 info->fix.ywrapstep = 0;
1833 info->fix.type_aux = 0;
1834 info->fix.mmio_start = rinfo->mmio_base_phys;
1835 info->fix.mmio_len = RADEON_REGSIZE;
1836 info->fix.accel = FB_ACCEL_ATI_RADEON;
1837
1838 fb_alloc_cmap(&info->cmap, 256, 0);
1839
1840 if (noaccel)
1841 info->flags |= FBINFO_HWACCEL_DISABLED;
1842
1843 return 0;
1844}
1845
1846
1847#ifdef CONFIG_PMAC_BACKLIGHT
1848
1849/* TODO: Dbl check these tables, we don't go up to full ON backlight
1850 * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1851 * having some more official numbers from ATI
1852 */
1853static int backlight_conv_m6[] = {
1854 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1855 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1856};
1857static int backlight_conv_m7[] = {
1858 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1859 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1860};
1861
1862#define BACKLIGHT_LVDS_OFF
1863#undef BACKLIGHT_DAC_OFF
1864
1865/* We turn off the LCD completely instead of just dimming the backlight.
1866 * This provides some greater power saving and the display is useless
1867 * without backlight anyway.
1868 */
1869static int radeon_set_backlight_enable(int on, int level, void *data)
1870{
1871 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1872 u32 lvds_gen_cntl, tmpPixclksCntl;
1873 int* conv_table;
1874
1875 if (rinfo->mon1_type != MT_LCD)
1876 return 0;
1877
1878 /* Pardon me for that hack... maybe some day we can figure
1879 * out in what direction backlight should work on a given
1880 * panel ?
1881 */
1882 if ((rinfo->family == CHIP_FAMILY_RV200 ||
1883 rinfo->family == CHIP_FAMILY_RV250 ||
1884 rinfo->family == CHIP_FAMILY_RV280 ||
1885 rinfo->family == CHIP_FAMILY_RV350) &&
1886 !machine_is_compatible("PowerBook4,3") &&
1887 !machine_is_compatible("PowerBook6,3") &&
1888 !machine_is_compatible("PowerBook6,5"))
1889 conv_table = backlight_conv_m7;
1890 else
1891 conv_table = backlight_conv_m6;
1892
1893 del_timer_sync(&rinfo->lvds_timer);
1894 radeon_engine_idle();
1895
1896 lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1897 if (on && (level > BACKLIGHT_OFF)) {
1898 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1899 if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
1900 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
1901 lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
1902 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1903 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1904 lvds_gen_cntl |= (conv_table[level] <<
1905 LVDS_BL_MOD_LEVEL_SHIFT);
1906 lvds_gen_cntl |= LVDS_ON;
1907 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
1908 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
1909 mod_timer(&rinfo->lvds_timer,
1910 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1911 } else {
1912 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1913 lvds_gen_cntl |= (conv_table[level] <<
1914 LVDS_BL_MOD_LEVEL_SHIFT);
1915 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1916 }
1917 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1918 rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl
1919 & LVDS_STATE_MASK;
1920 } else {
1921 /* Asic bug, when turning off LVDS_ON, we have to make sure
1922 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1923 */
1924 tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1925 if (rinfo->is_mobility || rinfo->is_IGP)
1926 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1927 lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
1928 lvds_gen_cntl |= (conv_table[0] <<
1929 LVDS_BL_MOD_LEVEL_SHIFT);
1930 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
1931 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1932 udelay(100);
1933 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
1934 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1935 lvds_gen_cntl &= ~(LVDS_DIGON);
1936 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
1937 mod_timer(&rinfo->lvds_timer,
1938 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1939 if (rinfo->is_mobility || rinfo->is_IGP)
1940 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
1941 }
1942 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1943 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
1944
1945 return 0;
1946}
1947
1948
1949static int radeon_set_backlight_level(int level, void *data)
1950{
1951 return radeon_set_backlight_enable(1, level, data);
1952}
1953#endif /* CONFIG_PMAC_BACKLIGHT */
1954
1955
1956/*
1957 * This reconfigure the card's internal memory map. In theory, we'd like
1958 * to setup the card's memory at the same address as it's PCI bus address,
1959 * and the AGP aperture right after that so that system RAM on 32 bits
1960 * machines at least, is directly accessible. However, doing so would
1961 * conflict with the current XFree drivers...
1962 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1963 * on the proper way to set this up and duplicate this here. In the meantime,
1964 * I put the card's memory at 0 in card space and AGP at some random high
1965 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1966 */
1967#ifdef CONFIG_PPC_OF
1968#undef SET_MC_FB_FROM_APERTURE
1969static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1970{
1971 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1972 u32 save_crtc_ext_cntl;
1973 u32 aper_base, aper_size;
1974 u32 agp_base;
1975
1976 /* First, we disable display to avoid interfering */
1977 if (rinfo->has_CRTC2) {
1978 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1979 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1980 }
1981 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1982 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1983
1984 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1985 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1986 mdelay(100);
1987
1988 aper_base = INREG(CONFIG_APER_0_BASE);
1989 aper_size = INREG(CONFIG_APER_SIZE);
1990
1991#ifdef SET_MC_FB_FROM_APERTURE
1992 /* Set framebuffer to be at the same address as set in PCI BAR */
1993 OUTREG(MC_FB_LOCATION,
1994 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1995 rinfo->fb_local_base = aper_base;
1996#else
1997 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1998 rinfo->fb_local_base = 0;
1999#endif
2000 agp_base = aper_base + aper_size;
2001 if (agp_base & 0xf0000000)
2002 agp_base = (aper_base | 0x0fffffff) + 1;
2003
2004 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
2005 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
2006 * always the case on PPCs afaik.
2007 */
2008#ifdef SET_MC_FB_FROM_APERTURE
2009 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
2010#else
2011 OUTREG(MC_AGP_LOCATION, 0xffffe000);
2012#endif
2013
2014 /* Fixup the display base addresses & engine offsets while we
2015 * are at it as well
2016 */
2017#ifdef SET_MC_FB_FROM_APERTURE
2018 OUTREG(DISPLAY_BASE_ADDR, aper_base);
2019 if (rinfo->has_CRTC2)
2020 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
2021 OUTREG(OV0_BASE_ADDR, aper_base);
2022#else
2023 OUTREG(DISPLAY_BASE_ADDR, 0);
2024 if (rinfo->has_CRTC2)
2025 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2026 OUTREG(OV0_BASE_ADDR, 0);
2027#endif
2028 mdelay(100);
2029
2030 /* Restore display settings */
2031 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2032 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2033 if (rinfo->has_CRTC2)
2034 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2035
2036 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2037 aper_base,
2038 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2039 0xffff0000 | (agp_base >> 16));
2040}
2041#endif /* CONFIG_PPC_OF */
2042
2043
2044static void radeon_identify_vram(struct radeonfb_info *rinfo)
2045{
2046 u32 tmp;
2047
2048 /* framebuffer size */
2049 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2050 (rinfo->family == CHIP_FAMILY_RS200) ||
2051 (rinfo->family == CHIP_FAMILY_RS300)) {
2052 u32 tom = INREG(NB_TOM);
2053 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2054
2055 radeon_fifo_wait(6);
2056 OUTREG(MC_FB_LOCATION, tom);
2057 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2058 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2059 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2060
2061 /* This is supposed to fix the crtc2 noise problem. */
2062 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2063
2064 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2065 (rinfo->family == CHIP_FAMILY_RS200)) {
2066 /* This is to workaround the asic bug for RMX, some versions
2067 of BIOS dosen't have this register initialized correctly.
2068 */
2069 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2070 ~CRTC_H_CUTOFF_ACTIVE_EN);
2071 }
2072 } else {
2073 tmp = INREG(CONFIG_MEMSIZE);
2074 }
2075
2076 /* mem size is bits [28:0], mask off the rest */
2077 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2078
2079 /*
2080 * Hack to get around some busted production M6's
2081 * reporting no ram
2082 */
2083 if (rinfo->video_ram == 0) {
2084 switch (rinfo->pdev->device) {
2085 case PCI_CHIP_RADEON_LY:
2086 case PCI_CHIP_RADEON_LZ:
2087 rinfo->video_ram = 8192 * 1024;
2088 break;
2089 default:
2090 break;
2091 }
2092 }
2093
2094
2095 /*
2096 * Now try to identify VRAM type
2097 */
2098 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2099 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2100 rinfo->vram_ddr = 1;
2101 else
2102 rinfo->vram_ddr = 0;
2103
2104 tmp = INREG(MEM_CNTL);
2105 if (IS_R300_VARIANT(rinfo)) {
2106 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2107 switch (tmp) {
2108 case 0: rinfo->vram_width = 64; break;
2109 case 1: rinfo->vram_width = 128; break;
2110 case 2: rinfo->vram_width = 256; break;
2111 default: rinfo->vram_width = 128; break;
2112 }
2113 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2114 (rinfo->family == CHIP_FAMILY_RS100) ||
2115 (rinfo->family == CHIP_FAMILY_RS200)){
2116 if (tmp & RV100_MEM_HALF_MODE)
2117 rinfo->vram_width = 32;
2118 else
2119 rinfo->vram_width = 64;
2120 } else {
2121 if (tmp & MEM_NUM_CHANNELS_MASK)
2122 rinfo->vram_width = 128;
2123 else
2124 rinfo->vram_width = 64;
2125 }
2126
2127 /* This may not be correct, as some cards can have half of channel disabled
2128 * ToDo: identify these cases
2129 */
2130
2131 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2132 pci_name(rinfo->pdev),
2133 rinfo->video_ram / 1024,
2134 rinfo->vram_ddr ? "DDR" : "SDRAM",
2135 rinfo->vram_width);
2136}
2137
2138/*
2139 * Sysfs
2140 */
2141
2142static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2143{
2144 if (off > EDID_LENGTH)
2145 return 0;
2146
2147 if (off + count > EDID_LENGTH)
2148 count = EDID_LENGTH - off;
2149
2150 memcpy(buf, edid + off, count);
2151
2152 return count;
2153}
2154
2155
2156static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2157{
2158 struct device *dev = container_of(kobj, struct device, kobj);
2159 struct pci_dev *pdev = to_pci_dev(dev);
2160 struct fb_info *info = pci_get_drvdata(pdev);
2161 struct radeonfb_info *rinfo = info->par;
2162
2163 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2164}
2165
2166
2167static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2168{
2169 struct device *dev = container_of(kobj, struct device, kobj);
2170 struct pci_dev *pdev = to_pci_dev(dev);
2171 struct fb_info *info = pci_get_drvdata(pdev);
2172 struct radeonfb_info *rinfo = info->par;
2173
2174 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2175}
2176
2177static struct bin_attribute edid1_attr = {
2178 .attr = {
2179 .name = "edid1",
2180 .owner = THIS_MODULE,
2181 .mode = 0444,
2182 },
2183 .size = EDID_LENGTH,
2184 .read = radeon_show_edid1,
2185};
2186
2187static struct bin_attribute edid2_attr = {
2188 .attr = {
2189 .name = "edid2",
2190 .owner = THIS_MODULE,
2191 .mode = 0444,
2192 },
2193 .size = EDID_LENGTH,
2194 .read = radeon_show_edid2,
2195};
2196
2197
2198static int radeonfb_pci_register (struct pci_dev *pdev,
2199 const struct pci_device_id *ent)
2200{
2201 struct fb_info *info;
2202 struct radeonfb_info *rinfo;
2203 int ret;
2204
2205 RTRACE("radeonfb_pci_register BEGIN\n");
2206
2207 /* Enable device in PCI config */
2208 ret = pci_enable_device(pdev);
2209 if (ret < 0) {
2210 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2211 pci_name(pdev));
2212 goto err_out;
2213 }
2214
2215 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2216 if (!info) {
2217 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2218 pci_name(pdev));
2219 ret = -ENOMEM;
2220 goto err_disable;
2221 }
2222 rinfo = info->par;
2223 rinfo->info = info;
2224 rinfo->pdev = pdev;
2225
2226 spin_lock_init(&rinfo->reg_lock);
2227 init_timer(&rinfo->lvds_timer);
2228 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2229 rinfo->lvds_timer.data = (unsigned long)rinfo;
2230
2231 strcpy(rinfo->name, "ATI Radeon XX ");
2232 rinfo->name[11] = ent->device >> 8;
2233 rinfo->name[12] = ent->device & 0xFF;
2234 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2235 rinfo->chipset = pdev->device;
2236 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2237 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2238 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2239
2240 /* Set base addrs */
2241 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2242 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2243
2244 /* request the mem regions */
2245 ret = pci_request_regions(pdev, "radeonfb");
2246 if (ret < 0) {
2247 printk( KERN_ERR "radeonfb (%s): cannot reserve PCI regions."
2248 " Someone already got them?\n", pci_name(rinfo->pdev));
2249 goto err_release_fb;
2250 }
2251
2252 /* map the regions */
2253 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2254 if (!rinfo->mmio_base) {
2255 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", pci_name(rinfo->pdev));
2256 ret = -EIO;
2257 goto err_release_pci;
2258 }
2259
2260 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2261
2262 /*
2263 * Check for errata
2264 */
2265 rinfo->errata = 0;
2266 if (rinfo->family == CHIP_FAMILY_R300 &&
2267 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2268 == CFG_ATI_REV_A11)
2269 rinfo->errata |= CHIP_ERRATA_R300_CG;
2270
2271 if (rinfo->family == CHIP_FAMILY_RV200 ||
2272 rinfo->family == CHIP_FAMILY_RS200)
2273 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2274
2275 if (rinfo->family == CHIP_FAMILY_RV100 ||
2276 rinfo->family == CHIP_FAMILY_RS100 ||
2277 rinfo->family == CHIP_FAMILY_RS200)
2278 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2279
2280#ifdef CONFIG_PPC_OF
2281 /* On PPC, we obtain the OF device-node pointer to the firmware
2282 * data for this chip
2283 */
2284 rinfo->of_node = pci_device_to_OF_node(pdev);
2285 if (rinfo->of_node == NULL)
2286 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2287 pci_name(rinfo->pdev));
2288
2289 /* On PPC, the firmware sets up a memory mapping that tends
2290 * to cause lockups when enabling the engine. We reconfigure
2291 * the card internal memory mappings properly
2292 */
2293 fixup_memory_mappings(rinfo);
2294#endif /* CONFIG_PPC_OF */
2295
2296 /* Get VRAM size and type */
2297 radeon_identify_vram(rinfo);
2298
2299 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2300
2301 do {
2302 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2303 rinfo->mapped_vram);
2304 } while ( rinfo->fb_base == 0 &&
2305 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2306
2307 if (rinfo->fb_base)
2308 memset_io(rinfo->fb_base, 0, rinfo->mapped_vram);
2309 else {
2310 printk (KERN_ERR "radeonfb (%s): cannot map FB\n", pci_name(rinfo->pdev));
2311 ret = -EIO;
2312 goto err_unmap_rom;
2313 }
2314
2315 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2316 rinfo->mapped_vram/1024);
2317
2318 /*
2319 * Map the BIOS ROM if any and retreive PLL parameters from
2320 * the BIOS. We skip that on mobility chips as the real panel
2321 * values we need aren't in the ROM but in the BIOS image in
2322 * memory. This is definitely not the best meacnism though,
2323 * we really need the arch code to tell us which is the "primary"
2324 * video adapter to use the memory image (or better, the arch
2325 * should provide us a copy of the BIOS image to shield us from
2326 * archs who would store that elsewhere and/or could initialize
2327 * more than one adapter during boot).
2328 */
2329 if (!rinfo->is_mobility)
2330 radeon_map_ROM(rinfo, pdev);
2331
2332 /*
2333 * On x86, the primary display on laptop may have it's BIOS
2334 * ROM elsewhere, try to locate it at the legacy memory hole.
2335 * We probably need to make sure this is the primary display,
2336 * but that is difficult without some arch support.
2337 */
2338#ifdef CONFIG_X86
2339 if (rinfo->bios_seg == NULL)
2340 radeon_find_mem_vbios(rinfo);
2341#endif
2342
2343 /* If both above failed, try the BIOS ROM again for mobility
2344 * chips
2345 */
2346 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2347 radeon_map_ROM(rinfo, pdev);
2348
2349 /* Get informations about the board's PLL */
2350 radeon_get_pllinfo(rinfo);
2351
2352#ifdef CONFIG_FB_RADEON_I2C
2353 /* Register I2C bus */
2354 radeon_create_i2c_busses(rinfo);
2355#endif
2356
2357 /* set all the vital stuff */
2358 radeon_set_fbinfo (rinfo);
2359
2360 /* Probe screen types */
2361 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2362
2363 /* Build mode list, check out panel native model */
2364 radeon_check_modes(rinfo, mode_option);
2365
2366 /* Register some sysfs stuff (should be done better) */
2367 if (rinfo->mon1_EDID)
2368 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2369 if (rinfo->mon2_EDID)
2370 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2371
2372 /* save current mode regs before we switch into the new one
2373 * so we can restore this upon __exit
2374 */
2375 radeon_save_state (rinfo, &rinfo->init_state);
2376 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2377
2378 /* Setup Power Management capabilities */
2379 if (default_dynclk < -1) {
2380 /* -2 is special: means ON on mobility chips and do not
2381 * change on others
2382 */
2383 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
2384 } else
2385 radeonfb_pm_init(rinfo, default_dynclk);
2386
2387 pci_set_drvdata(pdev, info);
2388
2389 /* Register with fbdev layer */
2390 ret = register_framebuffer(info);
2391 if (ret < 0) {
2392 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2393 pci_name(rinfo->pdev));
2394 goto err_unmap_fb;
2395 }
2396
2397#ifdef CONFIG_MTRR
2398 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2399 rinfo->video_ram,
2400 MTRR_TYPE_WRCOMB, 1);
2401#endif
2402
2403#ifdef CONFIG_PMAC_BACKLIGHT
2404 if (rinfo->mon1_type == MT_LCD) {
2405 register_backlight_controller(&radeon_backlight_controller,
2406 rinfo, "ati");
2407 register_backlight_controller(&radeon_backlight_controller,
2408 rinfo, "mnca");
2409 }
2410#endif
2411
2412 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2413
2414 if (rinfo->bios_seg)
2415 radeon_unmap_ROM(rinfo, pdev);
2416 RTRACE("radeonfb_pci_register END\n");
2417
2418 return 0;
2419err_unmap_fb:
2420 iounmap(rinfo->fb_base);
2421err_unmap_rom:
2422 kfree(rinfo->mon1_EDID);
2423 kfree(rinfo->mon2_EDID);
2424 if (rinfo->mon1_modedb)
2425 fb_destroy_modedb(rinfo->mon1_modedb);
2426 fb_dealloc_cmap(&info->cmap);
2427#ifdef CONFIG_FB_RADEON_I2C
2428 radeon_delete_i2c_busses(rinfo);
2429#endif
2430 if (rinfo->bios_seg)
2431 radeon_unmap_ROM(rinfo, pdev);
2432 iounmap(rinfo->mmio_base);
2433err_release_pci:
2434 pci_release_regions(pdev);
2435err_release_fb:
2436 framebuffer_release(info);
2437err_disable:
2438 pci_disable_device(pdev);
2439err_out:
2440 return ret;
2441}
2442
2443
2444
2445static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2446{
2447 struct fb_info *info = pci_get_drvdata(pdev);
2448 struct radeonfb_info *rinfo = info->par;
2449
2450 if (!rinfo)
2451 return;
2452
2453 radeonfb_pm_exit(rinfo);
2454
2455#if 0
2456 /* restore original state
2457 *
2458 * Doesn't quite work yet, I suspect if we come from a legacy
2459 * VGA mode (or worse, text mode), we need to do some VGA black
2460 * magic here that I know nothing about. --BenH
2461 */
2462 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2463 #endif
2464
2465 del_timer_sync(&rinfo->lvds_timer);
2466
2467#ifdef CONFIG_MTRR
2468 if (rinfo->mtrr_hdl >= 0)
2469 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2470#endif
2471
2472 unregister_framebuffer(info);
2473
2474 iounmap(rinfo->mmio_base);
2475 iounmap(rinfo->fb_base);
2476
2477 pci_release_regions(pdev);
2478
2479 kfree(rinfo->mon1_EDID);
2480 kfree(rinfo->mon2_EDID);
2481 if (rinfo->mon1_modedb)
2482 fb_destroy_modedb(rinfo->mon1_modedb);
2483#ifdef CONFIG_FB_RADEON_I2C
2484 radeon_delete_i2c_busses(rinfo);
2485#endif
2486 fb_dealloc_cmap(&info->cmap);
2487 framebuffer_release(info);
2488 pci_disable_device(pdev);
2489}
2490
2491
2492static struct pci_driver radeonfb_driver = {
2493 .name = "radeonfb",
2494 .id_table = radeonfb_pci_table,
2495 .probe = radeonfb_pci_register,
2496 .remove = __devexit_p(radeonfb_pci_unregister),
2497#ifdef CONFIG_PM
2498 .suspend = radeonfb_pci_suspend,
2499 .resume = radeonfb_pci_resume,
2500#endif /* CONFIG_PM */
2501};
2502
2503#ifndef MODULE
2504static int __init radeonfb_setup (char *options)
2505{
2506 char *this_opt;
2507
2508 if (!options || !*options)
2509 return 0;
2510
2511 while ((this_opt = strsep (&options, ",")) != NULL) {
2512 if (!*this_opt)
2513 continue;
2514
2515 if (!strncmp(this_opt, "noaccel", 7)) {
2516 noaccel = 1;
2517 } else if (!strncmp(this_opt, "mirror", 6)) {
2518 mirror = 1;
2519 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2520 force_dfp = 1;
2521 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2522 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2523#ifdef CONFIG_MTRR
2524 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2525 nomtrr = 1;
2526#endif
2527 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2528 nomodeset = 1;
2529 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2530 force_measure_pll = 1;
2531 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2532 ignore_edid = 1;
2533 } else
2534 mode_option = this_opt;
2535 }
2536 return 0;
2537}
2538#endif /* MODULE */
2539
2540static int __init radeonfb_init (void)
2541{
2542#ifndef MODULE
2543 char *option = NULL;
2544
2545 if (fb_get_options("radeonfb", &option))
2546 return -ENODEV;
2547 radeonfb_setup(option);
2548#endif
2549 return pci_register_driver (&radeonfb_driver);
2550}
2551
2552
2553static void __exit radeonfb_exit (void)
2554{
2555 pci_unregister_driver (&radeonfb_driver);
2556}
2557
2558module_init(radeonfb_init);
2559module_exit(radeonfb_exit);
2560
2561MODULE_AUTHOR("Ani Joshi");
2562MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2563MODULE_LICENSE("GPL");
2564module_param(noaccel, bool, 0);
2565module_param(default_dynclk, int, 0);
2566MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2567MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2568module_param(nomodeset, bool, 0);
2569MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2570module_param(mirror, bool, 0);
2571MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2572module_param(force_dfp, bool, 0);
2573MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2574module_param(ignore_edid, bool, 0);
2575MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2576module_param(monitor_layout, charp, 0);
2577MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2578module_param(force_measure_pll, bool, 0);
2579MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2580#ifdef CONFIG_MTRR
2581module_param(nomtrr, bool, 0);
2582MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2583#endif
2584module_param(panel_yres, int, 0);
2585MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2586module_param(mode_option, charp, 0);
2587MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
diff --git a/drivers/video/aty/radeon_i2c.c b/drivers/video/aty/radeon_i2c.c
new file mode 100644
index 000000000000..762244164c81
--- /dev/null
+++ b/drivers/video/aty/radeon_i2c.c
@@ -0,0 +1,265 @@
1#include <linux/config.h>
2#include <linux/module.h>
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/delay.h>
6#include <linux/pci.h>
7#include <linux/fb.h>
8
9
10#include <linux/i2c.h>
11#include <linux/i2c-id.h>
12#include <linux/i2c-algo-bit.h>
13
14#include <asm/io.h>
15
16#include <video/radeon.h>
17#include "radeonfb.h"
18#include "../edid.h"
19
20#define RADEON_DDC 0x50
21
22static void radeon_gpio_setscl(void* data, int state)
23{
24 struct radeon_i2c_chan *chan = data;
25 struct radeonfb_info *rinfo = chan->rinfo;
26 u32 val;
27
28 val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN);
29 if (!state)
30 val |= VGA_DDC_CLK_OUT_EN;
31
32 OUTREG(chan->ddc_reg, val);
33 (void)INREG(chan->ddc_reg);
34}
35
36static void radeon_gpio_setsda(void* data, int state)
37{
38 struct radeon_i2c_chan *chan = data;
39 struct radeonfb_info *rinfo = chan->rinfo;
40 u32 val;
41
42 val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN);
43 if (!state)
44 val |= VGA_DDC_DATA_OUT_EN;
45
46 OUTREG(chan->ddc_reg, val);
47 (void)INREG(chan->ddc_reg);
48}
49
50static int radeon_gpio_getscl(void* data)
51{
52 struct radeon_i2c_chan *chan = data;
53 struct radeonfb_info *rinfo = chan->rinfo;
54 u32 val;
55
56 val = INREG(chan->ddc_reg);
57
58 return (val & VGA_DDC_CLK_INPUT) ? 1 : 0;
59}
60
61static int radeon_gpio_getsda(void* data)
62{
63 struct radeon_i2c_chan *chan = data;
64 struct radeonfb_info *rinfo = chan->rinfo;
65 u32 val;
66
67 val = INREG(chan->ddc_reg);
68
69 return (val & VGA_DDC_DATA_INPUT) ? 1 : 0;
70}
71
72static int radeon_setup_i2c_bus(struct radeon_i2c_chan *chan, const char *name)
73{
74 int rc;
75
76 strcpy(chan->adapter.name, name);
77 chan->adapter.owner = THIS_MODULE;
78 chan->adapter.id = I2C_ALGO_ATI;
79 chan->adapter.algo_data = &chan->algo;
80 chan->adapter.dev.parent = &chan->rinfo->pdev->dev;
81 chan->algo.setsda = radeon_gpio_setsda;
82 chan->algo.setscl = radeon_gpio_setscl;
83 chan->algo.getsda = radeon_gpio_getsda;
84 chan->algo.getscl = radeon_gpio_getscl;
85 chan->algo.udelay = 40;
86 chan->algo.timeout = 20;
87 chan->algo.data = chan;
88
89 i2c_set_adapdata(&chan->adapter, chan);
90
91 /* Raise SCL and SDA */
92 radeon_gpio_setsda(chan, 1);
93 radeon_gpio_setscl(chan, 1);
94 udelay(20);
95
96 rc = i2c_bit_add_bus(&chan->adapter);
97 if (rc == 0)
98 dev_dbg(&chan->rinfo->pdev->dev, "I2C bus %s registered.\n", name);
99 else
100 dev_warn(&chan->rinfo->pdev->dev, "Failed to register I2C bus %s.\n", name);
101 return rc;
102}
103
104void radeon_create_i2c_busses(struct radeonfb_info *rinfo)
105{
106 rinfo->i2c[0].rinfo = rinfo;
107 rinfo->i2c[0].ddc_reg = GPIO_MONID;
108 radeon_setup_i2c_bus(&rinfo->i2c[0], "monid");
109
110 rinfo->i2c[1].rinfo = rinfo;
111 rinfo->i2c[1].ddc_reg = GPIO_DVI_DDC;
112 radeon_setup_i2c_bus(&rinfo->i2c[1], "dvi");
113
114 rinfo->i2c[2].rinfo = rinfo;
115 rinfo->i2c[2].ddc_reg = GPIO_VGA_DDC;
116 radeon_setup_i2c_bus(&rinfo->i2c[2], "vga");
117
118 rinfo->i2c[3].rinfo = rinfo;
119 rinfo->i2c[3].ddc_reg = GPIO_CRT2_DDC;
120 radeon_setup_i2c_bus(&rinfo->i2c[3], "crt2");
121}
122
123void radeon_delete_i2c_busses(struct radeonfb_info *rinfo)
124{
125 if (rinfo->i2c[0].rinfo)
126 i2c_bit_del_bus(&rinfo->i2c[0].adapter);
127 rinfo->i2c[0].rinfo = NULL;
128
129 if (rinfo->i2c[1].rinfo)
130 i2c_bit_del_bus(&rinfo->i2c[1].adapter);
131 rinfo->i2c[1].rinfo = NULL;
132
133 if (rinfo->i2c[2].rinfo)
134 i2c_bit_del_bus(&rinfo->i2c[2].adapter);
135 rinfo->i2c[2].rinfo = NULL;
136
137 if (rinfo->i2c[3].rinfo)
138 i2c_bit_del_bus(&rinfo->i2c[3].adapter);
139 rinfo->i2c[3].rinfo = NULL;
140}
141
142
143static u8 *radeon_do_probe_i2c_edid(struct radeon_i2c_chan *chan)
144{
145 u8 start = 0x0;
146 struct i2c_msg msgs[] = {
147 {
148 .addr = RADEON_DDC,
149 .len = 1,
150 .buf = &start,
151 }, {
152 .addr = RADEON_DDC,
153 .flags = I2C_M_RD,
154 .len = EDID_LENGTH,
155 },
156 };
157 u8 *buf;
158
159 buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
160 if (!buf) {
161 dev_warn(&chan->rinfo->pdev->dev, "Out of memory!\n");
162 return NULL;
163 }
164 msgs[1].buf = buf;
165
166 if (i2c_transfer(&chan->adapter, msgs, 2) == 2)
167 return buf;
168 dev_dbg(&chan->rinfo->pdev->dev, "Unable to read EDID block.\n");
169 kfree(buf);
170 return NULL;
171}
172
173
174int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid)
175{
176 u32 reg = rinfo->i2c[conn-1].ddc_reg;
177 u8 *edid = NULL;
178 int i, j;
179
180 OUTREG(reg, INREG(reg) &
181 ~(VGA_DDC_DATA_OUTPUT | VGA_DDC_CLK_OUTPUT));
182
183 OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
184 (void)INREG(reg);
185
186 for (i = 0; i < 3; i++) {
187 /* For some old monitors we need the
188 * following process to initialize/stop DDC
189 */
190 OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
191 (void)INREG(reg);
192 msleep(13);
193
194 OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
195 (void)INREG(reg);
196 for (j = 0; j < 5; j++) {
197 msleep(10);
198 if (INREG(reg) & VGA_DDC_CLK_INPUT)
199 break;
200 }
201 if (j == 5)
202 continue;
203
204 OUTREG(reg, INREG(reg) | VGA_DDC_DATA_OUT_EN);
205 (void)INREG(reg);
206 msleep(15);
207 OUTREG(reg, INREG(reg) | VGA_DDC_CLK_OUT_EN);
208 (void)INREG(reg);
209 msleep(15);
210 OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
211 (void)INREG(reg);
212 msleep(15);
213
214 /* Do the real work */
215 edid = radeon_do_probe_i2c_edid(&rinfo->i2c[conn-1]);
216
217 OUTREG(reg, INREG(reg) |
218 (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN));
219 (void)INREG(reg);
220 msleep(15);
221
222 OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
223 (void)INREG(reg);
224 for (j = 0; j < 10; j++) {
225 msleep(10);
226 if (INREG(reg) & VGA_DDC_CLK_INPUT)
227 break;
228 }
229
230 OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
231 (void)INREG(reg);
232 msleep(15);
233 OUTREG(reg, INREG(reg) |
234 (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN));
235 (void)INREG(reg);
236 if (edid)
237 break;
238 }
239 /* Release the DDC lines when done or the Apple Cinema HD display
240 * will switch off
241 */
242 OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN | VGA_DDC_DATA_OUT_EN));
243 (void)INREG(reg);
244
245 if (out_edid)
246 *out_edid = edid;
247 if (!edid) {
248 RTRACE("radeonfb: I2C (port %d) ... not found\n", conn);
249 return MT_NONE;
250 }
251 if (edid[0x14] & 0x80) {
252 /* Fix detection using BIOS tables */
253 if (rinfo->is_mobility /*&& conn == ddc_dvi*/ &&
254 (INREG(LVDS_GEN_CNTL) & LVDS_ON)) {
255 RTRACE("radeonfb: I2C (port %d) ... found LVDS panel\n", conn);
256 return MT_LCD;
257 } else {
258 RTRACE("radeonfb: I2C (port %d) ... found TMDS panel\n", conn);
259 return MT_DFP;
260 }
261 }
262 RTRACE("radeonfb: I2C (port %d) ... found CRT display\n", conn);
263 return MT_CRT;
264}
265
diff --git a/drivers/video/aty/radeon_monitor.c b/drivers/video/aty/radeon_monitor.c
new file mode 100644
index 000000000000..ea7c86306918
--- /dev/null
+++ b/drivers/video/aty/radeon_monitor.c
@@ -0,0 +1,1010 @@
1#include "radeonfb.h"
2#include "../edid.h"
3
4static struct fb_var_screeninfo radeonfb_default_var = {
5 .xres = 640,
6 .yres = 480,
7 .xres_virtual = 640,
8 .yres_virtual = 480,
9 .bits_per_pixel = 8,
10 .red = { .length = 8 },
11 .green = { .length = 8 },
12 .blue = { .length = 8 },
13 .activate = FB_ACTIVATE_NOW,
14 .height = -1,
15 .width = -1,
16 .pixclock = 39721,
17 .left_margin = 40,
18 .right_margin = 24,
19 .upper_margin = 32,
20 .lower_margin = 11,
21 .hsync_len = 96,
22 .vsync_len = 2,
23 .vmode = FB_VMODE_NONINTERLACED
24};
25
26static char *radeon_get_mon_name(int type)
27{
28 char *pret = NULL;
29
30 switch (type) {
31 case MT_NONE:
32 pret = "no";
33 break;
34 case MT_CRT:
35 pret = "CRT";
36 break;
37 case MT_DFP:
38 pret = "DFP";
39 break;
40 case MT_LCD:
41 pret = "LCD";
42 break;
43 case MT_CTV:
44 pret = "CTV";
45 break;
46 case MT_STV:
47 pret = "STV";
48 break;
49 }
50
51 return pret;
52}
53
54
55#ifdef CONFIG_PPC_OF
56/*
57 * Try to find monitor informations & EDID data out of the Open Firmware
58 * device-tree. This also contains some "hacks" to work around a few machine
59 * models with broken OF probing by hard-coding known EDIDs for some Mac
60 * laptops internal LVDS panel. (XXX: not done yet)
61 */
62static int __devinit radeon_parse_montype_prop(struct device_node *dp, u8 **out_EDID,
63 int hdno)
64{
65 static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID",
66 "EDID1", "EDID2", NULL };
67 u8 *pedid = NULL;
68 u8 *pmt = NULL;
69 u8 *tmp;
70 int i, mt = MT_NONE;
71
72 RTRACE("analyzing OF properties...\n");
73 pmt = (u8 *)get_property(dp, "display-type", NULL);
74 if (!pmt)
75 return MT_NONE;
76 RTRACE("display-type: %s\n", pmt);
77 /* OF says "LCD" for DFP as well, we discriminate from the caller of this
78 * function
79 */
80 if (!strcmp(pmt, "LCD") || !strcmp(pmt, "DFP"))
81 mt = MT_DFP;
82 else if (!strcmp(pmt, "CRT"))
83 mt = MT_CRT;
84 else {
85 if (strcmp(pmt, "NONE") != 0)
86 printk(KERN_WARNING "radeonfb: Unknown OF display-type: %s\n",
87 pmt);
88 return MT_NONE;
89 }
90
91 for (i = 0; propnames[i] != NULL; ++i) {
92 pedid = (u8 *)get_property(dp, propnames[i], NULL);
93 if (pedid != NULL)
94 break;
95 }
96 /* We didn't find the EDID in the leaf node, some cards will actually
97 * put EDID1/EDID2 in the parent, look for these (typically M6 tipb).
98 * single-head cards have hdno == -1 and skip this step
99 */
100 if (pedid == NULL && dp->parent && (hdno != -1))
101 pedid = get_property(dp->parent, (hdno == 0) ? "EDID1" : "EDID2", NULL);
102 if (pedid == NULL && dp->parent && (hdno == 0))
103 pedid = get_property(dp->parent, "EDID", NULL);
104 if (pedid == NULL)
105 return mt;
106
107 tmp = (u8 *)kmalloc(EDID_LENGTH, GFP_KERNEL);
108 if (!tmp)
109 return mt;
110 memcpy(tmp, pedid, EDID_LENGTH);
111 *out_EDID = tmp;
112 return mt;
113}
114
115static int __devinit radeon_probe_OF_head(struct radeonfb_info *rinfo, int head_no,
116 u8 **out_EDID)
117{
118 struct device_node *dp;
119
120 RTRACE("radeon_probe_OF_head\n");
121
122 dp = rinfo->of_node;
123 while (dp == NULL)
124 return MT_NONE;
125
126 if (rinfo->has_CRTC2) {
127 char *pname;
128 int len, second = 0;
129
130 dp = dp->child;
131 do {
132 if (!dp)
133 return MT_NONE;
134 pname = (char *)get_property(dp, "name", NULL);
135 if (!pname)
136 return MT_NONE;
137 len = strlen(pname);
138 RTRACE("head: %s (letter: %c, head_no: %d)\n",
139 pname, pname[len-1], head_no);
140 if (pname[len-1] == 'A' && head_no == 0) {
141 int mt = radeon_parse_montype_prop(dp, out_EDID, 0);
142 /* Maybe check for LVDS_GEN_CNTL here ? I need to check out
143 * what OF does when booting with lid closed
144 */
145 if (mt == MT_DFP && rinfo->is_mobility)
146 mt = MT_LCD;
147 return mt;
148 } else if (pname[len-1] == 'B' && head_no == 1)
149 return radeon_parse_montype_prop(dp, out_EDID, 1);
150 second = 1;
151 dp = dp->sibling;
152 } while(!second);
153 } else {
154 if (head_no > 0)
155 return MT_NONE;
156 return radeon_parse_montype_prop(dp, out_EDID, -1);
157 }
158 return MT_NONE;
159}
160#endif /* CONFIG_PPC_OF */
161
162
163static int __devinit radeon_get_panel_info_BIOS(struct radeonfb_info *rinfo)
164{
165 unsigned long tmp, tmp0;
166 char stmp[30];
167 int i;
168
169 if (!rinfo->bios_seg)
170 return 0;
171
172 if (!(tmp = BIOS_IN16(rinfo->fp_bios_start + 0x40))) {
173 printk(KERN_ERR "radeonfb: Failed to detect DFP panel info using BIOS\n");
174 rinfo->panel_info.pwr_delay = 200;
175 return 0;
176 }
177
178 for(i=0; i<24; i++)
179 stmp[i] = BIOS_IN8(tmp+i+1);
180 stmp[24] = 0;
181 printk("radeonfb: panel ID string: %s\n", stmp);
182 rinfo->panel_info.xres = BIOS_IN16(tmp + 25);
183 rinfo->panel_info.yres = BIOS_IN16(tmp + 27);
184 printk("radeonfb: detected LVDS panel size from BIOS: %dx%d\n",
185 rinfo->panel_info.xres, rinfo->panel_info.yres);
186
187 rinfo->panel_info.pwr_delay = BIOS_IN16(tmp + 44);
188 RTRACE("BIOS provided panel power delay: %d\n", rinfo->panel_info.pwr_delay);
189 if (rinfo->panel_info.pwr_delay > 2000 || rinfo->panel_info.pwr_delay <= 0)
190 rinfo->panel_info.pwr_delay = 2000;
191
192 /*
193 * Some panels only work properly with some divider combinations
194 */
195 rinfo->panel_info.ref_divider = BIOS_IN16(tmp + 46);
196 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48);
197 rinfo->panel_info.fbk_divider = BIOS_IN16(tmp + 49);
198 if (rinfo->panel_info.ref_divider != 0 &&
199 rinfo->panel_info.fbk_divider > 3) {
200 rinfo->panel_info.use_bios_dividers = 1;
201 printk(KERN_INFO "radeondb: BIOS provided dividers will be used\n");
202 RTRACE("ref_divider = %x\n", rinfo->panel_info.ref_divider);
203 RTRACE("post_divider = %x\n", rinfo->panel_info.post_divider);
204 RTRACE("fbk_divider = %x\n", rinfo->panel_info.fbk_divider);
205 }
206 RTRACE("Scanning BIOS table ...\n");
207 for(i=0; i<32; i++) {
208 tmp0 = BIOS_IN16(tmp+64+i*2);
209 if (tmp0 == 0)
210 break;
211 RTRACE(" %d x %d\n", BIOS_IN16(tmp0), BIOS_IN16(tmp0+2));
212 if ((BIOS_IN16(tmp0) == rinfo->panel_info.xres) &&
213 (BIOS_IN16(tmp0+2) == rinfo->panel_info.yres)) {
214 rinfo->panel_info.hblank = (BIOS_IN16(tmp0+17) - BIOS_IN16(tmp0+19)) * 8;
215 rinfo->panel_info.hOver_plus = ((BIOS_IN16(tmp0+21) -
216 BIOS_IN16(tmp0+19) -1) * 8) & 0x7fff;
217 rinfo->panel_info.hSync_width = BIOS_IN8(tmp0+23) * 8;
218 rinfo->panel_info.vblank = BIOS_IN16(tmp0+24) - BIOS_IN16(tmp0+26);
219 rinfo->panel_info.vOver_plus = (BIOS_IN16(tmp0+28) & 0x7ff) - BIOS_IN16(tmp0+26);
220 rinfo->panel_info.vSync_width = (BIOS_IN16(tmp0+28) & 0xf800) >> 11;
221 rinfo->panel_info.clock = BIOS_IN16(tmp0+9);
222 /* Assume high active syncs for now until ATI tells me more... maybe we
223 * can probe register values here ?
224 */
225 rinfo->panel_info.hAct_high = 1;
226 rinfo->panel_info.vAct_high = 1;
227 /* Mark panel infos valid */
228 rinfo->panel_info.valid = 1;
229
230 RTRACE("Found panel in BIOS table:\n");
231 RTRACE(" hblank: %d\n", rinfo->panel_info.hblank);
232 RTRACE(" hOver_plus: %d\n", rinfo->panel_info.hOver_plus);
233 RTRACE(" hSync_width: %d\n", rinfo->panel_info.hSync_width);
234 RTRACE(" vblank: %d\n", rinfo->panel_info.vblank);
235 RTRACE(" vOver_plus: %d\n", rinfo->panel_info.vOver_plus);
236 RTRACE(" vSync_width: %d\n", rinfo->panel_info.vSync_width);
237 RTRACE(" clock: %d\n", rinfo->panel_info.clock);
238
239 return 1;
240 }
241 }
242 RTRACE("Didn't find panel in BIOS table !\n");
243
244 return 0;
245}
246
247/* Try to extract the connector informations from the BIOS. This
248 * doesn't quite work yet, but it's output is still useful for
249 * debugging
250 */
251static void __devinit radeon_parse_connector_info(struct radeonfb_info *rinfo)
252{
253 int offset, chips, connectors, tmp, i, conn, type;
254
255 static char* __conn_type_table[16] = {
256 "NONE", "Proprietary", "CRT", "DVI-I", "DVI-D", "Unknown", "Unknown",
257 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown",
258 "Unknown", "Unknown", "Unknown"
259 };
260
261 if (!rinfo->bios_seg)
262 return;
263
264 offset = BIOS_IN16(rinfo->fp_bios_start + 0x50);
265 if (offset == 0) {
266 printk(KERN_WARNING "radeonfb: No connector info table detected\n");
267 return;
268 }
269
270 /* Don't do much more at this point but displaying the data if
271 * DEBUG is enabled
272 */
273 chips = BIOS_IN8(offset++) >> 4;
274 RTRACE("%d chips in connector info\n", chips);
275 for (i = 0; i < chips; i++) {
276 tmp = BIOS_IN8(offset++);
277 connectors = tmp & 0x0f;
278 RTRACE(" - chip %d has %d connectors\n", tmp >> 4, connectors);
279 for (conn = 0; ; conn++) {
280 tmp = BIOS_IN16(offset);
281 if (tmp == 0)
282 break;
283 offset += 2;
284 type = (tmp >> 12) & 0x0f;
285 RTRACE(" * connector %d of type %d (%s) : %04x\n",
286 conn, type, __conn_type_table[type], tmp);
287 }
288 }
289}
290
291
292/*
293 * Probe physical connection of a CRT. This code comes from XFree
294 * as well and currently is only implemented for the CRT DAC, the
295 * code for the TVDAC is commented out in XFree as "non working"
296 */
297static int __devinit radeon_crt_is_connected(struct radeonfb_info *rinfo, int is_crt_dac)
298{
299 int connected = 0;
300
301 /* the monitor either wasn't connected or it is a non-DDC CRT.
302 * try to probe it
303 */
304 if (is_crt_dac) {
305 unsigned long ulOrigVCLK_ECP_CNTL;
306 unsigned long ulOrigDAC_CNTL;
307 unsigned long ulOrigDAC_EXT_CNTL;
308 unsigned long ulOrigCRTC_EXT_CNTL;
309 unsigned long ulData;
310 unsigned long ulMask;
311
312 ulOrigVCLK_ECP_CNTL = INPLL(VCLK_ECP_CNTL);
313
314 ulData = ulOrigVCLK_ECP_CNTL;
315 ulData &= ~(PIXCLK_ALWAYS_ONb
316 | PIXCLK_DAC_ALWAYS_ONb);
317 ulMask = ~(PIXCLK_ALWAYS_ONb
318 | PIXCLK_DAC_ALWAYS_ONb);
319 OUTPLLP(VCLK_ECP_CNTL, ulData, ulMask);
320
321 ulOrigCRTC_EXT_CNTL = INREG(CRTC_EXT_CNTL);
322 ulData = ulOrigCRTC_EXT_CNTL;
323 ulData |= CRTC_CRT_ON;
324 OUTREG(CRTC_EXT_CNTL, ulData);
325
326 ulOrigDAC_EXT_CNTL = INREG(DAC_EXT_CNTL);
327 ulData = ulOrigDAC_EXT_CNTL;
328 ulData &= ~DAC_FORCE_DATA_MASK;
329 ulData |= (DAC_FORCE_BLANK_OFF_EN
330 |DAC_FORCE_DATA_EN
331 |DAC_FORCE_DATA_SEL_MASK);
332 if ((rinfo->family == CHIP_FAMILY_RV250) ||
333 (rinfo->family == CHIP_FAMILY_RV280))
334 ulData |= (0x01b6 << DAC_FORCE_DATA_SHIFT);
335 else
336 ulData |= (0x01ac << DAC_FORCE_DATA_SHIFT);
337
338 OUTREG(DAC_EXT_CNTL, ulData);
339
340 ulOrigDAC_CNTL = INREG(DAC_CNTL);
341 ulData = ulOrigDAC_CNTL;
342 ulData |= DAC_CMP_EN;
343 ulData &= ~(DAC_RANGE_CNTL_MASK
344 | DAC_PDWN);
345 ulData |= 0x2;
346 OUTREG(DAC_CNTL, ulData);
347
348 mdelay(1);
349
350 ulData = INREG(DAC_CNTL);
351 connected = (DAC_CMP_OUTPUT & ulData) ? 1 : 0;
352
353 ulData = ulOrigVCLK_ECP_CNTL;
354 ulMask = 0xFFFFFFFFL;
355 OUTPLLP(VCLK_ECP_CNTL, ulData, ulMask);
356
357 OUTREG(DAC_CNTL, ulOrigDAC_CNTL );
358 OUTREG(DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL );
359 OUTREG(CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL);
360 }
361
362 return connected ? MT_CRT : MT_NONE;
363}
364
365/*
366 * Parse the "monitor_layout" string if any. This code is mostly
367 * copied from XFree's radeon driver
368 */
369static int __devinit radeon_parse_monitor_layout(struct radeonfb_info *rinfo,
370 const char *monitor_layout)
371{
372 char s1[5], s2[5];
373 int i = 0, second = 0;
374 const char *s;
375
376 if (!monitor_layout)
377 return 0;
378
379 s = monitor_layout;
380 do {
381 switch(*s) {
382 case ',':
383 s1[i] = '\0';
384 i = 0;
385 second = 1;
386 break;
387 case ' ':
388 case '\0':
389 break;
390 default:
391 if (i > 4)
392 break;
393 if (second)
394 s2[i] = *s;
395 else
396 s1[i] = *s;
397 i++;
398 }
399 } while (*s++);
400 if (second)
401 s2[i] = 0;
402 else {
403 s1[i] = 0;
404 s2[0] = 0;
405 }
406 if (strcmp(s1, "CRT") == 0)
407 rinfo->mon1_type = MT_CRT;
408 else if (strcmp(s1, "TMDS") == 0)
409 rinfo->mon1_type = MT_DFP;
410 else if (strcmp(s1, "LVDS") == 0)
411 rinfo->mon1_type = MT_LCD;
412
413 if (strcmp(s2, "CRT") == 0)
414 rinfo->mon2_type = MT_CRT;
415 else if (strcmp(s2, "TMDS") == 0)
416 rinfo->mon2_type = MT_DFP;
417 else if (strcmp(s2, "LVDS") == 0)
418 rinfo->mon2_type = MT_LCD;
419
420 return 1;
421}
422
423/*
424 * Probe display on both primary and secondary card's connector (if any)
425 * by various available techniques (i2c, OF device tree, BIOS, ...) and
426 * try to retreive EDID. The algorithm here comes from XFree's radeon
427 * driver
428 */
429void __devinit radeon_probe_screens(struct radeonfb_info *rinfo,
430 const char *monitor_layout, int ignore_edid)
431{
432#ifdef CONFIG_FB_RADEON_I2C
433 int ddc_crt2_used = 0;
434#endif
435 int tmp, i;
436
437 radeon_parse_connector_info(rinfo);
438
439 if (radeon_parse_monitor_layout(rinfo, monitor_layout)) {
440
441 /*
442 * If user specified a monitor_layout option, use it instead
443 * of auto-detecting. Maybe we should only use this argument
444 * on the first radeon card probed or provide a way to specify
445 * a layout for each card ?
446 */
447
448 RTRACE("Using specified monitor layout: %s", monitor_layout);
449#ifdef CONFIG_FB_RADEON_I2C
450 if (!ignore_edid) {
451 if (rinfo->mon1_type != MT_NONE)
452 if (!radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID)) {
453 radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID);
454 ddc_crt2_used = 1;
455 }
456 if (rinfo->mon2_type != MT_NONE)
457 if (!radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID) &&
458 !ddc_crt2_used)
459 radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID);
460 }
461#endif /* CONFIG_FB_RADEON_I2C */
462 if (rinfo->mon1_type == MT_NONE) {
463 if (rinfo->mon2_type != MT_NONE) {
464 rinfo->mon1_type = rinfo->mon2_type;
465 rinfo->mon1_EDID = rinfo->mon2_EDID;
466 } else {
467 rinfo->mon1_type = MT_CRT;
468 printk(KERN_INFO "radeonfb: No valid monitor, assuming CRT on first port\n");
469 }
470 rinfo->mon2_type = MT_NONE;
471 rinfo->mon2_EDID = NULL;
472 }
473 } else {
474 /*
475 * Auto-detecting display type (well... trying to ...)
476 */
477
478 RTRACE("Starting monitor auto detection...\n");
479
480#if DEBUG && defined(CONFIG_FB_RADEON_I2C)
481 {
482 u8 *EDIDs[4] = { NULL, NULL, NULL, NULL };
483 int mon_types[4] = {MT_NONE, MT_NONE, MT_NONE, MT_NONE};
484 int i;
485
486 for (i = 0; i < 4; i++)
487 mon_types[i] = radeon_probe_i2c_connector(rinfo,
488 i+1, &EDIDs[i]);
489 }
490#endif /* DEBUG */
491 /*
492 * Old single head cards
493 */
494 if (!rinfo->has_CRTC2) {
495#ifdef CONFIG_PPC_OF
496 if (rinfo->mon1_type == MT_NONE)
497 rinfo->mon1_type = radeon_probe_OF_head(rinfo, 0,
498 &rinfo->mon1_EDID);
499#endif /* CONFIG_PPC_OF */
500#ifdef CONFIG_FB_RADEON_I2C
501 if (rinfo->mon1_type == MT_NONE)
502 rinfo->mon1_type =
503 radeon_probe_i2c_connector(rinfo, ddc_dvi,
504 &rinfo->mon1_EDID);
505 if (rinfo->mon1_type == MT_NONE)
506 rinfo->mon1_type =
507 radeon_probe_i2c_connector(rinfo, ddc_vga,
508 &rinfo->mon1_EDID);
509 if (rinfo->mon1_type == MT_NONE)
510 rinfo->mon1_type =
511 radeon_probe_i2c_connector(rinfo, ddc_crt2,
512 &rinfo->mon1_EDID);
513#endif /* CONFIG_FB_RADEON_I2C */
514 if (rinfo->mon1_type == MT_NONE)
515 rinfo->mon1_type = MT_CRT;
516 goto bail;
517 }
518
519 /*
520 * Check for cards with reversed DACs or TMDS controllers using BIOS
521 */
522 if (rinfo->bios_seg &&
523 (tmp = BIOS_IN16(rinfo->fp_bios_start + 0x50))) {
524 for (i = 1; i < 4; i++) {
525 unsigned int tmp0;
526
527 if (!BIOS_IN8(tmp + i*2) && i > 1)
528 break;
529 tmp0 = BIOS_IN16(tmp + i*2);
530 if ((!(tmp0 & 0x01)) && (((tmp0 >> 8) & 0x0f) == ddc_dvi)) {
531 rinfo->reversed_DAC = 1;
532 printk(KERN_INFO "radeonfb: Reversed DACs detected\n");
533 }
534 if ((((tmp0 >> 8) & 0x0f) == ddc_dvi) && ((tmp0 >> 4) & 0x01)) {
535 rinfo->reversed_TMDS = 1;
536 printk(KERN_INFO "radeonfb: Reversed TMDS detected\n");
537 }
538 }
539 }
540
541 /*
542 * Probe primary head (DVI or laptop internal panel)
543 */
544#ifdef CONFIG_PPC_OF
545 if (rinfo->mon1_type == MT_NONE)
546 rinfo->mon1_type = radeon_probe_OF_head(rinfo, 0,
547 &rinfo->mon1_EDID);
548#endif /* CONFIG_PPC_OF */
549#ifdef CONFIG_FB_RADEON_I2C
550 if (rinfo->mon1_type == MT_NONE)
551 rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi,
552 &rinfo->mon1_EDID);
553 if (rinfo->mon1_type == MT_NONE) {
554 rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2,
555 &rinfo->mon1_EDID);
556 if (rinfo->mon1_type != MT_NONE)
557 ddc_crt2_used = 1;
558 }
559#endif /* CONFIG_FB_RADEON_I2C */
560 if (rinfo->mon1_type == MT_NONE && rinfo->is_mobility &&
561 ((rinfo->bios_seg && (INREG(BIOS_4_SCRATCH) & 4))
562 || (INREG(LVDS_GEN_CNTL) & LVDS_ON))) {
563 rinfo->mon1_type = MT_LCD;
564 printk("Non-DDC laptop panel detected\n");
565 }
566 if (rinfo->mon1_type == MT_NONE)
567 rinfo->mon1_type = radeon_crt_is_connected(rinfo, rinfo->reversed_DAC);
568
569 /*
570 * Probe secondary head (mostly VGA, can be DVI)
571 */
572#ifdef CONFIG_PPC_OF
573 if (rinfo->mon2_type == MT_NONE)
574 rinfo->mon2_type = radeon_probe_OF_head(rinfo, 1,
575 &rinfo->mon2_EDID);
576#endif /* CONFIG_PPC_OF */
577#ifdef CONFIG_FB_RADEON_I2C
578 if (rinfo->mon2_type == MT_NONE)
579 rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_vga,
580 &rinfo->mon2_EDID);
581 if (rinfo->mon2_type == MT_NONE && !ddc_crt2_used)
582 rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_crt2,
583 &rinfo->mon2_EDID);
584#endif /* CONFIG_FB_RADEON_I2C */
585 if (rinfo->mon2_type == MT_NONE)
586 rinfo->mon2_type = radeon_crt_is_connected(rinfo, !rinfo->reversed_DAC);
587
588 /*
589 * If we only detected port 2, we swap them, if none detected,
590 * assume CRT (maybe fallback to old BIOS_SCRATCH stuff ? or look
591 * at FP registers ?)
592 */
593 if (rinfo->mon1_type == MT_NONE) {
594 if (rinfo->mon2_type != MT_NONE) {
595 rinfo->mon1_type = rinfo->mon2_type;
596 rinfo->mon1_EDID = rinfo->mon2_EDID;
597 } else
598 rinfo->mon1_type = MT_CRT;
599 rinfo->mon2_type = MT_NONE;
600 rinfo->mon2_EDID = NULL;
601 }
602
603 /*
604 * Deal with reversed TMDS
605 */
606 if (rinfo->reversed_TMDS) {
607 /* Always keep internal TMDS as primary head */
608 if (rinfo->mon1_type == MT_DFP || rinfo->mon2_type == MT_DFP) {
609 int tmp_type = rinfo->mon1_type;
610 u8 *tmp_EDID = rinfo->mon1_EDID;
611 rinfo->mon1_type = rinfo->mon2_type;
612 rinfo->mon1_EDID = rinfo->mon2_EDID;
613 rinfo->mon2_type = tmp_type;
614 rinfo->mon2_EDID = tmp_EDID;
615 if (rinfo->mon1_type == MT_CRT || rinfo->mon2_type == MT_CRT)
616 rinfo->reversed_DAC ^= 1;
617 }
618 }
619 }
620 if (ignore_edid) {
621 kfree(rinfo->mon1_EDID);
622 rinfo->mon1_EDID = NULL;
623 kfree(rinfo->mon2_EDID);
624 rinfo->mon2_EDID = NULL;
625 }
626
627 bail:
628 printk(KERN_INFO "radeonfb: Monitor 1 type %s found\n",
629 radeon_get_mon_name(rinfo->mon1_type));
630 if (rinfo->mon1_EDID)
631 printk(KERN_INFO "radeonfb: EDID probed\n");
632 if (!rinfo->has_CRTC2)
633 return;
634 printk(KERN_INFO "radeonfb: Monitor 2 type %s found\n",
635 radeon_get_mon_name(rinfo->mon2_type));
636 if (rinfo->mon2_EDID)
637 printk(KERN_INFO "radeonfb: EDID probed\n");
638}
639
640
641/*
642 * This functions applyes any arch/model/machine specific fixups
643 * to the panel info. It may eventually alter EDID block as
644 * well or whatever is specific to a given model and not probed
645 * properly by the default code
646 */
647static void radeon_fixup_panel_info(struct radeonfb_info *rinfo)
648{
649#ifdef CONFIG_PPC_OF
650 /*
651 * LCD Flat panels should use fixed dividers, we enfore that on
652 * PPC only for now...
653 */
654 if (!rinfo->panel_info.use_bios_dividers && rinfo->mon1_type == MT_LCD
655 && rinfo->is_mobility) {
656 int ppll_div_sel;
657 u32 ppll_divn;
658 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
659 radeon_pll_errata_after_index(rinfo);
660 ppll_divn = INPLL(PPLL_DIV_0 + ppll_div_sel);
661 rinfo->panel_info.ref_divider = rinfo->pll.ref_div;
662 rinfo->panel_info.fbk_divider = ppll_divn & 0x7ff;
663 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7;
664 rinfo->panel_info.use_bios_dividers = 1;
665
666 printk(KERN_DEBUG "radeonfb: Using Firmware dividers 0x%08x "
667 "from PPLL %d\n",
668 rinfo->panel_info.fbk_divider |
669 (rinfo->panel_info.post_divider << 16),
670 ppll_div_sel);
671 }
672#endif /* CONFIG_PPC_OF */
673}
674
675
676/*
677 * Fill up panel infos from a mode definition, either returned by the EDID
678 * or from the default mode when we can't do any better
679 */
680static void radeon_var_to_panel_info(struct radeonfb_info *rinfo, struct fb_var_screeninfo *var)
681{
682 rinfo->panel_info.xres = var->xres;
683 rinfo->panel_info.yres = var->yres;
684 rinfo->panel_info.clock = 100000000 / var->pixclock;
685 rinfo->panel_info.hOver_plus = var->right_margin;
686 rinfo->panel_info.hSync_width = var->hsync_len;
687 rinfo->panel_info.hblank = var->left_margin +
688 (var->right_margin + var->hsync_len);
689 rinfo->panel_info.vOver_plus = var->lower_margin;
690 rinfo->panel_info.vSync_width = var->vsync_len;
691 rinfo->panel_info.vblank = var->upper_margin +
692 (var->lower_margin + var->vsync_len);
693 rinfo->panel_info.hAct_high =
694 (var->sync & FB_SYNC_HOR_HIGH_ACT) != 0;
695 rinfo->panel_info.vAct_high =
696 (var->sync & FB_SYNC_VERT_HIGH_ACT) != 0;
697 rinfo->panel_info.valid = 1;
698 /* We use a default of 200ms for the panel power delay,
699 * I need to have a real schedule() instead of mdelay's in the panel code.
700 * we might be possible to figure out a better power delay either from
701 * MacOS OF tree or from the EDID block (proprietary extensions ?)
702 */
703 rinfo->panel_info.pwr_delay = 200;
704}
705
706static void radeon_videomode_to_var(struct fb_var_screeninfo *var,
707 const struct fb_videomode *mode)
708{
709 var->xres = mode->xres;
710 var->yres = mode->yres;
711 var->xres_virtual = mode->xres;
712 var->yres_virtual = mode->yres;
713 var->xoffset = 0;
714 var->yoffset = 0;
715 var->pixclock = mode->pixclock;
716 var->left_margin = mode->left_margin;
717 var->right_margin = mode->right_margin;
718 var->upper_margin = mode->upper_margin;
719 var->lower_margin = mode->lower_margin;
720 var->hsync_len = mode->hsync_len;
721 var->vsync_len = mode->vsync_len;
722 var->sync = mode->sync;
723 var->vmode = mode->vmode;
724}
725
726/*
727 * Build the modedb for head 1 (head 2 will come later), check panel infos
728 * from either BIOS or EDID, and pick up the default mode
729 */
730void __devinit radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option)
731{
732 struct fb_info * info = rinfo->info;
733 int has_default_mode = 0;
734
735 /*
736 * Fill default var first
737 */
738 info->var = radeonfb_default_var;
739 INIT_LIST_HEAD(&info->modelist);
740
741 /*
742 * First check out what BIOS has to say
743 */
744 if (rinfo->mon1_type == MT_LCD)
745 radeon_get_panel_info_BIOS(rinfo);
746
747 /*
748 * Parse EDID detailed timings and deduce panel infos if any. Right now
749 * we only deal with first entry returned by parse_EDID, we may do better
750 * some day...
751 */
752 if (!rinfo->panel_info.use_bios_dividers && rinfo->mon1_type != MT_CRT
753 && rinfo->mon1_EDID) {
754 struct fb_var_screeninfo var;
755 RTRACE("Parsing EDID data for panel info\n");
756 if (fb_parse_edid(rinfo->mon1_EDID, &var) == 0) {
757 if (var.xres >= rinfo->panel_info.xres &&
758 var.yres >= rinfo->panel_info.yres)
759 radeon_var_to_panel_info(rinfo, &var);
760 }
761 }
762
763 /*
764 * Do any additional platform/arch fixups to the panel infos
765 */
766 radeon_fixup_panel_info(rinfo);
767
768 /*
769 * If we have some valid panel infos, we setup the default mode based on
770 * those
771 */
772 if (rinfo->mon1_type != MT_CRT && rinfo->panel_info.valid) {
773 struct fb_var_screeninfo *var = &info->var;
774
775 RTRACE("Setting up default mode based on panel info\n");
776 var->xres = rinfo->panel_info.xres;
777 var->yres = rinfo->panel_info.yres;
778 var->xres_virtual = rinfo->panel_info.xres;
779 var->yres_virtual = rinfo->panel_info.yres;
780 var->xoffset = var->yoffset = 0;
781 var->bits_per_pixel = 8;
782 var->pixclock = 100000000 / rinfo->panel_info.clock;
783 var->left_margin = (rinfo->panel_info.hblank - rinfo->panel_info.hOver_plus
784 - rinfo->panel_info.hSync_width);
785 var->right_margin = rinfo->panel_info.hOver_plus;
786 var->upper_margin = (rinfo->panel_info.vblank - rinfo->panel_info.vOver_plus
787 - rinfo->panel_info.vSync_width);
788 var->lower_margin = rinfo->panel_info.vOver_plus;
789 var->hsync_len = rinfo->panel_info.hSync_width;
790 var->vsync_len = rinfo->panel_info.vSync_width;
791 var->sync = 0;
792 if (rinfo->panel_info.hAct_high)
793 var->sync |= FB_SYNC_HOR_HIGH_ACT;
794 if (rinfo->panel_info.vAct_high)
795 var->sync |= FB_SYNC_VERT_HIGH_ACT;
796 var->vmode = 0;
797 has_default_mode = 1;
798 }
799
800 /*
801 * Now build modedb from EDID
802 */
803 if (rinfo->mon1_EDID) {
804 fb_edid_to_monspecs(rinfo->mon1_EDID, &info->monspecs);
805 fb_videomode_to_modelist(info->monspecs.modedb,
806 info->monspecs.modedb_len,
807 &info->modelist);
808 rinfo->mon1_modedb = info->monspecs.modedb;
809 rinfo->mon1_dbsize = info->monspecs.modedb_len;
810 }
811
812
813 /*
814 * Finally, if we don't have panel infos we need to figure some (or
815 * we try to read it from card), we try to pick a default mode
816 * and create some panel infos. Whatever...
817 */
818 if (rinfo->mon1_type != MT_CRT && !rinfo->panel_info.valid) {
819 struct fb_videomode *modedb;
820 int dbsize;
821 char modename[32];
822
823 RTRACE("Guessing panel info...\n");
824 if (rinfo->panel_info.xres == 0 || rinfo->panel_info.yres == 0) {
825 u32 tmp = INREG(FP_HORZ_STRETCH) & HORZ_PANEL_SIZE;
826 rinfo->panel_info.xres = ((tmp >> HORZ_PANEL_SHIFT) + 1) * 8;
827 tmp = INREG(FP_VERT_STRETCH) & VERT_PANEL_SIZE;
828 rinfo->panel_info.yres = (tmp >> VERT_PANEL_SHIFT) + 1;
829 }
830 if (rinfo->panel_info.xres == 0 || rinfo->panel_info.yres == 0) {
831 printk(KERN_WARNING "radeonfb: Can't find panel size, going back to CRT\n");
832 rinfo->mon1_type = MT_CRT;
833 goto pickup_default;
834 }
835 printk(KERN_WARNING "radeonfb: Assuming panel size %dx%d\n",
836 rinfo->panel_info.xres, rinfo->panel_info.yres);
837 modedb = rinfo->mon1_modedb;
838 dbsize = rinfo->mon1_dbsize;
839 snprintf(modename, 31, "%dx%d", rinfo->panel_info.xres, rinfo->panel_info.yres);
840 if (fb_find_mode(&info->var, info, modename,
841 modedb, dbsize, NULL, 8) == 0) {
842 printk(KERN_WARNING "radeonfb: Can't find mode for panel size, going back to CRT\n");
843 rinfo->mon1_type = MT_CRT;
844 goto pickup_default;
845 }
846 has_default_mode = 1;
847 radeon_var_to_panel_info(rinfo, &info->var);
848 }
849
850 pickup_default:
851 /*
852 * Apply passed-in mode option if any
853 */
854 if (mode_option) {
855 if (fb_find_mode(&info->var, info, mode_option,
856 info->monspecs.modedb,
857 info->monspecs.modedb_len, NULL, 8) != 0)
858 has_default_mode = 1;
859 }
860
861 /*
862 * Still no mode, let's pick up a default from the db
863 */
864 if (!has_default_mode && info->monspecs.modedb != NULL) {
865 struct fb_monspecs *specs = &info->monspecs;
866 struct fb_videomode *modedb = NULL;
867
868 /* get preferred timing */
869 if (specs->misc & FB_MISC_1ST_DETAIL) {
870 int i;
871
872 for (i = 0; i < specs->modedb_len; i++) {
873 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
874 modedb = &specs->modedb[i];
875 break;
876 }
877 }
878 } else {
879 /* otherwise, get first mode in database */
880 modedb = &specs->modedb[0];
881 }
882 if (modedb != NULL) {
883 info->var.bits_per_pixel = 8;
884 radeon_videomode_to_var(&info->var, modedb);
885 has_default_mode = 1;
886 }
887 }
888 if (1) {
889 struct fb_videomode mode;
890 /* Make sure that whatever mode got selected is actually in the
891 * modelist or the kernel may die
892 */
893 fb_var_to_videomode(&mode, &info->var);
894 fb_add_videomode(&mode, &info->modelist);
895 }
896}
897
898/*
899 * The code below is used to pick up a mode in check_var and
900 * set_var. It should be made generic
901 */
902
903/*
904 * This is used when looking for modes. We assign a "distance" value
905 * to a mode in the modedb depending how "close" it is from what we
906 * are looking for.
907 * Currently, we don't compare that much, we could do better but
908 * the current fbcon doesn't quite mind ;)
909 */
910static int radeon_compare_modes(const struct fb_var_screeninfo *var,
911 const struct fb_videomode *mode)
912{
913 int distance = 0;
914
915 distance = mode->yres - var->yres;
916 distance += (mode->xres - var->xres)/2;
917 return distance;
918}
919
920/*
921 * This function is called by check_var, it gets the passed in mode parameter, and
922 * outputs a valid mode matching the passed-in one as closely as possible.
923 * We need something better ultimately. Things like fbcon basically pass us out
924 * current mode with xres/yres hacked, while things like XFree will actually
925 * produce a full timing that we should respect as much as possible.
926 *
927 * This is why I added the FB_ACTIVATE_FIND that is used by fbcon. Without this,
928 * we do a simple spec match, that's all. With it, we actually look for a mode in
929 * either our monitor modedb or the vesa one if none
930 *
931 */
932int radeon_match_mode(struct radeonfb_info *rinfo,
933 struct fb_var_screeninfo *dest,
934 const struct fb_var_screeninfo *src)
935{
936 const struct fb_videomode *db = vesa_modes;
937 int i, dbsize = 34;
938 int has_rmx, native_db = 0;
939 int distance = INT_MAX;
940 const struct fb_videomode *candidate = NULL;
941
942 /* Start with a copy of the requested mode */
943 memcpy(dest, src, sizeof(struct fb_var_screeninfo));
944
945 /* Check if we have a modedb built from EDID */
946 if (rinfo->mon1_modedb) {
947 db = rinfo->mon1_modedb;
948 dbsize = rinfo->mon1_dbsize;
949 native_db = 1;
950 }
951
952 /* Check if we have a scaler allowing any fancy mode */
953 has_rmx = rinfo->mon1_type == MT_LCD || rinfo->mon1_type == MT_DFP;
954
955 /* If we have a scaler and are passed FB_ACTIVATE_TEST or
956 * FB_ACTIVATE_NOW, just do basic checking and return if the
957 * mode match
958 */
959 if ((src->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_TEST ||
960 (src->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
961 /* We don't have an RMX, validate timings. If we don't have
962 * monspecs, we should be paranoid and not let use go above
963 * 640x480-60, but I assume userland knows what it's doing here
964 * (though I may be proven wrong...)
965 */
966 if (has_rmx == 0 && rinfo->mon1_modedb)
967 if (fb_validate_mode((struct fb_var_screeninfo *)src, rinfo->info))
968 return -EINVAL;
969 return 0;
970 }
971
972 /* Now look for a mode in the database */
973 while (db) {
974 for (i = 0; i < dbsize; i++) {
975 int d;
976
977 if (db[i].yres < src->yres)
978 continue;
979 if (db[i].xres < src->xres)
980 continue;
981 d = radeon_compare_modes(src, &db[i]);
982 /* If the new mode is at least as good as the previous one,
983 * then it's our new candidate
984 */
985 if (d < distance) {
986 candidate = &db[i];
987 distance = d;
988 }
989 }
990 db = NULL;
991 /* If we have a scaler, we allow any mode from the database */
992 if (native_db && has_rmx) {
993 db = vesa_modes;
994 dbsize = 34;
995 native_db = 0;
996 }
997 }
998
999 /* If we have found a match, return it */
1000 if (candidate != NULL) {
1001 radeon_videomode_to_var(dest, candidate);
1002 return 0;
1003 }
1004
1005 /* If we haven't and don't have a scaler, fail */
1006 if (!has_rmx)
1007 return -EINVAL;
1008
1009 return 0;
1010}
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c
new file mode 100644
index 000000000000..23c677e5093f
--- /dev/null
+++ b/drivers/video/aty/radeon_pm.c
@@ -0,0 +1,2801 @@
1/*
2 * drivers/video/aty/radeon_pm.c
3 *
4 * Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
5 * Copyright 2004 Paul Mackerras <paulus@samba.org>
6 *
7 * This is the power management code for ATI radeon chipsets. It contains
8 * some dynamic clock PM enable/disable code similar to what X.org does,
9 * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
10 * and the necessary bits to re-initialize from scratch a few chips found
11 * on PowerMacs as well. The later could be extended to more platforms
12 * provided the memory controller configuration code be made more generic,
13 * and you can get the proper mode register commands for your RAMs.
14 * Those things may be found in the BIOS image...
15 */
16
17#include "radeonfb.h"
18
19#include <linux/console.h>
20#include <linux/agp_backend.h>
21
22#ifdef CONFIG_PPC_PMAC
23#include <asm/processor.h>
24#include <asm/prom.h>
25#include <asm/pmac_feature.h>
26#endif
27
28#include "ati_ids.h"
29
30static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
31{
32 u32 tmp;
33
34 /* RV100 */
35 if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
36 if (rinfo->has_CRTC2) {
37 tmp = INPLL(pllSCLK_CNTL);
38 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
39 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
40 OUTPLL(pllSCLK_CNTL, tmp);
41 }
42 tmp = INPLL(pllMCLK_CNTL);
43 tmp |= (MCLK_CNTL__FORCE_MCLKA |
44 MCLK_CNTL__FORCE_MCLKB |
45 MCLK_CNTL__FORCE_YCLKA |
46 MCLK_CNTL__FORCE_YCLKB |
47 MCLK_CNTL__FORCE_AIC |
48 MCLK_CNTL__FORCE_MC);
49 OUTPLL(pllMCLK_CNTL, tmp);
50 return;
51 }
52 /* R100 */
53 if (!rinfo->has_CRTC2) {
54 tmp = INPLL(pllSCLK_CNTL);
55 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP |
56 SCLK_CNTL__FORCE_DISP1 | SCLK_CNTL__FORCE_TOP |
57 SCLK_CNTL__FORCE_E2 | SCLK_CNTL__FORCE_SE |
58 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_VIP |
59 SCLK_CNTL__FORCE_RE | SCLK_CNTL__FORCE_PB |
60 SCLK_CNTL__FORCE_TAM | SCLK_CNTL__FORCE_TDM |
61 SCLK_CNTL__FORCE_RB);
62 OUTPLL(pllSCLK_CNTL, tmp);
63 return;
64 }
65 /* RV350 (M10) */
66 if (rinfo->family == CHIP_FAMILY_RV350) {
67 /* for RV350/M10, no delays are required. */
68 tmp = INPLL(pllSCLK_CNTL2);
69 tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
70 SCLK_CNTL2__R300_FORCE_GA |
71 SCLK_CNTL2__R300_FORCE_CBA);
72 OUTPLL(pllSCLK_CNTL2, tmp);
73
74 tmp = INPLL(pllSCLK_CNTL);
75 tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
76 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
77 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
78 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
79 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
80 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
81 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
82 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
83 OUTPLL(pllSCLK_CNTL, tmp);
84
85 tmp = INPLL(pllSCLK_MORE_CNTL);
86 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI |
87 SCLK_MORE_CNTL__FORCE_MC_HOST);
88 OUTPLL(pllSCLK_MORE_CNTL, tmp);
89
90 tmp = INPLL(pllMCLK_CNTL);
91 tmp |= (MCLK_CNTL__FORCE_MCLKA |
92 MCLK_CNTL__FORCE_MCLKB |
93 MCLK_CNTL__FORCE_YCLKA |
94 MCLK_CNTL__FORCE_YCLKB |
95 MCLK_CNTL__FORCE_MC);
96 OUTPLL(pllMCLK_CNTL, tmp);
97
98 tmp = INPLL(pllVCLK_ECP_CNTL);
99 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
100 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
101 VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
102 OUTPLL(pllVCLK_ECP_CNTL, tmp);
103
104 tmp = INPLL(pllPIXCLKS_CNTL);
105 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
106 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
107 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
108 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
109 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
110 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
111 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
112 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
113 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
114 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
115 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
116 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
117 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
118 PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
119 OUTPLL(pllPIXCLKS_CNTL, tmp);
120
121 return;
122 }
123
124 /* Default */
125
126 /* Force Core Clocks */
127 tmp = INPLL(pllSCLK_CNTL);
128 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
129
130 /* XFree doesn't do that case, but we had this code from Apple and it
131 * seem necessary for proper suspend/resume operations
132 */
133 if (rinfo->is_mobility) {
134 tmp |= SCLK_CNTL__FORCE_HDP|
135 SCLK_CNTL__FORCE_DISP1|
136 SCLK_CNTL__FORCE_DISP2|
137 SCLK_CNTL__FORCE_TOP|
138 SCLK_CNTL__FORCE_SE|
139 SCLK_CNTL__FORCE_IDCT|
140 SCLK_CNTL__FORCE_VIP|
141 SCLK_CNTL__FORCE_PB|
142 SCLK_CNTL__FORCE_RE|
143 SCLK_CNTL__FORCE_TAM|
144 SCLK_CNTL__FORCE_TDM|
145 SCLK_CNTL__FORCE_RB|
146 SCLK_CNTL__FORCE_TV_SCLK|
147 SCLK_CNTL__FORCE_SUBPIC|
148 SCLK_CNTL__FORCE_OV0;
149 }
150 else if (rinfo->family == CHIP_FAMILY_R300 ||
151 rinfo->family == CHIP_FAMILY_R350) {
152 tmp |= SCLK_CNTL__FORCE_HDP |
153 SCLK_CNTL__FORCE_DISP1 |
154 SCLK_CNTL__FORCE_DISP2 |
155 SCLK_CNTL__FORCE_TOP |
156 SCLK_CNTL__FORCE_IDCT |
157 SCLK_CNTL__FORCE_VIP;
158 }
159 OUTPLL(pllSCLK_CNTL, tmp);
160 radeon_msleep(16);
161
162 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
163 tmp = INPLL(pllSCLK_CNTL2);
164 tmp |= SCLK_CNTL2__R300_FORCE_TCL |
165 SCLK_CNTL2__R300_FORCE_GA |
166 SCLK_CNTL2__R300_FORCE_CBA;
167 OUTPLL(pllSCLK_CNTL2, tmp);
168 radeon_msleep(16);
169 }
170
171 tmp = INPLL(pllCLK_PIN_CNTL);
172 tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
173 OUTPLL(pllCLK_PIN_CNTL, tmp);
174 radeon_msleep(15);
175
176 if (rinfo->is_IGP) {
177 /* Weird ... X is _un_ forcing clocks here, I think it's
178 * doing backward. Imitate it for now...
179 */
180 tmp = INPLL(pllMCLK_CNTL);
181 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
182 MCLK_CNTL__FORCE_YCLKA);
183 OUTPLL(pllMCLK_CNTL, tmp);
184 radeon_msleep(16);
185 }
186 /* Hrm... same shit, X doesn't do that but I have to */
187 else if (rinfo->is_mobility) {
188 tmp = INPLL(pllMCLK_CNTL);
189 tmp |= (MCLK_CNTL__FORCE_MCLKA |
190 MCLK_CNTL__FORCE_MCLKB |
191 MCLK_CNTL__FORCE_YCLKA |
192 MCLK_CNTL__FORCE_YCLKB);
193 OUTPLL(pllMCLK_CNTL, tmp);
194 radeon_msleep(16);
195
196 tmp = INPLL(pllMCLK_MISC);
197 tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
198 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
199 MCLK_MISC__MC_MCLK_DYN_ENABLE|
200 MCLK_MISC__IO_MCLK_DYN_ENABLE);
201 OUTPLL(pllMCLK_MISC, tmp);
202 radeon_msleep(15);
203 }
204
205 if (rinfo->is_mobility) {
206 tmp = INPLL(pllSCLK_MORE_CNTL);
207 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS|
208 SCLK_MORE_CNTL__FORCE_MC_GUI|
209 SCLK_MORE_CNTL__FORCE_MC_HOST;
210 OUTPLL(pllSCLK_MORE_CNTL, tmp);
211 radeon_msleep(16);
212 }
213
214 tmp = INPLL(pllPIXCLKS_CNTL);
215 tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
216 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
217 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
218 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
219 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
220 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
221 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
222 OUTPLL(pllPIXCLKS_CNTL, tmp);
223 radeon_msleep(16);
224
225 tmp = INPLL( pllVCLK_ECP_CNTL);
226 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
227 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
228 OUTPLL( pllVCLK_ECP_CNTL, tmp);
229 radeon_msleep(16);
230}
231
232static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
233{
234 u32 tmp;
235
236 /* R100 */
237 if (!rinfo->has_CRTC2) {
238 tmp = INPLL(pllSCLK_CNTL);
239
240 if ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
241 tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB);
242 tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
243 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE |
244 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_RE |
245 SCLK_CNTL__FORCE_PB | SCLK_CNTL__FORCE_TAM |
246 SCLK_CNTL__FORCE_TDM);
247 OUTPLL(pllSCLK_CNTL, tmp);
248 return;
249 }
250
251 /* M10 */
252 if (rinfo->family == CHIP_FAMILY_RV350) {
253 tmp = INPLL(pllSCLK_CNTL2);
254 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
255 SCLK_CNTL2__R300_FORCE_GA |
256 SCLK_CNTL2__R300_FORCE_CBA);
257 tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
258 SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT |
259 SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
260 OUTPLL(pllSCLK_CNTL2, tmp);
261
262 tmp = INPLL(pllSCLK_CNTL);
263 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
264 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
265 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
266 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
267 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
268 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
269 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
270 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
271 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
272 OUTPLL(pllSCLK_CNTL, tmp);
273
274 tmp = INPLL(pllSCLK_MORE_CNTL);
275 tmp &= ~SCLK_MORE_CNTL__FORCEON;
276 tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
277 SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
278 SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
279 OUTPLL(pllSCLK_MORE_CNTL, tmp);
280
281 tmp = INPLL(pllVCLK_ECP_CNTL);
282 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
283 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
284 OUTPLL(pllVCLK_ECP_CNTL, tmp);
285
286 tmp = INPLL(pllPIXCLKS_CNTL);
287 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
288 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
289 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
290 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
291 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
292 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
293 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
294 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
295 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
296 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
297 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
298 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
299 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb);
300 OUTPLL(pllPIXCLKS_CNTL, tmp);
301
302 tmp = INPLL(pllMCLK_MISC);
303 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
304 MCLK_MISC__IO_MCLK_DYN_ENABLE);
305 OUTPLL(pllMCLK_MISC, tmp);
306
307 tmp = INPLL(pllMCLK_CNTL);
308 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
309 tmp &= ~(MCLK_CNTL__FORCE_YCLKA |
310 MCLK_CNTL__FORCE_YCLKB |
311 MCLK_CNTL__FORCE_MC);
312
313 /* Some releases of vbios have set DISABLE_MC_MCLKA
314 * and DISABLE_MC_MCLKB bits in the vbios table. Setting these
315 * bits will cause H/W hang when reading video memory with dynamic
316 * clocking enabled.
317 */
318 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
319 (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
320 /* If both bits are set, then check the active channels */
321 tmp = INPLL(pllMCLK_CNTL);
322 if (rinfo->vram_width == 64) {
323 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
324 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
325 else
326 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
327 } else {
328 tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
329 MCLK_CNTL__R300_DISABLE_MC_MCLKB);
330 }
331 }
332 OUTPLL(pllMCLK_CNTL, tmp);
333 return;
334 }
335
336 /* R300 */
337 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
338 tmp = INPLL(pllSCLK_CNTL);
339 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
340 tmp |= SCLK_CNTL__FORCE_CP;
341 OUTPLL(pllSCLK_CNTL, tmp);
342 radeon_msleep(15);
343
344 tmp = INPLL(pllSCLK_CNTL2);
345 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
346 SCLK_CNTL2__R300_FORCE_GA |
347 SCLK_CNTL2__R300_FORCE_CBA);
348 OUTPLL(pllSCLK_CNTL2, tmp);
349 }
350
351 /* Others */
352
353 tmp = INPLL( pllCLK_PWRMGT_CNTL);
354 tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
355 CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
356 CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
357 tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
358 (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
359 OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
360 radeon_msleep(15);
361
362 tmp = INPLL(pllCLK_PIN_CNTL);
363 tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
364 OUTPLL(pllCLK_PIN_CNTL, tmp);
365 radeon_msleep(15);
366
367 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
368 * to lockup randomly, leave them as set by BIOS.
369 */
370 tmp = INPLL(pllSCLK_CNTL);
371 tmp &= ~SCLK_CNTL__FORCEON_MASK;
372
373 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
374 if ((rinfo->family == CHIP_FAMILY_RV250 &&
375 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
376 ((rinfo->family == CHIP_FAMILY_RV100) &&
377 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
378 tmp |= SCLK_CNTL__FORCE_CP;
379 tmp |= SCLK_CNTL__FORCE_VIP;
380 }
381 OUTPLL(pllSCLK_CNTL, tmp);
382 radeon_msleep(15);
383
384 if ((rinfo->family == CHIP_FAMILY_RV200) ||
385 (rinfo->family == CHIP_FAMILY_RV250) ||
386 (rinfo->family == CHIP_FAMILY_RV280)) {
387 tmp = INPLL(pllSCLK_MORE_CNTL);
388 tmp &= ~SCLK_MORE_CNTL__FORCEON;
389
390 /* RV200::A11 A12 RV250::A11 A12 */
391 if (((rinfo->family == CHIP_FAMILY_RV200) ||
392 (rinfo->family == CHIP_FAMILY_RV250)) &&
393 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
394 tmp |= SCLK_MORE_CNTL__FORCEON;
395
396 OUTPLL(pllSCLK_MORE_CNTL, tmp);
397 radeon_msleep(15);
398 }
399
400
401 /* RV200::A11 A12, RV250::A11 A12 */
402 if (((rinfo->family == CHIP_FAMILY_RV200) ||
403 (rinfo->family == CHIP_FAMILY_RV250)) &&
404 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
405 tmp = INPLL(pllPLL_PWRMGT_CNTL);
406 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
407 OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
408 radeon_msleep(15);
409 }
410
411 tmp = INPLL(pllPIXCLKS_CNTL);
412 tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
413 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
414 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
415 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
416 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
417 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
418 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
419 OUTPLL(pllPIXCLKS_CNTL, tmp);
420 radeon_msleep(15);
421
422 tmp = INPLL(pllVCLK_ECP_CNTL);
423 tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
424 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
425 OUTPLL(pllVCLK_ECP_CNTL, tmp);
426
427 /* X doesn't do that ... hrm, we do on mobility && Macs */
428#ifdef CONFIG_PPC_OF
429 if (rinfo->is_mobility) {
430 tmp = INPLL(pllMCLK_CNTL);
431 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
432 MCLK_CNTL__FORCE_MCLKB |
433 MCLK_CNTL__FORCE_YCLKA |
434 MCLK_CNTL__FORCE_YCLKB);
435 OUTPLL(pllMCLK_CNTL, tmp);
436 radeon_msleep(15);
437
438 tmp = INPLL(pllMCLK_MISC);
439 tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
440 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
441 MCLK_MISC__MC_MCLK_DYN_ENABLE|
442 MCLK_MISC__IO_MCLK_DYN_ENABLE;
443 OUTPLL(pllMCLK_MISC, tmp);
444 radeon_msleep(15);
445 }
446#endif /* CONFIG_PPC_OF */
447}
448
449#ifdef CONFIG_PM
450
451static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
452{
453 OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
454 OUTREG( MC_IND_DATA, value);
455}
456
457static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
458{
459 OUTREG( MC_IND_INDEX, indx);
460 return INREG( MC_IND_DATA);
461}
462
463static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
464{
465 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
466 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
467 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
468 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
469 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
470 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
471 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
472 rinfo->save_regs[7] = INPLL(MCLK_MISC);
473 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
474
475 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
476 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
477 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
478 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
479 rinfo->save_regs[14] = INREG(BUS_CNTL1);
480 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
481 rinfo->save_regs[16] = INREG(AGP_CNTL);
482 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
483 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
484 rinfo->save_regs[19] = INREG(GPIOPAD_A);
485 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
486 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
487 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
488 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
489 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
490 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
491 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
492 rinfo->save_regs[27] = INREG(GPIO_MONID);
493 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
494
495 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
496 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
497 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
498 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
499 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
500
501 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
502 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
503 rinfo->save_regs[36] = INREG(BUS_CNTL);
504 rinfo->save_regs[39] = INREG(RBBM_CNTL);
505 rinfo->save_regs[40] = INREG(DAC_CNTL);
506 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
507 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
508 rinfo->save_regs[38] = INREG(FCP_CNTL);
509
510 if (rinfo->is_mobility) {
511 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
512 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
513 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
514 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
515 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
516 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
517 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
518 }
519
520 if (rinfo->family >= CHIP_FAMILY_RV200) {
521 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
522 rinfo->save_regs[46] = INREG(MC_CNTL);
523 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
524 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
525 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
526 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
527 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
528 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
529 rinfo->save_regs[53] = INREG(MC_DEBUG);
530 }
531 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
532 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
533 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
534 rinfo->save_regs[57] = INREG(FW_CNTL);
535
536 if (rinfo->family >= CHIP_FAMILY_R300) {
537 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
538 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
539 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
540 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
541 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
542 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
543 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
544 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
545 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
546 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
547 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
548 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
549 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
550 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
551 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
552 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
553 } else {
554 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
555 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
556 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
557 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
558 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
559 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
560 }
561
562 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
563 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
564 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
565 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
566 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
567 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
568 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
569
570 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
571 rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
572 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
573 rinfo->save_regs[84] = INREG(TMDS_CNTL);
574 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
575 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
576 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
577 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
578 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
579 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
580 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
581 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
582 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
583 rinfo->save_regs[96] = INREG(HDP_DEBUG);
584 rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
585 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
586 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
587}
588
589static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
590{
591 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
592
593 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
594 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
595 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
596 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
597 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
598 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
599 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
600 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
601 if (rinfo->family == CHIP_FAMILY_RV350)
602 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
603
604 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
605 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
606 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
607 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
608 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
609 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
610
611 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
612 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
613 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
614 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
615 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
616 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
617 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
618 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
619 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
620 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
621 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
622
623 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
624 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
625 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
626 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
627 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
628 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
629 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
630 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
631 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
632 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
633}
634
635static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
636{
637 OUTREG(GPIOPAD_MASK, 0x0001ffff);
638 OUTREG(GPIOPAD_EN, 0x00000400);
639 OUTREG(GPIOPAD_A, 0x00000000);
640 OUTREG(ZV_LCDPAD_MASK, 0x00000000);
641 OUTREG(ZV_LCDPAD_EN, 0x00000000);
642 OUTREG(ZV_LCDPAD_A, 0x00000000);
643 OUTREG(GPIO_VGA_DDC, 0x00030000);
644 OUTREG(GPIO_DVI_DDC, 0x00000000);
645 OUTREG(GPIO_MONID, 0x00030000);
646 OUTREG(GPIO_CRT2_DDC, 0x00000000);
647}
648
649static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
650{
651 /* Set v2clk to 65MHz */
652 if (rinfo->family <= CHIP_FAMILY_RV280) {
653 OUTPLL(pllPIXCLKS_CNTL,
654 __INPLL(rinfo, pllPIXCLKS_CNTL)
655 & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
656
657 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
658 OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
659 } else {
660 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
661 INPLL(pllP2PLL_REF_DIV);
662 OUTPLL(pllP2PLL_CNTL, 0x0000a700);
663 }
664
665 OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
666
667 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
668 mdelay(1);
669
670 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
671 mdelay( 1);
672
673 OUTPLL(pllPIXCLKS_CNTL,
674 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
675 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
676 mdelay( 1);
677}
678
679static void radeon_pm_low_current(struct radeonfb_info *rinfo)
680{
681 u32 reg;
682
683 reg = INREG(BUS_CNTL1);
684 if (rinfo->family <= CHIP_FAMILY_RV280) {
685 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
686 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
687 } else {
688 reg |= 0x4080;
689 }
690 OUTREG(BUS_CNTL1, reg);
691
692 reg = INPLL(PLL_PWRMGT_CNTL);
693 reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
694 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
695 reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
696 reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
697 OUTPLL(PLL_PWRMGT_CNTL, reg);
698
699 reg = INREG(TV_DAC_CNTL);
700 reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
701 reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
702 TV_DAC_CNTL_BDACPD |
703 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
704 OUTREG(TV_DAC_CNTL, reg);
705
706 reg = INREG(TMDS_TRANSMITTER_CNTL);
707 reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
708 OUTREG(TMDS_TRANSMITTER_CNTL, reg);
709
710 reg = INREG(DAC_CNTL);
711 reg &= ~DAC_CMP_EN;
712 OUTREG(DAC_CNTL, reg);
713
714 reg = INREG(DAC_CNTL2);
715 reg &= ~DAC2_CMP_EN;
716 OUTREG(DAC_CNTL2, reg);
717
718 reg = INREG(TV_DAC_CNTL);
719 reg &= ~TV_DAC_CNTL_DETECT;
720 OUTREG(TV_DAC_CNTL, reg);
721}
722
723static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
724{
725
726 u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
727
728 u32 pll_pwrmgt_cntl;
729 u32 clk_pwrmgt_cntl;
730 u32 clk_pin_cntl;
731 u32 vclk_ecp_cntl;
732 u32 pixclks_cntl;
733 u32 disp_mis_cntl;
734 u32 disp_pwr_man;
735 u32 tmp;
736
737 /* Force Core Clocks */
738 sclk_cntl = INPLL( pllSCLK_CNTL);
739 sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
740 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
741 SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
742 SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
743 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
744 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
745 SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
746
747 SCLK_CNTL__FORCE_DISP2|
748 SCLK_CNTL__FORCE_CP|
749 SCLK_CNTL__FORCE_HDP|
750 SCLK_CNTL__FORCE_DISP1|
751 SCLK_CNTL__FORCE_TOP|
752 SCLK_CNTL__FORCE_E2|
753 SCLK_CNTL__FORCE_SE|
754 SCLK_CNTL__FORCE_IDCT|
755 SCLK_CNTL__FORCE_VIP|
756
757 SCLK_CNTL__FORCE_PB|
758 SCLK_CNTL__FORCE_TAM|
759 SCLK_CNTL__FORCE_TDM|
760 SCLK_CNTL__FORCE_RB|
761 SCLK_CNTL__FORCE_TV_SCLK|
762 SCLK_CNTL__FORCE_SUBPIC|
763 SCLK_CNTL__FORCE_OV0;
764 if (rinfo->family <= CHIP_FAMILY_RV280)
765 sclk_cntl |= SCLK_CNTL__FORCE_RE;
766 else
767 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
768 SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
769 SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
770 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
771 SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
772
773 OUTPLL( pllSCLK_CNTL, sclk_cntl);
774
775 sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
776 sclk_more_cntl |= SCLK_MORE_CNTL__FORCE_DISPREGS |
777 SCLK_MORE_CNTL__FORCE_MC_GUI |
778 SCLK_MORE_CNTL__FORCE_MC_HOST;
779
780 OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
781
782
783 mclk_cntl = INPLL( pllMCLK_CNTL);
784 mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
785 MCLK_CNTL__FORCE_MCLKB |
786 MCLK_CNTL__FORCE_YCLKA |
787 MCLK_CNTL__FORCE_YCLKB |
788 MCLK_CNTL__FORCE_MC
789 );
790 OUTPLL( pllMCLK_CNTL, mclk_cntl);
791
792 /* Force Display clocks */
793 vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
794 vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
795 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
796 vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
797 OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
798
799
800 pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
801 pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
802 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
803 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
804 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
805 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
806 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
807 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
808
809 OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
810
811 /* Switch off LVDS interface */
812 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
813 ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
814
815 /* Enable System power management */
816 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
817
818 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF |
819 PLL_PWRMGT_CNTL__MPLL_TURNOFF|
820 PLL_PWRMGT_CNTL__PPLL_TURNOFF|
821 PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
822 PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
823
824 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
825
826 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
827
828 clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
829 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
830 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
831 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
832 CLK_PWRMGT_CNTL__MCLK_TURNOFF|
833 CLK_PWRMGT_CNTL__SCLK_TURNOFF|
834 CLK_PWRMGT_CNTL__PCLK_TURNOFF|
835 CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
836 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
837 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
838 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
839 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
840 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
841 );
842
843 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
844 | CLK_PWRMGT_CNTL__DISP_PM;
845
846 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
847
848 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
849
850 clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
851
852 /* because both INPLL and OUTPLL take the same lock, that's why. */
853 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
854 OUTPLL( pllMCLK_MISC, tmp);
855
856 /* AGP PLL control */
857 if (rinfo->family <= CHIP_FAMILY_RV280) {
858 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID);
859
860 OUTREG(BUS_CNTL1,
861 (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
862 | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX
863 } else {
864 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
865 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
866 }
867
868 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
869 & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
870
871 clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
872 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
873 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
874
875 /* Solano2M */
876 OUTREG(AGP_CNTL,
877 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
878 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
879
880 /* ACPI mode */
881 /* because both INPLL and OUTPLL take the same lock, that's why. */
882 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
883 OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
884
885
886 disp_mis_cntl = INREG(DISP_MISC_CNTL);
887
888 disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
889 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
890 DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
891 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
892 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
893 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
894 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
895 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
896 DISP_MISC_CNTL__SOFT_RESET_LVDS|
897 DISP_MISC_CNTL__SOFT_RESET_TMDS|
898 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
899 DISP_MISC_CNTL__SOFT_RESET_TV);
900
901 OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
902
903 disp_pwr_man = INREG(DISP_PWR_MAN);
904
905 disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN |
906 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
907 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
908 DISP_PWR_MAN__DISP_D3_RST|
909 DISP_PWR_MAN__DISP_D3_REG_RST
910 );
911
912 disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
913 DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
914 DISP_PWR_MAN__DISP_D3_OV0_RST|
915 DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
916 DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
917 DISP_PWR_MAN__DISP_D1D2_OV0_RST|
918 DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
919 DISP_PWR_MAN__TV_ENABLE_RST|
920// DISP_PWR_MAN__AUTO_PWRUP_EN|
921 0;
922
923 OUTREG(DISP_PWR_MAN, disp_pwr_man);
924
925 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
926 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
927 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
928 disp_pwr_man = INREG(DISP_PWR_MAN);
929
930
931 /* D2 */
932 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
933 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
934 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
935 disp_pwr_man &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
936 | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
937
938 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
939 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
940 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
941 OUTREG(DISP_PWR_MAN, disp_pwr_man);
942
943 /* disable display request & disable display */
944 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
945 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
946 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
947 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
948
949 mdelay(17);
950
951}
952
953static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
954{
955 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
956
957 mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
958 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
959 mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
960 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
961
962 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
963 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
964 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
965 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
966
967 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
968 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
969
970 mdelay( 1);
971}
972
973static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
974{
975 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
976
977 mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
978 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
979 mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
980 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
981
982 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
983 mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
984 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
985 mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
986
987 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
988 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
989
990 mdelay( 1);
991}
992
993static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
994 u8 delay_required)
995{
996 u32 mem_sdram_mode;
997
998 mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG);
999
1000 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1001 mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1002 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1003 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1004 if (delay_required >= 2)
1005 mdelay(1);
1006
1007 mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1008 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1009 if (delay_required >= 2)
1010 mdelay(1);
1011
1012 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1013 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1014 if (delay_required >= 2)
1015 mdelay(1);
1016
1017 if (delay_required) {
1018 do {
1019 if (delay_required >= 2)
1020 mdelay(1);
1021 } while ((INREG(MC_STATUS)
1022 & (MC_STATUS__MEM_PWRUP_COMPL_A |
1023 MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1024 }
1025}
1026
1027static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1028{
1029 int cnt;
1030
1031 for (cnt = 0; cnt < 100; ++cnt) {
1032 mdelay(1);
1033 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1034 | MC_STATUS__MEM_PWRUP_COMPL_B))
1035 break;
1036 }
1037}
1038
1039
1040static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1041{
1042#define DLL_RESET_DELAY 5
1043#define DLL_SLEEP_DELAY 1
1044
1045 u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP
1046 | MDLL_CKO__MCKOA_RESET;
1047 u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1048 | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1049 | MDLL_RDCKA__MRDCKA1_RESET;
1050 u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1051 | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1052 | MDLL_RDCKB__MRDCKB1_RESET;
1053
1054 /* Setting up the DLL range for write */
1055 OUTPLL(pllMDLL_CKO, cko);
1056 OUTPLL(pllMDLL_RDCKA, cka);
1057 OUTPLL(pllMDLL_RDCKB, ckb);
1058
1059 mdelay(DLL_RESET_DELAY*2);
1060
1061 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1062 OUTPLL(pllMDLL_CKO, cko);
1063 mdelay(DLL_SLEEP_DELAY);
1064 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1065 OUTPLL(pllMDLL_CKO, cko);
1066 mdelay(DLL_RESET_DELAY);
1067
1068 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1069 OUTPLL(pllMDLL_RDCKA, cka);
1070 mdelay(DLL_SLEEP_DELAY);
1071 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1072 OUTPLL(pllMDLL_RDCKA, cka);
1073 mdelay(DLL_RESET_DELAY);
1074
1075 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1076 OUTPLL(pllMDLL_RDCKB, ckb);
1077 mdelay(DLL_SLEEP_DELAY);
1078 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1079 OUTPLL(pllMDLL_RDCKB, ckb);
1080 mdelay(DLL_RESET_DELAY);
1081
1082
1083#undef DLL_RESET_DELAY
1084#undef DLL_SLEEP_DELAY
1085}
1086
1087static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1088{
1089 u32 dll_value;
1090 u32 dll_sleep_mask = 0;
1091 u32 dll_reset_mask = 0;
1092 u32 mc;
1093
1094#define DLL_RESET_DELAY 5
1095#define DLL_SLEEP_DELAY 1
1096
1097 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1098 mc = INREG(MC_CNTL);
1099 /* Check which channels are enabled */
1100 switch (mc & 0x3) {
1101 case 1:
1102 if (mc & 0x4)
1103 break;
1104 case 2:
1105 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1106 dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1107 case 0:
1108 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1109 dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1110 }
1111 switch (mc & 0x3) {
1112 case 1:
1113 if (!(mc & 0x4))
1114 break;
1115 case 2:
1116 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1117 dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1118 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1119 dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1120 }
1121
1122 dll_value = INPLL(pllMDLL_RDCKA);
1123
1124 /* Power Up */
1125 dll_value &= ~(dll_sleep_mask);
1126 OUTPLL(pllMDLL_RDCKA, dll_value);
1127 mdelay( DLL_SLEEP_DELAY);
1128
1129 dll_value &= ~(dll_reset_mask);
1130 OUTPLL(pllMDLL_RDCKA, dll_value);
1131 mdelay( DLL_RESET_DELAY);
1132
1133#undef DLL_RESET_DELAY
1134#undef DLL_SLEEP_DELAY
1135}
1136
1137
1138static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1139{
1140 u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1141 fp_gen_cntl, fp2_gen_cntl;
1142
1143 crtcGenCntl = INREG( CRTC_GEN_CNTL);
1144 crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1145
1146 crtc_more_cntl = INREG( CRTC_MORE_CNTL);
1147 fp_gen_cntl = INREG( FP_GEN_CNTL);
1148 fp2_gen_cntl = INREG( FP2_GEN_CNTL);
1149
1150
1151 OUTREG( CRTC_MORE_CNTL, 0);
1152 OUTREG( FP_GEN_CNTL, 0);
1153 OUTREG( FP2_GEN_CNTL,0);
1154
1155 OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1156 OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1157
1158 /* This is the code for the Aluminium PowerBooks M10 */
1159 if (rinfo->family == CHIP_FAMILY_RV350) {
1160 u32 sdram_mode_reg = rinfo->save_regs[35];
1161 static u32 default_mrtable[] =
1162 { 0x21320032,
1163 0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1164 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1165 0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1166 0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1167 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1168 0x31320032 };
1169
1170 u32 *mrtable = default_mrtable;
1171 int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1172
1173 mdelay(30);
1174
1175 /* Disable refresh */
1176 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1177 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1178 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1179 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1180
1181 /* Configure and enable M & SPLLs */
1182 radeon_pm_enable_dll_m10(rinfo);
1183 radeon_pm_yclk_mclk_sync_m10(rinfo);
1184
1185#ifdef CONFIG_PPC_OF
1186 if (rinfo->of_node != NULL) {
1187 int size;
1188
1189 mrtable = (u32 *)get_property(rinfo->of_node, "ATY,MRT", &size);
1190 if (mrtable)
1191 mrtable_size = size >> 2;
1192 else
1193 mrtable = default_mrtable;
1194 }
1195#endif /* CONFIG_PPC_OF */
1196
1197 /* Program the SDRAM */
1198 sdram_mode_reg = mrtable[0];
1199 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1200 for (i = 0; i < mrtable_size; i++) {
1201 if (mrtable[i] == 0xffffffffu)
1202 radeon_pm_m10_program_mode_wait(rinfo);
1203 else {
1204 sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1205 | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1206 | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1207 sdram_mode_reg |= mrtable[i];
1208
1209 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1210 mdelay(1);
1211 }
1212 }
1213
1214 /* Restore memory refresh */
1215 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1216 mdelay(30);
1217
1218 }
1219 /* Here come the desktop RV200 "QW" card */
1220 else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1221 /* Disable refresh */
1222 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1223 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1224 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1225 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1226 mdelay(30);
1227
1228 /* Reset memory */
1229 OUTREG(MEM_SDRAM_MODE_REG,
1230 INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1231
1232 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1233 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1234 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1235
1236 OUTREG(MEM_SDRAM_MODE_REG,
1237 INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1238
1239 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1240
1241 }
1242 /* The M6 */
1243 else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1244 /* Disable refresh */
1245 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1246 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1247
1248 /* Reset memory */
1249 OUTREG( MEM_SDRAM_MODE_REG,
1250 INREG( MEM_SDRAM_MODE_REG)
1251 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1252
1253 /* DLL */
1254 radeon_pm_enable_dll(rinfo);
1255
1256 /* MLCK / YCLK sync */
1257 radeon_pm_yclk_mclk_sync(rinfo);
1258
1259 /* Program Mode Register */
1260 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1261 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1262 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1263 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1264 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1265
1266 /* Complete & re-enable refresh */
1267 OUTREG( MEM_SDRAM_MODE_REG,
1268 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1269
1270 OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1271 }
1272 /* And finally, the M7..M9 models, including M9+ (RV280) */
1273 else if (rinfo->is_mobility) {
1274
1275 /* Disable refresh */
1276 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1277 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1278 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1279 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1280
1281 /* Reset memory */
1282 OUTREG( MEM_SDRAM_MODE_REG,
1283 INREG( MEM_SDRAM_MODE_REG)
1284 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1285
1286 /* DLL */
1287 radeon_pm_enable_dll(rinfo);
1288
1289 /* MLCK / YCLK sync */
1290 radeon_pm_yclk_mclk_sync(rinfo);
1291
1292 /* M6, M7 and M9 so far ... */
1293 if (rinfo->family <= CHIP_FAMILY_RV250) {
1294 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1295 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1296 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1297 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1298 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1299 }
1300 /* M9+ (iBook G4) */
1301 else if (rinfo->family == CHIP_FAMILY_RV280) {
1302 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1303 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1304 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1305 }
1306
1307 /* Complete & re-enable refresh */
1308 OUTREG( MEM_SDRAM_MODE_REG,
1309 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1310
1311 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1312 }
1313
1314 OUTREG( CRTC_GEN_CNTL, crtcGenCntl);
1315 OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2);
1316 OUTREG( FP_GEN_CNTL, fp_gen_cntl);
1317 OUTREG( FP2_GEN_CNTL, fp2_gen_cntl);
1318
1319 OUTREG( CRTC_MORE_CNTL, crtc_more_cntl);
1320
1321 mdelay( 15);
1322}
1323
1324#ifdef CONFIG_PPC_OF
1325
1326static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1327{
1328 u32 tmp, tmp2;
1329 int i,j;
1330
1331 /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1332 INREG(PAD_CTLR_STRENGTH);
1333 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1334 tmp = INREG(PAD_CTLR_STRENGTH);
1335 for (i = j = 0; i < 65; ++i) {
1336 mdelay(1);
1337 tmp2 = INREG(PAD_CTLR_STRENGTH);
1338 if (tmp != tmp2) {
1339 tmp = tmp2;
1340 i = 0;
1341 j++;
1342 if (j > 10) {
1343 printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1344 "stabilize !\n");
1345 break;
1346 }
1347 }
1348 }
1349}
1350
1351static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1352{
1353 u32 tmp;
1354
1355 tmp = INPLL(pllPPLL_CNTL);
1356 OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1357 tmp = INPLL(pllP2PLL_CNTL);
1358 OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1359 tmp = INPLL(pllSPLL_CNTL);
1360 OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1361 tmp = INPLL(pllMPLL_CNTL);
1362 OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1363}
1364
1365static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1366{
1367 u32 tmp;
1368
1369 /* Switch SPLL to PCI source */
1370 tmp = INPLL(pllSCLK_CNTL);
1371 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1372
1373 /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1374 tmp = INPLL(pllSPLL_CNTL);
1375 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1376 radeon_pll_errata_after_index(rinfo);
1377 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1378 radeon_pll_errata_after_data(rinfo);
1379
1380 /* Set SPLL feedback divider */
1381 tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1382 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1383 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1384
1385 /* Power up SPLL */
1386 tmp = INPLL(pllSPLL_CNTL);
1387 OUTPLL(pllSPLL_CNTL, tmp & ~1);
1388 (void)INPLL(pllSPLL_CNTL);
1389
1390 mdelay(10);
1391
1392 /* Release SPLL reset */
1393 tmp = INPLL(pllSPLL_CNTL);
1394 OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1395 (void)INPLL(pllSPLL_CNTL);
1396
1397 mdelay(10);
1398
1399 /* Select SCLK source */
1400 tmp = INPLL(pllSCLK_CNTL);
1401 tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1402 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1403 OUTPLL(pllSCLK_CNTL, tmp);
1404 (void)INPLL(pllSCLK_CNTL);
1405
1406 mdelay(10);
1407
1408 /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1409 tmp = INPLL(pllMPLL_CNTL);
1410 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1411 radeon_pll_errata_after_index(rinfo);
1412 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1413 radeon_pll_errata_after_data(rinfo);
1414
1415 /* Set MPLL feedback divider */
1416 tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1417 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1418
1419 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1420 /* Power up MPLL */
1421 tmp = INPLL(pllMPLL_CNTL);
1422 OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1423 (void)INPLL(pllMPLL_CNTL);
1424
1425 mdelay(10);
1426
1427 /* Un-reset MPLL */
1428 tmp = INPLL(pllMPLL_CNTL);
1429 OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1430 (void)INPLL(pllMPLL_CNTL);
1431
1432 mdelay(10);
1433
1434 /* Select source for MCLK */
1435 tmp = INPLL(pllMCLK_CNTL);
1436 tmp |= rinfo->save_regs[2] & 0xffff;
1437 OUTPLL(pllMCLK_CNTL, tmp);
1438 (void)INPLL(pllMCLK_CNTL);
1439
1440 mdelay(10);
1441}
1442
1443static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1444{
1445 u32 r2ec;
1446
1447 /* GACK ! I though we didn't have a DDA on Radeon's anymore
1448 * here we rewrite with the same value, ... I suppose we clear
1449 * some bits that are already clear ? Or maybe this 0x2ec
1450 * register is something new ?
1451 */
1452 mdelay(20);
1453 r2ec = INREG(VGA_DDA_ON_OFF);
1454 OUTREG(VGA_DDA_ON_OFF, r2ec);
1455 mdelay(1);
1456
1457 /* Spread spectrum PLLL off */
1458 OUTPLL(pllSSPLL_CNTL, 0xbf03);
1459
1460 /* Spread spectrum disabled */
1461 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1462
1463 /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1464 * value, not sure what for...
1465 */
1466
1467 r2ec |= 0x3f0;
1468 OUTREG(VGA_DDA_ON_OFF, r2ec);
1469 mdelay(1);
1470}
1471
1472static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1473{
1474 u32 r2ec, tmp;
1475
1476 /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1477 * here we rewrite with the same value, ... I suppose we clear/set
1478 * some bits that are already clear/set ?
1479 */
1480 r2ec = INREG(VGA_DDA_ON_OFF);
1481 OUTREG(VGA_DDA_ON_OFF, r2ec);
1482 mdelay(1);
1483
1484 /* Enable spread spectrum */
1485 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1486 mdelay(3);
1487
1488 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1489 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1490 tmp = INPLL(pllSSPLL_CNTL);
1491 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1492 mdelay(6);
1493 tmp = INPLL(pllSSPLL_CNTL);
1494 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1495 mdelay(5);
1496
1497 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1498
1499 r2ec |= 8;
1500 OUTREG(VGA_DDA_ON_OFF, r2ec);
1501 mdelay(20);
1502
1503 /* Enable LVDS interface */
1504 tmp = INREG(LVDS_GEN_CNTL);
1505 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1506
1507 /* Enable LVDS_PLL */
1508 tmp = INREG(LVDS_PLL_CNTL);
1509 tmp &= ~0x30000;
1510 tmp |= 0x10000;
1511 OUTREG(LVDS_PLL_CNTL, tmp);
1512
1513 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1514 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1515
1516 /* The trace reads that one here, waiting for something to settle down ? */
1517 INREG(RBBM_STATUS);
1518
1519 /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1520 * R300 register spec at least...
1521 */
1522 tmp = INPLL(pllSS_TST_CNTL);
1523 tmp |= 0x00400000;
1524 OUTPLL(pllSS_TST_CNTL, tmp);
1525}
1526
1527static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1528{
1529 u32 tmp;
1530
1531 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1532 radeon_pll_errata_after_index(rinfo);
1533 OUTREG8(CLOCK_CNTL_DATA, 0);
1534 radeon_pll_errata_after_data(rinfo);
1535
1536 tmp = INPLL(pllVCLK_ECP_CNTL);
1537 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1538 mdelay(5);
1539
1540 tmp = INPLL(pllPPLL_REF_DIV);
1541 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1542 OUTPLL(pllPPLL_REF_DIV, tmp);
1543 INPLL(pllPPLL_REF_DIV);
1544
1545 /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1546 * probably useless since we already did it ...
1547 */
1548 tmp = INPLL(pllPPLL_CNTL);
1549 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1550 radeon_pll_errata_after_index(rinfo);
1551 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1552 radeon_pll_errata_after_data(rinfo);
1553
1554 /* Restore our "reference" PPLL divider set by firmware
1555 * according to proper spread spectrum calculations
1556 */
1557 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1558
1559 tmp = INPLL(pllPPLL_CNTL);
1560 OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1561 mdelay(5);
1562
1563 tmp = INPLL(pllPPLL_CNTL);
1564 OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1565 mdelay(5);
1566
1567 tmp = INPLL(pllVCLK_ECP_CNTL);
1568 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1569 mdelay(5);
1570
1571 tmp = INPLL(pllVCLK_ECP_CNTL);
1572 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1573 mdelay(5);
1574
1575 /* Switch pixel clock to firmware default div 0 */
1576 OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1577 radeon_pll_errata_after_index(rinfo);
1578 radeon_pll_errata_after_data(rinfo);
1579}
1580
1581static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1582{
1583 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1584 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1585 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1586 OUTREG(MEM_SDRAM_MODE_REG,
1587 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1588 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1589 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1590 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1591 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1592 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1593 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1594
1595 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1596 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1597 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1598 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1599 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1600 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1601 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1602 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1603 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1604 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1605 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1606 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1607 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1608 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1609 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1610 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1611 OUTREG(MC_IND_INDEX, 0);
1612}
1613
1614static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1615{
1616 u32 tmp, i;
1617
1618 /* Restore a bunch of registers first */
1619 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1620 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1621 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1622 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1623 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1624 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1625 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1626 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1627 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1628 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1629 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1630 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1631 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1632 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1633
1634 /* Hrm... */
1635 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1636
1637 /* Reset the PAD CTLR */
1638 radeon_pm_reset_pad_ctlr_strength(rinfo);
1639
1640 /* Some PLLs are Read & written identically in the trace here...
1641 * I suppose it's actually to switch them all off & reset,
1642 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1643 */
1644 radeon_pm_all_ppls_off(rinfo);
1645
1646 /* Clear tiling, reset swappers */
1647 INREG(SURFACE_CNTL);
1648 OUTREG(SURFACE_CNTL, 0);
1649
1650 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1651 * rather than hard coding...
1652 */
1653 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1654 tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1655 OUTREG(TV_DAC_CNTL, tmp);
1656
1657 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1658 tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1659 OUTREG(TV_DAC_CNTL, tmp);
1660
1661 /* More registers restored */
1662 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1663 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1664 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1665
1666 /* Hrmmm ... What is that ? */
1667 tmp = rinfo->save_regs[1]
1668 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1669 CLK_PWRMGT_CNTL__MC_BUSY);
1670 OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1671
1672 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1673 OUTREG(FW_CNTL, rinfo->save_regs[57]);
1674 OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1675 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1676 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1677 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1678
1679 /* Restore Memory Controller configuration */
1680 radeon_pm_m10_reconfigure_mc(rinfo);
1681
1682 /* Make sure CRTC's dont touch memory */
1683 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1684 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1685 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1686 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1687 mdelay(30);
1688
1689 /* Disable SDRAM refresh */
1690 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1691 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1692
1693 /* Restore XTALIN routing (CLK_PIN_CNTL) */
1694 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1695
1696 /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1697 tmp = rinfo->save_regs[2] & 0xff000000;
1698 tmp |= MCLK_CNTL__FORCE_MCLKA |
1699 MCLK_CNTL__FORCE_MCLKB |
1700 MCLK_CNTL__FORCE_YCLKA |
1701 MCLK_CNTL__FORCE_YCLKB |
1702 MCLK_CNTL__FORCE_MC;
1703 OUTPLL(pllMCLK_CNTL, tmp);
1704
1705 /* Force all clocks on in SCLK */
1706 tmp = INPLL(pllSCLK_CNTL);
1707 tmp |= SCLK_CNTL__FORCE_DISP2|
1708 SCLK_CNTL__FORCE_CP|
1709 SCLK_CNTL__FORCE_HDP|
1710 SCLK_CNTL__FORCE_DISP1|
1711 SCLK_CNTL__FORCE_TOP|
1712 SCLK_CNTL__FORCE_E2|
1713 SCLK_CNTL__FORCE_SE|
1714 SCLK_CNTL__FORCE_IDCT|
1715 SCLK_CNTL__FORCE_VIP|
1716 SCLK_CNTL__FORCE_PB|
1717 SCLK_CNTL__FORCE_TAM|
1718 SCLK_CNTL__FORCE_TDM|
1719 SCLK_CNTL__FORCE_RB|
1720 SCLK_CNTL__FORCE_TV_SCLK|
1721 SCLK_CNTL__FORCE_SUBPIC|
1722 SCLK_CNTL__FORCE_OV0;
1723 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT |
1724 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1725 SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
1726 SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
1727 SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
1728 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1729 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1730 SCLK_CNTL__RE_MAX_DYN_STOP_LAT |
1731 SCLK_CNTL__PB_MAX_DYN_STOP_LAT |
1732 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1733 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1734 SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1735 OUTPLL(pllSCLK_CNTL, tmp);
1736
1737 OUTPLL(pllVCLK_ECP_CNTL, 0);
1738 OUTPLL(pllPIXCLKS_CNTL, 0);
1739 OUTPLL(pllMCLK_MISC,
1740 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1741 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1742
1743 mdelay(5);
1744
1745 /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1746 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1747 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1748 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1749
1750 /* Now restore the major PLLs settings, keeping them off & reset though */
1751 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1752 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1753 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1754 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1755
1756 /* Restore MC DLL state and switch it off/reset too */
1757 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1758
1759 /* Switch MDLL off & reset */
1760 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1761 mdelay(5);
1762
1763 /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1764 * 0xa1100007... and MacOS writes 0xa1000007 ..
1765 */
1766 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1767
1768 /* Restore more stuffs */
1769 OUTPLL(pllHTOTAL_CNTL, 0);
1770 OUTPLL(pllHTOTAL2_CNTL, 0);
1771
1772 /* More PLL initial configuration */
1773 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
1774 OUTPLL(pllSCLK_CNTL2, tmp);
1775
1776 tmp = INPLL(pllSCLK_MORE_CNTL);
1777 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */
1778 SCLK_MORE_CNTL__FORCE_MC_GUI |
1779 SCLK_MORE_CNTL__FORCE_MC_HOST;
1780 OUTPLL(pllSCLK_MORE_CNTL, tmp);
1781
1782 /* Now we actually start MCLK and SCLK */
1783 radeon_pm_start_mclk_sclk(rinfo);
1784
1785 /* Full reset sdrams, this also re-inits the MDLL */
1786 radeon_pm_full_reset_sdram(rinfo);
1787
1788 /* Fill palettes */
1789 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
1790 for (i=0; i<256; i++)
1791 OUTREG(PALETTE_30_DATA, 0x15555555);
1792 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
1793 udelay(20);
1794 for (i=0; i<256; i++)
1795 OUTREG(PALETTE_30_DATA, 0x15555555);
1796
1797 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
1798 mdelay(3);
1799
1800 /* Restore TMDS */
1801 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1802 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1803
1804 /* Set LVDS registers but keep interface & pll down */
1805 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1806 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
1807 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1808
1809 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1810
1811 /* Restore GPIOPAD state */
1812 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1813 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1814 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1815
1816 /* write some stuff to the framebuffer... */
1817 for (i = 0; i < 0x8000; ++i)
1818 writeb(0, rinfo->fb_base + i);
1819
1820 mdelay(40);
1821 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
1822 mdelay(40);
1823
1824 /* Restore a few more things */
1825 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1826 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1827
1828 /* Take care of spread spectrum & PPLLs now */
1829 radeon_pm_m10_disable_spread_spectrum(rinfo);
1830 radeon_pm_restore_pixel_pll(rinfo);
1831
1832 /* GRRRR... I can't figure out the proper LVDS power sequence, and the
1833 * code I have for blank/unblank doesn't quite work on some laptop models
1834 * it seems ... Hrm. What I have here works most of the time ...
1835 */
1836 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1837}
1838
1839static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1840{
1841 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1842 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1843 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1844 OUTREG(MEM_SDRAM_MODE_REG,
1845 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1846 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1847 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1848 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1849 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1850 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1851 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1852
1853 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1854 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1855 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1856 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1857 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1858 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1859 OUTREG(MC_IND_INDEX, 0);
1860 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1861
1862 mdelay(20);
1863}
1864
1865static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1866{
1867 u32 tmp, i;
1868
1869 /* Restore a bunch of registers first */
1870 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1871 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1872 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1873 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1874 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1875 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1876 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1877 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1878 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1879 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1880 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1881
1882 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1883 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1884
1885 /* Reset the PAD CTLR */
1886 radeon_pm_reset_pad_ctlr_strength(rinfo);
1887
1888 /* Some PLLs are Read & written identically in the trace here...
1889 * I suppose it's actually to switch them all off & reset,
1890 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1891 */
1892 radeon_pm_all_ppls_off(rinfo);
1893
1894 /* Clear tiling, reset swappers */
1895 INREG(SURFACE_CNTL);
1896 OUTREG(SURFACE_CNTL, 0);
1897
1898 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1899 * rather than hard coding...
1900 */
1901 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1902 tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
1903 OUTREG(TV_DAC_CNTL, tmp);
1904
1905 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1906 tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
1907 OUTREG(TV_DAC_CNTL, tmp);
1908
1909 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
1910
1911 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1912 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1913 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1914
1915 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1916 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
1917 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1918
1919 tmp = rinfo->save_regs[1]
1920 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1921 CLK_PWRMGT_CNTL__MC_BUSY);
1922 OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1923
1924 OUTREG(FW_CNTL, rinfo->save_regs[57]);
1925
1926 /* Disable SDRAM refresh */
1927 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1928 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1929
1930 /* Restore XTALIN routing (CLK_PIN_CNTL) */
1931 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1932
1933 /* Force MCLK to be PCI sourced and forced ON */
1934 tmp = rinfo->save_regs[2] & 0xff000000;
1935 tmp |= MCLK_CNTL__FORCE_MCLKA |
1936 MCLK_CNTL__FORCE_MCLKB |
1937 MCLK_CNTL__FORCE_YCLKA |
1938 MCLK_CNTL__FORCE_YCLKB |
1939 MCLK_CNTL__FORCE_MC |
1940 MCLK_CNTL__FORCE_AIC;
1941 OUTPLL(pllMCLK_CNTL, tmp);
1942
1943 /* Force SCLK to be PCI sourced with a bunch forced */
1944 tmp = 0 |
1945 SCLK_CNTL__FORCE_DISP2|
1946 SCLK_CNTL__FORCE_CP|
1947 SCLK_CNTL__FORCE_HDP|
1948 SCLK_CNTL__FORCE_DISP1|
1949 SCLK_CNTL__FORCE_TOP|
1950 SCLK_CNTL__FORCE_E2|
1951 SCLK_CNTL__FORCE_SE|
1952 SCLK_CNTL__FORCE_IDCT|
1953 SCLK_CNTL__FORCE_VIP|
1954 SCLK_CNTL__FORCE_RE|
1955 SCLK_CNTL__FORCE_PB|
1956 SCLK_CNTL__FORCE_TAM|
1957 SCLK_CNTL__FORCE_TDM|
1958 SCLK_CNTL__FORCE_RB;
1959 OUTPLL(pllSCLK_CNTL, tmp);
1960
1961 /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */
1962 OUTPLL(pllVCLK_ECP_CNTL, 0);
1963 OUTPLL(pllPIXCLKS_CNTL, 0);
1964
1965 /* Setup MCLK_MISC, non dynamic mode */
1966 OUTPLL(pllMCLK_MISC,
1967 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1968 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1969
1970 mdelay(5);
1971
1972 /* Set back the default clock dividers */
1973 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1974 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1975 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1976
1977 /* PPLL and P2PLL default values & off */
1978 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1979 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1980
1981 /* S and M PLLs are reset & off, configure them */
1982 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1983 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1984
1985 /* Default values for MDLL ... fixme */
1986 OUTPLL(pllMDLL_CKO, 0x9c009c);
1987 OUTPLL(pllMDLL_RDCKA, 0x08830883);
1988 OUTPLL(pllMDLL_RDCKB, 0x08830883);
1989 mdelay(5);
1990
1991 /* Restore PLL_PWRMGT_CNTL */ // XXXX
1992 tmp = rinfo->save_regs[0];
1993 tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
1994 tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
1995 OUTPLL(PLL_PWRMGT_CNTL, tmp);
1996
1997 /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
1998 OUTPLL(pllHTOTAL_CNTL, 0);
1999 OUTPLL(pllHTOTAL2_CNTL, 0);
2000
2001 /* All outputs off */
2002 OUTREG(CRTC_GEN_CNTL, 0x04000000);
2003 OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2004 OUTREG(FP_GEN_CNTL, 0x00004008);
2005 OUTREG(FP2_GEN_CNTL, 0x00000008);
2006 OUTREG(LVDS_GEN_CNTL, 0x08000008);
2007
2008 /* Restore Memory Controller configuration */
2009 radeon_pm_m9p_reconfigure_mc(rinfo);
2010
2011 /* Now we actually start MCLK and SCLK */
2012 radeon_pm_start_mclk_sclk(rinfo);
2013
2014 /* Full reset sdrams, this also re-inits the MDLL */
2015 radeon_pm_full_reset_sdram(rinfo);
2016
2017 /* Fill palettes */
2018 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2019 for (i=0; i<256; i++)
2020 OUTREG(PALETTE_30_DATA, 0x15555555);
2021 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2022 udelay(20);
2023 for (i=0; i<256; i++)
2024 OUTREG(PALETTE_30_DATA, 0x15555555);
2025
2026 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2027 mdelay(3);
2028
2029 /* Restore TV stuff, make sure TV DAC is down */
2030 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2031 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2032
2033 /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2034 * possibly related to the weird PLL related workarounds and to the
2035 * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2036 * but we keep things the simple way here
2037 */
2038 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2039 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2040 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2041
2042 /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2043 * high bits from backup
2044 */
2045 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2046 tmp |= rinfo->save_regs[34] & 0xffff0000;
2047 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2048 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2049
2050 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2051 tmp |= rinfo->save_regs[34] & 0xffff0000;
2052 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2053 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2054
2055 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2056 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2057 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2058 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2059 mdelay(20);
2060
2061 /* write some stuff to the framebuffer... */
2062 for (i = 0; i < 0x8000; ++i)
2063 writeb(0, rinfo->fb_base + i);
2064
2065 OUTREG(0x2ec, 0x6332a020);
2066 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2067 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2068 tmp = INPLL(pllSSPLL_CNTL);
2069 tmp &= ~2;
2070 OUTPLL(pllSSPLL_CNTL, tmp);
2071 mdelay(6);
2072 tmp &= ~1;
2073 OUTPLL(pllSSPLL_CNTL, tmp);
2074 mdelay(5);
2075 tmp |= 3;
2076 OUTPLL(pllSSPLL_CNTL, tmp);
2077 mdelay(5);
2078
2079 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2080 OUTREG(0x2ec, 0x6332a3f0);
2081 mdelay(17);
2082
2083 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);;
2084 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2085
2086 mdelay(40);
2087 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2088 mdelay(40);
2089
2090 /* Restore a few more things */
2091 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2092 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2093
2094 /* Restore PPLL, spread spectrum & LVDS */
2095 radeon_pm_m10_disable_spread_spectrum(rinfo);
2096 radeon_pm_restore_pixel_pll(rinfo);
2097 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2098}
2099
2100#if 0 /* Not ready yet */
2101static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2102{
2103 int i;
2104 u32 tmp, tmp2;
2105 u32 cko, cka, ckb;
2106 u32 cgc, cec, c2gc;
2107
2108 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2109 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2110 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2111 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2112 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2113 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2114
2115 INREG(PAD_CTLR_STRENGTH);
2116 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2117 for (i = 0; i < 65; ++i) {
2118 mdelay(1);
2119 INREG(PAD_CTLR_STRENGTH);
2120 }
2121
2122 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2123 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2124 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2125 OUTREG(DAC_CNTL, 0xff00410a);
2126 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2127 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2128
2129 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2130 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2131 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2132 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2133
2134 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2135 OUTREG(MC_IND_INDEX, 0);
2136 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2137 OUTREG(MC_IND_INDEX, 0);
2138
2139 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2140
2141 tmp = INPLL(pllVCLK_ECP_CNTL);
2142 OUTPLL(pllVCLK_ECP_CNTL, tmp);
2143 tmp = INPLL(pllPIXCLKS_CNTL);
2144 OUTPLL(pllPIXCLKS_CNTL, tmp);
2145
2146 OUTPLL(MCLK_CNTL, 0xaa3f0000);
2147 OUTPLL(SCLK_CNTL, 0xffff0000);
2148 OUTPLL(pllMPLL_AUX_CNTL, 6);
2149 OUTPLL(pllSPLL_AUX_CNTL, 1);
2150 OUTPLL(MDLL_CKO, 0x9f009f);
2151 OUTPLL(MDLL_RDCKA, 0x830083);
2152 OUTPLL(pllMDLL_RDCKB, 0x830083);
2153 OUTPLL(PPLL_CNTL, 0xa433);
2154 OUTPLL(P2PLL_CNTL, 0xa433);
2155 OUTPLL(MPLL_CNTL, 0x0400a403);
2156 OUTPLL(SPLL_CNTL, 0x0400a433);
2157
2158 tmp = INPLL(M_SPLL_REF_FB_DIV);
2159 OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2160 tmp = INPLL(M_SPLL_REF_FB_DIV);
2161 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2162 INPLL(M_SPLL_REF_FB_DIV);
2163
2164 tmp = INPLL(MPLL_CNTL);
2165 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2166 radeon_pll_errata_after_index(rinfo);
2167 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2168 radeon_pll_errata_after_data(rinfo);
2169
2170 tmp = INPLL(M_SPLL_REF_FB_DIV);
2171 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2172
2173 tmp = INPLL(MPLL_CNTL);
2174 OUTPLL(MPLL_CNTL, tmp & ~0x2);
2175 mdelay(1);
2176 tmp = INPLL(MPLL_CNTL);
2177 OUTPLL(MPLL_CNTL, tmp & ~0x1);
2178 mdelay(10);
2179
2180 OUTPLL(MCLK_CNTL, 0xaa3f1212);
2181 mdelay(1);
2182
2183 INPLL(M_SPLL_REF_FB_DIV);
2184 INPLL(MCLK_CNTL);
2185 INPLL(M_SPLL_REF_FB_DIV);
2186
2187 tmp = INPLL(SPLL_CNTL);
2188 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2189 radeon_pll_errata_after_index(rinfo);
2190 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2191 radeon_pll_errata_after_data(rinfo);
2192
2193 tmp = INPLL(M_SPLL_REF_FB_DIV);
2194 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2195
2196 tmp = INPLL(SPLL_CNTL);
2197 OUTPLL(SPLL_CNTL, tmp & ~0x1);
2198 mdelay(1);
2199 tmp = INPLL(SPLL_CNTL);
2200 OUTPLL(SPLL_CNTL, tmp & ~0x2);
2201 mdelay(10);
2202
2203 tmp = INPLL(SCLK_CNTL);
2204 OUTPLL(SCLK_CNTL, tmp | 2);
2205 mdelay(1);
2206
2207 cko = INPLL(pllMDLL_CKO);
2208 cka = INPLL(pllMDLL_RDCKA);
2209 ckb = INPLL(pllMDLL_RDCKB);
2210
2211 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2212 OUTPLL(pllMDLL_CKO, cko);
2213 mdelay(1);
2214 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2215 OUTPLL(pllMDLL_CKO, cko);
2216 mdelay(5);
2217
2218 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2219 OUTPLL(pllMDLL_RDCKA, cka);
2220 mdelay(1);
2221 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2222 OUTPLL(pllMDLL_RDCKA, cka);
2223 mdelay(5);
2224
2225 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2226 OUTPLL(pllMDLL_RDCKB, ckb);
2227 mdelay(1);
2228 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2229 OUTPLL(pllMDLL_RDCKB, ckb);
2230 mdelay(5);
2231
2232 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2233 OUTREG(MC_IND_INDEX, 0);
2234 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2235 OUTREG(MC_IND_INDEX, 0);
2236 mdelay(1);
2237 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2238 OUTREG(MC_IND_INDEX, 0);
2239 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2240 OUTREG(MC_IND_INDEX, 0);
2241 mdelay(1);
2242
2243 OUTPLL(pllHTOTAL_CNTL, 0);
2244 OUTPLL(pllHTOTAL2_CNTL, 0);
2245
2246 OUTREG(MEM_CNTL, 0x29002901);
2247 OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2248 OUTREG(EXT_MEM_CNTL, 0x1a394333);
2249 OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2250 OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2251 OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */
2252 OUTREG(MC_DEBUG, 0);
2253 OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2254
2255 OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2256 OUTREG(MC_IND_INDEX, 0);
2257 OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2258 OUTREG(MC_IND_INDEX, 0);
2259
2260 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
2261
2262 radeon_pm_full_reset_sdram(rinfo);
2263
2264 INREG(FP_GEN_CNTL);
2265 OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */
2266 tmp = INREG(FP_GEN_CNTL);
2267 tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2268 OUTREG(FP_GEN_CNTL, tmp);
2269
2270 tmp = INREG(DISP_OUTPUT_CNTL);
2271 tmp &= ~0x400;
2272 OUTREG(DISP_OUTPUT_CNTL, tmp);
2273
2274 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2275 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2276 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2277
2278 tmp = INPLL(MCLK_MISC);
2279 tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2280 OUTPLL(MCLK_MISC, tmp);
2281
2282 tmp = INPLL(SCLK_CNTL);
2283 OUTPLL(SCLK_CNTL, tmp);
2284
2285 OUTREG(CRTC_MORE_CNTL, 0);
2286 OUTREG8(CRTC_GEN_CNTL+1, 6);
2287 OUTREG8(CRTC_GEN_CNTL+3, 1);
2288 OUTREG(CRTC_PITCH, 32);
2289
2290 tmp = INPLL(VCLK_ECP_CNTL);
2291 OUTPLL(VCLK_ECP_CNTL, tmp);
2292
2293 tmp = INPLL(PPLL_CNTL);
2294 OUTPLL(PPLL_CNTL, tmp);
2295
2296 /* palette stuff and BIOS_1_SCRATCH... */
2297
2298 tmp = INREG(FP_GEN_CNTL);
2299 tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2300 tmp |= 2;
2301 OUTREG(FP_GEN_CNTL, tmp);
2302 mdelay(5);
2303 OUTREG(FP_GEN_CNTL, tmp);
2304 mdelay(5);
2305 OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2306 OUTREG(CRTC_MORE_CNTL, 0);
2307 mdelay(20);
2308
2309 tmp = INREG(CRTC_MORE_CNTL);
2310 OUTREG(CRTC_MORE_CNTL, tmp);
2311
2312 cgc = INREG(CRTC_GEN_CNTL);
2313 cec = INREG(CRTC_EXT_CNTL);
2314 c2gc = INREG(CRTC2_GEN_CNTL);
2315
2316 OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2317 OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2318 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2319 radeon_pll_errata_after_index(rinfo);
2320 OUTREG8(CLOCK_CNTL_DATA, 0);
2321 radeon_pll_errata_after_data(rinfo);
2322 OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2323 OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2324 OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2325 OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2326 OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2327 OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2328 OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2329 OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2330 OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2331 OUTREG(FP_HORZ_STRETCH, 0);
2332 OUTREG(FP_VERT_STRETCH, 0);
2333 OUTREG(OVR_CLR, 0);
2334 OUTREG(OVR_WID_LEFT_RIGHT, 0);
2335 OUTREG(OVR_WID_TOP_BOTTOM, 0);
2336
2337 tmp = INPLL(PPLL_REF_DIV);
2338 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2339 OUTPLL(PPLL_REF_DIV, tmp);
2340 INPLL(PPLL_REF_DIV);
2341
2342 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2343 radeon_pll_errata_after_index(rinfo);
2344 OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2345 radeon_pll_errata_after_data(rinfo);
2346
2347 tmp = INREG(CLOCK_CNTL_INDEX);
2348 radeon_pll_errata_after_index(rinfo);
2349 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2350 radeon_pll_errata_after_index(rinfo);
2351 radeon_pll_errata_after_data(rinfo);
2352
2353 OUTPLL(PPLL_DIV_0, 0x48090);
2354
2355 tmp = INPLL(PPLL_CNTL);
2356 OUTPLL(PPLL_CNTL, tmp & ~0x2);
2357 mdelay(1);
2358 tmp = INPLL(PPLL_CNTL);
2359 OUTPLL(PPLL_CNTL, tmp & ~0x1);
2360 mdelay(10);
2361
2362 tmp = INPLL(VCLK_ECP_CNTL);
2363 OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2364 mdelay(1);
2365
2366 tmp = INPLL(VCLK_ECP_CNTL);
2367 OUTPLL(VCLK_ECP_CNTL, tmp);
2368
2369 c2gc |= CRTC2_DISP_REQ_EN_B;
2370 OUTREG(CRTC2_GEN_CNTL, c2gc);
2371 cgc |= CRTC_EN;
2372 OUTREG(CRTC_GEN_CNTL, cgc);
2373 OUTREG(CRTC_EXT_CNTL, cec);
2374 OUTREG(CRTC_PITCH, 0xa0);
2375 OUTREG(CRTC_OFFSET, 0);
2376 OUTREG(CRTC_OFFSET_CNTL, 0);
2377
2378 OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2379 OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2380
2381 tmp2 = INREG(FP_GEN_CNTL);
2382 tmp = INREG(TMDS_TRANSMITTER_CNTL);
2383 OUTREG(0x2a8, 0x0000061b);
2384 tmp |= TMDS_PLL_EN;
2385 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2386 mdelay(1);
2387 tmp &= ~TMDS_PLLRST;
2388 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2389 tmp2 &= ~2;
2390 tmp2 |= FP_TMDS_EN;
2391 OUTREG(FP_GEN_CNTL, tmp2);
2392 mdelay(5);
2393 tmp2 |= FP_FPON;
2394 OUTREG(FP_GEN_CNTL, tmp2);
2395
2396 OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2397 cgc = INREG(CRTC_GEN_CNTL);
2398 OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2399 cgc |= 0x10000;
2400 OUTREG(CUR_OFFSET, 0);
2401}
2402#endif /* 0 */
2403
2404#endif /* CONFIG_PPC_OF */
2405
2406static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2407{
2408 u16 pwr_cmd;
2409 u32 tmp;
2410 int i;
2411
2412 if (!rinfo->pm_reg)
2413 return;
2414
2415 /* Set the chip into appropriate suspend mode (we use D2,
2416 * D3 would require a compete re-initialization of the chip,
2417 * including PCI config registers, clocks, AGP conf, ...)
2418 */
2419 if (suspend) {
2420 printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2421 pci_name(rinfo->pdev));
2422
2423 /* Disable dynamic power management of clocks for the
2424 * duration of the suspend/resume process
2425 */
2426 radeon_pm_disable_dynamic_mode(rinfo);
2427
2428 /* Save some registers */
2429 radeon_pm_save_regs(rinfo, 0);
2430
2431 /* Prepare mobility chips for suspend.
2432 */
2433 if (rinfo->is_mobility) {
2434 /* Program V2CLK */
2435 radeon_pm_program_v2clk(rinfo);
2436
2437 /* Disable IO PADs */
2438 radeon_pm_disable_iopad(rinfo);
2439
2440 /* Set low current */
2441 radeon_pm_low_current(rinfo);
2442
2443 /* Prepare chip for power management */
2444 radeon_pm_setup_for_suspend(rinfo);
2445
2446 if (rinfo->family <= CHIP_FAMILY_RV280) {
2447 /* Reset the MDLL */
2448 /* because both INPLL and OUTPLL take the same
2449 * lock, that's why. */
2450 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2451 | MDLL_CKO__MCKOB_RESET;
2452 OUTPLL( pllMDLL_CKO, tmp );
2453 }
2454 }
2455
2456 for (i = 0; i < 64; ++i)
2457 pci_read_config_dword(rinfo->pdev, i * 4,
2458 &rinfo->cfg_save[i]);
2459
2460 /* Switch PCI power managment to D2. */
2461 pci_disable_device(rinfo->pdev);
2462 for (;;) {
2463 pci_read_config_word(
2464 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2465 &pwr_cmd);
2466 if (pwr_cmd & 2)
2467 break;
2468 pci_write_config_word(
2469 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2470 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2471 mdelay(500);
2472 }
2473 } else {
2474 printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2475 pci_name(rinfo->pdev));
2476
2477 /* Switch back PCI powermanagment to D0 */
2478 mdelay(200);
2479 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2480 mdelay(500);
2481
2482 if (rinfo->family <= CHIP_FAMILY_RV250) {
2483 /* Reset the SDRAM controller */
2484 radeon_pm_full_reset_sdram(rinfo);
2485
2486 /* Restore some registers */
2487 radeon_pm_restore_regs(rinfo);
2488 } else {
2489 /* Restore registers first */
2490 radeon_pm_restore_regs(rinfo);
2491 /* init sdram controller */
2492 radeon_pm_full_reset_sdram(rinfo);
2493 }
2494 }
2495}
2496
2497static int radeon_restore_pci_cfg(struct radeonfb_info *rinfo)
2498{
2499 int i;
2500 static u32 radeon_cfg_after_resume[64];
2501
2502 for (i = 0; i < 64; ++i)
2503 pci_read_config_dword(rinfo->pdev, i * 4,
2504 &radeon_cfg_after_resume[i]);
2505
2506 if (radeon_cfg_after_resume[PCI_BASE_ADDRESS_0/4]
2507 == rinfo->cfg_save[PCI_BASE_ADDRESS_0/4])
2508 return 0; /* assume everything is ok */
2509
2510 for (i = PCI_BASE_ADDRESS_0/4; i < 64; ++i) {
2511 if (radeon_cfg_after_resume[i] != rinfo->cfg_save[i])
2512 pci_write_config_dword(rinfo->pdev, i * 4,
2513 rinfo->cfg_save[i]);
2514 }
2515 pci_write_config_word(rinfo->pdev, PCI_CACHE_LINE_SIZE,
2516 rinfo->cfg_save[PCI_CACHE_LINE_SIZE/4]);
2517 pci_write_config_word(rinfo->pdev, PCI_COMMAND,
2518 rinfo->cfg_save[PCI_COMMAND/4]);
2519 return 1;
2520}
2521
2522
2523static/*extern*/ int susdisking = 0;
2524
2525int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2526{
2527 struct fb_info *info = pci_get_drvdata(pdev);
2528 struct radeonfb_info *rinfo = info->par;
2529 u8 agp;
2530 int i;
2531
2532 if (state == pdev->dev.power.power_state)
2533 return 0;
2534
2535 printk(KERN_DEBUG "radeonfb (%s): suspending to state: %d...\n",
2536 pci_name(pdev), state);
2537
2538 /* For suspend-to-disk, we cheat here. We don't suspend anything and
2539 * let fbcon continue drawing until we are all set. That shouldn't
2540 * really cause any problem at this point, provided that the wakeup
2541 * code knows that any state in memory may not match the HW
2542 */
2543 if (state != PM_SUSPEND_MEM)
2544 goto done;
2545 if (susdisking) {
2546 printk("radeonfb (%s): suspending to disk but state = %d\n",
2547 pci_name(pdev), state);
2548 goto done;
2549 }
2550
2551 acquire_console_sem();
2552
2553 fb_set_suspend(info, 1);
2554
2555 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2556 /* Make sure engine is reset */
2557 radeon_engine_idle();
2558 radeonfb_engine_reset(rinfo);
2559 radeon_engine_idle();
2560 }
2561
2562 /* Blank display and LCD */
2563 radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2564
2565 /* Sleep */
2566 rinfo->asleep = 1;
2567 rinfo->lock_blank = 1;
2568 del_timer_sync(&rinfo->lvds_timer);
2569
2570 /* Disable AGP. The AGP host should have done it, but since ordering
2571 * isn't always properly guaranteed in this specific case, let's make
2572 * sure it's disabled on card side now. Ultimately, when merging fbdev
2573 * and dri into some common infrastructure, this will be handled
2574 * more nicely. The host bridge side will (or will not) be dealt with
2575 * by the bridge AGP driver, we don't attempt to touch it here.
2576 */
2577 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2578 if (agp) {
2579 u32 cmd;
2580
2581 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
2582 if (cmd & PCI_AGP_COMMAND_AGP) {
2583 printk(KERN_INFO "radeonfb (%s): AGP was enabled, "
2584 "disabling ...\n",
2585 pci_name(pdev));
2586 cmd &= ~PCI_AGP_COMMAND_AGP;
2587 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND,
2588 cmd);
2589 }
2590 }
2591
2592 /* If we support wakeup from poweroff, we save all regs we can including cfg
2593 * space
2594 */
2595 if (rinfo->pm_mode & radeon_pm_off) {
2596 /* Always disable dynamic clocks or weird things are happening when
2597 * the chip goes off (basically the panel doesn't shut down properly
2598 * and we crash on wakeup),
2599 * also, we want the saved regs context to have no dynamic clocks in
2600 * it, we'll restore the dynamic clocks state on wakeup
2601 */
2602 radeon_pm_disable_dynamic_mode(rinfo);
2603 mdelay(50);
2604 radeon_pm_save_regs(rinfo, 1);
2605
2606 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2607 /* Switch off LVDS interface */
2608 mdelay(1);
2609 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2610 mdelay(1);
2611 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2612 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2613 mdelay(20);
2614 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2615 }
2616 // FIXME: Use PCI layer
2617 for (i = 0; i < 64; ++i)
2618 pci_read_config_dword(pdev, i * 4, &rinfo->cfg_save[i]);
2619 pci_disable_device(pdev);
2620 }
2621 /* If we support D2, we go to it (should be fixed later with a flag forcing
2622 * D3 only for some laptops)
2623 */
2624 if (rinfo->pm_mode & radeon_pm_d2)
2625 radeon_set_suspend(rinfo, 1);
2626
2627 release_console_sem();
2628
2629 done:
2630 pdev->dev.power.power_state = state;
2631
2632 return 0;
2633}
2634
2635int radeonfb_pci_resume(struct pci_dev *pdev)
2636{
2637 struct fb_info *info = pci_get_drvdata(pdev);
2638 struct radeonfb_info *rinfo = info->par;
2639 int rc = 0;
2640
2641 if (pdev->dev.power.power_state == 0)
2642 return 0;
2643
2644 if (rinfo->no_schedule) {
2645 if (try_acquire_console_sem())
2646 return 0;
2647 } else
2648 acquire_console_sem();
2649
2650 printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2651 pci_name(pdev), pdev->dev.power.power_state);
2652
2653
2654 if (pci_enable_device(pdev)) {
2655 rc = -ENODEV;
2656 printk(KERN_ERR "radeonfb (%s): can't enable PCI device !\n",
2657 pci_name(pdev));
2658 goto bail;
2659 }
2660 pci_set_master(pdev);
2661
2662 if (pdev->dev.power.power_state == PM_SUSPEND_MEM) {
2663 /* Wakeup chip. Check from config space if we were powered off
2664 * (todo: additionally, check CLK_PIN_CNTL too)
2665 */
2666 if ((rinfo->pm_mode & radeon_pm_off) && radeon_restore_pci_cfg(rinfo)) {
2667 if (rinfo->reinit_func != NULL)
2668 rinfo->reinit_func(rinfo);
2669 else {
2670 printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2671 " D3 cold, need softboot !", pci_name(pdev));
2672 rc = -EIO;
2673 goto bail;
2674 }
2675 }
2676 /* If we support D2, try to resume... we should check what was our
2677 * state though... (were we really in D2 state ?). Right now, this code
2678 * is only enable on Macs so it's fine.
2679 */
2680 else if (rinfo->pm_mode & radeon_pm_d2)
2681 radeon_set_suspend(rinfo, 0);
2682
2683 rinfo->asleep = 0;
2684 } else
2685 radeon_engine_idle();
2686
2687 /* Restore display & engine */
2688 radeon_write_mode (rinfo, &rinfo->state, 1);
2689 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2690 radeonfb_engine_init (rinfo);
2691
2692 fb_pan_display(info, &info->var);
2693 fb_set_cmap(&info->cmap, info);
2694
2695 /* Refresh */
2696 fb_set_suspend(info, 0);
2697
2698 /* Unblank */
2699 rinfo->lock_blank = 0;
2700 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2701
2702 /* Check status of dynclk */
2703 if (rinfo->dynclk == 1)
2704 radeon_pm_enable_dynamic_mode(rinfo);
2705 else if (rinfo->dynclk == 0)
2706 radeon_pm_disable_dynamic_mode(rinfo);
2707
2708 pdev->dev.power.power_state = PMSG_ON;
2709
2710 bail:
2711 release_console_sem();
2712
2713 return rc;
2714}
2715
2716#ifdef CONFIG_PPC_OF
2717static void radeonfb_early_resume(void *data)
2718{
2719 struct radeonfb_info *rinfo = data;
2720
2721 rinfo->no_schedule = 1;
2722 radeonfb_pci_resume(rinfo->pdev);
2723 rinfo->no_schedule = 0;
2724}
2725#endif /* CONFIG_PPC_OF */
2726
2727#endif /* CONFIG_PM */
2728
2729void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk)
2730{
2731 /* Find PM registers in config space if any*/
2732 rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM);
2733
2734 /* Enable/Disable dynamic clocks: TODO add sysfs access */
2735 rinfo->dynclk = dynclk;
2736 if (dynclk == 1) {
2737 radeon_pm_enable_dynamic_mode(rinfo);
2738 printk("radeonfb: Dynamic Clock Power Management enabled\n");
2739 } else if (dynclk == 0) {
2740 radeon_pm_disable_dynamic_mode(rinfo);
2741 printk("radeonfb: Dynamic Clock Power Management disabled\n");
2742 }
2743
2744 /* Check if we can power manage on suspend/resume. We can do
2745 * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2746 * "Mac" cards, but that's all. We need more infos about what the
2747 * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2748 * reason. --BenH
2749 */
2750#if defined(CONFIG_PM) && defined(CONFIG_PPC_OF)
2751 if (_machine == _MACH_Pmac && rinfo->of_node) {
2752 if (rinfo->is_mobility && rinfo->pm_reg &&
2753 rinfo->family <= CHIP_FAMILY_RV250)
2754 rinfo->pm_mode |= radeon_pm_d2;
2755
2756 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2757 * in some desktop G4s), and Via (M9+ chip on iBook G4)
2758 */
2759 if (!strcmp(rinfo->of_node->name, "ATY,JasperParent")) {
2760 rinfo->reinit_func = radeon_reinitialize_M10;
2761 rinfo->pm_mode |= radeon_pm_off;
2762 }
2763#if 0 /* Not ready yet */
2764 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2765 rinfo->reinit_func = radeon_reinitialize_QW;
2766 rinfo->pm_mode |= radeon_pm_off;
2767 }
2768#endif
2769 if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
2770 rinfo->reinit_func = radeon_reinitialize_M9P;
2771 rinfo->pm_mode |= radeon_pm_off;
2772 }
2773
2774 /* If any of the above is set, we assume the machine can sleep/resume.
2775 * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2776 * from the platform about what happens to the chip...
2777 * Now we tell the platform about our capability
2778 */
2779 if (rinfo->pm_mode != radeon_pm_none) {
2780 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2781 pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2782 }
2783
2784#if 0
2785 /* Power down TV DAC, taht saves a significant amount of power,
2786 * we'll have something better once we actually have some TVOut
2787 * support
2788 */
2789 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2790#endif
2791 }
2792#endif /* defined(CONFIG_PM) && defined(CONFIG_PPC_OF) */
2793}
2794
2795void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2796{
2797#if defined(CONFIG_PM) && defined(CONFIG_PPC_OF)
2798 if (rinfo->pm_mode != radeon_pm_none)
2799 pmac_set_early_video_resume(NULL, NULL);
2800#endif
2801}
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
new file mode 100644
index 000000000000..659bc9f62244
--- /dev/null
+++ b/drivers/video/aty/radeonfb.h
@@ -0,0 +1,625 @@
1#ifndef __RADEONFB_H__
2#define __RADEONFB_H__
3
4#include <linux/config.h>
5#include <linux/module.h>
6#include <linux/kernel.h>
7#include <linux/sched.h>
8#include <linux/delay.h>
9#include <linux/pci.h>
10#include <linux/fb.h>
11
12
13#include <linux/i2c.h>
14#include <linux/i2c-id.h>
15#include <linux/i2c-algo-bit.h>
16
17#include <asm/io.h>
18
19#ifdef CONFIG_PPC_OF
20#include <asm/prom.h>
21#endif
22
23#include <video/radeon.h>
24
25/***************************************************************
26 * Most of the definitions here are adapted right from XFree86 *
27 ***************************************************************/
28
29
30/*
31 * Chip families. Must fit in the low 16 bits of a long word
32 */
33enum radeon_family {
34 CHIP_FAMILY_UNKNOW,
35 CHIP_FAMILY_LEGACY,
36 CHIP_FAMILY_RADEON,
37 CHIP_FAMILY_RV100,
38 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
39 CHIP_FAMILY_RV200,
40 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
41 RS250 (IGP 7000) */
42 CHIP_FAMILY_R200,
43 CHIP_FAMILY_RV250,
44 CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
45 CHIP_FAMILY_RV280,
46 CHIP_FAMILY_R300,
47 CHIP_FAMILY_R350,
48 CHIP_FAMILY_RV350,
49 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
50 CHIP_FAMILY_R420, /* R420/R423/M18 */
51 CHIP_FAMILY_LAST,
52};
53
54#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
55 ((rinfo)->family == CHIP_FAMILY_RV200) || \
56 ((rinfo)->family == CHIP_FAMILY_RS100) || \
57 ((rinfo)->family == CHIP_FAMILY_RS200) || \
58 ((rinfo)->family == CHIP_FAMILY_RV250) || \
59 ((rinfo)->family == CHIP_FAMILY_RV280) || \
60 ((rinfo)->family == CHIP_FAMILY_RS300))
61
62
63#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
64 ((rinfo)->family == CHIP_FAMILY_RV350) || \
65 ((rinfo)->family == CHIP_FAMILY_R350) || \
66 ((rinfo)->family == CHIP_FAMILY_RV380) || \
67 ((rinfo)->family == CHIP_FAMILY_R420))
68
69/*
70 * Chip flags
71 */
72enum radeon_chip_flags {
73 CHIP_FAMILY_MASK = 0x0000ffffUL,
74 CHIP_FLAGS_MASK = 0xffff0000UL,
75 CHIP_IS_MOBILITY = 0x00010000UL,
76 CHIP_IS_IGP = 0x00020000UL,
77 CHIP_HAS_CRTC2 = 0x00040000UL,
78};
79
80/*
81 * Errata workarounds
82 */
83enum radeon_errata {
84 CHIP_ERRATA_R300_CG = 0x00000001,
85 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
86 CHIP_ERRATA_PLL_DELAY = 0x00000004,
87};
88
89
90/*
91 * Monitor types
92 */
93enum radeon_montype {
94 MT_NONE = 0,
95 MT_CRT, /* CRT */
96 MT_LCD, /* LCD */
97 MT_DFP, /* DVI */
98 MT_CTV, /* composite TV */
99 MT_STV /* S-Video out */
100};
101
102/*
103 * DDC i2c ports
104 */
105enum ddc_type {
106 ddc_none,
107 ddc_monid,
108 ddc_dvi,
109 ddc_vga,
110 ddc_crt2,
111};
112
113/*
114 * Connector types
115 */
116enum conn_type {
117 conn_none,
118 conn_proprietary,
119 conn_crt,
120 conn_DVI_I,
121 conn_DVI_D,
122};
123
124
125/*
126 * PLL infos
127 */
128struct pll_info {
129 int ppll_max;
130 int ppll_min;
131 int sclk, mclk;
132 int ref_div;
133 int ref_clk;
134};
135
136
137/*
138 * This structure contains the various registers manipulated by this
139 * driver for setting or restoring a mode. It's mostly copied from
140 * XFree's RADEONSaveRec structure. A few chip settings might still be
141 * tweaked without beeing reflected or saved in these registers though
142 */
143struct radeon_regs {
144 /* Common registers */
145 u32 ovr_clr;
146 u32 ovr_wid_left_right;
147 u32 ovr_wid_top_bottom;
148 u32 ov0_scale_cntl;
149 u32 mpp_tb_config;
150 u32 mpp_gp_config;
151 u32 subpic_cntl;
152 u32 viph_control;
153 u32 i2c_cntl_1;
154 u32 gen_int_cntl;
155 u32 cap0_trig_cntl;
156 u32 cap1_trig_cntl;
157 u32 bus_cntl;
158 u32 surface_cntl;
159 u32 bios_5_scratch;
160
161 /* Other registers to save for VT switches or driver load/unload */
162 u32 dp_datatype;
163 u32 rbbm_soft_reset;
164 u32 clock_cntl_index;
165 u32 amcgpio_en_reg;
166 u32 amcgpio_mask;
167
168 /* Surface/tiling registers */
169 u32 surf_lower_bound[8];
170 u32 surf_upper_bound[8];
171 u32 surf_info[8];
172
173 /* CRTC registers */
174 u32 crtc_gen_cntl;
175 u32 crtc_ext_cntl;
176 u32 dac_cntl;
177 u32 crtc_h_total_disp;
178 u32 crtc_h_sync_strt_wid;
179 u32 crtc_v_total_disp;
180 u32 crtc_v_sync_strt_wid;
181 u32 crtc_offset;
182 u32 crtc_offset_cntl;
183 u32 crtc_pitch;
184 u32 disp_merge_cntl;
185 u32 grph_buffer_cntl;
186 u32 crtc_more_cntl;
187
188 /* CRTC2 registers */
189 u32 crtc2_gen_cntl;
190 u32 dac2_cntl;
191 u32 disp_output_cntl;
192 u32 disp_hw_debug;
193 u32 disp2_merge_cntl;
194 u32 grph2_buffer_cntl;
195 u32 crtc2_h_total_disp;
196 u32 crtc2_h_sync_strt_wid;
197 u32 crtc2_v_total_disp;
198 u32 crtc2_v_sync_strt_wid;
199 u32 crtc2_offset;
200 u32 crtc2_offset_cntl;
201 u32 crtc2_pitch;
202
203 /* Flat panel regs */
204 u32 fp_crtc_h_total_disp;
205 u32 fp_crtc_v_total_disp;
206 u32 fp_gen_cntl;
207 u32 fp2_gen_cntl;
208 u32 fp_h_sync_strt_wid;
209 u32 fp2_h_sync_strt_wid;
210 u32 fp_horz_stretch;
211 u32 fp_panel_cntl;
212 u32 fp_v_sync_strt_wid;
213 u32 fp2_v_sync_strt_wid;
214 u32 fp_vert_stretch;
215 u32 lvds_gen_cntl;
216 u32 lvds_pll_cntl;
217 u32 tmds_crc;
218 u32 tmds_transmitter_cntl;
219
220 /* Computed values for PLL */
221 u32 dot_clock_freq;
222 int feedback_div;
223 int post_div;
224
225 /* PLL registers */
226 u32 ppll_div_3;
227 u32 ppll_ref_div;
228 u32 vclk_ecp_cntl;
229 u32 clk_cntl_index;
230
231 /* Computed values for PLL2 */
232 u32 dot_clock_freq_2;
233 int feedback_div_2;
234 int post_div_2;
235
236 /* PLL2 registers */
237 u32 p2pll_ref_div;
238 u32 p2pll_div_0;
239 u32 htotal_cntl2;
240
241 /* Palette */
242 int palette_valid;
243};
244
245struct panel_info {
246 int xres, yres;
247 int valid;
248 int clock;
249 int hOver_plus, hSync_width, hblank;
250 int vOver_plus, vSync_width, vblank;
251 int hAct_high, vAct_high, interlaced;
252 int pwr_delay;
253 int use_bios_dividers;
254 int ref_divider;
255 int post_divider;
256 int fbk_divider;
257};
258
259struct radeonfb_info;
260
261#ifdef CONFIG_FB_RADEON_I2C
262struct radeon_i2c_chan {
263 struct radeonfb_info *rinfo;
264 u32 ddc_reg;
265 struct i2c_adapter adapter;
266 struct i2c_algo_bit_data algo;
267};
268#endif
269
270enum radeon_pm_mode {
271 radeon_pm_none = 0, /* Nothing supported */
272 radeon_pm_d2 = 0x00000001, /* Can do D2 state */
273 radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
274};
275
276struct radeonfb_info {
277 struct fb_info *info;
278
279 struct radeon_regs state;
280 struct radeon_regs init_state;
281
282 char name[DEVICE_NAME_SIZE];
283
284 unsigned long mmio_base_phys;
285 unsigned long fb_base_phys;
286
287 void __iomem *mmio_base;
288 void __iomem *fb_base;
289
290 unsigned long fb_local_base;
291
292 struct pci_dev *pdev;
293#ifdef CONFIG_PPC_OF
294 struct device_node *of_node;
295#endif
296
297 void __iomem *bios_seg;
298 int fp_bios_start;
299
300 u32 pseudo_palette[17];
301 struct { u8 red, green, blue, pad; }
302 palette[256];
303
304 int chipset;
305 u8 family;
306 u8 rev;
307 unsigned int errata;
308 unsigned long video_ram;
309 unsigned long mapped_vram;
310 int vram_width;
311 int vram_ddr;
312
313 int pitch, bpp, depth;
314
315 int has_CRTC2;
316 int is_mobility;
317 int is_IGP;
318 int reversed_DAC;
319 int reversed_TMDS;
320 struct panel_info panel_info;
321 int mon1_type;
322 u8 *mon1_EDID;
323 struct fb_videomode *mon1_modedb;
324 int mon1_dbsize;
325 int mon2_type;
326 u8 *mon2_EDID;
327
328 u32 dp_gui_master_cntl;
329
330 struct pll_info pll;
331
332 int mtrr_hdl;
333
334 int pm_reg;
335 u32 save_regs[100];
336 int asleep;
337 int lock_blank;
338 int dynclk;
339 int no_schedule;
340 enum radeon_pm_mode pm_mode;
341 void (*reinit_func)(struct radeonfb_info *rinfo);
342
343 /* Lock on register access */
344 spinlock_t reg_lock;
345
346 /* Timer used for delayed LVDS operations */
347 struct timer_list lvds_timer;
348 u32 pending_lvds_gen_cntl;
349
350#ifdef CONFIG_FB_RADEON_I2C
351 struct radeon_i2c_chan i2c[4];
352#endif
353
354 u32 cfg_save[64];
355};
356
357
358#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
359
360
361/*
362 * Debugging stuffs
363 */
364#ifdef CONFIG_FB_RADEON_DEBUG
365#define DEBUG 1
366#else
367#define DEBUG 0
368#endif
369
370#if DEBUG
371#define RTRACE printk
372#else
373#define RTRACE if(0) printk
374#endif
375
376
377/*
378 * IO macros
379 */
380
381/* Note about this function: we have some rare cases where we must not schedule,
382 * this typically happen with our special "wake up early" hook which allows us to
383 * wake up the graphic chip (and thus get the console back) before everything else
384 * on some machines that support that mecanism. At this point, interrupts are off
385 * and scheduling is not permitted
386 */
387static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
388{
389 if (rinfo->no_schedule || oops_in_progress)
390 mdelay(ms);
391 else
392 msleep(ms);
393}
394
395
396#define INREG8(addr) readb((rinfo->mmio_base)+addr)
397#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
398#define INREG(addr) readl((rinfo->mmio_base)+addr)
399#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
400
401static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
402 u32 val, u32 mask)
403{
404 unsigned long flags;
405 unsigned int tmp;
406
407 spin_lock_irqsave(&rinfo->reg_lock, flags);
408 tmp = INREG(addr);
409 tmp &= (mask);
410 tmp |= (val);
411 OUTREG(addr, tmp);
412 spin_unlock_irqrestore(&rinfo->reg_lock, flags);
413}
414
415#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
416
417/*
418 * Note about PLL register accesses:
419 *
420 * I have removed the spinlock on them on purpose. The driver now
421 * expects that it will only manipulate the PLL registers in normal
422 * task environment, where radeon_msleep() will be called, protected
423 * by a semaphore (currently the console semaphore) so that no conflict
424 * will happen on the PLL register index.
425 *
426 * With the latest changes to the VT layer, this is guaranteed for all
427 * calls except the actual drawing/blits which aren't supposed to use
428 * the PLL registers anyway
429 *
430 * This is very important for the workarounds to work properly. The only
431 * possible exception to this rule is the call to unblank(), which may
432 * be done at irq time if an oops is in progress.
433 */
434static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
435{
436 if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
437 return;
438
439 (void)INREG(CLOCK_CNTL_DATA);
440 (void)INREG(CRTC_GEN_CNTL);
441}
442
443static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
444{
445 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
446 /* we can't deal with posted writes here ... */
447 _radeon_msleep(rinfo, 5);
448 }
449 if (rinfo->errata & CHIP_ERRATA_R300_CG) {
450 u32 save, tmp;
451 save = INREG(CLOCK_CNTL_INDEX);
452 tmp = save & ~(0x3f | PLL_WR_EN);
453 OUTREG(CLOCK_CNTL_INDEX, tmp);
454 tmp = INREG(CLOCK_CNTL_DATA);
455 OUTREG(CLOCK_CNTL_INDEX, save);
456 }
457}
458
459static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
460{
461 u32 data;
462
463 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
464 radeon_pll_errata_after_index(rinfo);
465 data = INREG(CLOCK_CNTL_DATA);
466 radeon_pll_errata_after_data(rinfo);
467 return data;
468}
469
470static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
471 u32 val)
472{
473
474 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
475 radeon_pll_errata_after_index(rinfo);
476 OUTREG(CLOCK_CNTL_DATA, val);
477 radeon_pll_errata_after_data(rinfo);
478}
479
480
481static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
482 u32 val, u32 mask)
483{
484 unsigned int tmp;
485
486 tmp = __INPLL(rinfo, index);
487 tmp &= (mask);
488 tmp |= (val);
489 __OUTPLL(rinfo, index, tmp);
490}
491
492
493#define INPLL(addr) __INPLL(rinfo, addr)
494#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
495#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
496
497
498#define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
499#define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
500 (readb(rinfo->bios_seg + (v) + 1) << 8))
501#define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
502 (readb(rinfo->bios_seg + (v) + 1) << 8) | \
503 (readb(rinfo->bios_seg + (v) + 2) << 16) | \
504 (readb(rinfo->bios_seg + (v) + 3) << 24))
505
506/*
507 * Inline utilities
508 */
509static inline int round_div(int num, int den)
510{
511 return (num + (den / 2)) / den;
512}
513
514static inline int var_to_depth(const struct fb_var_screeninfo *var)
515{
516 if (var->bits_per_pixel != 16)
517 return var->bits_per_pixel;
518 return (var->green.length == 5) ? 15 : 16;
519}
520
521static inline u32 radeon_get_dstbpp(u16 depth)
522{
523 switch (depth) {
524 case 8:
525 return DST_8BPP;
526 case 15:
527 return DST_15BPP;
528 case 16:
529 return DST_16BPP;
530 case 32:
531 return DST_32BPP;
532 default:
533 return 0;
534 }
535}
536
537/*
538 * 2D Engine helper routines
539 */
540static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
541{
542 int i;
543
544 /* initiate flush */
545 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
546 ~RB2D_DC_FLUSH_ALL);
547
548 for (i=0; i < 2000000; i++) {
549 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
550 return;
551 udelay(1);
552 }
553 printk(KERN_ERR "radeonfb: Flush Timeout !\n");
554}
555
556
557static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
558{
559 int i;
560
561 for (i=0; i<2000000; i++) {
562 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
563 return;
564 udelay(1);
565 }
566 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
567}
568
569
570static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
571{
572 int i;
573
574 /* ensure FIFO is empty before waiting for idle */
575 _radeon_fifo_wait (rinfo, 64);
576
577 for (i=0; i<2000000; i++) {
578 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
579 radeon_engine_flush (rinfo);
580 return;
581 }
582 udelay(1);
583 }
584 printk(KERN_ERR "radeonfb: Idle Timeout !\n");
585}
586
587
588#define radeon_engine_idle() _radeon_engine_idle(rinfo)
589#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
590#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
591
592
593/* I2C Functions */
594extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
595extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
596extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
597
598/* PM Functions */
599extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
600extern int radeonfb_pci_resume(struct pci_dev *pdev);
601extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk);
602extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
603
604/* Monitor probe functions */
605extern void radeon_probe_screens(struct radeonfb_info *rinfo,
606 const char *monitor_layout, int ignore_edid);
607extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
608extern int radeon_match_mode(struct radeonfb_info *rinfo,
609 struct fb_var_screeninfo *dest,
610 const struct fb_var_screeninfo *src);
611
612/* Accel functions */
613extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
614extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
615extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
616extern int radeonfb_sync(struct fb_info *info);
617extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
618extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
619
620/* Other functions */
621extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
622extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
623 int reg_only);
624
625#endif /* __RADEONFB_H__ */
diff --git a/drivers/video/aty/xlinit.c b/drivers/video/aty/xlinit.c
new file mode 100644
index 000000000000..92643af12581
--- /dev/null
+++ b/drivers/video/aty/xlinit.c
@@ -0,0 +1,354 @@
1/*
2 * ATI Rage XL Initialization. Support for Xpert98 and Victoria
3 * PCI cards.
4 *
5 * Copyright (C) 2002 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * stevel@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/config.h>
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/errno.h>
33#include <linux/string.h>
34#include <linux/mm.h>
35#include <linux/slab.h>
36#include <linux/vmalloc.h>
37#include <linux/delay.h>
38#include <linux/fb.h>
39#include <linux/init.h>
40#include <linux/pci.h>
41#include <asm/io.h>
42#include <video/mach64.h>
43#include "atyfb.h"
44
45#define MPLL_GAIN 0xad
46#define VPLL_GAIN 0xd5
47
48enum {
49 VICTORIA = 0,
50 XPERT98,
51 NUM_XL_CARDS
52};
53
54extern const struct aty_pll_ops aty_pll_ct;
55
56#define DEFAULT_CARD XPERT98
57static int xl_card = DEFAULT_CARD;
58
59static const struct xl_card_cfg_t {
60 int ref_crystal; // 10^4 Hz
61 int mem_type;
62 int mem_size;
63 u32 mem_cntl;
64 u32 ext_mem_cntl;
65 u32 mem_addr_config;
66 u32 bus_cntl;
67 u32 dac_cntl;
68 u32 hw_debug;
69 u32 custom_macro_cntl;
70 u8 dll2_cntl;
71 u8 pll_yclk_cntl;
72} card_cfg[NUM_XL_CARDS] = {
73 // VICTORIA
74 { 2700, SDRAM, 0x800000,
75 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
76 0x82010102, 0x48803800, 0x005E0179,
77 0x50, 0x25
78 },
79 // XPERT98
80 { 1432, WRAM, 0x800000,
81 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
82 0x8000000A, 0x48833800, 0x007F0779,
83 0x10, 0x19
84 }
85};
86
87typedef struct {
88 u8 lcd_reg;
89 u32 val;
90} lcd_tbl_t;
91
92static const lcd_tbl_t lcd_tbl[] = {
93 { 0x01, 0x000520C0 },
94 { 0x08, 0x02000408 },
95 { 0x03, 0x00000F00 },
96 { 0x00, 0x00000000 },
97 { 0x02, 0x00000000 },
98 { 0x04, 0x00000000 },
99 { 0x05, 0x00000000 },
100 { 0x06, 0x00000000 },
101 { 0x33, 0x00000000 },
102 { 0x34, 0x00000000 },
103 { 0x35, 0x00000000 },
104 { 0x36, 0x00000000 },
105 { 0x37, 0x00000000 }
106};
107
108static void reset_gui(struct atyfb_par *par)
109{
110 aty_st_8(GEN_TEST_CNTL+1, 0x01, par);
111 aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
112 aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
113 mdelay(5);
114}
115
116static void reset_sdram(struct atyfb_par *par)
117{
118 u8 temp;
119
120 temp = aty_ld_8(EXT_MEM_CNTL, par);
121 temp |= 0x02;
122 aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_SDRAM_RESET = 1b
123 temp |= 0x08;
124 aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 10b
125 temp |= 0x0c;
126 aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 11b
127 mdelay(5);
128 temp &= 0xf3;
129 aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 00b
130 temp &= 0xfd;
131 aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_SDRAM_REST = 0b
132 mdelay(5);
133}
134
135static void init_dll(struct atyfb_par *par)
136{
137 // enable DLL
138 aty_st_pll_ct(PLL_GEN_CNTL,
139 aty_ld_pll_ct(PLL_GEN_CNTL, par) & 0x7f,
140 par);
141
142 // reset DLL
143 aty_st_pll_ct(DLL_CNTL, 0x82, par);
144 aty_st_pll_ct(DLL_CNTL, 0xE2, par);
145 mdelay(5);
146 aty_st_pll_ct(DLL_CNTL, 0x82, par);
147 mdelay(6);
148}
149
150static void reset_clocks(struct atyfb_par *par, struct pll_ct *pll,
151 int hsync_enb)
152{
153 reset_gui(par);
154 aty_st_pll_ct(MCLK_FB_DIV, pll->mclk_fb_div, par);
155 aty_st_pll_ct(SCLK_FB_DIV, pll->sclk_fb_div, par);
156
157 mdelay(15);
158 init_dll(par);
159 aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
160 mdelay(5);
161 aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
162 mdelay(6);
163 reset_sdram(par);
164 aty_st_8(CRTC_GEN_CNTL+3,
165 hsync_enb ? 0x00 : 0x04, par);
166
167 aty_st_pll_ct(SPLL_CNTL2, pll->spll_cntl2, par);
168 aty_st_pll_ct(PLL_GEN_CNTL, pll->pll_gen_cntl, par);
169 aty_st_pll_ct(PLL_VCLK_CNTL, pll->pll_vclk_cntl, par);
170}
171
172int atyfb_xl_init(struct fb_info *info)
173{
174 const struct xl_card_cfg_t * card = &card_cfg[xl_card];
175 struct atyfb_par *par = (struct atyfb_par *) info->par;
176 union aty_pll pll;
177 int i, err;
178 u32 temp;
179
180 aty_st_8(CONFIG_STAT0, 0x85, par);
181 mdelay(10);
182
183 /*
184 * The following needs to be set before the call
185 * to var_to_pll() below. They'll be re-set again
186 * to the same values in aty_init().
187 */
188 par->ref_clk_per = 100000000UL/card->ref_crystal;
189 par->ram_type = card->mem_type;
190 info->fix.smem_len = card->mem_size;
191 if (xl_card == VICTORIA) {
192 // the MCLK, XCLK are 120MHz on victoria card
193 par->mclk_per = 1000000/120;
194 par->xclk_per = 1000000/120;
195 par->features &= ~M64F_MFB_FORCE_4;
196 }
197
198 /*
199 * Calculate mclk and xclk dividers, etc. The passed
200 * pixclock and bpp values don't matter yet, the vclk
201 * isn't programmed until later.
202 */
203 if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll)))
204 return err;
205
206 aty_st_pll_ct(LVDS_CNTL0, 0x00, par);
207 aty_st_pll_ct(DLL2_CNTL, card->dll2_cntl, par);
208 aty_st_pll_ct(V2PLL_CNTL, 0x10, par);
209 aty_st_pll_ct(MPLL_CNTL, MPLL_GAIN, par);
210 aty_st_pll_ct(VPLL_CNTL, VPLL_GAIN, par);
211 aty_st_pll_ct(PLL_VCLK_CNTL, 0x00, par);
212 aty_st_pll_ct(VFC_CNTL, 0x1B, par);
213 aty_st_pll_ct(PLL_REF_DIV, pll.ct.pll_ref_div, par);
214 aty_st_pll_ct(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, par);
215 aty_st_pll_ct(SPLL_CNTL2, 0x03, par);
216 aty_st_pll_ct(PLL_GEN_CNTL, 0x44, par);
217
218 reset_clocks(par, &pll.ct, 0);
219 mdelay(10);
220
221 aty_st_pll_ct(VCLK_POST_DIV, 0x03, par);
222 aty_st_pll_ct(VCLK0_FB_DIV, 0xDA, par);
223 aty_st_pll_ct(VCLK_POST_DIV, 0x0F, par);
224 aty_st_pll_ct(VCLK1_FB_DIV, 0xF5, par);
225 aty_st_pll_ct(VCLK_POST_DIV, 0x3F, par);
226 aty_st_pll_ct(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, par);
227 aty_st_pll_ct(VCLK2_FB_DIV, 0x00, par);
228 aty_st_pll_ct(VCLK_POST_DIV, 0xFF, par);
229 aty_st_pll_ct(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, par);
230 aty_st_pll_ct(VCLK3_FB_DIV, 0x00, par);
231
232 aty_st_8(BUS_CNTL, 0x01, par);
233 aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, par);
234
235 aty_st_le32(CRTC_GEN_CNTL, 0x04000200, par);
236 aty_st_le16(CONFIG_STAT0, 0x0020, par);
237 aty_st_le32(MEM_CNTL, 0x10151A33, par);
238 aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, par);
239 aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, par);
240 aty_st_le32(DAC_CNTL, card->dac_cntl, par);
241 aty_st_le16(GEN_TEST_CNTL, 0x0100, par);
242 aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, par);
243 aty_st_le32(MEM_BUF_CNTL, 0x00382848, par);
244
245 aty_st_le32(HW_DEBUG, card->hw_debug, par);
246 aty_st_le16(MEM_ADDR_CONFIG, 0x0000, par);
247 aty_st_le16(GP_IO+2, 0x0000, par);
248 aty_st_le16(GEN_TEST_CNTL, 0x0000, par);
249 aty_st_le16(EXT_DAC_REGS+2, 0x0000, par);
250 aty_st_le32(CRTC_INT_CNTL, 0x00000000, par);
251 aty_st_le32(TIMER_CONFIG, 0x00000000, par);
252 aty_st_le32(0xEC, 0x00000000, par);
253 aty_st_le32(0xFC, 0x00000000, par);
254
255 for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
256 aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, par);
257 }
258
259 aty_st_le16(CONFIG_STAT0, 0x00A4, par);
260 mdelay(10);
261
262 aty_st_8(BUS_CNTL+1, 0xA0, par);
263 mdelay(10);
264
265 reset_clocks(par, &pll.ct, 1);
266 mdelay(10);
267
268 // something about power management
269 aty_st_8(LCD_INDEX, 0x08, par);
270 aty_st_8(LCD_DATA, 0x0A, par);
271 aty_st_8(LCD_INDEX, 0x08, par);
272 aty_st_8(LCD_DATA+3, 0x02, par);
273 aty_st_8(LCD_INDEX, 0x08, par);
274 aty_st_8(LCD_DATA, 0x0B, par);
275 mdelay(2);
276
277 // enable display requests, enable CRTC
278 aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
279 // disable display
280 aty_st_8(CRTC_GEN_CNTL, 0x40, par);
281 // disable display requests, disable CRTC
282 aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
283 mdelay(10);
284
285 aty_st_pll_ct(PLL_YCLK_CNTL, 0x25, par);
286
287 aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, par);
288 aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, par);
289 aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, par);
290 aty_st_8(CUSTOM_MACRO_CNTL+1,
291 (card->custom_macro_cntl>>8) & 0xff, par);
292
293 aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, par);
294 aty_st_le32(MEM_CNTL, card->mem_cntl, par);
295 aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, par);
296
297 aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, par);
298
299 aty_st_pll_ct(PLL_YCLK_CNTL, 0x01, par);
300 mdelay(15);
301 aty_st_pll_ct(PLL_YCLK_CNTL, card->pll_yclk_cntl, par);
302 mdelay(1);
303
304 reset_clocks(par, &pll.ct, 0);
305 mdelay(50);
306 reset_clocks(par, &pll.ct, 0);
307 mdelay(50);
308
309 // enable extended register block
310 aty_st_8(BUS_CNTL+3, 0x7B, par);
311 mdelay(1);
312 // disable extended register block
313 aty_st_8(BUS_CNTL+3, 0x73, par);
314
315 aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, par);
316
317 // disable display requests, disable CRTC
318 aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
319 // disable mapping registers in VGA aperture
320 aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, par) & ~0x04, par);
321 mdelay(50);
322 // enable display requests, enable CRTC
323 aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
324
325 // make GPIO's 14,15,16 all inputs
326 aty_st_8(LCD_INDEX, 0x07, par);
327 aty_st_8(LCD_DATA+3, 0x00, par);
328
329 // enable the display
330 aty_st_8(CRTC_GEN_CNTL, 0x00, par);
331 mdelay(17);
332 // reset the memory controller
333 aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
334 mdelay(15);
335 aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
336 mdelay(30);
337
338 // enable extended register block
339 aty_st_8(BUS_CNTL+3,
340 (u8)(aty_ld_8(BUS_CNTL+3, par) | 0x08),
341 par);
342 // set FIFO size to 512 (PIO)
343 aty_st_le32(GUI_CNTL,
344 aty_ld_le32(GUI_CNTL, par) & ~0x3,
345 par);
346
347 // enable CRT and disable lcd
348 aty_st_8(LCD_INDEX, 0x01, par);
349 temp = aty_ld_le32(LCD_DATA, par);
350 temp = (temp | 0x01) & ~0x02;
351 aty_st_le32(LCD_DATA, temp, par);
352 return 0;
353}
354
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 01:19:02 -0400