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path: root/drivers/video/aty/radeonfb.h
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Diffstat (limited to 'drivers/video/aty/radeonfb.h')
-rw-r--r--drivers/video/aty/radeonfb.h53
1 files changed, 32 insertions, 21 deletions
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
index ccbfffd12805..ea0b5b47acaf 100644
--- a/drivers/video/aty/radeonfb.h
+++ b/drivers/video/aty/radeonfb.h
@@ -53,6 +53,7 @@ enum radeon_family {
53 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ 53 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
54 CHIP_FAMILY_R420, /* R420/R423/M18 */ 54 CHIP_FAMILY_R420, /* R420/R423/M18 */
55 CHIP_FAMILY_RC410, 55 CHIP_FAMILY_RC410,
56 CHIP_FAMILY_RS400,
56 CHIP_FAMILY_RS480, 57 CHIP_FAMILY_RS480,
57 CHIP_FAMILY_LAST, 58 CHIP_FAMILY_LAST,
58}; 59};
@@ -335,7 +336,15 @@ struct radeonfb_info {
335 int mon2_type; 336 int mon2_type;
336 u8 *mon2_EDID; 337 u8 *mon2_EDID;
337 338
338 u32 dp_gui_master_cntl; 339 /* accel bits */
340 u32 dp_gui_mc_base;
341 u32 dp_gui_mc_cache;
342 u32 dp_cntl_cache;
343 u32 dp_brush_fg_cache;
344 u32 dp_brush_bg_cache;
345 u32 dp_src_fg_cache;
346 u32 dp_src_bg_cache;
347 u32 fifo_free;
339 348
340 struct pll_info pll; 349 struct pll_info pll;
341 350
@@ -347,6 +356,7 @@ struct radeonfb_info {
347 int lock_blank; 356 int lock_blank;
348 int dynclk; 357 int dynclk;
349 int no_schedule; 358 int no_schedule;
359 int gfx_mode;
350 enum radeon_pm_mode pm_mode; 360 enum radeon_pm_mode pm_mode;
351 reinit_function_ptr reinit_func; 361 reinit_function_ptr reinit_func;
352 362
@@ -391,8 +401,14 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
391#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) 401#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
392#define INREG16(addr) readw((rinfo->mmio_base)+addr) 402#define INREG16(addr) readw((rinfo->mmio_base)+addr)
393#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) 403#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
404
405#ifdef CONFIG_PPC
406#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
407#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
408#else
394#define INREG(addr) readl((rinfo->mmio_base)+addr) 409#define INREG(addr) readl((rinfo->mmio_base)+addr)
395#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) 410#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
411#endif
396 412
397static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, 413static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
398 u32 val, u32 mask) 414 u32 val, u32 mask)
@@ -533,16 +549,25 @@ static inline u32 radeon_get_dstbpp(u16 depth)
533/* 549/*
534 * 2D Engine helper routines 550 * 2D Engine helper routines
535 */ 551 */
552
553extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries);
554
536static inline void radeon_engine_flush (struct radeonfb_info *rinfo) 555static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
537{ 556{
538 int i; 557 int i;
539 558
540 /* initiate flush */ 559 /* Initiate flush */
541 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, 560 OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
542 ~RB2D_DC_FLUSH_ALL); 561 ~RB2D_DC_FLUSH_ALL);
543 562
563 /* Ensure FIFO is empty, ie, make sure the flush commands
564 * has reached the cache
565 */
566 radeon_fifo_update_and_wait(rinfo, 64);
567
568 /* Wait for the flush to complete */
544 for (i=0; i < 2000000; i++) { 569 for (i=0; i < 2000000; i++) {
545 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) 570 if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
546 return; 571 return;
547 udelay(1); 572 udelay(1);
548 } 573 }
@@ -550,25 +575,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
550} 575}
551 576
552 577
553static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) 578static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
554{
555 int i;
556
557 for (i=0; i<2000000; i++) {
558 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
559 return;
560 udelay(1);
561 }
562 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
563}
564
565
566static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
567{ 579{
568 int i; 580 int i;
569 581
570 /* ensure FIFO is empty before waiting for idle */ 582 /* ensure FIFO is empty before waiting for idle */
571 _radeon_fifo_wait (rinfo, 64); 583 radeon_fifo_update_and_wait (rinfo, 64);
572 584
573 for (i=0; i<2000000; i++) { 585 for (i=0; i<2000000; i++) {
574 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { 586 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
@@ -581,8 +593,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
581} 593}
582 594
583 595
584#define radeon_engine_idle() _radeon_engine_idle(rinfo)
585#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
586#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) 596#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
587 597
588 598
@@ -612,6 +622,7 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
612extern int radeonfb_sync(struct fb_info *info); 622extern int radeonfb_sync(struct fb_info *info);
613extern void radeonfb_engine_init (struct radeonfb_info *rinfo); 623extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
614extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); 624extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
625extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
615 626
616/* Other functions */ 627/* Other functions */
617extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); 628extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);