diff options
Diffstat (limited to 'drivers/video/aty/radeonfb.h')
-rw-r--r-- | drivers/video/aty/radeonfb.h | 38 |
1 files changed, 21 insertions, 17 deletions
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h index 3ea1b00fdd22..ea0b5b47acaf 100644 --- a/drivers/video/aty/radeonfb.h +++ b/drivers/video/aty/radeonfb.h | |||
@@ -336,7 +336,15 @@ struct radeonfb_info { | |||
336 | int mon2_type; | 336 | int mon2_type; |
337 | u8 *mon2_EDID; | 337 | u8 *mon2_EDID; |
338 | 338 | ||
339 | u32 dp_gui_master_cntl; | 339 | /* accel bits */ |
340 | u32 dp_gui_mc_base; | ||
341 | u32 dp_gui_mc_cache; | ||
342 | u32 dp_cntl_cache; | ||
343 | u32 dp_brush_fg_cache; | ||
344 | u32 dp_brush_bg_cache; | ||
345 | u32 dp_src_fg_cache; | ||
346 | u32 dp_src_bg_cache; | ||
347 | u32 fifo_free; | ||
340 | 348 | ||
341 | struct pll_info pll; | 349 | struct pll_info pll; |
342 | 350 | ||
@@ -348,6 +356,7 @@ struct radeonfb_info { | |||
348 | int lock_blank; | 356 | int lock_blank; |
349 | int dynclk; | 357 | int dynclk; |
350 | int no_schedule; | 358 | int no_schedule; |
359 | int gfx_mode; | ||
351 | enum radeon_pm_mode pm_mode; | 360 | enum radeon_pm_mode pm_mode; |
352 | reinit_function_ptr reinit_func; | 361 | reinit_function_ptr reinit_func; |
353 | 362 | ||
@@ -392,8 +401,14 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) | |||
392 | #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) | 401 | #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) |
393 | #define INREG16(addr) readw((rinfo->mmio_base)+addr) | 402 | #define INREG16(addr) readw((rinfo->mmio_base)+addr) |
394 | #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) | 403 | #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) |
404 | |||
405 | #ifdef CONFIG_PPC | ||
406 | #define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); }) | ||
407 | #define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0) | ||
408 | #else | ||
395 | #define INREG(addr) readl((rinfo->mmio_base)+addr) | 409 | #define INREG(addr) readl((rinfo->mmio_base)+addr) |
396 | #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) | 410 | #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) |
411 | #endif | ||
397 | 412 | ||
398 | static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, | 413 | static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, |
399 | u32 val, u32 mask) | 414 | u32 val, u32 mask) |
@@ -535,17 +550,7 @@ static inline u32 radeon_get_dstbpp(u16 depth) | |||
535 | * 2D Engine helper routines | 550 | * 2D Engine helper routines |
536 | */ | 551 | */ |
537 | 552 | ||
538 | static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) | 553 | extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries); |
539 | { | ||
540 | int i; | ||
541 | |||
542 | for (i=0; i<2000000; i++) { | ||
543 | if ((INREG(RBBM_STATUS) & 0x7f) >= entries) | ||
544 | return; | ||
545 | udelay(1); | ||
546 | } | ||
547 | printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); | ||
548 | } | ||
549 | 554 | ||
550 | static inline void radeon_engine_flush (struct radeonfb_info *rinfo) | 555 | static inline void radeon_engine_flush (struct radeonfb_info *rinfo) |
551 | { | 556 | { |
@@ -558,7 +563,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) | |||
558 | /* Ensure FIFO is empty, ie, make sure the flush commands | 563 | /* Ensure FIFO is empty, ie, make sure the flush commands |
559 | * has reached the cache | 564 | * has reached the cache |
560 | */ | 565 | */ |
561 | _radeon_fifo_wait (rinfo, 64); | 566 | radeon_fifo_update_and_wait(rinfo, 64); |
562 | 567 | ||
563 | /* Wait for the flush to complete */ | 568 | /* Wait for the flush to complete */ |
564 | for (i=0; i < 2000000; i++) { | 569 | for (i=0; i < 2000000; i++) { |
@@ -570,12 +575,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) | |||
570 | } | 575 | } |
571 | 576 | ||
572 | 577 | ||
573 | static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) | 578 | static inline void radeon_engine_idle(struct radeonfb_info *rinfo) |
574 | { | 579 | { |
575 | int i; | 580 | int i; |
576 | 581 | ||
577 | /* ensure FIFO is empty before waiting for idle */ | 582 | /* ensure FIFO is empty before waiting for idle */ |
578 | _radeon_fifo_wait (rinfo, 64); | 583 | radeon_fifo_update_and_wait (rinfo, 64); |
579 | 584 | ||
580 | for (i=0; i<2000000; i++) { | 585 | for (i=0; i<2000000; i++) { |
581 | if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { | 586 | if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { |
@@ -588,8 +593,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) | |||
588 | } | 593 | } |
589 | 594 | ||
590 | 595 | ||
591 | #define radeon_engine_idle() _radeon_engine_idle(rinfo) | ||
592 | #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) | ||
593 | #define radeon_msleep(ms) _radeon_msleep(rinfo,ms) | 596 | #define radeon_msleep(ms) _radeon_msleep(rinfo,ms) |
594 | 597 | ||
595 | 598 | ||
@@ -619,6 +622,7 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image); | |||
619 | extern int radeonfb_sync(struct fb_info *info); | 622 | extern int radeonfb_sync(struct fb_info *info); |
620 | extern void radeonfb_engine_init (struct radeonfb_info *rinfo); | 623 | extern void radeonfb_engine_init (struct radeonfb_info *rinfo); |
621 | extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); | 624 | extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); |
625 | extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo); | ||
622 | 626 | ||
623 | /* Other functions */ | 627 | /* Other functions */ |
624 | extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); | 628 | extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); |