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path: root/drivers/video/aty/radeon_base.c
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Diffstat (limited to 'drivers/video/aty/radeon_base.c')
-rw-r--r--drivers/video/aty/radeon_base.c46
1 files changed, 15 insertions, 31 deletions
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index d5b27f9d374d..d0f1a7fc2c9d 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -282,8 +282,6 @@ static int backlight = 1;
282static int backlight = 0; 282static int backlight = 0;
283#endif 283#endif
284 284
285int accel_cexp = 0;
286
287/* 285/*
288 * prototypes 286 * prototypes
289 */ 287 */
@@ -854,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var,
854 if (rinfo->asleep) 852 if (rinfo->asleep)
855 return 0; 853 return 0;
856 854
855 radeon_fifo_wait(2);
857 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) 856 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
858 * var->bits_per_pixel / 8) & ~7); 857 * var->bits_per_pixel / 8) & ~7);
859 return 0; 858 return 0;
@@ -883,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
883 if (rc) 882 if (rc)
884 return rc; 883 return rc;
885 884
885 radeon_fifo_wait(2);
886 if (value & 0x01) { 886 if (value & 0x01) {
887 tmp = INREG(LVDS_GEN_CNTL); 887 tmp = INREG(LVDS_GEN_CNTL);
888 888
@@ -940,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
940 if (rinfo->lock_blank) 940 if (rinfo->lock_blank)
941 return 0; 941 return 0;
942 942
943 radeon_engine_idle(rinfo); 943 radeon_engine_idle();
944 944
945 val = INREG(CRTC_EXT_CNTL); 945 val = INREG(CRTC_EXT_CNTL);
946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | 946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
@@ -1048,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info)
1048 1048
1049 if (rinfo->asleep) 1049 if (rinfo->asleep)
1050 return 0; 1050 return 0;
1051 1051
1052 return radeon_screen_blank(rinfo, blank, 0); 1052 return radeon_screen_blank(rinfo, blank, 0);
1053} 1053}
1054 1054
@@ -1074,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1074 pindex = regno; 1074 pindex = regno;
1075 1075
1076 if (!rinfo->asleep) { 1076 if (!rinfo->asleep) {
1077 radeon_fifo_wait(9);
1078
1077 if (rinfo->bpp == 16) { 1079 if (rinfo->bpp == 16) {
1078 pindex = regno * 8; 1080 pindex = regno * 8;
1079 1081
@@ -1242,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
1242{ 1244{
1243 int i; 1245 int i;
1244 1246
1247 radeon_fifo_wait(20);
1248
1245 /* Workaround from XFree */ 1249 /* Workaround from XFree */
1246 if (rinfo->is_mobility) { 1250 if (rinfo->is_mobility) {
1247 /* A temporal workaround for the occational blanking on certain laptop 1251 /* A temporal workaround for the occational blanking on certain laptop
@@ -1337,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data)
1337{ 1341{
1338 struct radeonfb_info *rinfo = (struct radeonfb_info *)data; 1342 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1339 1343
1340 radeon_engine_idle(rinfo); 1344 radeon_engine_idle();
1341 1345
1342 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); 1346 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1343} 1347}
@@ -1355,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1355 if (nomodeset) 1359 if (nomodeset)
1356 return; 1360 return;
1357 1361
1358 radeon_engine_idle(rinfo);
1359
1360 if (!regs_only) 1362 if (!regs_only)
1361 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); 1363 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1362 1364
1365 radeon_fifo_wait(31);
1363 for (i=0; i<10; i++) 1366 for (i=0; i<10; i++)
1364 OUTREG(common_regs[i].reg, common_regs[i].val); 1367 OUTREG(common_regs[i].reg, common_regs[i].val);
1365 1368
@@ -1387,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1387 radeon_write_pll_regs(rinfo, mode); 1390 radeon_write_pll_regs(rinfo, mode);
1388 1391
1389 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1392 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1393 radeon_fifo_wait(10);
1390 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); 1394 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1391 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); 1395 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1392 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); 1396 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
@@ -1401,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1401 if (!regs_only) 1405 if (!regs_only)
1402 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); 1406 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1403 1407
1408 radeon_fifo_wait(2);
1404 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); 1409 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1405 1410
1406 return; 1411 return;
@@ -1551,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info)
1551 /* We always want engine to be idle on a mode switch, even 1556 /* We always want engine to be idle on a mode switch, even
1552 * if we won't actually change the mode 1557 * if we won't actually change the mode
1553 */ 1558 */
1554 radeon_engine_idle(rinfo); 1559 radeon_engine_idle();
1555 1560
1556 hSyncStart = mode->xres + mode->right_margin; 1561 hSyncStart = mode->xres + mode->right_margin;
1557 hSyncEnd = hSyncStart + mode->hsync_len; 1562 hSyncEnd = hSyncStart + mode->hsync_len;
@@ -1846,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info)
1846 return 0; 1851 return 0;
1847} 1852}
1848 1853
1854
1849static struct fb_ops radeonfb_ops = { 1855static struct fb_ops radeonfb_ops = {
1850 .owner = THIS_MODULE, 1856 .owner = THIS_MODULE,
1851 .fb_check_var = radeonfb_check_var, 1857 .fb_check_var = radeonfb_check_var,
@@ -1869,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1869 info->par = rinfo; 1875 info->par = rinfo;
1870 info->pseudo_palette = rinfo->pseudo_palette; 1876 info->pseudo_palette = rinfo->pseudo_palette;
1871 info->flags = FBINFO_DEFAULT 1877 info->flags = FBINFO_DEFAULT
1872 | FBINFO_HWACCEL_IMAGEBLIT
1873 | FBINFO_HWACCEL_COPYAREA 1878 | FBINFO_HWACCEL_COPYAREA
1874 | FBINFO_HWACCEL_FILLRECT 1879 | FBINFO_HWACCEL_FILLRECT
1875 | FBINFO_HWACCEL_XPAN 1880 | FBINFO_HWACCEL_XPAN
@@ -1877,7 +1882,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1877 info->fbops = &radeonfb_ops; 1882 info->fbops = &radeonfb_ops;
1878 info->screen_base = rinfo->fb_base; 1883 info->screen_base = rinfo->fb_base;
1879 info->screen_size = rinfo->mapped_vram; 1884 info->screen_size = rinfo->mapped_vram;
1880
1881 /* Fill fix common fields */ 1885 /* Fill fix common fields */
1882 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); 1886 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1883 info->fix.smem_start = rinfo->fb_base_phys; 1887 info->fix.smem_start = rinfo->fb_base_phys;
@@ -1892,25 +1896,8 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1892 info->fix.mmio_len = RADEON_REGSIZE; 1896 info->fix.mmio_len = RADEON_REGSIZE;
1893 info->fix.accel = FB_ACCEL_ATI_RADEON; 1897 info->fix.accel = FB_ACCEL_ATI_RADEON;
1894 1898
1895 /* Allocate colormap */
1896 fb_alloc_cmap(&info->cmap, 256, 0); 1899 fb_alloc_cmap(&info->cmap, 256, 0);
1897 1900
1898 /* Setup pixmap used for acceleration */
1899#define PIXMAP_SIZE (2048 * 4)
1900
1901 info->pixmap.addr = kmalloc(PIXMAP_SIZE, GFP_KERNEL);
1902 if (!info->pixmap.addr) {
1903 printk(KERN_ERR "radeonfb: Failed to allocate pixmap !\n");
1904 noaccel = 1;
1905 goto bail;
1906 }
1907 info->pixmap.size = PIXMAP_SIZE;
1908 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1909 info->pixmap.scan_align = 4;
1910 info->pixmap.buf_align = 4;
1911 info->pixmap.access_align = 32;
1912
1913bail:
1914 if (noaccel) 1901 if (noaccel)
1915 info->flags |= FBINFO_HWACCEL_DISABLED; 1902 info->flags |= FBINFO_HWACCEL_DISABLED;
1916 1903
@@ -2019,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
2019 u32 tom = INREG(NB_TOM); 2006 u32 tom = INREG(NB_TOM);
2020 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 2007 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2021 2008
2009 radeon_fifo_wait(6);
2022 OUTREG(MC_FB_LOCATION, tom); 2010 OUTREG(MC_FB_LOCATION, tom);
2023 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2011 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2024 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2012 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
@@ -2522,8 +2510,6 @@ static int __init radeonfb_setup (char *options)
2522 } else if (!strncmp(this_opt, "ignore_devlist", 14)) { 2510 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2523 ignore_devlist = 1; 2511 ignore_devlist = 1;
2524#endif 2512#endif
2525 } else if (!strncmp(this_opt, "accel_cexp", 12)) {
2526 accel_cexp = 1;
2527 } else 2513 } else
2528 mode_option = this_opt; 2514 mode_option = this_opt;
2529 } 2515 }
@@ -2571,8 +2557,6 @@ module_param(monitor_layout, charp, 0);
2571MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); 2557MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2572module_param(force_measure_pll, bool, 0); 2558module_param(force_measure_pll, bool, 0);
2573MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); 2559MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2574module_param(accel_cexp, bool, 0);
2575MODULE_PARM_DESC(accel_cexp, "Use acceleration engine for color expansion");
2576#ifdef CONFIG_MTRR 2560#ifdef CONFIG_MTRR
2577module_param(nomtrr, bool, 0); 2561module_param(nomtrr, bool, 0);
2578MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); 2562MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");