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path: root/drivers/video/aty/aty128fb.c
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Diffstat (limited to 'drivers/video/aty/aty128fb.c')
-rw-r--r--drivers/video/aty/aty128fb.c33
1 files changed, 19 insertions, 14 deletions
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c
index db16112cf197..e6e299feb51b 100644
--- a/drivers/video/aty/aty128fb.c
+++ b/drivers/video/aty/aty128fb.c
@@ -1475,7 +1475,7 @@ static int aty128fb_set_par(struct fb_info *info)
1475 aty128_set_pll(&par->pll, par); 1475 aty128_set_pll(&par->pll, par);
1476 aty128_set_fifo(&par->fifo_reg, par); 1476 aty128_set_fifo(&par->fifo_reg, par);
1477 1477
1478 config = aty_ld_le32(CONFIG_CNTL) & ~3; 1478 config = aty_ld_le32(CNFG_CNTL) & ~3;
1479 1479
1480#if defined(__BIG_ENDIAN) 1480#if defined(__BIG_ENDIAN)
1481 if (par->crtc.bpp == 32) 1481 if (par->crtc.bpp == 32)
@@ -1484,7 +1484,7 @@ static int aty128fb_set_par(struct fb_info *info)
1484 config |= 1; /* make aperture do 16 bit swapping */ 1484 config |= 1; /* make aperture do 16 bit swapping */
1485#endif 1485#endif
1486 1486
1487 aty_st_le32(CONFIG_CNTL, config); 1487 aty_st_le32(CNFG_CNTL, config);
1488 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ 1488 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1489 1489
1490 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; 1490 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
@@ -1875,7 +1875,7 @@ static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_i
1875 u32 dac; 1875 u32 dac;
1876 1876
1877 /* Get the chip revision */ 1877 /* Get the chip revision */
1878 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F; 1878 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1879 1879
1880 strcpy(video_card, "Rage128 XX "); 1880 strcpy(video_card, "Rage128 XX ");
1881 video_card[8] = ent->device >> 8; 1881 video_card[8] = ent->device >> 8;
@@ -2057,7 +2057,7 @@ static int __devinit aty128_probe(struct pci_dev *pdev, const struct pci_device_
2057 2057
2058 /* Grab memory size from the card */ 2058 /* Grab memory size from the card */
2059 // How does this relate to the resource length from the PCI hardware? 2059 // How does this relate to the resource length from the PCI hardware?
2060 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF; 2060 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2061 2061
2062 /* Virtualize the framebuffer */ 2062 /* Virtualize the framebuffer */
2063 info->screen_base = ioremap(fb_addr, par->vram_size); 2063 info->screen_base = ioremap(fb_addr, par->vram_size);
@@ -2374,6 +2374,8 @@ static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2374 /* Set the chip into the appropriate suspend mode (we use D2, 2374 /* Set the chip into the appropriate suspend mode (we use D2,
2375 * D3 would require a complete re-initialisation of the chip, 2375 * D3 would require a complete re-initialisation of the chip,
2376 * including PCI config registers, clocks, AGP configuration, ...) 2376 * including PCI config registers, clocks, AGP configuration, ...)
2377 *
2378 * For resume, the core will have already brought us back to D0
2377 */ 2379 */
2378 if (suspend) { 2380 if (suspend) {
2379 /* Make sure CRTC2 is reset. Remove that the day we decide to 2381 /* Make sure CRTC2 is reset. Remove that the day we decide to
@@ -2391,17 +2393,9 @@ static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2391 aty_st_le32(BUS_CNTL1, 0x00000010); 2393 aty_st_le32(BUS_CNTL1, 0x00000010);
2392 aty_st_le32(MEM_POWER_MISC, 0x0c830000); 2394 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2393 mdelay(100); 2395 mdelay(100);
2394 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command); 2396
2395 /* Switch PCI power management to D2 */ 2397 /* Switch PCI power management to D2 */
2396 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 2398 pci_set_power_state(pdev, PCI_D2);
2397 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2398 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2399 } else {
2400 /* Switch back PCI power management to D0 */
2401 mdelay(100);
2402 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2403 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2404 mdelay(100);
2405 } 2399 }
2406} 2400}
2407 2401
@@ -2410,6 +2404,12 @@ static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2410 struct fb_info *info = pci_get_drvdata(pdev); 2404 struct fb_info *info = pci_get_drvdata(pdev);
2411 struct aty128fb_par *par = info->par; 2405 struct aty128fb_par *par = info->par;
2412 2406
2407 /* Because we may change PCI D state ourselves, we need to
2408 * first save the config space content so the core can
2409 * restore it properly on resume.
2410 */
2411 pci_save_state(pdev);
2412
2413 /* We don't do anything but D2, for now we return 0, but 2413 /* We don't do anything but D2, for now we return 0, but
2414 * we may want to change that. How do we know if the BIOS 2414 * we may want to change that. How do we know if the BIOS
2415 * can properly take care of D3 ? Also, with swsusp, we 2415 * can properly take care of D3 ? Also, with swsusp, we
@@ -2476,6 +2476,11 @@ static int aty128_do_resume(struct pci_dev *pdev)
2476 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2476 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2477 return 0; 2477 return 0;
2478 2478
2479 /* PCI state will have been restored by the core, so
2480 * we should be in D0 now with our config space fully
2481 * restored
2482 */
2483
2479 /* Wakeup chip */ 2484 /* Wakeup chip */
2480 aty128_set_suspend(par, 0); 2485 aty128_set_suspend(par, 0);
2481 par->asleep = 0; 2486 par->asleep = 0;