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path: root/drivers/video/atmel_lcdfb.c
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Diffstat (limited to 'drivers/video/atmel_lcdfb.c')
-rw-r--r--drivers/video/atmel_lcdfb.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 8ffdf3578768..b004036d4087 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -441,14 +441,15 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
441 441
442 value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock)); 442 value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
443 443
444 value = (value / 2) - 1; 444 if (value < 2) {
445 dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", value);
446
447 if (value <= 0) {
448 dev_notice(info->device, "Bypassing pixel clock divider\n"); 445 dev_notice(info->device, "Bypassing pixel clock divider\n");
449 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); 446 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
450 } else { 447 } else {
451 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET); 448 value = (value / 2) - 1;
449 dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n",
450 value);
451 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
452 value << ATMEL_LCDC_CLKVAL_OFFSET);
452 info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1))); 453 info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1)));
453 dev_dbg(info->device, " updated pixclk: %lu KHz\n", 454 dev_dbg(info->device, " updated pixclk: %lu KHz\n",
454 PICOS2KHZ(info->var.pixclock)); 455 PICOS2KHZ(info->var.pixclock));