diff options
Diffstat (limited to 'drivers/video/arkfb.c')
-rw-r--r-- | drivers/video/arkfb.c | 160 |
1 files changed, 96 insertions, 64 deletions
diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 391ac939f011..8686429cbdf0 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c | |||
@@ -158,12 +158,19 @@ static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map) | |||
158 | } | 158 | } |
159 | } | 159 | } |
160 | 160 | ||
161 | static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) | ||
162 | { | ||
163 | struct arkfb_info *par = info->par; | ||
164 | |||
165 | svga_tilecursor(par->state.vgabase, info, cursor); | ||
166 | } | ||
167 | |||
161 | static struct fb_tile_ops arkfb_tile_ops = { | 168 | static struct fb_tile_ops arkfb_tile_ops = { |
162 | .fb_settile = arkfb_settile, | 169 | .fb_settile = arkfb_settile, |
163 | .fb_tilecopy = svga_tilecopy, | 170 | .fb_tilecopy = svga_tilecopy, |
164 | .fb_tilefill = svga_tilefill, | 171 | .fb_tilefill = svga_tilefill, |
165 | .fb_tileblit = svga_tileblit, | 172 | .fb_tileblit = svga_tileblit, |
166 | .fb_tilecursor = svga_tilecursor, | 173 | .fb_tilecursor = arkfb_tilecursor, |
167 | .fb_get_tilemax = svga_get_tilemax, | 174 | .fb_get_tilemax = svga_get_tilemax, |
168 | }; | 175 | }; |
169 | 176 | ||
@@ -466,32 +473,40 @@ static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7}; | |||
466 | 473 | ||
467 | static void ark_dac_read_regs(void *data, u8 *code, int count) | 474 | static void ark_dac_read_regs(void *data, u8 *code, int count) |
468 | { | 475 | { |
469 | u8 regval = vga_rseq(NULL, 0x1C); | 476 | struct fb_info *info = data; |
477 | struct arkfb_info *par; | ||
478 | u8 regval; | ||
470 | 479 | ||
480 | par = info->par; | ||
481 | regval = vga_rseq(par->state.vgabase, 0x1C); | ||
471 | while (count != 0) | 482 | while (count != 0) |
472 | { | 483 | { |
473 | vga_wseq(NULL, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); | 484 | vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); |
474 | code[1] = vga_r(NULL, dac_regs[code[0] & 3]); | 485 | code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]); |
475 | count--; | 486 | count--; |
476 | code += 2; | 487 | code += 2; |
477 | } | 488 | } |
478 | 489 | ||
479 | vga_wseq(NULL, 0x1C, regval); | 490 | vga_wseq(par->state.vgabase, 0x1C, regval); |
480 | } | 491 | } |
481 | 492 | ||
482 | static void ark_dac_write_regs(void *data, u8 *code, int count) | 493 | static void ark_dac_write_regs(void *data, u8 *code, int count) |
483 | { | 494 | { |
484 | u8 regval = vga_rseq(NULL, 0x1C); | 495 | struct fb_info *info = data; |
496 | struct arkfb_info *par; | ||
497 | u8 regval; | ||
485 | 498 | ||
499 | par = info->par; | ||
500 | regval = vga_rseq(par->state.vgabase, 0x1C); | ||
486 | while (count != 0) | 501 | while (count != 0) |
487 | { | 502 | { |
488 | vga_wseq(NULL, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); | 503 | vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); |
489 | vga_w(NULL, dac_regs[code[0] & 3], code[1]); | 504 | vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]); |
490 | count--; | 505 | count--; |
491 | code += 2; | 506 | code += 2; |
492 | } | 507 | } |
493 | 508 | ||
494 | vga_wseq(NULL, 0x1C, regval); | 509 | vga_wseq(par->state.vgabase, 0x1C, regval); |
495 | } | 510 | } |
496 | 511 | ||
497 | 512 | ||
@@ -507,8 +522,8 @@ static void ark_set_pixclock(struct fb_info *info, u32 pixclock) | |||
507 | } | 522 | } |
508 | 523 | ||
509 | /* Set VGA misc register */ | 524 | /* Set VGA misc register */ |
510 | regval = vga_r(NULL, VGA_MIS_R); | 525 | regval = vga_r(par->state.vgabase, VGA_MIS_R); |
511 | vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); | 526 | vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); |
512 | } | 527 | } |
513 | 528 | ||
514 | 529 | ||
@@ -520,7 +535,10 @@ static int arkfb_open(struct fb_info *info, int user) | |||
520 | 535 | ||
521 | mutex_lock(&(par->open_lock)); | 536 | mutex_lock(&(par->open_lock)); |
522 | if (par->ref_count == 0) { | 537 | if (par->ref_count == 0) { |
538 | void __iomem *vgabase = par->state.vgabase; | ||
539 | |||
523 | memset(&(par->state), 0, sizeof(struct vgastate)); | 540 | memset(&(par->state), 0, sizeof(struct vgastate)); |
541 | par->state.vgabase = vgabase; | ||
524 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; | 542 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; |
525 | par->state.num_crtc = 0x60; | 543 | par->state.num_crtc = 0x60; |
526 | par->state.num_seq = 0x30; | 544 | par->state.num_seq = 0x30; |
@@ -646,50 +664,50 @@ static int arkfb_set_par(struct fb_info *info) | |||
646 | info->var.activate = FB_ACTIVATE_NOW; | 664 | info->var.activate = FB_ACTIVATE_NOW; |
647 | 665 | ||
648 | /* Unlock registers */ | 666 | /* Unlock registers */ |
649 | svga_wcrt_mask(0x11, 0x00, 0x80); | 667 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); |
650 | 668 | ||
651 | /* Blank screen and turn off sync */ | 669 | /* Blank screen and turn off sync */ |
652 | svga_wseq_mask(0x01, 0x20, 0x20); | 670 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
653 | svga_wcrt_mask(0x17, 0x00, 0x80); | 671 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); |
654 | 672 | ||
655 | /* Set default values */ | 673 | /* Set default values */ |
656 | svga_set_default_gfx_regs(); | 674 | svga_set_default_gfx_regs(par->state.vgabase); |
657 | svga_set_default_atc_regs(); | 675 | svga_set_default_atc_regs(par->state.vgabase); |
658 | svga_set_default_seq_regs(); | 676 | svga_set_default_seq_regs(par->state.vgabase); |
659 | svga_set_default_crt_regs(); | 677 | svga_set_default_crt_regs(par->state.vgabase); |
660 | svga_wcrt_multi(ark_line_compare_regs, 0xFFFFFFFF); | 678 | svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF); |
661 | svga_wcrt_multi(ark_start_address_regs, 0); | 679 | svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0); |
662 | 680 | ||
663 | /* ARK specific initialization */ | 681 | /* ARK specific initialization */ |
664 | svga_wseq_mask(0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */ | 682 | svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */ |
665 | svga_wseq_mask(0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */ | 683 | svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */ |
666 | 684 | ||
667 | vga_wseq(NULL, 0x13, info->fix.smem_start >> 16); | 685 | vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16); |
668 | vga_wseq(NULL, 0x14, info->fix.smem_start >> 24); | 686 | vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24); |
669 | vga_wseq(NULL, 0x15, 0); | 687 | vga_wseq(par->state.vgabase, 0x15, 0); |
670 | vga_wseq(NULL, 0x16, 0); | 688 | vga_wseq(par->state.vgabase, 0x16, 0); |
671 | 689 | ||
672 | /* Set the FIFO threshold register */ | 690 | /* Set the FIFO threshold register */ |
673 | /* It is fascinating way to store 5-bit value in 8-bit register */ | 691 | /* It is fascinating way to store 5-bit value in 8-bit register */ |
674 | regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1; | 692 | regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1; |
675 | vga_wseq(NULL, 0x18, regval); | 693 | vga_wseq(par->state.vgabase, 0x18, regval); |
676 | 694 | ||
677 | /* Set the offset register */ | 695 | /* Set the offset register */ |
678 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); | 696 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); |
679 | svga_wcrt_multi(ark_offset_regs, offset_value); | 697 | svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value); |
680 | 698 | ||
681 | /* fix for hi-res textmode */ | 699 | /* fix for hi-res textmode */ |
682 | svga_wcrt_mask(0x40, 0x08, 0x08); | 700 | svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); |
683 | 701 | ||
684 | if (info->var.vmode & FB_VMODE_DOUBLE) | 702 | if (info->var.vmode & FB_VMODE_DOUBLE) |
685 | svga_wcrt_mask(0x09, 0x80, 0x80); | 703 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); |
686 | else | 704 | else |
687 | svga_wcrt_mask(0x09, 0x00, 0x80); | 705 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); |
688 | 706 | ||
689 | if (info->var.vmode & FB_VMODE_INTERLACED) | 707 | if (info->var.vmode & FB_VMODE_INTERLACED) |
690 | svga_wcrt_mask(0x44, 0x04, 0x04); | 708 | svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04); |
691 | else | 709 | else |
692 | svga_wcrt_mask(0x44, 0x00, 0x04); | 710 | svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04); |
693 | 711 | ||
694 | hmul = 1; | 712 | hmul = 1; |
695 | hdiv = 1; | 713 | hdiv = 1; |
@@ -699,40 +717,40 @@ static int arkfb_set_par(struct fb_info *info) | |||
699 | switch (mode) { | 717 | switch (mode) { |
700 | case 0: | 718 | case 0: |
701 | pr_debug("fb%d: text mode\n", info->node); | 719 | pr_debug("fb%d: text mode\n", info->node); |
702 | svga_set_textmode_vga_regs(); | 720 | svga_set_textmode_vga_regs(par->state.vgabase); |
703 | 721 | ||
704 | vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ | 722 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ |
705 | svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */ | 723 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ |
706 | dac_set_mode(par->dac, DAC_PSEUDO8_8); | 724 | dac_set_mode(par->dac, DAC_PSEUDO8_8); |
707 | 725 | ||
708 | break; | 726 | break; |
709 | case 1: | 727 | case 1: |
710 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | 728 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); |
711 | vga_wgfx(NULL, VGA_GFX_MODE, 0x40); | 729 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
712 | 730 | ||
713 | vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ | 731 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ |
714 | svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */ | 732 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ |
715 | dac_set_mode(par->dac, DAC_PSEUDO8_8); | 733 | dac_set_mode(par->dac, DAC_PSEUDO8_8); |
716 | break; | 734 | break; |
717 | case 2: | 735 | case 2: |
718 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); | 736 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); |
719 | 737 | ||
720 | vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */ | 738 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ |
721 | svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */ | 739 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ |
722 | dac_set_mode(par->dac, DAC_PSEUDO8_8); | 740 | dac_set_mode(par->dac, DAC_PSEUDO8_8); |
723 | break; | 741 | break; |
724 | case 3: | 742 | case 3: |
725 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); | 743 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); |
726 | 744 | ||
727 | vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode */ | 745 | vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */ |
728 | 746 | ||
729 | if (info->var.pixclock > 20000) { | 747 | if (info->var.pixclock > 20000) { |
730 | pr_debug("fb%d: not using multiplex\n", info->node); | 748 | pr_debug("fb%d: not using multiplex\n", info->node); |
731 | svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */ | 749 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ |
732 | dac_set_mode(par->dac, DAC_PSEUDO8_8); | 750 | dac_set_mode(par->dac, DAC_PSEUDO8_8); |
733 | } else { | 751 | } else { |
734 | pr_debug("fb%d: using multiplex\n", info->node); | 752 | pr_debug("fb%d: using multiplex\n", info->node); |
735 | svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ | 753 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
736 | dac_set_mode(par->dac, DAC_PSEUDO8_16); | 754 | dac_set_mode(par->dac, DAC_PSEUDO8_16); |
737 | hdiv = 2; | 755 | hdiv = 2; |
738 | } | 756 | } |
@@ -740,22 +758,22 @@ static int arkfb_set_par(struct fb_info *info) | |||
740 | case 4: | 758 | case 4: |
741 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); | 759 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); |
742 | 760 | ||
743 | vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */ | 761 | vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ |
744 | svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ | 762 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
745 | dac_set_mode(par->dac, DAC_RGB1555_16); | 763 | dac_set_mode(par->dac, DAC_RGB1555_16); |
746 | break; | 764 | break; |
747 | case 5: | 765 | case 5: |
748 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); | 766 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); |
749 | 767 | ||
750 | vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */ | 768 | vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ |
751 | svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ | 769 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
752 | dac_set_mode(par->dac, DAC_RGB0565_16); | 770 | dac_set_mode(par->dac, DAC_RGB0565_16); |
753 | break; | 771 | break; |
754 | case 6: | 772 | case 6: |
755 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); | 773 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); |
756 | 774 | ||
757 | vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode ??? */ | 775 | vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */ |
758 | svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ | 776 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
759 | dac_set_mode(par->dac, DAC_RGB0888_16); | 777 | dac_set_mode(par->dac, DAC_RGB0888_16); |
760 | hmul = 3; | 778 | hmul = 3; |
761 | hdiv = 2; | 779 | hdiv = 2; |
@@ -763,8 +781,8 @@ static int arkfb_set_par(struct fb_info *info) | |||
763 | case 7: | 781 | case 7: |
764 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); | 782 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); |
765 | 783 | ||
766 | vga_wseq(NULL, 0x11, 0x1E); /* 32bpp accel mode */ | 784 | vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */ |
767 | svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */ | 785 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
768 | dac_set_mode(par->dac, DAC_RGB8888_16); | 786 | dac_set_mode(par->dac, DAC_RGB8888_16); |
769 | hmul = 2; | 787 | hmul = 2; |
770 | break; | 788 | break; |
@@ -774,7 +792,7 @@ static int arkfb_set_par(struct fb_info *info) | |||
774 | } | 792 | } |
775 | 793 | ||
776 | ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul); | 794 | ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul); |
777 | svga_set_timings(&ark_timing_regs, &(info->var), hmul, hdiv, | 795 | svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv, |
778 | (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, | 796 | (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, |
779 | (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, | 797 | (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, |
780 | hmul, info->node); | 798 | hmul, info->node); |
@@ -782,12 +800,12 @@ static int arkfb_set_par(struct fb_info *info) | |||
782 | /* Set interlaced mode start/end register */ | 800 | /* Set interlaced mode start/end register */ |
783 | value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; | 801 | value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; |
784 | value = ((value * hmul / hdiv) / 8) - 5; | 802 | value = ((value * hmul / hdiv) / 8) - 5; |
785 | vga_wcrt(NULL, 0x42, (value + 1) / 2); | 803 | vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2); |
786 | 804 | ||
787 | memset_io(info->screen_base, 0x00, screen_size); | 805 | memset_io(info->screen_base, 0x00, screen_size); |
788 | /* Device and screen back on */ | 806 | /* Device and screen back on */ |
789 | svga_wcrt_mask(0x17, 0x80, 0x80); | 807 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
790 | svga_wseq_mask(0x01, 0x00, 0x20); | 808 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
791 | 809 | ||
792 | return 0; | 810 | return 0; |
793 | } | 811 | } |
@@ -857,23 +875,25 @@ static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |||
857 | 875 | ||
858 | static int arkfb_blank(int blank_mode, struct fb_info *info) | 876 | static int arkfb_blank(int blank_mode, struct fb_info *info) |
859 | { | 877 | { |
878 | struct arkfb_info *par = info->par; | ||
879 | |||
860 | switch (blank_mode) { | 880 | switch (blank_mode) { |
861 | case FB_BLANK_UNBLANK: | 881 | case FB_BLANK_UNBLANK: |
862 | pr_debug("fb%d: unblank\n", info->node); | 882 | pr_debug("fb%d: unblank\n", info->node); |
863 | svga_wseq_mask(0x01, 0x00, 0x20); | 883 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
864 | svga_wcrt_mask(0x17, 0x80, 0x80); | 884 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
865 | break; | 885 | break; |
866 | case FB_BLANK_NORMAL: | 886 | case FB_BLANK_NORMAL: |
867 | pr_debug("fb%d: blank\n", info->node); | 887 | pr_debug("fb%d: blank\n", info->node); |
868 | svga_wseq_mask(0x01, 0x20, 0x20); | 888 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
869 | svga_wcrt_mask(0x17, 0x80, 0x80); | 889 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
870 | break; | 890 | break; |
871 | case FB_BLANK_POWERDOWN: | 891 | case FB_BLANK_POWERDOWN: |
872 | case FB_BLANK_HSYNC_SUSPEND: | 892 | case FB_BLANK_HSYNC_SUSPEND: |
873 | case FB_BLANK_VSYNC_SUSPEND: | 893 | case FB_BLANK_VSYNC_SUSPEND: |
874 | pr_debug("fb%d: sync down\n", info->node); | 894 | pr_debug("fb%d: sync down\n", info->node); |
875 | svga_wseq_mask(0x01, 0x20, 0x20); | 895 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
876 | svga_wcrt_mask(0x17, 0x00, 0x80); | 896 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); |
877 | break; | 897 | break; |
878 | } | 898 | } |
879 | return 0; | 899 | return 0; |
@@ -884,6 +904,7 @@ static int arkfb_blank(int blank_mode, struct fb_info *info) | |||
884 | 904 | ||
885 | static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | 905 | static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
886 | { | 906 | { |
907 | struct arkfb_info *par = info->par; | ||
887 | unsigned int offset; | 908 | unsigned int offset; |
888 | 909 | ||
889 | /* Calculate the offset */ | 910 | /* Calculate the offset */ |
@@ -897,7 +918,7 @@ static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info | |||
897 | } | 918 | } |
898 | 919 | ||
899 | /* Set the offset */ | 920 | /* Set the offset */ |
900 | svga_wcrt_multi(ark_start_address_regs, offset); | 921 | svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset); |
901 | 922 | ||
902 | return 0; | 923 | return 0; |
903 | } | 924 | } |
@@ -930,6 +951,8 @@ static struct fb_ops arkfb_ops = { | |||
930 | /* PCI probe */ | 951 | /* PCI probe */ |
931 | static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | 952 | static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) |
932 | { | 953 | { |
954 | struct pci_bus_region bus_reg; | ||
955 | struct resource vga_res; | ||
933 | struct fb_info *info; | 956 | struct fb_info *info; |
934 | struct arkfb_info *par; | 957 | struct arkfb_info *par; |
935 | int rc; | 958 | int rc; |
@@ -985,8 +1008,17 @@ static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_ | |||
985 | goto err_iomap; | 1008 | goto err_iomap; |
986 | } | 1009 | } |
987 | 1010 | ||
1011 | bus_reg.start = 0; | ||
1012 | bus_reg.end = 64 * 1024; | ||
1013 | |||
1014 | vga_res.flags = IORESOURCE_IO; | ||
1015 | |||
1016 | pcibios_bus_to_resource(dev, &vga_res, &bus_reg); | ||
1017 | |||
1018 | par->state.vgabase = (void __iomem *) vga_res.start; | ||
1019 | |||
988 | /* FIXME get memsize */ | 1020 | /* FIXME get memsize */ |
989 | regval = vga_rseq(NULL, 0x10); | 1021 | regval = vga_rseq(par->state.vgabase, 0x10); |
990 | info->screen_size = (1 << (regval >> 6)) << 20; | 1022 | info->screen_size = (1 << (regval >> 6)) << 20; |
991 | info->fix.smem_len = info->screen_size; | 1023 | info->fix.smem_len = info->screen_size; |
992 | 1024 | ||