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-rw-r--r--drivers/usb/gadget/pxa2xx_udc.c30
1 files changed, 0 insertions, 30 deletions
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c
index 63b9521c1322..72b4ebbf132d 100644
--- a/drivers/usb/gadget/pxa2xx_udc.c
+++ b/drivers/usb/gadget/pxa2xx_udc.c
@@ -93,8 +93,6 @@ static const char driver_name [] = "pxa2xx_udc";
93static const char ep0name [] = "ep0"; 93static const char ep0name [] = "ep0";
94 94
95 95
96// #define DISABLE_TEST_MODE
97
98#ifdef CONFIG_ARCH_IXP4XX 96#ifdef CONFIG_ARCH_IXP4XX
99 97
100/* cpu-specific register addresses are compiled in to this code */ 98/* cpu-specific register addresses are compiled in to this code */
@@ -113,17 +111,6 @@ static const char ep0name [] = "ep0";
113#define SIZE_STR "" 111#define SIZE_STR ""
114#endif 112#endif
115 113
116#ifdef DISABLE_TEST_MODE
117/* (mode == 0) == no undocumented chip tweaks
118 * (mode & 1) == double buffer bulk IN
119 * (mode & 2) == double buffer bulk OUT
120 * ... so mode = 3 (or 7, 15, etc) does it for both
121 */
122static ushort fifo_mode = 0;
123module_param(fifo_mode, ushort, 0);
124MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
125#endif
126
127/* --------------------------------------------------------------------------- 114/* ---------------------------------------------------------------------------
128 * endpoint related parts of the api to the usb controller hardware, 115 * endpoint related parts of the api to the usb controller hardware,
129 * used by gadget driver; and the inner talker-to-hardware core. 116 * used by gadget driver; and the inner talker-to-hardware core.
@@ -1252,23 +1239,6 @@ static void udc_enable (struct pxa2xx_udc *dev)
1252 UDC_RES2 = 0x00; 1239 UDC_RES2 = 0x00;
1253 } 1240 }
1254 1241
1255#ifdef DISABLE_TEST_MODE
1256 /* "test mode" seems to have become the default in later chip
1257 * revs, preventing double buffering (and invalidating docs).
1258 * this EXPERIMENT enables it for bulk endpoints by tweaking
1259 * undefined/reserved register bits (that other drivers clear).
1260 * Belcarra code comments noted this usage.
1261 */
1262 if (fifo_mode & 1) { /* IN endpoints */
1263 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1264 UDC_RES2 |= USIR1_IR11;
1265 }
1266 if (fifo_mode & 2) { /* OUT endpoints */
1267 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1268 UDC_RES2 |= USIR1_IR12;
1269 }
1270#endif
1271
1272 /* enable suspend/resume and reset irqs */ 1242 /* enable suspend/resume and reset irqs */
1273 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM); 1243 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1274 1244