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-rw-r--r--drivers/usb/Kconfig2
-rw-r--r--drivers/usb/gadget/Kconfig10
-rw-r--r--drivers/usb/musb/Kconfig176
-rw-r--r--drivers/usb/musb/Makefile86
-rw-r--r--drivers/usb/musb/cppi_dma.c1540
-rw-r--r--drivers/usb/musb/cppi_dma.h133
-rw-r--r--drivers/usb/musb/davinci.c462
-rw-r--r--drivers/usb/musb/davinci.h100
-rw-r--r--drivers/usb/musb/musb_core.c2266
-rw-r--r--drivers/usb/musb/musb_core.h517
-rw-r--r--drivers/usb/musb/musb_debug.h66
-rw-r--r--drivers/usb/musb/musb_dma.h172
-rw-r--r--drivers/usb/musb/musb_gadget.c2033
-rw-r--r--drivers/usb/musb/musb_gadget.h108
-rw-r--r--drivers/usb/musb/musb_gadget_ep0.c981
-rw-r--r--drivers/usb/musb/musb_host.c2170
-rw-r--r--drivers/usb/musb/musb_host.h110
-rw-r--r--drivers/usb/musb/musb_io.h115
-rw-r--r--drivers/usb/musb/musb_procfs.c830
-rw-r--r--drivers/usb/musb/musb_regs.h300
-rw-r--r--drivers/usb/musb/musb_virthub.c425
-rw-r--r--drivers/usb/musb/musbhsdma.c433
-rw-r--r--drivers/usb/musb/omap2430.c324
-rw-r--r--drivers/usb/musb/omap2430.h56
-rw-r--r--drivers/usb/musb/tusb6010.c1151
-rw-r--r--drivers/usb/musb/tusb6010.h402
-rw-r--r--drivers/usb/musb/tusb6010_omap.c719
27 files changed, 15687 insertions, 0 deletions
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 4f9b5ecfb721..bcefbddeba50 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -99,6 +99,8 @@ source "drivers/usb/mon/Kconfig"
99 99
100source "drivers/usb/host/Kconfig" 100source "drivers/usb/host/Kconfig"
101 101
102source "drivers/usb/musb/Kconfig"
103
102source "drivers/usb/class/Kconfig" 104source "drivers/usb/class/Kconfig"
103 105
104source "drivers/usb/storage/Kconfig" 106source "drivers/usb/storage/Kconfig"
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index c6a8c6b1116a..acc95b2ac6f8 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -284,6 +284,16 @@ config USB_LH7A40X
284 default USB_GADGET 284 default USB_GADGET
285 select USB_GADGET_SELECTED 285 select USB_GADGET_SELECTED
286 286
287# built in ../musb along with host support
288config USB_GADGET_MUSB_HDRC
289 boolean "Inventra HDRC USB Peripheral (TI, ...)"
290 depends on USB_MUSB_HDRC && (USB_MUSB_PERIPHERAL || USB_MUSB_OTG)
291 select USB_GADGET_DUALSPEED
292 select USB_GADGET_SELECTED
293 help
294 This OTG-capable silicon IP is used in dual designs including
295 the TI DaVinci, OMAP 243x, OMAP 343x, and TUSB 6010.
296
287config USB_GADGET_OMAP 297config USB_GADGET_OMAP
288 boolean "OMAP USB Device Controller" 298 boolean "OMAP USB Device Controller"
289 depends on ARCH_OMAP 299 depends on ARCH_OMAP
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
new file mode 100644
index 000000000000..faca4333f27a
--- /dev/null
+++ b/drivers/usb/musb/Kconfig
@@ -0,0 +1,176 @@
1#
2# USB Dual Role (OTG-ready) Controller Drivers
3# for silicon based on Mentor Graphics INVENTRA designs
4#
5
6comment "Enable Host or Gadget support to see Inventra options"
7 depends on !USB && USB_GADGET=n
8
9# (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
10config USB_MUSB_HDRC
11 depends on (USB || USB_GADGET) && HAVE_CLK
12 select TWL4030_USB if MACH_OMAP_3430SDP
13 tristate 'Inventra Highspeed Dual Role Controller (TI, ...)'
14 help
15 Say Y here if your system has a dual role high speed USB
16 controller based on the Mentor Graphics silicon IP. Then
17 configure options to match your silicon and the board
18 it's being used with, including the USB peripheral role,
19 or the USB host role, or both.
20
21 Texas Instruments parts using this IP include DaVinci 644x,
22 OMAP 243x, OMAP 343x, and TUSB 6010.
23
24 If you do not know what this is, please say N.
25
26 To compile this driver as a module, choose M here; the
27 module will be called "musb_hdrc".
28
29config USB_MUSB_SOC
30 boolean
31 depends on USB_MUSB_HDRC
32 default y if ARCH_DAVINCI
33 default y if ARCH_OMAP2430
34 default y if ARCH_OMAP34XX
35 help
36 Use a static <asm/arch/hdrc_cnf.h> file to describe how the
37 controller is configured (endpoints, mechanisms, etc) on the
38 current iteration of a given system-on-chip.
39
40comment "DaVinci 644x USB support"
41 depends on USB_MUSB_HDRC && ARCH_DAVINCI
42
43comment "OMAP 243x high speed USB support"
44 depends on USB_MUSB_HDRC && ARCH_OMAP2430
45
46comment "OMAP 343x high speed USB support"
47 depends on USB_MUSB_HDRC && ARCH_OMAP34XX
48
49config USB_TUSB6010
50 boolean "TUSB 6010 support"
51 depends on USB_MUSB_HDRC && !USB_MUSB_SOC
52 default y
53 help
54 The TUSB 6010 chip, from Texas Instruments, connects a discrete
55 HDRC core using a 16-bit parallel bus (NOR flash style) or VLYNQ
56 (a high speed serial link). It can use system-specific external
57 DMA controllers.
58
59choice
60 prompt "Driver Mode"
61 depends on USB_MUSB_HDRC
62 help
63 Dual-Role devices can support both host and peripheral roles,
64 as well as a the special "OTG Device" role which can switch
65 between both roles as needed.
66
67# use USB_MUSB_HDRC_HCD not USB_MUSB_HOST to #ifdef host side support;
68# OTG needs both roles, not just USB_MUSB_HOST.
69config USB_MUSB_HOST
70 depends on USB
71 bool "USB Host"
72 help
73 Say Y here if your system supports the USB host role.
74 If it has a USB "A" (rectangular), "Mini-A" (uncommon),
75 or "Mini-AB" connector, it supports the host role.
76 (With a "Mini-AB" connector, you should enable USB OTG.)
77
78# use USB_GADGET_MUSB_HDRC not USB_MUSB_PERIPHERAL to #ifdef peripheral
79# side support ... OTG needs both roles
80config USB_MUSB_PERIPHERAL
81 depends on USB_GADGET
82 bool "USB Peripheral (gadget stack)"
83 select USB_GADGET_MUSB_HDRC
84 help
85 Say Y here if your system supports the USB peripheral role.
86 If it has a USB "B" (squarish), "Mini-B", or "Mini-AB"
87 connector, it supports the peripheral role.
88 (With a "Mini-AB" connector, you should enable USB OTG.)
89
90config USB_MUSB_OTG
91 depends on USB && USB_GADGET && PM && EXPERIMENTAL
92 bool "Both host and peripheral: USB OTG (On The Go) Device"
93 select USB_GADGET_MUSB_HDRC
94 select USB_OTG
95 help
96 The most notable feature of USB OTG is support for a
97 "Dual-Role" device, which can act as either a device
98 or a host. The initial role choice can be changed
99 later, when two dual-role devices talk to each other.
100
101 At this writing, the OTG support in this driver is incomplete,
102 omitting the mandatory HNP or SRP protocols. However, some
103 of the cable based role switching works. (That is, grounding
104 the ID pin switches the controller to host mode, while leaving
105 it floating leaves it in peripheral mode.)
106
107 Select this if your system has a Mini-AB connector, or
108 to simplify certain kinds of configuration.
109
110 To implement your OTG Targeted Peripherals List (TPL), enable
111 USB_OTG_WHITELIST and update "drivers/usb/core/otg_whitelist.h"
112 to match your requirements.
113
114endchoice
115
116# enable peripheral support (including with OTG)
117config USB_GADGET_MUSB_HDRC
118 bool
119 depends on USB_MUSB_HDRC && (USB_MUSB_PERIPHERAL || USB_MUSB_OTG)
120# default y
121# select USB_GADGET_DUALSPEED
122# select USB_GADGET_SELECTED
123
124# enables host support (including with OTG)
125config USB_MUSB_HDRC_HCD
126 bool
127 depends on USB_MUSB_HDRC && (USB_MUSB_HOST || USB_MUSB_OTG)
128 select USB_OTG if USB_GADGET_MUSB_HDRC
129 default y
130
131
132config MUSB_PIO_ONLY
133 bool 'Disable DMA (always use PIO)'
134 depends on USB_MUSB_HDRC
135 default y if USB_TUSB6010
136 help
137 All data is copied between memory and FIFO by the CPU.
138 DMA controllers are ignored.
139
140 Do not select 'n' here unless DMA support for your SOC or board
141 is unavailable (or unstable). When DMA is enabled at compile time,
142 you can still disable it at run time using the "use_dma=n" module
143 parameter.
144
145config USB_INVENTRA_DMA
146 bool
147 depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
148 default ARCH_OMAP2430 || ARCH_OMAP34XX
149 help
150 Enable DMA transfers using Mentor's engine.
151
152config USB_TI_CPPI_DMA
153 bool
154 depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
155 default ARCH_DAVINCI
156 help
157 Enable DMA transfers when TI CPPI DMA is available.
158
159config USB_TUSB_OMAP_DMA
160 bool
161 depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
162 depends on USB_TUSB6010
163 depends on ARCH_OMAP
164 default y
165 help
166 Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
167
168config USB_MUSB_LOGLEVEL
169 depends on USB_MUSB_HDRC
170 int 'Logging Level (0 - none / 3 - annoying / ... )'
171 default 0
172 help
173 Set the logging level. 0 disables the debugging altogether,
174 although when USB_DEBUG is set the value is at least 1.
175 Starting at level 3, per-transfer (urb, usb_request, packet,
176 or dma transfer) tracing may kick in.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
new file mode 100644
index 000000000000..88eb67de08ae
--- /dev/null
+++ b/drivers/usb/musb/Makefile
@@ -0,0 +1,86 @@
1#
2# for USB OTG silicon based on Mentor Graphics INVENTRA designs
3#
4
5musb_hdrc-objs := musb_core.o
6
7obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
8
9ifeq ($(CONFIG_ARCH_DAVINCI),y)
10 musb_hdrc-objs += davinci.o
11endif
12
13ifeq ($(CONFIG_USB_TUSB6010),y)
14 musb_hdrc-objs += tusb6010.o
15endif
16
17ifeq ($(CONFIG_ARCH_OMAP2430),y)
18 musb_hdrc-objs += omap2430.o
19endif
20
21ifeq ($(CONFIG_ARCH_OMAP3430),y)
22 musb_hdrc-objs += omap2430.o
23endif
24
25ifeq ($(CONFIG_USB_GADGET_MUSB_HDRC),y)
26 musb_hdrc-objs += musb_gadget_ep0.o musb_gadget.o
27endif
28
29ifeq ($(CONFIG_USB_MUSB_HDRC_HCD),y)
30 musb_hdrc-objs += musb_virthub.o musb_host.o
31endif
32
33# the kconfig must guarantee that only one of the
34# possible I/O schemes will be enabled at a time ...
35# PIO only, or DMA (several potential schemes).
36# though PIO is always there to back up DMA, and for ep0
37
38ifneq ($(CONFIG_MUSB_PIO_ONLY),y)
39
40 ifeq ($(CONFIG_USB_INVENTRA_DMA),y)
41 musb_hdrc-objs += musbhsdma.o
42
43 else
44 ifeq ($(CONFIG_USB_TI_CPPI_DMA),y)
45 musb_hdrc-objs += cppi_dma.o
46
47 else
48 ifeq ($(CONFIG_USB_TUSB_OMAP_DMA),y)
49 musb_hdrc-objs += tusb6010_omap.o
50
51 endif
52 endif
53 endif
54endif
55
56
57################################################################################
58
59# FIXME remove all these extra "-DMUSB_* things, stick to CONFIG_*
60
61ifeq ($(CONFIG_USB_INVENTRA_MUSB_HAS_AHB_ID),y)
62 EXTRA_CFLAGS += -DMUSB_AHB_ID
63endif
64
65# Debugging
66
67MUSB_DEBUG:=$(CONFIG_USB_MUSB_LOGLEVEL)
68
69ifeq ("$(strip $(MUSB_DEBUG))","")
70 ifdef CONFIG_USB_DEBUG
71 MUSB_DEBUG:=1
72 else
73 MUSB_DEBUG:=0
74 endif
75endif
76
77ifneq ($(MUSB_DEBUG),0)
78 EXTRA_CFLAGS += -DDEBUG
79
80 ifeq ($(CONFIG_PROC_FS),y)
81 musb_hdrc-objs += musb_procfs.o
82 endif
83
84endif
85
86EXTRA_CFLAGS += -DMUSB_DEBUG=$(MUSB_DEBUG)
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
new file mode 100644
index 000000000000..5ad6d0893cbe
--- /dev/null
+++ b/drivers/usb/musb/cppi_dma.c
@@ -0,0 +1,1540 @@
1/*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * This file implements a DMA interface using TI's CPPI DMA.
5 * For now it's DaVinci-only, but CPPI isn't specific to DaVinci or USB.
6 * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci.
7 */
8
9#include <linux/usb.h>
10
11#include "musb_core.h"
12#include "cppi_dma.h"
13
14
15/* CPPI DMA status 7-mar-2006:
16 *
17 * - See musb_{host,gadget}.c for more info
18 *
19 * - Correct RX DMA generally forces the engine into irq-per-packet mode,
20 * which can easily saturate the CPU under non-mass-storage loads.
21 *
22 * NOTES 24-aug-2006 (2.6.18-rc4):
23 *
24 * - peripheral RXDMA wedged in a test with packets of length 512/512/1.
25 * evidently after the 1 byte packet was received and acked, the queue
26 * of BDs got garbaged so it wouldn't empty the fifo. (rxcsr 0x2003,
27 * and RX DMA0: 4 left, 80000000 8feff880, 8feff860 8feff860; 8f321401
28 * 004001ff 00000001 .. 8feff860) Host was just getting NAKed on tx
29 * of its next (512 byte) packet. IRQ issues?
30 *
31 * REVISIT: the "transfer DMA" glue between CPPI and USB fifos will
32 * evidently also directly update the RX and TX CSRs ... so audit all
33 * host and peripheral side DMA code to avoid CSR access after DMA has
34 * been started.
35 */
36
37/* REVISIT now we can avoid preallocating these descriptors; or
38 * more simply, switch to a global freelist not per-channel ones.
39 * Note: at full speed, 64 descriptors == 4K bulk data.
40 */
41#define NUM_TXCHAN_BD 64
42#define NUM_RXCHAN_BD 64
43
44static inline void cpu_drain_writebuffer(void)
45{
46 wmb();
47#ifdef CONFIG_CPU_ARM926T
48 /* REVISIT this "should not be needed",
49 * but lack of it sure seemed to hurt ...
50 */
51 asm("mcr p15, 0, r0, c7, c10, 4 @ drain write buffer\n");
52#endif
53}
54
55static inline struct cppi_descriptor *cppi_bd_alloc(struct cppi_channel *c)
56{
57 struct cppi_descriptor *bd = c->freelist;
58
59 if (bd)
60 c->freelist = bd->next;
61 return bd;
62}
63
64static inline void
65cppi_bd_free(struct cppi_channel *c, struct cppi_descriptor *bd)
66{
67 if (!bd)
68 return;
69 bd->next = c->freelist;
70 c->freelist = bd;
71}
72
73/*
74 * Start DMA controller
75 *
76 * Initialize the DMA controller as necessary.
77 */
78
79/* zero out entire rx state RAM entry for the channel */
80static void cppi_reset_rx(struct cppi_rx_stateram __iomem *rx)
81{
82 musb_writel(&rx->rx_skipbytes, 0, 0);
83 musb_writel(&rx->rx_head, 0, 0);
84 musb_writel(&rx->rx_sop, 0, 0);
85 musb_writel(&rx->rx_current, 0, 0);
86 musb_writel(&rx->rx_buf_current, 0, 0);
87 musb_writel(&rx->rx_len_len, 0, 0);
88 musb_writel(&rx->rx_cnt_cnt, 0, 0);
89}
90
91/* zero out entire tx state RAM entry for the channel */
92static void cppi_reset_tx(struct cppi_tx_stateram __iomem *tx, u32 ptr)
93{
94 musb_writel(&tx->tx_head, 0, 0);
95 musb_writel(&tx->tx_buf, 0, 0);
96 musb_writel(&tx->tx_current, 0, 0);
97 musb_writel(&tx->tx_buf_current, 0, 0);
98 musb_writel(&tx->tx_info, 0, 0);
99 musb_writel(&tx->tx_rem_len, 0, 0);
100 /* musb_writel(&tx->tx_dummy, 0, 0); */
101 musb_writel(&tx->tx_complete, 0, ptr);
102}
103
104static void __init cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
105{
106 int j;
107
108 /* initialize channel fields */
109 c->head = NULL;
110 c->tail = NULL;
111 c->last_processed = NULL;
112 c->channel.status = MUSB_DMA_STATUS_UNKNOWN;
113 c->controller = cppi;
114 c->is_rndis = 0;
115 c->freelist = NULL;
116
117 /* build the BD Free list for the channel */
118 for (j = 0; j < NUM_TXCHAN_BD + 1; j++) {
119 struct cppi_descriptor *bd;
120 dma_addr_t dma;
121
122 bd = dma_pool_alloc(cppi->pool, GFP_KERNEL, &dma);
123 bd->dma = dma;
124 cppi_bd_free(c, bd);
125 }
126}
127
128static int cppi_channel_abort(struct dma_channel *);
129
130static void cppi_pool_free(struct cppi_channel *c)
131{
132 struct cppi *cppi = c->controller;
133 struct cppi_descriptor *bd;
134
135 (void) cppi_channel_abort(&c->channel);
136 c->channel.status = MUSB_DMA_STATUS_UNKNOWN;
137 c->controller = NULL;
138
139 /* free all its bds */
140 bd = c->last_processed;
141 do {
142 if (bd)
143 dma_pool_free(cppi->pool, bd, bd->dma);
144 bd = cppi_bd_alloc(c);
145 } while (bd);
146 c->last_processed = NULL;
147}
148
149static int __init cppi_controller_start(struct dma_controller *c)
150{
151 struct cppi *controller;
152 void __iomem *tibase;
153 int i;
154
155 controller = container_of(c, struct cppi, controller);
156
157 /* do whatever is necessary to start controller */
158 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
159 controller->tx[i].transmit = true;
160 controller->tx[i].index = i;
161 }
162 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) {
163 controller->rx[i].transmit = false;
164 controller->rx[i].index = i;
165 }
166
167 /* setup BD list on a per channel basis */
168 for (i = 0; i < ARRAY_SIZE(controller->tx); i++)
169 cppi_pool_init(controller, controller->tx + i);
170 for (i = 0; i < ARRAY_SIZE(controller->rx); i++)
171 cppi_pool_init(controller, controller->rx + i);
172
173 tibase = controller->tibase;
174 INIT_LIST_HEAD(&controller->tx_complete);
175
176 /* initialise tx/rx channel head pointers to zero */
177 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
178 struct cppi_channel *tx_ch = controller->tx + i;
179 struct cppi_tx_stateram __iomem *tx;
180
181 INIT_LIST_HEAD(&tx_ch->tx_complete);
182
183 tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i);
184 tx_ch->state_ram = tx;
185 cppi_reset_tx(tx, 0);
186 }
187 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) {
188 struct cppi_channel *rx_ch = controller->rx + i;
189 struct cppi_rx_stateram __iomem *rx;
190
191 INIT_LIST_HEAD(&rx_ch->tx_complete);
192
193 rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i);
194 rx_ch->state_ram = rx;
195 cppi_reset_rx(rx);
196 }
197
198 /* enable individual cppi channels */
199 musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
200 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
201 musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG,
202 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
203
204 /* enable tx/rx CPPI control */
205 musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
206 musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
207
208 /* disable RNDIS mode, also host rx RNDIS autorequest */
209 musb_writel(tibase, DAVINCI_RNDIS_REG, 0);
210 musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0);
211
212 return 0;
213}
214
215/*
216 * Stop DMA controller
217 *
218 * De-Init the DMA controller as necessary.
219 */
220
221static int cppi_controller_stop(struct dma_controller *c)
222{
223 struct cppi *controller;
224 void __iomem *tibase;
225 int i;
226
227 controller = container_of(c, struct cppi, controller);
228
229 tibase = controller->tibase;
230 /* DISABLE INDIVIDUAL CHANNEL Interrupts */
231 musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,
232 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
233 musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
234 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
235
236 DBG(1, "Tearing down RX and TX Channels\n");
237 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
238 /* FIXME restructure of txdma to use bds like rxdma */
239 controller->tx[i].last_processed = NULL;
240 cppi_pool_free(controller->tx + i);
241 }
242 for (i = 0; i < ARRAY_SIZE(controller->rx); i++)
243 cppi_pool_free(controller->rx + i);
244
245 /* in Tx Case proper teardown is supported. We resort to disabling
246 * Tx/Rx CPPI after cleanup of Tx channels. Before TX teardown is
247 * complete TX CPPI cannot be disabled.
248 */
249 /*disable tx/rx cppi */
250 musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
251 musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
252
253 return 0;
254}
255
256/* While dma channel is allocated, we only want the core irqs active
257 * for fault reports, otherwise we'd get irqs that we don't care about.
258 * Except for TX irqs, where dma done != fifo empty and reusable ...
259 *
260 * NOTE: docs don't say either way, but irq masking **enables** irqs.
261 *
262 * REVISIT same issue applies to pure PIO usage too, and non-cppi dma...
263 */
264static inline void core_rxirq_disable(void __iomem *tibase, unsigned epnum)
265{
266 musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8));
267}
268
269static inline void core_rxirq_enable(void __iomem *tibase, unsigned epnum)
270{
271 musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8));
272}
273
274
275/*
276 * Allocate a CPPI Channel for DMA. With CPPI, channels are bound to
277 * each transfer direction of a non-control endpoint, so allocating
278 * (and deallocating) is mostly a way to notice bad housekeeping on
279 * the software side. We assume the irqs are always active.
280 */
281static struct dma_channel *
282cppi_channel_allocate(struct dma_controller *c,
283 struct musb_hw_ep *ep, u8 transmit)
284{
285 struct cppi *controller;
286 u8 index;
287 struct cppi_channel *cppi_ch;
288 void __iomem *tibase;
289
290 controller = container_of(c, struct cppi, controller);
291 tibase = controller->tibase;
292
293 /* ep0 doesn't use DMA; remember cppi indices are 0..N-1 */
294 index = ep->epnum - 1;
295
296 /* return the corresponding CPPI Channel Handle, and
297 * probably disable the non-CPPI irq until we need it.
298 */
299 if (transmit) {
300 if (index >= ARRAY_SIZE(controller->tx)) {
301 DBG(1, "no %cX%d CPPI channel\n", 'T', index);
302 return NULL;
303 }
304 cppi_ch = controller->tx + index;
305 } else {
306 if (index >= ARRAY_SIZE(controller->rx)) {
307 DBG(1, "no %cX%d CPPI channel\n", 'R', index);
308 return NULL;
309 }
310 cppi_ch = controller->rx + index;
311 core_rxirq_disable(tibase, ep->epnum);
312 }
313
314 /* REVISIT make this an error later once the same driver code works
315 * with the other DMA engine too
316 */
317 if (cppi_ch->hw_ep)
318 DBG(1, "re-allocating DMA%d %cX channel %p\n",
319 index, transmit ? 'T' : 'R', cppi_ch);
320 cppi_ch->hw_ep = ep;
321 cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
322
323 DBG(4, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
324 return &cppi_ch->channel;
325}
326
327/* Release a CPPI Channel. */
328static void cppi_channel_release(struct dma_channel *channel)
329{
330 struct cppi_channel *c;
331 void __iomem *tibase;
332
333 /* REVISIT: for paranoia, check state and abort if needed... */
334
335 c = container_of(channel, struct cppi_channel, channel);
336 tibase = c->controller->tibase;
337 if (!c->hw_ep)
338 DBG(1, "releasing idle DMA channel %p\n", c);
339 else if (!c->transmit)
340 core_rxirq_enable(tibase, c->index + 1);
341
342 /* for now, leave its cppi IRQ enabled (we won't trigger it) */
343 c->hw_ep = NULL;
344 channel->status = MUSB_DMA_STATUS_UNKNOWN;
345}
346
347/* Context: controller irqlocked */
348static void
349cppi_dump_rx(int level, struct cppi_channel *c, const char *tag)
350{
351 void __iomem *base = c->controller->mregs;
352 struct cppi_rx_stateram __iomem *rx = c->state_ram;
353
354 musb_ep_select(base, c->index + 1);
355
356 DBG(level, "RX DMA%d%s: %d left, csr %04x, "
357 "%08x H%08x S%08x C%08x, "
358 "B%08x L%08x %08x .. %08x"
359 "\n",
360 c->index, tag,
361 musb_readl(c->controller->tibase,
362 DAVINCI_RXCPPI_BUFCNT0_REG + 4 * c->index),
363 musb_readw(c->hw_ep->regs, MUSB_RXCSR),
364
365 musb_readl(&rx->rx_skipbytes, 0),
366 musb_readl(&rx->rx_head, 0),
367 musb_readl(&rx->rx_sop, 0),
368 musb_readl(&rx->rx_current, 0),
369
370 musb_readl(&rx->rx_buf_current, 0),
371 musb_readl(&rx->rx_len_len, 0),
372 musb_readl(&rx->rx_cnt_cnt, 0),
373 musb_readl(&rx->rx_complete, 0)
374 );
375}
376
377/* Context: controller irqlocked */
378static void
379cppi_dump_tx(int level, struct cppi_channel *c, const char *tag)
380{
381 void __iomem *base = c->controller->mregs;
382 struct cppi_tx_stateram __iomem *tx = c->state_ram;
383
384 musb_ep_select(base, c->index + 1);
385
386 DBG(level, "TX DMA%d%s: csr %04x, "
387 "H%08x S%08x C%08x %08x, "
388 "F%08x L%08x .. %08x"
389 "\n",
390 c->index, tag,
391 musb_readw(c->hw_ep->regs, MUSB_TXCSR),
392
393 musb_readl(&tx->tx_head, 0),
394 musb_readl(&tx->tx_buf, 0),
395 musb_readl(&tx->tx_current, 0),
396 musb_readl(&tx->tx_buf_current, 0),
397
398 musb_readl(&tx->tx_info, 0),
399 musb_readl(&tx->tx_rem_len, 0),
400 /* dummy/unused word 6 */
401 musb_readl(&tx->tx_complete, 0)
402 );
403}
404
405/* Context: controller irqlocked */
406static inline void
407cppi_rndis_update(struct cppi_channel *c, int is_rx,
408 void __iomem *tibase, int is_rndis)
409{
410 /* we may need to change the rndis flag for this cppi channel */
411 if (c->is_rndis != is_rndis) {
412 u32 value = musb_readl(tibase, DAVINCI_RNDIS_REG);
413 u32 temp = 1 << (c->index);
414
415 if (is_rx)
416 temp <<= 16;
417 if (is_rndis)
418 value |= temp;
419 else
420 value &= ~temp;
421 musb_writel(tibase, DAVINCI_RNDIS_REG, value);
422 c->is_rndis = is_rndis;
423 }
424}
425
426static void cppi_dump_rxbd(const char *tag, struct cppi_descriptor *bd)
427{
428 pr_debug("RXBD/%s %08x: "
429 "nxt %08x buf %08x off.blen %08x opt.plen %08x\n",
430 tag, bd->dma,
431 bd->hw_next, bd->hw_bufp, bd->hw_off_len,
432 bd->hw_options);
433}
434
435static void cppi_dump_rxq(int level, const char *tag, struct cppi_channel *rx)
436{
437#if MUSB_DEBUG > 0
438 struct cppi_descriptor *bd;
439
440 if (!_dbg_level(level))
441 return;
442 cppi_dump_rx(level, rx, tag);
443 if (rx->last_processed)
444 cppi_dump_rxbd("last", rx->last_processed);
445 for (bd = rx->head; bd; bd = bd->next)
446 cppi_dump_rxbd("active", bd);
447#endif
448}
449
450
451/* NOTE: DaVinci autoreq is ignored except for host side "RNDIS" mode RX;
452 * so we won't ever use it (see "CPPI RX Woes" below).
453 */
454static inline int cppi_autoreq_update(struct cppi_channel *rx,
455 void __iomem *tibase, int onepacket, unsigned n_bds)
456{
457 u32 val;
458
459#ifdef RNDIS_RX_IS_USABLE
460 u32 tmp;
461 /* assert(is_host_active(musb)) */
462
463 /* start from "AutoReq never" */
464 tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
465 val = tmp & ~((0x3) << (rx->index * 2));
466
467 /* HCD arranged reqpkt for packet #1. we arrange int
468 * for all but the last one, maybe in two segments.
469 */
470 if (!onepacket) {
471#if 0
472 /* use two segments, autoreq "all" then the last "never" */
473 val |= ((0x3) << (rx->index * 2));
474 n_bds--;
475#else
476 /* one segment, autoreq "all-but-last" */
477 val |= ((0x1) << (rx->index * 2));
478#endif
479 }
480
481 if (val != tmp) {
482 int n = 100;
483
484 /* make sure that autoreq is updated before continuing */
485 musb_writel(tibase, DAVINCI_AUTOREQ_REG, val);
486 do {
487 tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
488 if (tmp == val)
489 break;
490 cpu_relax();
491 } while (n-- > 0);
492 }
493#endif
494
495 /* REQPKT is turned off after each segment */
496 if (n_bds && rx->channel.actual_len) {
497 void __iomem *regs = rx->hw_ep->regs;
498
499 val = musb_readw(regs, MUSB_RXCSR);
500 if (!(val & MUSB_RXCSR_H_REQPKT)) {
501 val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
502 musb_writew(regs, MUSB_RXCSR, val);
503 /* flush writebufer */
504 val = musb_readw(regs, MUSB_RXCSR);
505 }
506 }
507 return n_bds;
508}
509
510
511/* Buffer enqueuing Logic:
512 *
513 * - RX builds new queues each time, to help handle routine "early
514 * termination" cases (faults, including errors and short reads)
515 * more correctly.
516 *
517 * - for now, TX reuses the same queue of BDs every time
518 *
519 * REVISIT long term, we want a normal dynamic model.
520 * ... the goal will be to append to the
521 * existing queue, processing completed "dma buffers" (segments) on the fly.
522 *
523 * Otherwise we force an IRQ latency between requests, which slows us a lot
524 * (especially in "transparent" dma). Unfortunately that model seems to be
525 * inherent in the DMA model from the Mentor code, except in the rare case
526 * of transfers big enough (~128+ KB) that we could append "middle" segments
527 * in the TX paths. (RX can't do this, see below.)
528 *
529 * That's true even in the CPPI- friendly iso case, where most urbs have
530 * several small segments provided in a group and where the "packet at a time"
531 * "transparent" DMA model is always correct, even on the RX side.
532 */
533
534/*
535 * CPPI TX:
536 * ========
537 * TX is a lot more reasonable than RX; it doesn't need to run in
538 * irq-per-packet mode very often. RNDIS mode seems to behave too
539 * (except how it handles the exactly-N-packets case). Building a
540 * txdma queue with multiple requests (urb or usb_request) looks
541 * like it would work ... but fault handling would need much testing.
542 *
543 * The main issue with TX mode RNDIS relates to transfer lengths that
544 * are an exact multiple of the packet length. It appears that there's
545 * a hiccup in that case (maybe the DMA completes before the ZLP gets
546 * written?) boiling down to not being able to rely on CPPI writing any
547 * terminating zero length packet before the next transfer is written.
548 * So that's punted to PIO; better yet, gadget drivers can avoid it.
549 *
550 * Plus, there's allegedly an undocumented constraint that rndis transfer
551 * length be a multiple of 64 bytes ... but the chip doesn't act that
552 * way, and we really don't _want_ that behavior anyway.
553 *
554 * On TX, "transparent" mode works ... although experiments have shown
555 * problems trying to use the SOP/EOP bits in different USB packets.
556 *
557 * REVISIT try to handle terminating zero length packets using CPPI
558 * instead of doing it by PIO after an IRQ. (Meanwhile, make Ethernet
559 * links avoid that issue by forcing them to avoid zlps.)
560 */
561static void
562cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
563{
564 unsigned maxpacket = tx->maxpacket;
565 dma_addr_t addr = tx->buf_dma + tx->offset;
566 size_t length = tx->buf_len - tx->offset;
567 struct cppi_descriptor *bd;
568 unsigned n_bds;
569 unsigned i;
570 struct cppi_tx_stateram __iomem *tx_ram = tx->state_ram;
571 int rndis;
572
573 /* TX can use the CPPI "rndis" mode, where we can probably fit this
574 * transfer in one BD and one IRQ. The only time we would NOT want
575 * to use it is when hardware constraints prevent it, or if we'd
576 * trigger the "send a ZLP?" confusion.
577 */
578 rndis = (maxpacket & 0x3f) == 0
579 && length < 0xffff
580 && (length % maxpacket) != 0;
581
582 if (rndis) {
583 maxpacket = length;
584 n_bds = 1;
585 } else {
586 n_bds = length / maxpacket;
587 if (!length || (length % maxpacket))
588 n_bds++;
589 n_bds = min(n_bds, (unsigned) NUM_TXCHAN_BD);
590 length = min(n_bds * maxpacket, length);
591 }
592
593 DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%x len %u\n",
594 tx->index,
595 maxpacket,
596 rndis ? "rndis" : "transparent",
597 n_bds,
598 addr, length);
599
600 cppi_rndis_update(tx, 0, musb->ctrl_base, rndis);
601
602 /* assuming here that channel_program is called during
603 * transfer initiation ... current code maintains state
604 * for one outstanding request only (no queues, not even
605 * the implicit ones of an iso urb).
606 */
607
608 bd = tx->freelist;
609 tx->head = bd;
610 tx->last_processed = NULL;
611
612 /* FIXME use BD pool like RX side does, and just queue
613 * the minimum number for this request.
614 */
615
616 /* Prepare queue of BDs first, then hand it to hardware.
617 * All BDs except maybe the last should be of full packet
618 * size; for RNDIS there _is_ only that last packet.
619 */
620 for (i = 0; i < n_bds; ) {
621 if (++i < n_bds && bd->next)
622 bd->hw_next = bd->next->dma;
623 else
624 bd->hw_next = 0;
625
626 bd->hw_bufp = tx->buf_dma + tx->offset;
627
628 /* FIXME set EOP only on the last packet,
629 * SOP only on the first ... avoid IRQs
630 */
631 if ((tx->offset + maxpacket) <= tx->buf_len) {
632 tx->offset += maxpacket;
633 bd->hw_off_len = maxpacket;
634 bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET
635 | CPPI_OWN_SET | maxpacket;
636 } else {
637 /* only this one may be a partial USB Packet */
638 u32 partial_len;
639
640 partial_len = tx->buf_len - tx->offset;
641 tx->offset = tx->buf_len;
642 bd->hw_off_len = partial_len;
643
644 bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET
645 | CPPI_OWN_SET | partial_len;
646 if (partial_len == 0)
647 bd->hw_options |= CPPI_ZERO_SET;
648 }
649
650 DBG(5, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
651 bd, bd->hw_next, bd->hw_bufp,
652 bd->hw_off_len, bd->hw_options);
653
654 /* update the last BD enqueued to the list */
655 tx->tail = bd;
656 bd = bd->next;
657 }
658
659 /* BDs live in DMA-coherent memory, but writes might be pending */
660 cpu_drain_writebuffer();
661
662 /* Write to the HeadPtr in state RAM to trigger */
663 musb_writel(&tx_ram->tx_head, 0, (u32)tx->freelist->dma);
664
665 cppi_dump_tx(5, tx, "/S");
666}
667
668/*
669 * CPPI RX Woes:
670 * =============
671 * Consider a 1KB bulk RX buffer in two scenarios: (a) it's fed two 300 byte
672 * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back.
673 * (Full speed transfers have similar scenarios.)
674 *
675 * The correct behavior for Linux is that (a) fills the buffer with 300 bytes,
676 * and the next packet goes into a buffer that's queued later; while (b) fills
677 * the buffer with 1024 bytes. How to do that with CPPI?
678 *
679 * - RX queues in "rndis" mode -- one single BD -- handle (a) correctly, but
680 * (b) loses **BADLY** because nothing (!) happens when that second packet
681 * fills the buffer, much less when a third one arrives. (Which makes this
682 * not a "true" RNDIS mode. In the RNDIS protocol short-packet termination
683 * is optional, and it's fine if peripherals -- not hosts! -- pad messages
684 * out to end-of-buffer. Standard PCI host controller DMA descriptors
685 * implement that mode by default ... which is no accident.)
686 *
687 * - RX queues in "transparent" mode -- two BDs with 512 bytes each -- have
688 * converse problems: (b) is handled right, but (a) loses badly. CPPI RX
689 * ignores SOP/EOP markings and processes both of those BDs; so both packets
690 * are loaded into the buffer (with a 212 byte gap between them), and the next
691 * buffer queued will NOT get its 300 bytes of data. (It seems like SOP/EOP
692 * are intended as outputs for RX queues, not inputs...)
693 *
694 * - A variant of "transparent" mode -- one BD at a time -- is the only way to
695 * reliably make both cases work, with software handling both cases correctly
696 * and at the significant penalty of needing an IRQ per packet. (The lack of
697 * I/O overlap can be slightly ameliorated by enabling double buffering.)
698 *
699 * So how to get rid of IRQ-per-packet? The transparent multi-BD case could
700 * be used in special cases like mass storage, which sets URB_SHORT_NOT_OK
701 * (or maybe its peripheral side counterpart) to flag (a) scenarios as errors
702 * with guaranteed driver level fault recovery and scrubbing out what's left
703 * of that garbaged datastream.
704 *
705 * But there seems to be no way to identify the cases where CPPI RNDIS mode
706 * is appropriate -- which do NOT include RNDIS host drivers, but do include
707 * the CDC Ethernet driver! -- and the documentation is incomplete/wrong.
708 * So we can't _ever_ use RX RNDIS mode ... except by using a heuristic
709 * that applies best on the peripheral side (and which could fail rudely).
710 *
711 * Leaving only "transparent" mode; we avoid multi-bd modes in almost all
712 * cases other than mass storage class. Otherwise we're correct but slow,
713 * since CPPI penalizes our need for a "true RNDIS" default mode.
714 */
715
716
717/* Heuristic, intended to kick in for ethernet/rndis peripheral ONLY
718 *
719 * IFF
720 * (a) peripheral mode ... since rndis peripherals could pad their
721 * writes to hosts, causing i/o failure; or we'd have to cope with
722 * a largely unknowable variety of host side protocol variants
723 * (b) and short reads are NOT errors ... since full reads would
724 * cause those same i/o failures
725 * (c) and read length is
726 * - less than 64KB (max per cppi descriptor)
727 * - not a multiple of 4096 (g_zero default, full reads typical)
728 * - N (>1) packets long, ditto (full reads not EXPECTED)
729 * THEN
730 * try rx rndis mode
731 *
732 * Cost of heuristic failing: RXDMA wedges at the end of transfers that
733 * fill out the whole buffer. Buggy host side usb network drivers could
734 * trigger that, but "in the field" such bugs seem to be all but unknown.
735 *
736 * So this module parameter lets the heuristic be disabled. When using
737 * gadgetfs, the heuristic will probably need to be disabled.
738 */
739static int cppi_rx_rndis = 1;
740
741module_param(cppi_rx_rndis, bool, 0);
742MODULE_PARM_DESC(cppi_rx_rndis, "enable/disable RX RNDIS heuristic");
743
744
745/**
746 * cppi_next_rx_segment - dma read for the next chunk of a buffer
747 * @musb: the controller
748 * @rx: dma channel
749 * @onepacket: true unless caller treats short reads as errors, and
750 * performs fault recovery above usbcore.
751 * Context: controller irqlocked
752 *
753 * See above notes about why we can't use multi-BD RX queues except in
754 * rare cases (mass storage class), and can never use the hardware "rndis"
755 * mode (since it's not a "true" RNDIS mode) with complete safety..
756 *
757 * It's ESSENTIAL that callers specify "onepacket" mode unless they kick in
758 * code to recover from corrupted datastreams after each short transfer.
759 */
760static void
761cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
762{
763 unsigned maxpacket = rx->maxpacket;
764 dma_addr_t addr = rx->buf_dma + rx->offset;
765 size_t length = rx->buf_len - rx->offset;
766 struct cppi_descriptor *bd, *tail;
767 unsigned n_bds;
768 unsigned i;
769 void __iomem *tibase = musb->ctrl_base;
770 int is_rndis = 0;
771 struct cppi_rx_stateram __iomem *rx_ram = rx->state_ram;
772
773 if (onepacket) {
774 /* almost every USB driver, host or peripheral side */
775 n_bds = 1;
776
777 /* maybe apply the heuristic above */
778 if (cppi_rx_rndis
779 && is_peripheral_active(musb)
780 && length > maxpacket
781 && (length & ~0xffff) == 0
782 && (length & 0x0fff) != 0
783 && (length & (maxpacket - 1)) == 0) {
784 maxpacket = length;
785 is_rndis = 1;
786 }
787 } else {
788 /* virtually nothing except mass storage class */
789 if (length > 0xffff) {
790 n_bds = 0xffff / maxpacket;
791 length = n_bds * maxpacket;
792 } else {
793 n_bds = length / maxpacket;
794 if (length % maxpacket)
795 n_bds++;
796 }
797 if (n_bds == 1)
798 onepacket = 1;
799 else
800 n_bds = min(n_bds, (unsigned) NUM_RXCHAN_BD);
801 }
802
803 /* In host mode, autorequest logic can generate some IN tokens; it's
804 * tricky since we can't leave REQPKT set in RXCSR after the transfer
805 * finishes. So: multipacket transfers involve two or more segments.
806 * And always at least two IRQs ... RNDIS mode is not an option.
807 */
808 if (is_host_active(musb))
809 n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds);
810
811 cppi_rndis_update(rx, 1, musb->ctrl_base, is_rndis);
812
813 length = min(n_bds * maxpacket, length);
814
815 DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
816 "dma 0x%x len %u %u/%u\n",
817 rx->index, maxpacket,
818 onepacket
819 ? (is_rndis ? "rndis" : "onepacket")
820 : "multipacket",
821 n_bds,
822 musb_readl(tibase,
823 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
824 & 0xffff,
825 addr, length, rx->channel.actual_len, rx->buf_len);
826
827 /* only queue one segment at a time, since the hardware prevents
828 * correct queue shutdown after unexpected short packets
829 */
830 bd = cppi_bd_alloc(rx);
831 rx->head = bd;
832
833 /* Build BDs for all packets in this segment */
834 for (i = 0, tail = NULL; bd && i < n_bds; i++, tail = bd) {
835 u32 bd_len;
836
837 if (i) {
838 bd = cppi_bd_alloc(rx);
839 if (!bd)
840 break;
841 tail->next = bd;
842 tail->hw_next = bd->dma;
843 }
844 bd->hw_next = 0;
845
846 /* all but the last packet will be maxpacket size */
847 if (maxpacket < length)
848 bd_len = maxpacket;
849 else
850 bd_len = length;
851
852 bd->hw_bufp = addr;
853 addr += bd_len;
854 rx->offset += bd_len;
855
856 bd->hw_off_len = (0 /*offset*/ << 16) + bd_len;
857 bd->buflen = bd_len;
858
859 bd->hw_options = CPPI_OWN_SET | (i == 0 ? length : 0);
860 length -= bd_len;
861 }
862
863 /* we always expect at least one reusable BD! */
864 if (!tail) {
865 WARNING("rx dma%d -- no BDs? need %d\n", rx->index, n_bds);
866 return;
867 } else if (i < n_bds)
868 WARNING("rx dma%d -- only %d of %d BDs\n", rx->index, i, n_bds);
869
870 tail->next = NULL;
871 tail->hw_next = 0;
872
873 bd = rx->head;
874 rx->tail = tail;
875
876 /* short reads and other faults should terminate this entire
877 * dma segment. we want one "dma packet" per dma segment, not
878 * one per USB packet, terminating the whole queue at once...
879 * NOTE that current hardware seems to ignore SOP and EOP.
880 */
881 bd->hw_options |= CPPI_SOP_SET;
882 tail->hw_options |= CPPI_EOP_SET;
883
884 if (debug >= 5) {
885 struct cppi_descriptor *d;
886
887 for (d = rx->head; d; d = d->next)
888 cppi_dump_rxbd("S", d);
889 }
890
891 /* in case the preceding transfer left some state... */
892 tail = rx->last_processed;
893 if (tail) {
894 tail->next = bd;
895 tail->hw_next = bd->dma;
896 }
897
898 core_rxirq_enable(tibase, rx->index + 1);
899
900 /* BDs live in DMA-coherent memory, but writes might be pending */
901 cpu_drain_writebuffer();
902
903 /* REVISIT specs say to write this AFTER the BUFCNT register
904 * below ... but that loses badly.
905 */
906 musb_writel(&rx_ram->rx_head, 0, bd->dma);
907
908 /* bufferCount must be at least 3, and zeroes on completion
909 * unless it underflows below zero, or stops at two, or keeps
910 * growing ... grr.
911 */
912 i = musb_readl(tibase,
913 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
914 & 0xffff;
915
916 if (!i)
917 musb_writel(tibase,
918 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
919 n_bds + 2);
920 else if (n_bds > (i - 3))
921 musb_writel(tibase,
922 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
923 n_bds - (i - 3));
924
925 i = musb_readl(tibase,
926 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
927 & 0xffff;
928 if (i < (2 + n_bds)) {
929 DBG(2, "bufcnt%d underrun - %d (for %d)\n",
930 rx->index, i, n_bds);
931 musb_writel(tibase,
932 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
933 n_bds + 2);
934 }
935
936 cppi_dump_rx(4, rx, "/S");
937}
938
939/**
940 * cppi_channel_program - program channel for data transfer
941 * @ch: the channel
942 * @maxpacket: max packet size
943 * @mode: For RX, 1 unless the usb protocol driver promised to treat
944 * all short reads as errors and kick in high level fault recovery.
945 * For TX, ignored because of RNDIS mode races/glitches.
946 * @dma_addr: dma address of buffer
947 * @len: length of buffer
948 * Context: controller irqlocked
949 */
950static int cppi_channel_program(struct dma_channel *ch,
951 u16 maxpacket, u8 mode,
952 dma_addr_t dma_addr, u32 len)
953{
954 struct cppi_channel *cppi_ch;
955 struct cppi *controller;
956 struct musb *musb;
957
958 cppi_ch = container_of(ch, struct cppi_channel, channel);
959 controller = cppi_ch->controller;
960 musb = controller->musb;
961
962 switch (ch->status) {
963 case MUSB_DMA_STATUS_BUS_ABORT:
964 case MUSB_DMA_STATUS_CORE_ABORT:
965 /* fault irq handler should have handled cleanup */
966 WARNING("%cX DMA%d not cleaned up after abort!\n",
967 cppi_ch->transmit ? 'T' : 'R',
968 cppi_ch->index);
969 /* WARN_ON(1); */
970 break;
971 case MUSB_DMA_STATUS_BUSY:
972 WARNING("program active channel? %cX DMA%d\n",
973 cppi_ch->transmit ? 'T' : 'R',
974 cppi_ch->index);
975 /* WARN_ON(1); */
976 break;
977 case MUSB_DMA_STATUS_UNKNOWN:
978 DBG(1, "%cX DMA%d not allocated!\n",
979 cppi_ch->transmit ? 'T' : 'R',
980 cppi_ch->index);
981 /* FALLTHROUGH */
982 case MUSB_DMA_STATUS_FREE:
983 break;
984 }
985
986 ch->status = MUSB_DMA_STATUS_BUSY;
987
988 /* set transfer parameters, then queue up its first segment */
989 cppi_ch->buf_dma = dma_addr;
990 cppi_ch->offset = 0;
991 cppi_ch->maxpacket = maxpacket;
992 cppi_ch->buf_len = len;
993
994 /* TX channel? or RX? */
995 if (cppi_ch->transmit)
996 cppi_next_tx_segment(musb, cppi_ch);
997 else
998 cppi_next_rx_segment(musb, cppi_ch, mode);
999
1000 return true;
1001}
1002
1003static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1004{
1005 struct cppi_channel *rx = &cppi->rx[ch];
1006 struct cppi_rx_stateram __iomem *state = rx->state_ram;
1007 struct cppi_descriptor *bd;
1008 struct cppi_descriptor *last = rx->last_processed;
1009 bool completed = false;
1010 bool acked = false;
1011 int i;
1012 dma_addr_t safe2ack;
1013 void __iomem *regs = rx->hw_ep->regs;
1014
1015 cppi_dump_rx(6, rx, "/K");
1016
1017 bd = last ? last->next : rx->head;
1018 if (!bd)
1019 return false;
1020
1021 /* run through all completed BDs */
1022 for (i = 0, safe2ack = musb_readl(&state->rx_complete, 0);
1023 (safe2ack || completed) && bd && i < NUM_RXCHAN_BD;
1024 i++, bd = bd->next) {
1025 u16 len;
1026
1027 /* catch latest BD writes from CPPI */
1028 rmb();
1029 if (!completed && (bd->hw_options & CPPI_OWN_SET))
1030 break;
1031
1032 DBG(5, "C/RXBD %08x: nxt %08x buf %08x "
1033 "off.len %08x opt.len %08x (%d)\n",
1034 bd->dma, bd->hw_next, bd->hw_bufp,
1035 bd->hw_off_len, bd->hw_options,
1036 rx->channel.actual_len);
1037
1038 /* actual packet received length */
1039 if ((bd->hw_options & CPPI_SOP_SET) && !completed)
1040 len = bd->hw_off_len & CPPI_RECV_PKTLEN_MASK;
1041 else
1042 len = 0;
1043
1044 if (bd->hw_options & CPPI_EOQ_MASK)
1045 completed = true;
1046
1047 if (!completed && len < bd->buflen) {
1048 /* NOTE: when we get a short packet, RXCSR_H_REQPKT
1049 * must have been cleared, and no more DMA packets may
1050 * active be in the queue... TI docs didn't say, but
1051 * CPPI ignores those BDs even though OWN is still set.
1052 */
1053 completed = true;
1054 DBG(3, "rx short %d/%d (%d)\n",
1055 len, bd->buflen,
1056 rx->channel.actual_len);
1057 }
1058
1059 /* If we got here, we expect to ack at least one BD; meanwhile
1060 * CPPI may completing other BDs while we scan this list...
1061 *
1062 * RACE: we can notice OWN cleared before CPPI raises the
1063 * matching irq by writing that BD as the completion pointer.
1064 * In such cases, stop scanning and wait for the irq, avoiding
1065 * lost acks and states where BD ownership is unclear.
1066 */
1067 if (bd->dma == safe2ack) {
1068 musb_writel(&state->rx_complete, 0, safe2ack);
1069 safe2ack = musb_readl(&state->rx_complete, 0);
1070 acked = true;
1071 if (bd->dma == safe2ack)
1072 safe2ack = 0;
1073 }
1074
1075 rx->channel.actual_len += len;
1076
1077 cppi_bd_free(rx, last);
1078 last = bd;
1079
1080 /* stop scanning on end-of-segment */
1081 if (bd->hw_next == 0)
1082 completed = true;
1083 }
1084 rx->last_processed = last;
1085
1086 /* dma abort, lost ack, or ... */
1087 if (!acked && last) {
1088 int csr;
1089
1090 if (safe2ack == 0 || safe2ack == rx->last_processed->dma)
1091 musb_writel(&state->rx_complete, 0, safe2ack);
1092 if (safe2ack == 0) {
1093 cppi_bd_free(rx, last);
1094 rx->last_processed = NULL;
1095
1096 /* if we land here on the host side, H_REQPKT will
1097 * be clear and we need to restart the queue...
1098 */
1099 WARN_ON(rx->head);
1100 }
1101 musb_ep_select(cppi->mregs, rx->index + 1);
1102 csr = musb_readw(regs, MUSB_RXCSR);
1103 if (csr & MUSB_RXCSR_DMAENAB) {
1104 DBG(4, "list%d %p/%p, last %08x%s, csr %04x\n",
1105 rx->index,
1106 rx->head, rx->tail,
1107 rx->last_processed
1108 ? rx->last_processed->dma
1109 : 0,
1110 completed ? ", completed" : "",
1111 csr);
1112 cppi_dump_rxq(4, "/what?", rx);
1113 }
1114 }
1115 if (!completed) {
1116 int csr;
1117
1118 rx->head = bd;
1119
1120 /* REVISIT seems like "autoreq all but EOP" doesn't...
1121 * setting it here "should" be racey, but seems to work
1122 */
1123 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
1124 if (is_host_active(cppi->musb)
1125 && bd
1126 && !(csr & MUSB_RXCSR_H_REQPKT)) {
1127 csr |= MUSB_RXCSR_H_REQPKT;
1128 musb_writew(regs, MUSB_RXCSR,
1129 MUSB_RXCSR_H_WZC_BITS | csr);
1130 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
1131 }
1132 } else {
1133 rx->head = NULL;
1134 rx->tail = NULL;
1135 }
1136
1137 cppi_dump_rx(6, rx, completed ? "/completed" : "/cleaned");
1138 return completed;
1139}
1140
1141void cppi_completion(struct musb *musb, u32 rx, u32 tx)
1142{
1143 void __iomem *tibase;
1144 int i, index;
1145 struct cppi *cppi;
1146 struct musb_hw_ep *hw_ep = NULL;
1147
1148 cppi = container_of(musb->dma_controller, struct cppi, controller);
1149
1150 tibase = musb->ctrl_base;
1151
1152 /* process TX channels */
1153 for (index = 0; tx; tx = tx >> 1, index++) {
1154 struct cppi_channel *tx_ch;
1155 struct cppi_tx_stateram __iomem *tx_ram;
1156 bool completed = false;
1157 struct cppi_descriptor *bd;
1158
1159 if (!(tx & 1))
1160 continue;
1161
1162 tx_ch = cppi->tx + index;
1163 tx_ram = tx_ch->state_ram;
1164
1165 /* FIXME need a cppi_tx_scan() routine, which
1166 * can also be called from abort code
1167 */
1168
1169 cppi_dump_tx(5, tx_ch, "/E");
1170
1171 bd = tx_ch->head;
1172
1173 if (NULL == bd) {
1174 DBG(1, "null BD\n");
1175 continue;
1176 }
1177
1178 /* run through all completed BDs */
1179 for (i = 0; !completed && bd && i < NUM_TXCHAN_BD;
1180 i++, bd = bd->next) {
1181 u16 len;
1182
1183 /* catch latest BD writes from CPPI */
1184 rmb();
1185 if (bd->hw_options & CPPI_OWN_SET)
1186 break;
1187
1188 DBG(5, "C/TXBD %p n %x b %x off %x opt %x\n",
1189 bd, bd->hw_next, bd->hw_bufp,
1190 bd->hw_off_len, bd->hw_options);
1191
1192 len = bd->hw_off_len & CPPI_BUFFER_LEN_MASK;
1193 tx_ch->channel.actual_len += len;
1194
1195 tx_ch->last_processed = bd;
1196
1197 /* write completion register to acknowledge
1198 * processing of completed BDs, and possibly
1199 * release the IRQ; EOQ might not be set ...
1200 *
1201 * REVISIT use the same ack strategy as rx
1202 *
1203 * REVISIT have observed bit 18 set; huh??
1204 */
1205 /* if ((bd->hw_options & CPPI_EOQ_MASK)) */
1206 musb_writel(&tx_ram->tx_complete, 0, bd->dma);
1207
1208 /* stop scanning on end-of-segment */
1209 if (bd->hw_next == 0)
1210 completed = true;
1211 }
1212
1213 /* on end of segment, maybe go to next one */
1214 if (completed) {
1215 /* cppi_dump_tx(4, tx_ch, "/complete"); */
1216
1217 /* transfer more, or report completion */
1218 if (tx_ch->offset >= tx_ch->buf_len) {
1219 tx_ch->head = NULL;
1220 tx_ch->tail = NULL;
1221 tx_ch->channel.status = MUSB_DMA_STATUS_FREE;
1222
1223 hw_ep = tx_ch->hw_ep;
1224
1225 /* Peripheral role never repurposes the
1226 * endpoint, so immediate completion is
1227 * safe. Host role waits for the fifo
1228 * to empty (TXPKTRDY irq) before going
1229 * to the next queued bulk transfer.
1230 */
1231 if (is_host_active(cppi->musb)) {
1232#if 0
1233 /* WORKAROUND because we may
1234 * not always get TXKPTRDY ...
1235 */
1236 int csr;
1237
1238 csr = musb_readw(hw_ep->regs,
1239 MUSB_TXCSR);
1240 if (csr & MUSB_TXCSR_TXPKTRDY)
1241#endif
1242 completed = false;
1243 }
1244 if (completed)
1245 musb_dma_completion(musb, index + 1, 1);
1246
1247 } else {
1248 /* Bigger transfer than we could fit in
1249 * that first batch of descriptors...
1250 */
1251 cppi_next_tx_segment(musb, tx_ch);
1252 }
1253 } else
1254 tx_ch->head = bd;
1255 }
1256
1257 /* Start processing the RX block */
1258 for (index = 0; rx; rx = rx >> 1, index++) {
1259
1260 if (rx & 1) {
1261 struct cppi_channel *rx_ch;
1262
1263 rx_ch = cppi->rx + index;
1264
1265 /* let incomplete dma segments finish */
1266 if (!cppi_rx_scan(cppi, index))
1267 continue;
1268
1269 /* start another dma segment if needed */
1270 if (rx_ch->channel.actual_len != rx_ch->buf_len
1271 && rx_ch->channel.actual_len
1272 == rx_ch->offset) {
1273 cppi_next_rx_segment(musb, rx_ch, 1);
1274 continue;
1275 }
1276
1277 /* all segments completed! */
1278 rx_ch->channel.status = MUSB_DMA_STATUS_FREE;
1279
1280 hw_ep = rx_ch->hw_ep;
1281
1282 core_rxirq_disable(tibase, index + 1);
1283 musb_dma_completion(musb, index + 1, 0);
1284 }
1285 }
1286
1287 /* write to CPPI EOI register to re-enable interrupts */
1288 musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
1289}
1290
1291/* Instantiate a software object representing a DMA controller. */
1292struct dma_controller *__init
1293dma_controller_create(struct musb *musb, void __iomem *mregs)
1294{
1295 struct cppi *controller;
1296
1297 controller = kzalloc(sizeof *controller, GFP_KERNEL);
1298 if (!controller)
1299 return NULL;
1300
1301 controller->mregs = mregs;
1302 controller->tibase = mregs - DAVINCI_BASE_OFFSET;
1303
1304 controller->musb = musb;
1305 controller->controller.start = cppi_controller_start;
1306 controller->controller.stop = cppi_controller_stop;
1307 controller->controller.channel_alloc = cppi_channel_allocate;
1308 controller->controller.channel_release = cppi_channel_release;
1309 controller->controller.channel_program = cppi_channel_program;
1310 controller->controller.channel_abort = cppi_channel_abort;
1311
1312 /* NOTE: allocating from on-chip SRAM would give the least
1313 * contention for memory access, if that ever matters here.
1314 */
1315
1316 /* setup BufferPool */
1317 controller->pool = dma_pool_create("cppi",
1318 controller->musb->controller,
1319 sizeof(struct cppi_descriptor),
1320 CPPI_DESCRIPTOR_ALIGN, 0);
1321 if (!controller->pool) {
1322 kfree(controller);
1323 return NULL;
1324 }
1325
1326 return &controller->controller;
1327}
1328
1329/*
1330 * Destroy a previously-instantiated DMA controller.
1331 */
1332void dma_controller_destroy(struct dma_controller *c)
1333{
1334 struct cppi *cppi;
1335
1336 cppi = container_of(c, struct cppi, controller);
1337
1338 /* assert: caller stopped the controller first */
1339 dma_pool_destroy(cppi->pool);
1340
1341 kfree(cppi);
1342}
1343
1344/*
1345 * Context: controller irqlocked, endpoint selected
1346 */
1347static int cppi_channel_abort(struct dma_channel *channel)
1348{
1349 struct cppi_channel *cppi_ch;
1350 struct cppi *controller;
1351 void __iomem *mbase;
1352 void __iomem *tibase;
1353 void __iomem *regs;
1354 u32 value;
1355 struct cppi_descriptor *queue;
1356
1357 cppi_ch = container_of(channel, struct cppi_channel, channel);
1358
1359 controller = cppi_ch->controller;
1360
1361 switch (channel->status) {
1362 case MUSB_DMA_STATUS_BUS_ABORT:
1363 case MUSB_DMA_STATUS_CORE_ABORT:
1364 /* from RX or TX fault irq handler */
1365 case MUSB_DMA_STATUS_BUSY:
1366 /* the hardware needs shutting down */
1367 regs = cppi_ch->hw_ep->regs;
1368 break;
1369 case MUSB_DMA_STATUS_UNKNOWN:
1370 case MUSB_DMA_STATUS_FREE:
1371 return 0;
1372 default:
1373 return -EINVAL;
1374 }
1375
1376 if (!cppi_ch->transmit && cppi_ch->head)
1377 cppi_dump_rxq(3, "/abort", cppi_ch);
1378
1379 mbase = controller->mregs;
1380 tibase = controller->tibase;
1381
1382 queue = cppi_ch->head;
1383 cppi_ch->head = NULL;
1384 cppi_ch->tail = NULL;
1385
1386 /* REVISIT should rely on caller having done this,
1387 * and caller should rely on us not changing it.
1388 * peripheral code is safe ... check host too.
1389 */
1390 musb_ep_select(mbase, cppi_ch->index + 1);
1391
1392 if (cppi_ch->transmit) {
1393 struct cppi_tx_stateram __iomem *tx_ram;
1394 int enabled;
1395
1396 /* mask interrupts raised to signal teardown complete. */
1397 enabled = musb_readl(tibase, DAVINCI_TXCPPI_INTENAB_REG)
1398 & (1 << cppi_ch->index);
1399 if (enabled)
1400 musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,
1401 (1 << cppi_ch->index));
1402
1403 /* REVISIT put timeouts on these controller handshakes */
1404
1405 cppi_dump_tx(6, cppi_ch, " (teardown)");
1406
1407 /* teardown DMA engine then usb core */
1408 do {
1409 value = musb_readl(tibase, DAVINCI_TXCPPI_TEAR_REG);
1410 } while (!(value & CPPI_TEAR_READY));
1411 musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index);
1412
1413 tx_ram = cppi_ch->state_ram;
1414 do {
1415 value = musb_readl(&tx_ram->tx_complete, 0);
1416 } while (0xFFFFFFFC != value);
1417 musb_writel(&tx_ram->tx_complete, 0, 0xFFFFFFFC);
1418
1419 /* FIXME clean up the transfer state ... here?
1420 * the completion routine should get called with
1421 * an appropriate status code.
1422 */
1423
1424 value = musb_readw(regs, MUSB_TXCSR);
1425 value &= ~MUSB_TXCSR_DMAENAB;
1426 value |= MUSB_TXCSR_FLUSHFIFO;
1427 musb_writew(regs, MUSB_TXCSR, value);
1428 musb_writew(regs, MUSB_TXCSR, value);
1429
1430 /* re-enable interrupt */
1431 if (enabled)
1432 musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
1433 (1 << cppi_ch->index));
1434
1435 /* While we scrub the TX state RAM, ensure that we clean
1436 * up any interrupt that's currently asserted:
1437 * 1. Write to completion Ptr value 0x1(bit 0 set)
1438 * (write back mode)
1439 * 2. Write to completion Ptr value 0x0(bit 0 cleared)
1440 * (compare mode)
1441 * Value written is compared(for bits 31:2) and when
1442 * equal, interrupt is deasserted.
1443 */
1444 cppi_reset_tx(tx_ram, 1);
1445 musb_writel(&tx_ram->tx_complete, 0, 0);
1446
1447 cppi_dump_tx(5, cppi_ch, " (done teardown)");
1448
1449 /* REVISIT tx side _should_ clean up the same way
1450 * as the RX side ... this does no cleanup at all!
1451 */
1452
1453 } else /* RX */ {
1454 u16 csr;
1455
1456 /* NOTE: docs don't guarantee any of this works ... we
1457 * expect that if the usb core stops telling the cppi core
1458 * to pull more data from it, then it'll be safe to flush
1459 * current RX DMA state iff any pending fifo transfer is done.
1460 */
1461
1462 core_rxirq_disable(tibase, cppi_ch->index + 1);
1463
1464 /* for host, ensure ReqPkt is never set again */
1465 if (is_host_active(cppi_ch->controller->musb)) {
1466 value = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
1467 value &= ~((0x3) << (cppi_ch->index * 2));
1468 musb_writel(tibase, DAVINCI_AUTOREQ_REG, value);
1469 }
1470
1471 csr = musb_readw(regs, MUSB_RXCSR);
1472
1473 /* for host, clear (just) ReqPkt at end of current packet(s) */
1474 if (is_host_active(cppi_ch->controller->musb)) {
1475 csr |= MUSB_RXCSR_H_WZC_BITS;
1476 csr &= ~MUSB_RXCSR_H_REQPKT;
1477 } else
1478 csr |= MUSB_RXCSR_P_WZC_BITS;
1479
1480 /* clear dma enable */
1481 csr &= ~(MUSB_RXCSR_DMAENAB);
1482 musb_writew(regs, MUSB_RXCSR, csr);
1483 csr = musb_readw(regs, MUSB_RXCSR);
1484
1485 /* Quiesce: wait for current dma to finish (if not cleanup).
1486 * We can't use bit zero of stateram->rx_sop, since that
1487 * refers to an entire "DMA packet" not just emptying the
1488 * current fifo. Most segments need multiple usb packets.
1489 */
1490 if (channel->status == MUSB_DMA_STATUS_BUSY)
1491 udelay(50);
1492
1493 /* scan the current list, reporting any data that was
1494 * transferred and acking any IRQ
1495 */
1496 cppi_rx_scan(controller, cppi_ch->index);
1497
1498 /* clobber the existing state once it's idle
1499 *
1500 * NOTE: arguably, we should also wait for all the other
1501 * RX channels to quiesce (how??) and then temporarily
1502 * disable RXCPPI_CTRL_REG ... but it seems that we can
1503 * rely on the controller restarting from state ram, with
1504 * only RXCPPI_BUFCNT state being bogus. BUFCNT will
1505 * correct itself after the next DMA transfer though.
1506 *
1507 * REVISIT does using rndis mode change that?
1508 */
1509 cppi_reset_rx(cppi_ch->state_ram);
1510
1511 /* next DMA request _should_ load cppi head ptr */
1512
1513 /* ... we don't "free" that list, only mutate it in place. */
1514 cppi_dump_rx(5, cppi_ch, " (done abort)");
1515
1516 /* clean up previously pending bds */
1517 cppi_bd_free(cppi_ch, cppi_ch->last_processed);
1518 cppi_ch->last_processed = NULL;
1519
1520 while (queue) {
1521 struct cppi_descriptor *tmp = queue->next;
1522
1523 cppi_bd_free(cppi_ch, queue);
1524 queue = tmp;
1525 }
1526 }
1527
1528 channel->status = MUSB_DMA_STATUS_FREE;
1529 cppi_ch->buf_dma = 0;
1530 cppi_ch->offset = 0;
1531 cppi_ch->buf_len = 0;
1532 cppi_ch->maxpacket = 0;
1533 return 0;
1534}
1535
1536/* TBD Queries:
1537 *
1538 * Power Management ... probably turn off cppi during suspend, restart;
1539 * check state ram? Clocking is presumably shared with usb core.
1540 */
diff --git a/drivers/usb/musb/cppi_dma.h b/drivers/usb/musb/cppi_dma.h
new file mode 100644
index 000000000000..fc5216b5d2c5
--- /dev/null
+++ b/drivers/usb/musb/cppi_dma.h
@@ -0,0 +1,133 @@
1/* Copyright (C) 2005-2006 by Texas Instruments */
2
3#ifndef _CPPI_DMA_H_
4#define _CPPI_DMA_H_
5
6#include <linux/slab.h>
7#include <linux/list.h>
8#include <linux/smp_lock.h>
9#include <linux/errno.h>
10#include <linux/dmapool.h>
11
12#include "musb_dma.h"
13#include "musb_core.h"
14
15
16/* FIXME fully isolate CPPI from DaVinci ... the "CPPI generic" registers
17 * would seem to be shared with the TUSB6020 (over VLYNQ).
18 */
19
20#include "davinci.h"
21
22
23/* CPPI RX/TX state RAM */
24
25struct cppi_tx_stateram {
26 u32 tx_head; /* "DMA packet" head descriptor */
27 u32 tx_buf;
28 u32 tx_current; /* current descriptor */
29 u32 tx_buf_current;
30 u32 tx_info; /* flags, remaining buflen */
31 u32 tx_rem_len;
32 u32 tx_dummy; /* unused */
33 u32 tx_complete;
34};
35
36struct cppi_rx_stateram {
37 u32 rx_skipbytes;
38 u32 rx_head;
39 u32 rx_sop; /* "DMA packet" head descriptor */
40 u32 rx_current; /* current descriptor */
41 u32 rx_buf_current;
42 u32 rx_len_len;
43 u32 rx_cnt_cnt;
44 u32 rx_complete;
45};
46
47/* hw_options bits in CPPI buffer descriptors */
48#define CPPI_SOP_SET ((u32)(1 << 31))
49#define CPPI_EOP_SET ((u32)(1 << 30))
50#define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */
51#define CPPI_EOQ_MASK ((u32)(1 << 28))
52#define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */
53#define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */
54
55#define CPPI_RECV_PKTLEN_MASK 0xFFFF
56#define CPPI_BUFFER_LEN_MASK 0xFFFF
57
58#define CPPI_TEAR_READY ((u32)(1 << 31))
59
60/* CPPI data structure definitions */
61
62#define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */
63
64struct cppi_descriptor {
65 /* hardware overlay */
66 u32 hw_next; /* next buffer descriptor Pointer */
67 u32 hw_bufp; /* i/o buffer pointer */
68 u32 hw_off_len; /* buffer_offset16, buffer_length16 */
69 u32 hw_options; /* flags: SOP, EOP etc*/
70
71 struct cppi_descriptor *next;
72 dma_addr_t dma; /* address of this descriptor */
73 u32 buflen; /* for RX: original buffer length */
74} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN)));
75
76
77struct cppi;
78
79/* CPPI Channel Control structure */
80struct cppi_channel {
81 struct dma_channel channel;
82
83 /* back pointer to the DMA controller structure */
84 struct cppi *controller;
85
86 /* which direction of which endpoint? */
87 struct musb_hw_ep *hw_ep;
88 bool transmit;
89 u8 index;
90
91 /* DMA modes: RNDIS or "transparent" */
92 u8 is_rndis;
93
94 /* book keeping for current transfer request */
95 dma_addr_t buf_dma;
96 u32 buf_len;
97 u32 maxpacket;
98 u32 offset; /* dma requested */
99
100 void __iomem *state_ram; /* CPPI state */
101
102 struct cppi_descriptor *freelist;
103
104 /* BD management fields */
105 struct cppi_descriptor *head;
106 struct cppi_descriptor *tail;
107 struct cppi_descriptor *last_processed;
108
109 /* use tx_complete in host role to track endpoints waiting for
110 * FIFONOTEMPTY to clear.
111 */
112 struct list_head tx_complete;
113};
114
115/* CPPI DMA controller object */
116struct cppi {
117 struct dma_controller controller;
118 struct musb *musb;
119 void __iomem *mregs; /* Mentor regs */
120 void __iomem *tibase; /* TI/CPPI regs */
121
122 struct cppi_channel tx[MUSB_C_NUM_EPT - 1];
123 struct cppi_channel rx[MUSB_C_NUM_EPR - 1];
124
125 struct dma_pool *pool;
126
127 struct list_head tx_complete;
128};
129
130/* irq handling hook */
131extern void cppi_completion(struct musb *, u32 rx, u32 tx);
132
133#endif /* end of ifndef _CPPI_DMA_H_ */
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
new file mode 100644
index 000000000000..75baf181a8cd
--- /dev/null
+++ b/drivers/usb/musb/davinci.c
@@ -0,0 +1,462 @@
1/*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * This file is part of the Inventra Controller Driver for Linux.
5 *
6 * The Inventra Controller Driver for Linux is free software; you
7 * can redistribute it and/or modify it under the terms of the GNU
8 * General Public License version 2 as published by the Free Software
9 * Foundation.
10 *
11 * The Inventra Controller Driver for Linux is distributed in
12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
13 * without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 * License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with The Inventra Controller Driver for Linux ; if not,
19 * write to the Free Software Foundation, Inc., 59 Temple Place,
20 * Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/list.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33
34#include <asm/arch/hardware.h>
35#include <asm/arch/memory.h>
36#include <asm/arch/gpio.h>
37#include <asm/mach-types.h>
38
39#include "musb_core.h"
40
41#ifdef CONFIG_MACH_DAVINCI_EVM
42#include <asm/arch/i2c-client.h>
43#endif
44
45#include "davinci.h"
46#include "cppi_dma.h"
47
48
49/* REVISIT (PM) we should be able to keep the PHY in low power mode most
50 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
51 * and, when in host mode, autosuspending idle root ports... PHYPLLON
52 * (overriding SUSPENDM?) then likely needs to stay off.
53 */
54
55static inline void phy_on(void)
56{
57 /* start the on-chip PHY and its PLL */
58 __raw_writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON,
59 (void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
60 while ((__raw_readl((void __force __iomem *)
61 IO_ADDRESS(USBPHY_CTL_PADDR))
62 & USBPHY_PHYCLKGD) == 0)
63 cpu_relax();
64}
65
66static inline void phy_off(void)
67{
68 /* powerdown the on-chip PHY and its oscillator */
69 __raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, (void __force __iomem *)
70 IO_ADDRESS(USBPHY_CTL_PADDR));
71}
72
73static int dma_off = 1;
74
75void musb_platform_enable(struct musb *musb)
76{
77 u32 tmp, old, val;
78
79 /* workaround: setup irqs through both register sets */
80 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
81 << DAVINCI_USB_TXINT_SHIFT;
82 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
83 old = tmp;
84 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
85 << DAVINCI_USB_RXINT_SHIFT;
86 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
87 tmp |= old;
88
89 val = ~MUSB_INTR_SOF;
90 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
91 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
92
93 if (is_dma_capable() && !dma_off)
94 printk(KERN_WARNING "%s %s: dma not reactivated\n",
95 __FILE__, __func__);
96 else
97 dma_off = 0;
98
99 /* force a DRVVBUS irq so we can start polling for ID change */
100 if (is_otg_enabled(musb))
101 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
102 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
103}
104
105/*
106 * Disable the HDRC and flush interrupts
107 */
108void musb_platform_disable(struct musb *musb)
109{
110 /* because we don't set CTRLR.UINT, "important" to:
111 * - not read/write INTRUSB/INTRUSBE
112 * - (except during initial setup, as workaround)
113 * - use INTSETR/INTCLRR instead
114 */
115 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
116 DAVINCI_USB_USBINT_MASK
117 | DAVINCI_USB_TXINT_MASK
118 | DAVINCI_USB_RXINT_MASK);
119 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
120 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
121
122 if (is_dma_capable() && !dma_off)
123 WARNING("dma still active\n");
124}
125
126
127/* REVISIT it's not clear whether DaVinci can support full OTG. */
128
129static int vbus_state = -1;
130
131#ifdef CONFIG_USB_MUSB_HDRC_HCD
132#define portstate(stmt) stmt
133#else
134#define portstate(stmt)
135#endif
136
137
138/* VBUS SWITCHING IS BOARD-SPECIFIC */
139
140#ifdef CONFIG_MACH_DAVINCI_EVM
141#ifndef CONFIG_MACH_DAVINCI_EVM_OTG
142
143/* I2C operations are always synchronous, and require a task context.
144 * With unloaded systems, using the shared workqueue seems to suffice
145 * to satisfy the 100msec A_WAIT_VRISE timeout...
146 */
147static void evm_deferred_drvvbus(struct work_struct *ignored)
148{
149 davinci_i2c_expander_op(0x3a, USB_DRVVBUS, vbus_state);
150 vbus_state = !vbus_state;
151}
152static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
153
154#endif /* modified board */
155#endif /* EVM */
156
157static void davinci_source_power(struct musb *musb, int is_on, int immediate)
158{
159 if (is_on)
160 is_on = 1;
161
162 if (vbus_state == is_on)
163 return;
164 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
165
166#ifdef CONFIG_MACH_DAVINCI_EVM
167 if (machine_is_davinci_evm()) {
168#ifdef CONFIG_MACH_DAVINCI_EVM_OTG
169 /* modified EVM board switching VBUS with GPIO(6) not I2C
170 * NOTE: PINMUX0.RGB888 (bit23) must be clear
171 */
172 if (is_on)
173 gpio_set(GPIO(6));
174 else
175 gpio_clear(GPIO(6));
176 immediate = 1;
177#else
178 if (immediate)
179 davinci_i2c_expander_op(0x3a, USB_DRVVBUS, !is_on);
180 else
181 schedule_work(&evm_vbus_work);
182#endif
183 }
184#endif
185 if (immediate)
186 vbus_state = is_on;
187}
188
189static void davinci_set_vbus(struct musb *musb, int is_on)
190{
191 WARN_ON(is_on && is_peripheral_active(musb));
192 davinci_source_power(musb, is_on, 0);
193}
194
195
196#define POLL_SECONDS 2
197
198static struct timer_list otg_workaround;
199
200static void otg_timer(unsigned long _musb)
201{
202 struct musb *musb = (void *)_musb;
203 void __iomem *mregs = musb->mregs;
204 u8 devctl;
205 unsigned long flags;
206
207 /* We poll because DaVinci's won't expose several OTG-critical
208 * status change events (from the transceiver) otherwise.
209 */
210 devctl = musb_readb(mregs, MUSB_DEVCTL);
211 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
212
213 spin_lock_irqsave(&musb->lock, flags);
214 switch (musb->xceiv.state) {
215 case OTG_STATE_A_WAIT_VFALL:
216 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
217 * seems to mis-handle session "start" otherwise (or in our
218 * case "recover"), in routine "VBUS was valid by the time
219 * VBUSERR got reported during enumeration" cases.
220 */
221 if (devctl & MUSB_DEVCTL_VBUS) {
222 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
223 break;
224 }
225 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
226 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
227 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
228 break;
229 case OTG_STATE_B_IDLE:
230 if (!is_peripheral_enabled(musb))
231 break;
232
233 /* There's no ID-changed IRQ, so we have no good way to tell
234 * when to switch to the A-Default state machine (by setting
235 * the DEVCTL.SESSION flag).
236 *
237 * Workaround: whenever we're in B_IDLE, try setting the
238 * session flag every few seconds. If it works, ID was
239 * grounded and we're now in the A-Default state machine.
240 *
241 * NOTE setting the session flag is _supposed_ to trigger
242 * SRP, but clearly it doesn't.
243 */
244 musb_writeb(mregs, MUSB_DEVCTL,
245 devctl | MUSB_DEVCTL_SESSION);
246 devctl = musb_readb(mregs, MUSB_DEVCTL);
247 if (devctl & MUSB_DEVCTL_BDEVICE)
248 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
249 else
250 musb->xceiv.state = OTG_STATE_A_IDLE;
251 break;
252 default:
253 break;
254 }
255 spin_unlock_irqrestore(&musb->lock, flags);
256}
257
258static irqreturn_t davinci_interrupt(int irq, void *__hci)
259{
260 unsigned long flags;
261 irqreturn_t retval = IRQ_NONE;
262 struct musb *musb = __hci;
263 void __iomem *tibase = musb->ctrl_base;
264 u32 tmp;
265
266 spin_lock_irqsave(&musb->lock, flags);
267
268 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
269 * the Mentor registers (except for setup), use the TI ones and EOI.
270 *
271 * Docs describe irq "vector" registers asociated with the CPPI and
272 * USB EOI registers. These hold a bitmask corresponding to the
273 * current IRQ, not an irq handler address. Would using those bits
274 * resolve some of the races observed in this dispatch code??
275 */
276
277 /* CPPI interrupts share the same IRQ line, but have their own
278 * mask, state, "vector", and EOI registers.
279 */
280 if (is_cppi_enabled()) {
281 u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
282 u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
283
284 if (cppi_tx || cppi_rx) {
285 DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
286 cppi_completion(musb, cppi_rx, cppi_tx);
287 retval = IRQ_HANDLED;
288 }
289 }
290
291 /* ack and handle non-CPPI interrupts */
292 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
293 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
294 DBG(4, "IRQ %08x\n", tmp);
295
296 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
297 >> DAVINCI_USB_RXINT_SHIFT;
298 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
299 >> DAVINCI_USB_TXINT_SHIFT;
300 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
301 >> DAVINCI_USB_USBINT_SHIFT;
302
303 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
304 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
305 * switch appropriately between halves of the OTG state machine.
306 * Managing DEVCTL.SESSION per Mentor docs requires we know its
307 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
308 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
309 */
310 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
311 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
312 void __iomem *mregs = musb->mregs;
313 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
314 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
315
316 err = is_host_enabled(musb)
317 && (musb->int_usb & MUSB_INTR_VBUSERROR);
318 if (err) {
319 /* The Mentor core doesn't debounce VBUS as needed
320 * to cope with device connect current spikes. This
321 * means it's not uncommon for bus-powered devices
322 * to get VBUS errors during enumeration.
323 *
324 * This is a workaround, but newer RTL from Mentor
325 * seems to allow a better one: "re"starting sessions
326 * without waiting (on EVM, a **long** time) for VBUS
327 * to stop registering in devctl.
328 */
329 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
330 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
331 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
332 WARNING("VBUS error workaround (delay coming)\n");
333 } else if (is_host_enabled(musb) && drvvbus) {
334 musb->is_active = 1;
335 MUSB_HST_MODE(musb);
336 musb->xceiv.default_a = 1;
337 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
338 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
339 del_timer(&otg_workaround);
340 } else {
341 musb->is_active = 0;
342 MUSB_DEV_MODE(musb);
343 musb->xceiv.default_a = 0;
344 musb->xceiv.state = OTG_STATE_B_IDLE;
345 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
346 }
347
348 /* NOTE: this must complete poweron within 100 msec */
349 davinci_source_power(musb, drvvbus, 0);
350 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
351 drvvbus ? "on" : "off",
352 otg_state_string(musb),
353 err ? " ERROR" : "",
354 devctl);
355 retval = IRQ_HANDLED;
356 }
357
358 if (musb->int_tx || musb->int_rx || musb->int_usb)
359 retval |= musb_interrupt(musb);
360
361 /* irq stays asserted until EOI is written */
362 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
363
364 /* poll for ID change */
365 if (is_otg_enabled(musb)
366 && musb->xceiv.state == OTG_STATE_B_IDLE)
367 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
368
369 spin_unlock_irqrestore(&musb->lock, flags);
370
371 /* REVISIT we sometimes get unhandled IRQs
372 * (e.g. ep0). not clear why...
373 */
374 if (retval != IRQ_HANDLED)
375 DBG(5, "unhandled? %08x\n", tmp);
376 return IRQ_HANDLED;
377}
378
379int __init musb_platform_init(struct musb *musb)
380{
381 void __iomem *tibase = musb->ctrl_base;
382 u32 revision;
383
384 musb->mregs += DAVINCI_BASE_OFFSET;
385#if 0
386 /* REVISIT there's something odd about clocking, this
387 * didn't appear do the job ...
388 */
389 musb->clock = clk_get(pDevice, "usb");
390 if (IS_ERR(musb->clock))
391 return PTR_ERR(musb->clock);
392
393 status = clk_enable(musb->clock);
394 if (status < 0)
395 return -ENODEV;
396#endif
397
398 /* returns zero if e.g. not clocked */
399 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
400 if (revision == 0)
401 return -ENODEV;
402
403 if (is_host_enabled(musb))
404 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
405
406 musb->board_set_vbus = davinci_set_vbus;
407 davinci_source_power(musb, 0, 1);
408
409 /* reset the controller */
410 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
411
412 /* start the on-chip PHY and its PLL */
413 phy_on();
414
415 msleep(5);
416
417 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
418 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
419 revision, __raw_readl((void __force __iomem *)
420 IO_ADDRESS(USBPHY_CTL_PADDR)),
421 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
422
423 musb->isr = davinci_interrupt;
424 return 0;
425}
426
427int musb_platform_exit(struct musb *musb)
428{
429 if (is_host_enabled(musb))
430 del_timer_sync(&otg_workaround);
431
432 davinci_source_power(musb, 0 /*off*/, 1);
433
434 /* delay, to avoid problems with module reload */
435 if (is_host_enabled(musb) && musb->xceiv.default_a) {
436 int maxdelay = 30;
437 u8 devctl, warn = 0;
438
439 /* if there's no peripheral connected, this can take a
440 * long time to fall, especially on EVM with huge C133.
441 */
442 do {
443 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
444 if (!(devctl & MUSB_DEVCTL_VBUS))
445 break;
446 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
447 warn = devctl & MUSB_DEVCTL_VBUS;
448 DBG(1, "VBUS %d\n",
449 warn >> MUSB_DEVCTL_VBUS_SHIFT);
450 }
451 msleep(1000);
452 maxdelay--;
453 } while (maxdelay > 0);
454
455 /* in OTG mode, another host might be connected */
456 if (devctl & MUSB_DEVCTL_VBUS)
457 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
458 }
459
460 phy_off();
461 return 0;
462}
diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h
new file mode 100644
index 000000000000..7fb6238e270f
--- /dev/null
+++ b/drivers/usb/musb/davinci.h
@@ -0,0 +1,100 @@
1/*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * The Inventra Controller Driver for Linux is free software; you
5 * can redistribute it and/or modify it under the terms of the GNU
6 * General Public License version 2 as published by the Free Software
7 * Foundation.
8 */
9
10#ifndef __MUSB_HDRDF_H__
11#define __MUSB_HDRDF_H__
12
13/*
14 * DaVinci-specific definitions
15 */
16
17/* Integrated highspeed/otg PHY */
18#define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34)
19#define USBPHY_PHYCLKGD (1 << 8)
20#define USBPHY_SESNDEN (1 << 7) /* v(sess_end) comparator */
21#define USBPHY_VBDTCTEN (1 << 6) /* v(bus) comparator */
22#define USBPHY_PHYPLLON (1 << 4) /* override pll suspend */
23#define USBPHY_CLKO1SEL (1 << 3)
24#define USBPHY_OSCPDWN (1 << 2)
25#define USBPHY_PHYPDWN (1 << 0)
26
27/* For now include usb OTG module registers here */
28#define DAVINCI_USB_VERSION_REG 0x00
29#define DAVINCI_USB_CTRL_REG 0x04
30#define DAVINCI_USB_STAT_REG 0x08
31#define DAVINCI_RNDIS_REG 0x10
32#define DAVINCI_AUTOREQ_REG 0x14
33#define DAVINCI_USB_INT_SOURCE_REG 0x20
34#define DAVINCI_USB_INT_SET_REG 0x24
35#define DAVINCI_USB_INT_SRC_CLR_REG 0x28
36#define DAVINCI_USB_INT_MASK_REG 0x2c
37#define DAVINCI_USB_INT_MASK_SET_REG 0x30
38#define DAVINCI_USB_INT_MASK_CLR_REG 0x34
39#define DAVINCI_USB_INT_SRC_MASKED_REG 0x38
40#define DAVINCI_USB_EOI_REG 0x3c
41#define DAVINCI_USB_EOI_INTVEC 0x40
42
43/* BEGIN CPPI-generic (?) */
44
45/* CPPI related registers */
46#define DAVINCI_TXCPPI_CTRL_REG 0x80
47#define DAVINCI_TXCPPI_TEAR_REG 0x84
48#define DAVINCI_CPPI_EOI_REG 0x88
49#define DAVINCI_CPPI_INTVEC_REG 0x8c
50#define DAVINCI_TXCPPI_MASKED_REG 0x90
51#define DAVINCI_TXCPPI_RAW_REG 0x94
52#define DAVINCI_TXCPPI_INTENAB_REG 0x98
53#define DAVINCI_TXCPPI_INTCLR_REG 0x9c
54
55#define DAVINCI_RXCPPI_CTRL_REG 0xC0
56#define DAVINCI_RXCPPI_MASKED_REG 0xD0
57#define DAVINCI_RXCPPI_RAW_REG 0xD4
58#define DAVINCI_RXCPPI_INTENAB_REG 0xD8
59#define DAVINCI_RXCPPI_INTCLR_REG 0xDC
60
61#define DAVINCI_RXCPPI_BUFCNT0_REG 0xE0
62#define DAVINCI_RXCPPI_BUFCNT1_REG 0xE4
63#define DAVINCI_RXCPPI_BUFCNT2_REG 0xE8
64#define DAVINCI_RXCPPI_BUFCNT3_REG 0xEC
65
66/* CPPI state RAM entries */
67#define DAVINCI_CPPI_STATERAM_BASE_OFFSET 0x100
68
69#define DAVINCI_TXCPPI_STATERAM_OFFSET(chnum) \
70 (DAVINCI_CPPI_STATERAM_BASE_OFFSET + ((chnum) * 0x40))
71#define DAVINCI_RXCPPI_STATERAM_OFFSET(chnum) \
72 (DAVINCI_CPPI_STATERAM_BASE_OFFSET + 0x20 + ((chnum) * 0x40))
73
74/* CPPI masks */
75#define DAVINCI_DMA_CTRL_ENABLE 1
76#define DAVINCI_DMA_CTRL_DISABLE 0
77
78#define DAVINCI_DMA_ALL_CHANNELS_ENABLE 0xF
79#define DAVINCI_DMA_ALL_CHANNELS_DISABLE 0xF
80
81/* END CPPI-generic (?) */
82
83#define DAVINCI_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
84#define DAVINCI_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
85
86#define DAVINCI_USB_USBINT_SHIFT 16
87#define DAVINCI_USB_TXINT_SHIFT 0
88#define DAVINCI_USB_RXINT_SHIFT 8
89
90#define DAVINCI_INTR_DRVVBUS 0x0100
91
92#define DAVINCI_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
93#define DAVINCI_USB_TXINT_MASK \
94 (DAVINCI_USB_TX_ENDPTS_MASK << DAVINCI_USB_TXINT_SHIFT)
95#define DAVINCI_USB_RXINT_MASK \
96 (DAVINCI_USB_RX_ENDPTS_MASK << DAVINCI_USB_RXINT_SHIFT)
97
98#define DAVINCI_BASE_OFFSET 0x400
99
100#endif /* __MUSB_HDRDF_H__ */
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
new file mode 100644
index 000000000000..462586d06da9
--- /dev/null
+++ b/drivers/usb/musb/musb_core.c
@@ -0,0 +1,2266 @@
1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/init.h>
97#include <linux/list.h>
98#include <linux/kobject.h>
99#include <linux/platform_device.h>
100#include <linux/io.h>
101
102#ifdef CONFIG_ARM
103#include <asm/arch/hardware.h>
104#include <asm/arch/memory.h>
105#include <asm/mach-types.h>
106#endif
107
108#include "musb_core.h"
109
110
111#ifdef CONFIG_ARCH_DAVINCI
112#include "davinci.h"
113#endif
114
115
116
117#if MUSB_DEBUG > 0
118unsigned debug = MUSB_DEBUG;
119module_param(debug, uint, 0);
120MODULE_PARM_DESC(debug, "initial debug message level");
121
122#define MUSB_VERSION_SUFFIX "/dbg"
123#endif
124
125#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
126#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
127
128#define MUSB_VERSION_BASE "6.0"
129
130#ifndef MUSB_VERSION_SUFFIX
131#define MUSB_VERSION_SUFFIX ""
132#endif
133#define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
134
135#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
136
137#define MUSB_DRIVER_NAME "musb_hdrc"
138const char musb_driver_name[] = MUSB_DRIVER_NAME;
139
140MODULE_DESCRIPTION(DRIVER_INFO);
141MODULE_AUTHOR(DRIVER_AUTHOR);
142MODULE_LICENSE("GPL");
143MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
144
145
146/*-------------------------------------------------------------------------*/
147
148static inline struct musb *dev_to_musb(struct device *dev)
149{
150#ifdef CONFIG_USB_MUSB_HDRC_HCD
151 /* usbcore insists dev->driver_data is a "struct hcd *" */
152 return hcd_to_musb(dev_get_drvdata(dev));
153#else
154 return dev_get_drvdata(dev);
155#endif
156}
157
158/*-------------------------------------------------------------------------*/
159
160#ifndef CONFIG_USB_TUSB6010
161/*
162 * Load an endpoint's FIFO
163 */
164void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
165{
166 void __iomem *fifo = hw_ep->fifo;
167
168 prefetch((u8 *)src);
169
170 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
171 'T', hw_ep->epnum, fifo, len, src);
172
173 /* we can't assume unaligned reads work */
174 if (likely((0x01 & (unsigned long) src) == 0)) {
175 u16 index = 0;
176
177 /* best case is 32bit-aligned source address */
178 if ((0x02 & (unsigned long) src) == 0) {
179 if (len >= 4) {
180 writesl(fifo, src + index, len >> 2);
181 index += len & ~0x03;
182 }
183 if (len & 0x02) {
184 musb_writew(fifo, 0, *(u16 *)&src[index]);
185 index += 2;
186 }
187 } else {
188 if (len >= 2) {
189 writesw(fifo, src + index, len >> 1);
190 index += len & ~0x01;
191 }
192 }
193 if (len & 0x01)
194 musb_writeb(fifo, 0, src[index]);
195 } else {
196 /* byte aligned */
197 writesb(fifo, src, len);
198 }
199}
200
201/*
202 * Unload an endpoint's FIFO
203 */
204void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
205{
206 void __iomem *fifo = hw_ep->fifo;
207
208 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
209 'R', hw_ep->epnum, fifo, len, dst);
210
211 /* we can't assume unaligned writes work */
212 if (likely((0x01 & (unsigned long) dst) == 0)) {
213 u16 index = 0;
214
215 /* best case is 32bit-aligned destination address */
216 if ((0x02 & (unsigned long) dst) == 0) {
217 if (len >= 4) {
218 readsl(fifo, dst, len >> 2);
219 index = len & ~0x03;
220 }
221 if (len & 0x02) {
222 *(u16 *)&dst[index] = musb_readw(fifo, 0);
223 index += 2;
224 }
225 } else {
226 if (len >= 2) {
227 readsw(fifo, dst, len >> 1);
228 index = len & ~0x01;
229 }
230 }
231 if (len & 0x01)
232 dst[index] = musb_readb(fifo, 0);
233 } else {
234 /* byte aligned */
235 readsb(fifo, dst, len);
236 }
237}
238
239#endif /* normal PIO */
240
241
242/*-------------------------------------------------------------------------*/
243
244/* for high speed test mode; see USB 2.0 spec 7.1.20 */
245static const u8 musb_test_packet[53] = {
246 /* implicit SYNC then DATA0 to start */
247
248 /* JKJKJKJK x9 */
249 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
250 /* JJKKJJKK x8 */
251 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
252 /* JJJJKKKK x8 */
253 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
254 /* JJJJJJJKKKKKKK x8 */
255 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
256 /* JJJJJJJK x8 */
257 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
258 /* JKKKKKKK x10, JK */
259 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
260
261 /* implicit CRC16 then EOP to end */
262};
263
264void musb_load_testpacket(struct musb *musb)
265{
266 void __iomem *regs = musb->endpoints[0].regs;
267
268 musb_ep_select(musb->mregs, 0);
269 musb_write_fifo(musb->control_ep,
270 sizeof(musb_test_packet), musb_test_packet);
271 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
272}
273
274/*-------------------------------------------------------------------------*/
275
276const char *otg_state_string(struct musb *musb)
277{
278 switch (musb->xceiv.state) {
279 case OTG_STATE_A_IDLE: return "a_idle";
280 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
281 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
282 case OTG_STATE_A_HOST: return "a_host";
283 case OTG_STATE_A_SUSPEND: return "a_suspend";
284 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
285 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
286 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
287 case OTG_STATE_B_IDLE: return "b_idle";
288 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
289 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
290 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
291 case OTG_STATE_B_HOST: return "b_host";
292 default: return "UNDEFINED";
293 }
294}
295
296#ifdef CONFIG_USB_MUSB_OTG
297
298/*
299 * See also USB_OTG_1-3.pdf 6.6.5 Timers
300 * REVISIT: Are the other timers done in the hardware?
301 */
302#define TB_ASE0_BRST 100 /* Min 3.125 ms */
303
304/*
305 * Handles OTG hnp timeouts, such as b_ase0_brst
306 */
307void musb_otg_timer_func(unsigned long data)
308{
309 struct musb *musb = (struct musb *)data;
310 unsigned long flags;
311
312 spin_lock_irqsave(&musb->lock, flags);
313 switch (musb->xceiv.state) {
314 case OTG_STATE_B_WAIT_ACON:
315 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
316 musb_g_disconnect(musb);
317 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
318 musb->is_active = 0;
319 break;
320 case OTG_STATE_A_WAIT_BCON:
321 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
322 musb_hnp_stop(musb);
323 break;
324 default:
325 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
326 }
327 musb->ignore_disconnect = 0;
328 spin_unlock_irqrestore(&musb->lock, flags);
329}
330
331static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
332
333/*
334 * Stops the B-device HNP state. Caller must take care of locking.
335 */
336void musb_hnp_stop(struct musb *musb)
337{
338 struct usb_hcd *hcd = musb_to_hcd(musb);
339 void __iomem *mbase = musb->mregs;
340 u8 reg;
341
342 switch (musb->xceiv.state) {
343 case OTG_STATE_A_PERIPHERAL:
344 case OTG_STATE_A_WAIT_VFALL:
345 case OTG_STATE_A_WAIT_BCON:
346 DBG(1, "HNP: Switching back to A-host\n");
347 musb_g_disconnect(musb);
348 musb->xceiv.state = OTG_STATE_A_IDLE;
349 MUSB_HST_MODE(musb);
350 musb->is_active = 0;
351 break;
352 case OTG_STATE_B_HOST:
353 DBG(1, "HNP: Disabling HR\n");
354 hcd->self.is_b_host = 0;
355 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
356 MUSB_DEV_MODE(musb);
357 reg = musb_readb(mbase, MUSB_POWER);
358 reg |= MUSB_POWER_SUSPENDM;
359 musb_writeb(mbase, MUSB_POWER, reg);
360 /* REVISIT: Start SESSION_REQUEST here? */
361 break;
362 default:
363 DBG(1, "HNP: Stopping in unknown state %s\n",
364 otg_state_string(musb));
365 }
366
367 /*
368 * When returning to A state after HNP, avoid hub_port_rebounce(),
369 * which cause occasional OPT A "Did not receive reset after connect"
370 * errors.
371 */
372 musb->port1_status &=
373 ~(1 << USB_PORT_FEAT_C_CONNECTION);
374}
375
376#endif
377
378/*
379 * Interrupt Service Routine to record USB "global" interrupts.
380 * Since these do not happen often and signify things of
381 * paramount importance, it seems OK to check them individually;
382 * the order of the tests is specified in the manual
383 *
384 * @param musb instance pointer
385 * @param int_usb register contents
386 * @param devctl
387 * @param power
388 */
389
390#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
391 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
392 | MUSB_INTR_RESET)
393
394static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
395 u8 devctl, u8 power)
396{
397 irqreturn_t handled = IRQ_NONE;
398 void __iomem *mbase = musb->mregs;
399
400 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
401 int_usb);
402
403 /* in host mode, the peripheral may issue remote wakeup.
404 * in peripheral mode, the host may resume the link.
405 * spurious RESUME irqs happen too, paired with SUSPEND.
406 */
407 if (int_usb & MUSB_INTR_RESUME) {
408 handled = IRQ_HANDLED;
409 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
410
411 if (devctl & MUSB_DEVCTL_HM) {
412#ifdef CONFIG_USB_MUSB_HDRC_HCD
413 switch (musb->xceiv.state) {
414 case OTG_STATE_A_SUSPEND:
415 /* remote wakeup? later, GetPortStatus
416 * will stop RESUME signaling
417 */
418
419 if (power & MUSB_POWER_SUSPENDM) {
420 /* spurious */
421 musb->int_usb &= ~MUSB_INTR_SUSPEND;
422 DBG(2, "Spurious SUSPENDM\n");
423 break;
424 }
425
426 power &= ~MUSB_POWER_SUSPENDM;
427 musb_writeb(mbase, MUSB_POWER,
428 power | MUSB_POWER_RESUME);
429
430 musb->port1_status |=
431 (USB_PORT_STAT_C_SUSPEND << 16)
432 | MUSB_PORT_STAT_RESUME;
433 musb->rh_timer = jiffies
434 + msecs_to_jiffies(20);
435
436 musb->xceiv.state = OTG_STATE_A_HOST;
437 musb->is_active = 1;
438 usb_hcd_resume_root_hub(musb_to_hcd(musb));
439 break;
440 case OTG_STATE_B_WAIT_ACON:
441 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
442 musb->is_active = 1;
443 MUSB_DEV_MODE(musb);
444 break;
445 default:
446 WARNING("bogus %s RESUME (%s)\n",
447 "host",
448 otg_state_string(musb));
449 }
450#endif
451 } else {
452 switch (musb->xceiv.state) {
453#ifdef CONFIG_USB_MUSB_HDRC_HCD
454 case OTG_STATE_A_SUSPEND:
455 /* possibly DISCONNECT is upcoming */
456 musb->xceiv.state = OTG_STATE_A_HOST;
457 usb_hcd_resume_root_hub(musb_to_hcd(musb));
458 break;
459#endif
460#ifdef CONFIG_USB_GADGET_MUSB_HDRC
461 case OTG_STATE_B_WAIT_ACON:
462 case OTG_STATE_B_PERIPHERAL:
463 /* disconnect while suspended? we may
464 * not get a disconnect irq...
465 */
466 if ((devctl & MUSB_DEVCTL_VBUS)
467 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
468 ) {
469 musb->int_usb |= MUSB_INTR_DISCONNECT;
470 musb->int_usb &= ~MUSB_INTR_SUSPEND;
471 break;
472 }
473 musb_g_resume(musb);
474 break;
475 case OTG_STATE_B_IDLE:
476 musb->int_usb &= ~MUSB_INTR_SUSPEND;
477 break;
478#endif
479 default:
480 WARNING("bogus %s RESUME (%s)\n",
481 "peripheral",
482 otg_state_string(musb));
483 }
484 }
485 }
486
487#ifdef CONFIG_USB_MUSB_HDRC_HCD
488 /* see manual for the order of the tests */
489 if (int_usb & MUSB_INTR_SESSREQ) {
490 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
491
492 /* IRQ arrives from ID pin sense or (later, if VBUS power
493 * is removed) SRP. responses are time critical:
494 * - turn on VBUS (with silicon-specific mechanism)
495 * - go through A_WAIT_VRISE
496 * - ... to A_WAIT_BCON.
497 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
498 */
499 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
500 musb->ep0_stage = MUSB_EP0_START;
501 musb->xceiv.state = OTG_STATE_A_IDLE;
502 MUSB_HST_MODE(musb);
503 musb_set_vbus(musb, 1);
504
505 handled = IRQ_HANDLED;
506 }
507
508 if (int_usb & MUSB_INTR_VBUSERROR) {
509 int ignore = 0;
510
511 /* During connection as an A-Device, we may see a short
512 * current spikes causing voltage drop, because of cable
513 * and peripheral capacitance combined with vbus draw.
514 * (So: less common with truly self-powered devices, where
515 * vbus doesn't act like a power supply.)
516 *
517 * Such spikes are short; usually less than ~500 usec, max
518 * of ~2 msec. That is, they're not sustained overcurrent
519 * errors, though they're reported using VBUSERROR irqs.
520 *
521 * Workarounds: (a) hardware: use self powered devices.
522 * (b) software: ignore non-repeated VBUS errors.
523 *
524 * REVISIT: do delays from lots of DEBUG_KERNEL checks
525 * make trouble here, keeping VBUS < 4.4V ?
526 */
527 switch (musb->xceiv.state) {
528 case OTG_STATE_A_HOST:
529 /* recovery is dicey once we've gotten past the
530 * initial stages of enumeration, but if VBUS
531 * stayed ok at the other end of the link, and
532 * another reset is due (at least for high speed,
533 * to redo the chirp etc), it might work OK...
534 */
535 case OTG_STATE_A_WAIT_BCON:
536 case OTG_STATE_A_WAIT_VRISE:
537 if (musb->vbuserr_retry) {
538 musb->vbuserr_retry--;
539 ignore = 1;
540 devctl |= MUSB_DEVCTL_SESSION;
541 musb_writeb(mbase, MUSB_DEVCTL, devctl);
542 } else {
543 musb->port1_status |=
544 (1 << USB_PORT_FEAT_OVER_CURRENT)
545 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
546 }
547 break;
548 default:
549 break;
550 }
551
552 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
553 otg_state_string(musb),
554 devctl,
555 ({ char *s;
556 switch (devctl & MUSB_DEVCTL_VBUS) {
557 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
558 s = "<SessEnd"; break;
559 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
560 s = "<AValid"; break;
561 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
562 s = "<VBusValid"; break;
563 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
564 default:
565 s = "VALID"; break;
566 }; s; }),
567 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
568 musb->port1_status);
569
570 /* go through A_WAIT_VFALL then start a new session */
571 if (!ignore)
572 musb_set_vbus(musb, 0);
573 handled = IRQ_HANDLED;
574 }
575
576 if (int_usb & MUSB_INTR_CONNECT) {
577 struct usb_hcd *hcd = musb_to_hcd(musb);
578
579 handled = IRQ_HANDLED;
580 musb->is_active = 1;
581 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
582
583 musb->ep0_stage = MUSB_EP0_START;
584
585#ifdef CONFIG_USB_MUSB_OTG
586 /* flush endpoints when transitioning from Device Mode */
587 if (is_peripheral_active(musb)) {
588 /* REVISIT HNP; just force disconnect */
589 }
590 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
591 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
592 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
593#endif
594 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
595 |USB_PORT_STAT_HIGH_SPEED
596 |USB_PORT_STAT_ENABLE
597 );
598 musb->port1_status |= USB_PORT_STAT_CONNECTION
599 |(USB_PORT_STAT_C_CONNECTION << 16);
600
601 /* high vs full speed is just a guess until after reset */
602 if (devctl & MUSB_DEVCTL_LSDEV)
603 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
604
605 if (hcd->status_urb)
606 usb_hcd_poll_rh_status(hcd);
607 else
608 usb_hcd_resume_root_hub(hcd);
609
610 MUSB_HST_MODE(musb);
611
612 /* indicate new connection to OTG machine */
613 switch (musb->xceiv.state) {
614 case OTG_STATE_B_PERIPHERAL:
615 if (int_usb & MUSB_INTR_SUSPEND) {
616 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
617 musb->xceiv.state = OTG_STATE_B_HOST;
618 hcd->self.is_b_host = 1;
619 int_usb &= ~MUSB_INTR_SUSPEND;
620 } else
621 DBG(1, "CONNECT as b_peripheral???\n");
622 break;
623 case OTG_STATE_B_WAIT_ACON:
624 DBG(1, "HNP: Waiting to switch to b_host state\n");
625 musb->xceiv.state = OTG_STATE_B_HOST;
626 hcd->self.is_b_host = 1;
627 break;
628 default:
629 if ((devctl & MUSB_DEVCTL_VBUS)
630 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
631 musb->xceiv.state = OTG_STATE_A_HOST;
632 hcd->self.is_b_host = 0;
633 }
634 break;
635 }
636 DBG(1, "CONNECT (%s) devctl %02x\n",
637 otg_state_string(musb), devctl);
638 }
639#endif /* CONFIG_USB_MUSB_HDRC_HCD */
640
641 /* mentor saves a bit: bus reset and babble share the same irq.
642 * only host sees babble; only peripheral sees bus reset.
643 */
644 if (int_usb & MUSB_INTR_RESET) {
645 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
646 /*
647 * Looks like non-HS BABBLE can be ignored, but
648 * HS BABBLE is an error condition. For HS the solution
649 * is to avoid babble in the first place and fix what
650 * caused BABBLE. When HS BABBLE happens we can only
651 * stop the session.
652 */
653 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
654 DBG(1, "BABBLE devctl: %02x\n", devctl);
655 else {
656 ERR("Stopping host session -- babble\n");
657 musb_writeb(mbase, MUSB_DEVCTL, 0);
658 }
659 } else if (is_peripheral_capable()) {
660 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
661 switch (musb->xceiv.state) {
662#ifdef CONFIG_USB_OTG
663 case OTG_STATE_A_SUSPEND:
664 /* We need to ignore disconnect on suspend
665 * otherwise tusb 2.0 won't reconnect after a
666 * power cycle, which breaks otg compliance.
667 */
668 musb->ignore_disconnect = 1;
669 musb_g_reset(musb);
670 /* FALLTHROUGH */
671 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
672 DBG(1, "HNP: Setting timer as %s\n",
673 otg_state_string(musb));
674 musb_otg_timer.data = (unsigned long)musb;
675 mod_timer(&musb_otg_timer, jiffies
676 + msecs_to_jiffies(100));
677 break;
678 case OTG_STATE_A_PERIPHERAL:
679 musb_hnp_stop(musb);
680 break;
681 case OTG_STATE_B_WAIT_ACON:
682 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
683 otg_state_string(musb));
684 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
685 musb_g_reset(musb);
686 break;
687#endif
688 case OTG_STATE_B_IDLE:
689 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
690 /* FALLTHROUGH */
691 case OTG_STATE_B_PERIPHERAL:
692 musb_g_reset(musb);
693 break;
694 default:
695 DBG(1, "Unhandled BUS RESET as %s\n",
696 otg_state_string(musb));
697 }
698 }
699
700 handled = IRQ_HANDLED;
701 }
702 schedule_work(&musb->irq_work);
703
704 return handled;
705}
706
707/*
708 * Interrupt Service Routine to record USB "global" interrupts.
709 * Since these do not happen often and signify things of
710 * paramount importance, it seems OK to check them individually;
711 * the order of the tests is specified in the manual
712 *
713 * @param musb instance pointer
714 * @param int_usb register contents
715 * @param devctl
716 * @param power
717 */
718static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
719 u8 devctl, u8 power)
720{
721 irqreturn_t handled = IRQ_NONE;
722
723#if 0
724/* REVISIT ... this would be for multiplexing periodic endpoints, or
725 * supporting transfer phasing to prevent exceeding ISO bandwidth
726 * limits of a given frame or microframe.
727 *
728 * It's not needed for peripheral side, which dedicates endpoints;
729 * though it _might_ use SOF irqs for other purposes.
730 *
731 * And it's not currently needed for host side, which also dedicates
732 * endpoints, relies on TX/RX interval registers, and isn't claimed
733 * to support ISO transfers yet.
734 */
735 if (int_usb & MUSB_INTR_SOF) {
736 void __iomem *mbase = musb->mregs;
737 struct musb_hw_ep *ep;
738 u8 epnum;
739 u16 frame;
740
741 DBG(6, "START_OF_FRAME\n");
742 handled = IRQ_HANDLED;
743
744 /* start any periodic Tx transfers waiting for current frame */
745 frame = musb_readw(mbase, MUSB_FRAME);
746 ep = musb->endpoints;
747 for (epnum = 1; (epnum < musb->nr_endpoints)
748 && (musb->epmask >= (1 << epnum));
749 epnum++, ep++) {
750 /*
751 * FIXME handle framecounter wraps (12 bits)
752 * eliminate duplicated StartUrb logic
753 */
754 if (ep->dwWaitFrame >= frame) {
755 ep->dwWaitFrame = 0;
756 pr_debug("SOF --> periodic TX%s on %d\n",
757 ep->tx_channel ? " DMA" : "",
758 epnum);
759 if (!ep->tx_channel)
760 musb_h_tx_start(musb, epnum);
761 else
762 cppi_hostdma_start(musb, epnum);
763 }
764 } /* end of for loop */
765 }
766#endif
767
768 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
769 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
770 otg_state_string(musb),
771 MUSB_MODE(musb), devctl);
772 handled = IRQ_HANDLED;
773
774 switch (musb->xceiv.state) {
775#ifdef CONFIG_USB_MUSB_HDRC_HCD
776 case OTG_STATE_A_HOST:
777 case OTG_STATE_A_SUSPEND:
778 musb_root_disconnect(musb);
779 if (musb->a_wait_bcon != 0)
780 musb_platform_try_idle(musb, jiffies
781 + msecs_to_jiffies(musb->a_wait_bcon));
782 break;
783#endif /* HOST */
784#ifdef CONFIG_USB_MUSB_OTG
785 case OTG_STATE_B_HOST:
786 musb_hnp_stop(musb);
787 break;
788 case OTG_STATE_A_PERIPHERAL:
789 musb_hnp_stop(musb);
790 musb_root_disconnect(musb);
791 /* FALLTHROUGH */
792 case OTG_STATE_B_WAIT_ACON:
793 /* FALLTHROUGH */
794#endif /* OTG */
795#ifdef CONFIG_USB_GADGET_MUSB_HDRC
796 case OTG_STATE_B_PERIPHERAL:
797 case OTG_STATE_B_IDLE:
798 musb_g_disconnect(musb);
799 break;
800#endif /* GADGET */
801 default:
802 WARNING("unhandled DISCONNECT transition (%s)\n",
803 otg_state_string(musb));
804 break;
805 }
806
807 schedule_work(&musb->irq_work);
808 }
809
810 if (int_usb & MUSB_INTR_SUSPEND) {
811 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
812 otg_state_string(musb), devctl, power);
813 handled = IRQ_HANDLED;
814
815 switch (musb->xceiv.state) {
816#ifdef CONFIG_USB_MUSB_OTG
817 case OTG_STATE_A_PERIPHERAL:
818 /*
819 * We cannot stop HNP here, devctl BDEVICE might be
820 * still set.
821 */
822 break;
823#endif
824 case OTG_STATE_B_PERIPHERAL:
825 musb_g_suspend(musb);
826 musb->is_active = is_otg_enabled(musb)
827 && musb->xceiv.gadget->b_hnp_enable;
828 if (musb->is_active) {
829#ifdef CONFIG_USB_MUSB_OTG
830 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
831 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
832 musb_otg_timer.data = (unsigned long)musb;
833 mod_timer(&musb_otg_timer, jiffies
834 + msecs_to_jiffies(TB_ASE0_BRST));
835#endif
836 }
837 break;
838 case OTG_STATE_A_WAIT_BCON:
839 if (musb->a_wait_bcon != 0)
840 musb_platform_try_idle(musb, jiffies
841 + msecs_to_jiffies(musb->a_wait_bcon));
842 break;
843 case OTG_STATE_A_HOST:
844 musb->xceiv.state = OTG_STATE_A_SUSPEND;
845 musb->is_active = is_otg_enabled(musb)
846 && musb->xceiv.host->b_hnp_enable;
847 break;
848 case OTG_STATE_B_HOST:
849 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
850 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
851 break;
852 default:
853 /* "should not happen" */
854 musb->is_active = 0;
855 break;
856 }
857 schedule_work(&musb->irq_work);
858 }
859
860
861 return handled;
862}
863
864/*-------------------------------------------------------------------------*/
865
866/*
867* Program the HDRC to start (enable interrupts, dma, etc.).
868*/
869void musb_start(struct musb *musb)
870{
871 void __iomem *regs = musb->mregs;
872 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
873
874 DBG(2, "<== devctl %02x\n", devctl);
875
876 /* Set INT enable registers, enable interrupts */
877 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
878 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
879 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
880
881 musb_writeb(regs, MUSB_TESTMODE, 0);
882
883 /* put into basic highspeed mode and start session */
884 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
885 | MUSB_POWER_SOFTCONN
886 | MUSB_POWER_HSENAB
887 /* ENSUSPEND wedges tusb */
888 /* | MUSB_POWER_ENSUSPEND */
889 );
890
891 musb->is_active = 0;
892 devctl = musb_readb(regs, MUSB_DEVCTL);
893 devctl &= ~MUSB_DEVCTL_SESSION;
894
895 if (is_otg_enabled(musb)) {
896 /* session started after:
897 * (a) ID-grounded irq, host mode;
898 * (b) vbus present/connect IRQ, peripheral mode;
899 * (c) peripheral initiates, using SRP
900 */
901 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
902 musb->is_active = 1;
903 else
904 devctl |= MUSB_DEVCTL_SESSION;
905
906 } else if (is_host_enabled(musb)) {
907 /* assume ID pin is hard-wired to ground */
908 devctl |= MUSB_DEVCTL_SESSION;
909
910 } else /* peripheral is enabled */ {
911 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
912 musb->is_active = 1;
913 }
914 musb_platform_enable(musb);
915 musb_writeb(regs, MUSB_DEVCTL, devctl);
916}
917
918
919static void musb_generic_disable(struct musb *musb)
920{
921 void __iomem *mbase = musb->mregs;
922 u16 temp;
923
924 /* disable interrupts */
925 musb_writeb(mbase, MUSB_INTRUSBE, 0);
926 musb_writew(mbase, MUSB_INTRTXE, 0);
927 musb_writew(mbase, MUSB_INTRRXE, 0);
928
929 /* off */
930 musb_writeb(mbase, MUSB_DEVCTL, 0);
931
932 /* flush pending interrupts */
933 temp = musb_readb(mbase, MUSB_INTRUSB);
934 temp = musb_readw(mbase, MUSB_INTRTX);
935 temp = musb_readw(mbase, MUSB_INTRRX);
936
937}
938
939/*
940 * Make the HDRC stop (disable interrupts, etc.);
941 * reversible by musb_start
942 * called on gadget driver unregister
943 * with controller locked, irqs blocked
944 * acts as a NOP unless some role activated the hardware
945 */
946void musb_stop(struct musb *musb)
947{
948 /* stop IRQs, timers, ... */
949 musb_platform_disable(musb);
950 musb_generic_disable(musb);
951 DBG(3, "HDRC disabled\n");
952
953 /* FIXME
954 * - mark host and/or peripheral drivers unusable/inactive
955 * - disable DMA (and enable it in HdrcStart)
956 * - make sure we can musb_start() after musb_stop(); with
957 * OTG mode, gadget driver module rmmod/modprobe cycles that
958 * - ...
959 */
960 musb_platform_try_idle(musb, 0);
961}
962
963static void musb_shutdown(struct platform_device *pdev)
964{
965 struct musb *musb = dev_to_musb(&pdev->dev);
966 unsigned long flags;
967
968 spin_lock_irqsave(&musb->lock, flags);
969 musb_platform_disable(musb);
970 musb_generic_disable(musb);
971 if (musb->clock) {
972 clk_put(musb->clock);
973 musb->clock = NULL;
974 }
975 spin_unlock_irqrestore(&musb->lock, flags);
976
977 /* FIXME power down */
978}
979
980
981/*-------------------------------------------------------------------------*/
982
983/*
984 * The silicon either has hard-wired endpoint configurations, or else
985 * "dynamic fifo" sizing. The driver has support for both, though at this
986 * writing only the dynamic sizing is very well tested. We use normal
987 * idioms to so both modes are compile-tested, but dead code elimination
988 * leaves only the relevant one in the object file.
989 *
990 * We don't currently use dynamic fifo setup capability to do anything
991 * more than selecting one of a bunch of predefined configurations.
992 */
993#ifdef MUSB_C_DYNFIFO_DEF
994#define can_dynfifo() 1
995#else
996#define can_dynfifo() 0
997#endif
998
999#if defined(CONFIG_USB_TUSB6010) || \
1000 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1001static ushort __initdata fifo_mode = 4;
1002#else
1003static ushort __initdata fifo_mode = 2;
1004#endif
1005
1006/* "modprobe ... fifo_mode=1" etc */
1007module_param(fifo_mode, ushort, 0);
1008MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1009
1010
1011#define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
1012
1013enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1014enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1015
1016struct fifo_cfg {
1017 u8 hw_ep_num;
1018 enum fifo_style style;
1019 enum buf_mode mode;
1020 u16 maxpacket;
1021};
1022
1023/*
1024 * tables defining fifo_mode values. define more if you like.
1025 * for host side, make sure both halves of ep1 are set up.
1026 */
1027
1028/* mode 0 - fits in 2KB */
1029static struct fifo_cfg __initdata mode_0_cfg[] = {
1030{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1031{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1032{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1033{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1034{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1035};
1036
1037/* mode 1 - fits in 4KB */
1038static struct fifo_cfg __initdata mode_1_cfg[] = {
1039{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1040{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1041{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1042{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1043{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1044};
1045
1046/* mode 2 - fits in 4KB */
1047static struct fifo_cfg __initdata mode_2_cfg[] = {
1048{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1049{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1050{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1051{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1052{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1053{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1054};
1055
1056/* mode 3 - fits in 4KB */
1057static struct fifo_cfg __initdata mode_3_cfg[] = {
1058{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1059{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1060{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1061{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1062{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1063{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1064};
1065
1066/* mode 4 - fits in 16KB */
1067static struct fifo_cfg __initdata mode_4_cfg[] = {
1068{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1069{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1070{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1071{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1072{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1073{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1074{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1075{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1076{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1077{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1078{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1079{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1080{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1081{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1082{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1083{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1084{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1085{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1086{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1087{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1088{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1089{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1090{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1091{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1092{ .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1093{ .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1094{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1095{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1096};
1097
1098
1099/*
1100 * configure a fifo; for non-shared endpoints, this may be called
1101 * once for a tx fifo and once for an rx fifo.
1102 *
1103 * returns negative errno or offset for next fifo.
1104 */
1105static int __init
1106fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1107 const struct fifo_cfg *cfg, u16 offset)
1108{
1109 void __iomem *mbase = musb->mregs;
1110 int size = 0;
1111 u16 maxpacket = cfg->maxpacket;
1112 u16 c_off = offset >> 3;
1113 u8 c_size;
1114
1115 /* expect hw_ep has already been zero-initialized */
1116
1117 size = ffs(max(maxpacket, (u16) 8)) - 1;
1118 maxpacket = 1 << size;
1119
1120 c_size = size - 3;
1121 if (cfg->mode == BUF_DOUBLE) {
1122 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1123 return -EMSGSIZE;
1124 c_size |= MUSB_FIFOSZ_DPB;
1125 } else {
1126 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1127 return -EMSGSIZE;
1128 }
1129
1130 /* configure the FIFO */
1131 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1132
1133#ifdef CONFIG_USB_MUSB_HDRC_HCD
1134 /* EP0 reserved endpoint for control, bidirectional;
1135 * EP1 reserved for bulk, two unidirection halves.
1136 */
1137 if (hw_ep->epnum == 1)
1138 musb->bulk_ep = hw_ep;
1139 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1140#endif
1141 switch (cfg->style) {
1142 case FIFO_TX:
1143 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1144 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1145 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1146 hw_ep->max_packet_sz_tx = maxpacket;
1147 break;
1148 case FIFO_RX:
1149 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1150 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1151 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1152 hw_ep->max_packet_sz_rx = maxpacket;
1153 break;
1154 case FIFO_RXTX:
1155 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1156 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1157 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1158 hw_ep->max_packet_sz_rx = maxpacket;
1159
1160 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1161 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1162 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1163 hw_ep->max_packet_sz_tx = maxpacket;
1164
1165 hw_ep->is_shared_fifo = true;
1166 break;
1167 }
1168
1169 /* NOTE rx and tx endpoint irqs aren't managed separately,
1170 * which happens to be ok
1171 */
1172 musb->epmask |= (1 << hw_ep->epnum);
1173
1174 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1175}
1176
1177static struct fifo_cfg __initdata ep0_cfg = {
1178 .style = FIFO_RXTX, .maxpacket = 64,
1179};
1180
1181static int __init ep_config_from_table(struct musb *musb)
1182{
1183 const struct fifo_cfg *cfg;
1184 unsigned i, n;
1185 int offset;
1186 struct musb_hw_ep *hw_ep = musb->endpoints;
1187
1188 switch (fifo_mode) {
1189 default:
1190 fifo_mode = 0;
1191 /* FALLTHROUGH */
1192 case 0:
1193 cfg = mode_0_cfg;
1194 n = ARRAY_SIZE(mode_0_cfg);
1195 break;
1196 case 1:
1197 cfg = mode_1_cfg;
1198 n = ARRAY_SIZE(mode_1_cfg);
1199 break;
1200 case 2:
1201 cfg = mode_2_cfg;
1202 n = ARRAY_SIZE(mode_2_cfg);
1203 break;
1204 case 3:
1205 cfg = mode_3_cfg;
1206 n = ARRAY_SIZE(mode_3_cfg);
1207 break;
1208 case 4:
1209 cfg = mode_4_cfg;
1210 n = ARRAY_SIZE(mode_4_cfg);
1211 break;
1212 }
1213
1214 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1215 musb_driver_name, fifo_mode);
1216
1217
1218 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1219 /* assert(offset > 0) */
1220
1221 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1222 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1223 */
1224
1225 for (i = 0; i < n; i++) {
1226 u8 epn = cfg->hw_ep_num;
1227
1228 if (epn >= MUSB_C_NUM_EPS) {
1229 pr_debug("%s: invalid ep %d\n",
1230 musb_driver_name, epn);
1231 continue;
1232 }
1233 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1234 if (offset < 0) {
1235 pr_debug("%s: mem overrun, ep %d\n",
1236 musb_driver_name, epn);
1237 return -EINVAL;
1238 }
1239 epn++;
1240 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1241 }
1242
1243 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1244 musb_driver_name,
1245 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1246 offset, DYN_FIFO_SIZE);
1247
1248#ifdef CONFIG_USB_MUSB_HDRC_HCD
1249 if (!musb->bulk_ep) {
1250 pr_debug("%s: missing bulk\n", musb_driver_name);
1251 return -EINVAL;
1252 }
1253#endif
1254
1255 return 0;
1256}
1257
1258
1259/*
1260 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1261 * @param musb the controller
1262 */
1263static int __init ep_config_from_hw(struct musb *musb)
1264{
1265 u8 epnum = 0, reg;
1266 struct musb_hw_ep *hw_ep;
1267 void *mbase = musb->mregs;
1268
1269 DBG(2, "<== static silicon ep config\n");
1270
1271 /* FIXME pick up ep0 maxpacket size */
1272
1273 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1274 musb_ep_select(mbase, epnum);
1275 hw_ep = musb->endpoints + epnum;
1276
1277 /* read from core using indexed model */
1278 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1279 if (!reg) {
1280 /* 0's returned when no more endpoints */
1281 break;
1282 }
1283 musb->nr_endpoints++;
1284 musb->epmask |= (1 << epnum);
1285
1286 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1287
1288 /* shared TX/RX FIFO? */
1289 if ((reg & 0xf0) == 0xf0) {
1290 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1291 hw_ep->is_shared_fifo = true;
1292 continue;
1293 } else {
1294 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1295 hw_ep->is_shared_fifo = false;
1296 }
1297
1298 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1299
1300#ifdef CONFIG_USB_MUSB_HDRC_HCD
1301 /* pick an RX/TX endpoint for bulk */
1302 if (hw_ep->max_packet_sz_tx < 512
1303 || hw_ep->max_packet_sz_rx < 512)
1304 continue;
1305
1306 /* REVISIT: this algorithm is lazy, we should at least
1307 * try to pick a double buffered endpoint.
1308 */
1309 if (musb->bulk_ep)
1310 continue;
1311 musb->bulk_ep = hw_ep;
1312#endif
1313 }
1314
1315#ifdef CONFIG_USB_MUSB_HDRC_HCD
1316 if (!musb->bulk_ep) {
1317 pr_debug("%s: missing bulk\n", musb_driver_name);
1318 return -EINVAL;
1319 }
1320#endif
1321
1322 return 0;
1323}
1324
1325enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1326
1327/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1328 * configure endpoints, or take their config from silicon
1329 */
1330static int __init musb_core_init(u16 musb_type, struct musb *musb)
1331{
1332#ifdef MUSB_AHB_ID
1333 u32 data;
1334#endif
1335 u8 reg;
1336 char *type;
1337 u16 hwvers, rev_major, rev_minor;
1338 char aInfo[78], aRevision[32], aDate[12];
1339 void __iomem *mbase = musb->mregs;
1340 int status = 0;
1341 int i;
1342
1343 /* log core options (read using indexed model) */
1344 musb_ep_select(mbase, 0);
1345 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1346
1347 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1348 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1349 strcat(aInfo, ", dyn FIFOs");
1350 if (reg & MUSB_CONFIGDATA_MPRXE) {
1351 strcat(aInfo, ", bulk combine");
1352#ifdef C_MP_RX
1353 musb->bulk_combine = true;
1354#else
1355 strcat(aInfo, " (X)"); /* no driver support */
1356#endif
1357 }
1358 if (reg & MUSB_CONFIGDATA_MPTXE) {
1359 strcat(aInfo, ", bulk split");
1360#ifdef C_MP_TX
1361 musb->bulk_split = true;
1362#else
1363 strcat(aInfo, " (X)"); /* no driver support */
1364#endif
1365 }
1366 if (reg & MUSB_CONFIGDATA_HBRXE) {
1367 strcat(aInfo, ", HB-ISO Rx");
1368 strcat(aInfo, " (X)"); /* no driver support */
1369 }
1370 if (reg & MUSB_CONFIGDATA_HBTXE) {
1371 strcat(aInfo, ", HB-ISO Tx");
1372 strcat(aInfo, " (X)"); /* no driver support */
1373 }
1374 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1375 strcat(aInfo, ", SoftConn");
1376
1377 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1378 musb_driver_name, reg, aInfo);
1379
1380#ifdef MUSB_AHB_ID
1381 data = musb_readl(mbase, 0x404);
1382 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1383 (data >> 16) & 0xff, (data >> 24) & 0xff);
1384 /* FIXME ID2 and ID3 are unused */
1385 data = musb_readl(mbase, 0x408);
1386 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1387 data = musb_readl(mbase, 0x40c);
1388 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1389 reg = musb_readb(mbase, 0x400);
1390 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1391#else
1392 aDate[0] = 0;
1393#endif
1394 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1395 musb->is_multipoint = 1;
1396 type = "M";
1397 } else {
1398 musb->is_multipoint = 0;
1399 type = "";
1400#ifdef CONFIG_USB_MUSB_HDRC_HCD
1401#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1402 printk(KERN_ERR
1403 "%s: kernel must blacklist external hubs\n",
1404 musb_driver_name);
1405#endif
1406#endif
1407 }
1408
1409 /* log release info */
1410 hwvers = musb_readw(mbase, MUSB_HWVERS);
1411 rev_major = (hwvers >> 10) & 0x1f;
1412 rev_minor = hwvers & 0x3ff;
1413 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1414 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1415 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1416 musb_driver_name, type, aRevision, aDate);
1417
1418 /* configure ep0 */
1419 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1420 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1421
1422 /* discover endpoint configuration */
1423 musb->nr_endpoints = 1;
1424 musb->epmask = 1;
1425
1426 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1427 if (can_dynfifo())
1428 status = ep_config_from_table(musb);
1429 else {
1430 ERR("reconfigure software for Dynamic FIFOs\n");
1431 status = -ENODEV;
1432 }
1433 } else {
1434 if (!can_dynfifo())
1435 status = ep_config_from_hw(musb);
1436 else {
1437 ERR("reconfigure software for static FIFOs\n");
1438 return -ENODEV;
1439 }
1440 }
1441
1442 if (status < 0)
1443 return status;
1444
1445 /* finish init, and print endpoint config */
1446 for (i = 0; i < musb->nr_endpoints; i++) {
1447 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1448
1449 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1450#ifdef CONFIG_USB_TUSB6010
1451 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1452 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1453 hw_ep->fifo_sync_va =
1454 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1455
1456 if (i == 0)
1457 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1458 else
1459 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1460#endif
1461
1462 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1463#ifdef CONFIG_USB_MUSB_HDRC_HCD
1464 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1465 hw_ep->rx_reinit = 1;
1466 hw_ep->tx_reinit = 1;
1467#endif
1468
1469 if (hw_ep->max_packet_sz_tx) {
1470 printk(KERN_DEBUG
1471 "%s: hw_ep %d%s, %smax %d\n",
1472 musb_driver_name, i,
1473 hw_ep->is_shared_fifo ? "shared" : "tx",
1474 hw_ep->tx_double_buffered
1475 ? "doublebuffer, " : "",
1476 hw_ep->max_packet_sz_tx);
1477 }
1478 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1479 printk(KERN_DEBUG
1480 "%s: hw_ep %d%s, %smax %d\n",
1481 musb_driver_name, i,
1482 "rx",
1483 hw_ep->rx_double_buffered
1484 ? "doublebuffer, " : "",
1485 hw_ep->max_packet_sz_rx);
1486 }
1487 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1488 DBG(1, "hw_ep %d not configured\n", i);
1489 }
1490
1491 return 0;
1492}
1493
1494/*-------------------------------------------------------------------------*/
1495
1496#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1497
1498static irqreturn_t generic_interrupt(int irq, void *__hci)
1499{
1500 unsigned long flags;
1501 irqreturn_t retval = IRQ_NONE;
1502 struct musb *musb = __hci;
1503
1504 spin_lock_irqsave(&musb->lock, flags);
1505
1506 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1507 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1508 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1509
1510 if (musb->int_usb || musb->int_tx || musb->int_rx)
1511 retval = musb_interrupt(musb);
1512
1513 spin_unlock_irqrestore(&musb->lock, flags);
1514
1515 /* REVISIT we sometimes get spurious IRQs on g_ep0
1516 * not clear why...
1517 */
1518 if (retval != IRQ_HANDLED)
1519 DBG(5, "spurious?\n");
1520
1521 return IRQ_HANDLED;
1522}
1523
1524#else
1525#define generic_interrupt NULL
1526#endif
1527
1528/*
1529 * handle all the irqs defined by the HDRC core. for now we expect: other
1530 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1531 * will be assigned, and the irq will already have been acked.
1532 *
1533 * called in irq context with spinlock held, irqs blocked
1534 */
1535irqreturn_t musb_interrupt(struct musb *musb)
1536{
1537 irqreturn_t retval = IRQ_NONE;
1538 u8 devctl, power;
1539 int ep_num;
1540 u32 reg;
1541
1542 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1543 power = musb_readb(musb->mregs, MUSB_POWER);
1544
1545 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1546 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1547 musb->int_usb, musb->int_tx, musb->int_rx);
1548
1549 /* the core can interrupt us for multiple reasons; docs have
1550 * a generic interrupt flowchart to follow
1551 */
1552 if (musb->int_usb & STAGE0_MASK)
1553 retval |= musb_stage0_irq(musb, musb->int_usb,
1554 devctl, power);
1555
1556 /* "stage 1" is handling endpoint irqs */
1557
1558 /* handle endpoint 0 first */
1559 if (musb->int_tx & 1) {
1560 if (devctl & MUSB_DEVCTL_HM)
1561 retval |= musb_h_ep0_irq(musb);
1562 else
1563 retval |= musb_g_ep0_irq(musb);
1564 }
1565
1566 /* RX on endpoints 1-15 */
1567 reg = musb->int_rx >> 1;
1568 ep_num = 1;
1569 while (reg) {
1570 if (reg & 1) {
1571 /* musb_ep_select(musb->mregs, ep_num); */
1572 /* REVISIT just retval = ep->rx_irq(...) */
1573 retval = IRQ_HANDLED;
1574 if (devctl & MUSB_DEVCTL_HM) {
1575 if (is_host_capable())
1576 musb_host_rx(musb, ep_num);
1577 } else {
1578 if (is_peripheral_capable())
1579 musb_g_rx(musb, ep_num);
1580 }
1581 }
1582
1583 reg >>= 1;
1584 ep_num++;
1585 }
1586
1587 /* TX on endpoints 1-15 */
1588 reg = musb->int_tx >> 1;
1589 ep_num = 1;
1590 while (reg) {
1591 if (reg & 1) {
1592 /* musb_ep_select(musb->mregs, ep_num); */
1593 /* REVISIT just retval |= ep->tx_irq(...) */
1594 retval = IRQ_HANDLED;
1595 if (devctl & MUSB_DEVCTL_HM) {
1596 if (is_host_capable())
1597 musb_host_tx(musb, ep_num);
1598 } else {
1599 if (is_peripheral_capable())
1600 musb_g_tx(musb, ep_num);
1601 }
1602 }
1603 reg >>= 1;
1604 ep_num++;
1605 }
1606
1607 /* finish handling "global" interrupts after handling fifos */
1608 if (musb->int_usb)
1609 retval |= musb_stage2_irq(musb,
1610 musb->int_usb, devctl, power);
1611
1612 return retval;
1613}
1614
1615
1616#ifndef CONFIG_MUSB_PIO_ONLY
1617static int __initdata use_dma = 1;
1618
1619/* "modprobe ... use_dma=0" etc */
1620module_param(use_dma, bool, 0);
1621MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1622
1623void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1624{
1625 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1626
1627 /* called with controller lock already held */
1628
1629 if (!epnum) {
1630#ifndef CONFIG_USB_TUSB_OMAP_DMA
1631 if (!is_cppi_enabled()) {
1632 /* endpoint 0 */
1633 if (devctl & MUSB_DEVCTL_HM)
1634 musb_h_ep0_irq(musb);
1635 else
1636 musb_g_ep0_irq(musb);
1637 }
1638#endif
1639 } else {
1640 /* endpoints 1..15 */
1641 if (transmit) {
1642 if (devctl & MUSB_DEVCTL_HM) {
1643 if (is_host_capable())
1644 musb_host_tx(musb, epnum);
1645 } else {
1646 if (is_peripheral_capable())
1647 musb_g_tx(musb, epnum);
1648 }
1649 } else {
1650 /* receive */
1651 if (devctl & MUSB_DEVCTL_HM) {
1652 if (is_host_capable())
1653 musb_host_rx(musb, epnum);
1654 } else {
1655 if (is_peripheral_capable())
1656 musb_g_rx(musb, epnum);
1657 }
1658 }
1659 }
1660}
1661
1662#else
1663#define use_dma 0
1664#endif
1665
1666/*-------------------------------------------------------------------------*/
1667
1668#ifdef CONFIG_SYSFS
1669
1670static ssize_t
1671musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1672{
1673 struct musb *musb = dev_to_musb(dev);
1674 unsigned long flags;
1675 int ret = -EINVAL;
1676
1677 spin_lock_irqsave(&musb->lock, flags);
1678 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1679 spin_unlock_irqrestore(&musb->lock, flags);
1680
1681 return ret;
1682}
1683
1684static ssize_t
1685musb_mode_store(struct device *dev, struct device_attribute *attr,
1686 const char *buf, size_t n)
1687{
1688 struct musb *musb = dev_to_musb(dev);
1689 unsigned long flags;
1690
1691 spin_lock_irqsave(&musb->lock, flags);
1692 if (!strncmp(buf, "host", 4))
1693 musb_platform_set_mode(musb, MUSB_HOST);
1694 if (!strncmp(buf, "peripheral", 10))
1695 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1696 if (!strncmp(buf, "otg", 3))
1697 musb_platform_set_mode(musb, MUSB_OTG);
1698 spin_unlock_irqrestore(&musb->lock, flags);
1699
1700 return n;
1701}
1702static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1703
1704static ssize_t
1705musb_vbus_store(struct device *dev, struct device_attribute *attr,
1706 const char *buf, size_t n)
1707{
1708 struct musb *musb = dev_to_musb(dev);
1709 unsigned long flags;
1710 unsigned long val;
1711
1712 if (sscanf(buf, "%lu", &val) < 1) {
1713 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1714 return -EINVAL;
1715 }
1716
1717 spin_lock_irqsave(&musb->lock, flags);
1718 musb->a_wait_bcon = val;
1719 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1720 musb->is_active = 0;
1721 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1722 spin_unlock_irqrestore(&musb->lock, flags);
1723
1724 return n;
1725}
1726
1727static ssize_t
1728musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1729{
1730 struct musb *musb = dev_to_musb(dev);
1731 unsigned long flags;
1732 unsigned long val;
1733 int vbus;
1734
1735 spin_lock_irqsave(&musb->lock, flags);
1736 val = musb->a_wait_bcon;
1737 vbus = musb_platform_get_vbus_status(musb);
1738 spin_unlock_irqrestore(&musb->lock, flags);
1739
1740 return sprintf(buf, "Vbus %s, timeout %lu\n",
1741 vbus ? "on" : "off", val);
1742}
1743static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1744
1745#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1746
1747/* Gadget drivers can't know that a host is connected so they might want
1748 * to start SRP, but users can. This allows userspace to trigger SRP.
1749 */
1750static ssize_t
1751musb_srp_store(struct device *dev, struct device_attribute *attr,
1752 const char *buf, size_t n)
1753{
1754 struct musb *musb = dev_to_musb(dev);
1755 unsigned short srp;
1756
1757 if (sscanf(buf, "%hu", &srp) != 1
1758 || (srp != 1)) {
1759 printk(KERN_ERR "SRP: Value must be 1\n");
1760 return -EINVAL;
1761 }
1762
1763 if (srp == 1)
1764 musb_g_wakeup(musb);
1765
1766 return n;
1767}
1768static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1769
1770#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1771
1772#endif /* sysfs */
1773
1774/* Only used to provide driver mode change events */
1775static void musb_irq_work(struct work_struct *data)
1776{
1777 struct musb *musb = container_of(data, struct musb, irq_work);
1778 static int old_state;
1779
1780 if (musb->xceiv.state != old_state) {
1781 old_state = musb->xceiv.state;
1782 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1783 }
1784}
1785
1786/* --------------------------------------------------------------------------
1787 * Init support
1788 */
1789
1790static struct musb *__init
1791allocate_instance(struct device *dev, void __iomem *mbase)
1792{
1793 struct musb *musb;
1794 struct musb_hw_ep *ep;
1795 int epnum;
1796#ifdef CONFIG_USB_MUSB_HDRC_HCD
1797 struct usb_hcd *hcd;
1798
1799 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1800 if (!hcd)
1801 return NULL;
1802 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1803
1804 musb = hcd_to_musb(hcd);
1805 INIT_LIST_HEAD(&musb->control);
1806 INIT_LIST_HEAD(&musb->in_bulk);
1807 INIT_LIST_HEAD(&musb->out_bulk);
1808
1809 hcd->uses_new_polling = 1;
1810
1811 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1812#else
1813 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1814 if (!musb)
1815 return NULL;
1816 dev_set_drvdata(dev, musb);
1817
1818#endif
1819
1820 musb->mregs = mbase;
1821 musb->ctrl_base = mbase;
1822 musb->nIrq = -ENODEV;
1823 for (epnum = 0, ep = musb->endpoints;
1824 epnum < MUSB_C_NUM_EPS;
1825 epnum++, ep++) {
1826
1827 ep->musb = musb;
1828 ep->epnum = epnum;
1829 }
1830
1831 musb->controller = dev;
1832 return musb;
1833}
1834
1835static void musb_free(struct musb *musb)
1836{
1837 /* this has multiple entry modes. it handles fault cleanup after
1838 * probe(), where things may be partially set up, as well as rmmod
1839 * cleanup after everything's been de-activated.
1840 */
1841
1842#ifdef CONFIG_SYSFS
1843 device_remove_file(musb->controller, &dev_attr_mode);
1844 device_remove_file(musb->controller, &dev_attr_vbus);
1845#ifdef CONFIG_USB_MUSB_OTG
1846 device_remove_file(musb->controller, &dev_attr_srp);
1847#endif
1848#endif
1849
1850#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1851 musb_gadget_cleanup(musb);
1852#endif
1853
1854 if (musb->nIrq >= 0) {
1855 disable_irq_wake(musb->nIrq);
1856 free_irq(musb->nIrq, musb);
1857 }
1858 if (is_dma_capable() && musb->dma_controller) {
1859 struct dma_controller *c = musb->dma_controller;
1860
1861 (void) c->stop(c);
1862 dma_controller_destroy(c);
1863 }
1864
1865 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1866 musb_platform_exit(musb);
1867 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1868
1869 if (musb->clock) {
1870 clk_disable(musb->clock);
1871 clk_put(musb->clock);
1872 }
1873
1874#ifdef CONFIG_USB_MUSB_OTG
1875 put_device(musb->xceiv.dev);
1876#endif
1877
1878#ifdef CONFIG_USB_MUSB_HDRC_HCD
1879 usb_put_hcd(musb_to_hcd(musb));
1880#else
1881 kfree(musb);
1882#endif
1883}
1884
1885/*
1886 * Perform generic per-controller initialization.
1887 *
1888 * @pDevice: the controller (already clocked, etc)
1889 * @nIrq: irq
1890 * @mregs: virtual address of controller registers,
1891 * not yet corrected for platform-specific offsets
1892 */
1893static int __init
1894musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1895{
1896 int status;
1897 struct musb *musb;
1898 struct musb_hdrc_platform_data *plat = dev->platform_data;
1899
1900 /* The driver might handle more features than the board; OK.
1901 * Fail when the board needs a feature that's not enabled.
1902 */
1903 if (!plat) {
1904 dev_dbg(dev, "no platform_data?\n");
1905 return -ENODEV;
1906 }
1907 switch (plat->mode) {
1908 case MUSB_HOST:
1909#ifdef CONFIG_USB_MUSB_HDRC_HCD
1910 break;
1911#else
1912 goto bad_config;
1913#endif
1914 case MUSB_PERIPHERAL:
1915#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1916 break;
1917#else
1918 goto bad_config;
1919#endif
1920 case MUSB_OTG:
1921#ifdef CONFIG_USB_MUSB_OTG
1922 break;
1923#else
1924bad_config:
1925#endif
1926 default:
1927 dev_err(dev, "incompatible Kconfig role setting\n");
1928 return -EINVAL;
1929 }
1930
1931 /* allocate */
1932 musb = allocate_instance(dev, ctrl);
1933 if (!musb)
1934 return -ENOMEM;
1935
1936 spin_lock_init(&musb->lock);
1937 musb->board_mode = plat->mode;
1938 musb->board_set_power = plat->set_power;
1939 musb->set_clock = plat->set_clock;
1940 musb->min_power = plat->min_power;
1941
1942 /* Clock usage is chip-specific ... functional clock (DaVinci,
1943 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1944 * code does is make sure a clock handle is available; platform
1945 * code manages it during start/stop and suspend/resume.
1946 */
1947 if (plat->clock) {
1948 musb->clock = clk_get(dev, plat->clock);
1949 if (IS_ERR(musb->clock)) {
1950 status = PTR_ERR(musb->clock);
1951 musb->clock = NULL;
1952 goto fail;
1953 }
1954 }
1955
1956 /* assume vbus is off */
1957
1958 /* platform adjusts musb->mregs and musb->isr if needed,
1959 * and activates clocks
1960 */
1961 musb->isr = generic_interrupt;
1962 status = musb_platform_init(musb);
1963
1964 if (status < 0)
1965 goto fail;
1966 if (!musb->isr) {
1967 status = -ENODEV;
1968 goto fail2;
1969 }
1970
1971#ifndef CONFIG_MUSB_PIO_ONLY
1972 if (use_dma && dev->dma_mask) {
1973 struct dma_controller *c;
1974
1975 c = dma_controller_create(musb, musb->mregs);
1976 musb->dma_controller = c;
1977 if (c)
1978 (void) c->start(c);
1979 }
1980#endif
1981 /* ideally this would be abstracted in platform setup */
1982 if (!is_dma_capable() || !musb->dma_controller)
1983 dev->dma_mask = NULL;
1984
1985 /* be sure interrupts are disabled before connecting ISR */
1986 musb_platform_disable(musb);
1987 musb_generic_disable(musb);
1988
1989 /* setup musb parts of the core (especially endpoints) */
1990 status = musb_core_init(plat->multipoint
1991 ? MUSB_CONTROLLER_MHDRC
1992 : MUSB_CONTROLLER_HDRC, musb);
1993 if (status < 0)
1994 goto fail2;
1995
1996 /* Init IRQ workqueue before request_irq */
1997 INIT_WORK(&musb->irq_work, musb_irq_work);
1998
1999 /* attach to the IRQ */
2000 if (request_irq(nIrq, musb->isr, 0, dev->bus_id, musb)) {
2001 dev_err(dev, "request_irq %d failed!\n", nIrq);
2002 status = -ENODEV;
2003 goto fail2;
2004 }
2005 musb->nIrq = nIrq;
2006/* FIXME this handles wakeup irqs wrong */
2007 if (enable_irq_wake(nIrq) == 0)
2008 device_init_wakeup(dev, 1);
2009
2010 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2011 musb_driver_name,
2012 ({char *s;
2013 switch (musb->board_mode) {
2014 case MUSB_HOST: s = "Host"; break;
2015 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2016 default: s = "OTG"; break;
2017 }; s; }),
2018 ctrl,
2019 (is_dma_capable() && musb->dma_controller)
2020 ? "DMA" : "PIO",
2021 musb->nIrq);
2022
2023#ifdef CONFIG_USB_MUSB_HDRC_HCD
2024 /* host side needs more setup, except for no-host modes */
2025 if (musb->board_mode != MUSB_PERIPHERAL) {
2026 struct usb_hcd *hcd = musb_to_hcd(musb);
2027
2028 if (musb->board_mode == MUSB_OTG)
2029 hcd->self.otg_port = 1;
2030 musb->xceiv.host = &hcd->self;
2031 hcd->power_budget = 2 * (plat->power ? : 250);
2032 }
2033#endif /* CONFIG_USB_MUSB_HDRC_HCD */
2034
2035 /* For the host-only role, we can activate right away.
2036 * (We expect the ID pin to be forcibly grounded!!)
2037 * Otherwise, wait till the gadget driver hooks up.
2038 */
2039 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2040 MUSB_HST_MODE(musb);
2041 musb->xceiv.default_a = 1;
2042 musb->xceiv.state = OTG_STATE_A_IDLE;
2043
2044 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2045
2046 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2047 "HOST", status,
2048 musb_readb(musb->mregs, MUSB_DEVCTL),
2049 (musb_readb(musb->mregs, MUSB_DEVCTL)
2050 & MUSB_DEVCTL_BDEVICE
2051 ? 'B' : 'A'));
2052
2053 } else /* peripheral is enabled */ {
2054 MUSB_DEV_MODE(musb);
2055 musb->xceiv.default_a = 0;
2056 musb->xceiv.state = OTG_STATE_B_IDLE;
2057
2058 status = musb_gadget_setup(musb);
2059
2060 DBG(1, "%s mode, status %d, dev%02x\n",
2061 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2062 status,
2063 musb_readb(musb->mregs, MUSB_DEVCTL));
2064
2065 }
2066
2067 if (status == 0)
2068 musb_debug_create("driver/musb_hdrc", musb);
2069 else {
2070fail:
2071 if (musb->clock)
2072 clk_put(musb->clock);
2073 device_init_wakeup(dev, 0);
2074 musb_free(musb);
2075 return status;
2076 }
2077
2078#ifdef CONFIG_SYSFS
2079 status = device_create_file(dev, &dev_attr_mode);
2080 status = device_create_file(dev, &dev_attr_vbus);
2081#ifdef CONFIG_USB_GADGET_MUSB_HDRC
2082 status = device_create_file(dev, &dev_attr_srp);
2083#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2084 status = 0;
2085#endif
2086
2087 return status;
2088
2089fail2:
2090 musb_platform_exit(musb);
2091 goto fail;
2092}
2093
2094/*-------------------------------------------------------------------------*/
2095
2096/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2097 * bridge to a platform device; this driver then suffices.
2098 */
2099
2100#ifndef CONFIG_MUSB_PIO_ONLY
2101static u64 *orig_dma_mask;
2102#endif
2103
2104static int __init musb_probe(struct platform_device *pdev)
2105{
2106 struct device *dev = &pdev->dev;
2107 int irq = platform_get_irq(pdev, 0);
2108 struct resource *iomem;
2109 void __iomem *base;
2110
2111 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2112 if (!iomem || irq == 0)
2113 return -ENODEV;
2114
2115 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2116 if (!base) {
2117 dev_err(dev, "ioremap failed\n");
2118 return -ENOMEM;
2119 }
2120
2121#ifndef CONFIG_MUSB_PIO_ONLY
2122 /* clobbered by use_dma=n */
2123 orig_dma_mask = dev->dma_mask;
2124#endif
2125 return musb_init_controller(dev, irq, base);
2126}
2127
2128static int __devexit musb_remove(struct platform_device *pdev)
2129{
2130 struct musb *musb = dev_to_musb(&pdev->dev);
2131 void __iomem *ctrl_base = musb->ctrl_base;
2132
2133 /* this gets called on rmmod.
2134 * - Host mode: host may still be active
2135 * - Peripheral mode: peripheral is deactivated (or never-activated)
2136 * - OTG mode: both roles are deactivated (or never-activated)
2137 */
2138 musb_shutdown(pdev);
2139 musb_debug_delete("driver/musb_hdrc", musb);
2140#ifdef CONFIG_USB_MUSB_HDRC_HCD
2141 if (musb->board_mode == MUSB_HOST)
2142 usb_remove_hcd(musb_to_hcd(musb));
2143#endif
2144 musb_free(musb);
2145 iounmap(ctrl_base);
2146 device_init_wakeup(&pdev->dev, 0);
2147#ifndef CONFIG_MUSB_PIO_ONLY
2148 pdev->dev.dma_mask = orig_dma_mask;
2149#endif
2150 return 0;
2151}
2152
2153#ifdef CONFIG_PM
2154
2155static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2156{
2157 unsigned long flags;
2158 struct musb *musb = dev_to_musb(&pdev->dev);
2159
2160 if (!musb->clock)
2161 return 0;
2162
2163 spin_lock_irqsave(&musb->lock, flags);
2164
2165 if (is_peripheral_active(musb)) {
2166 /* FIXME force disconnect unless we know USB will wake
2167 * the system up quickly enough to respond ...
2168 */
2169 } else if (is_host_active(musb)) {
2170 /* we know all the children are suspended; sometimes
2171 * they will even be wakeup-enabled.
2172 */
2173 }
2174
2175 if (musb->set_clock)
2176 musb->set_clock(musb->clock, 0);
2177 else
2178 clk_disable(musb->clock);
2179 spin_unlock_irqrestore(&musb->lock, flags);
2180 return 0;
2181}
2182
2183static int musb_resume(struct platform_device *pdev)
2184{
2185 unsigned long flags;
2186 struct musb *musb = dev_to_musb(&pdev->dev);
2187
2188 if (!musb->clock)
2189 return 0;
2190
2191 spin_lock_irqsave(&musb->lock, flags);
2192
2193 if (musb->set_clock)
2194 musb->set_clock(musb->clock, 1);
2195 else
2196 clk_enable(musb->clock);
2197
2198 /* for static cmos like DaVinci, register values were preserved
2199 * unless for some reason the whole soc powered down and we're
2200 * not treating that as a whole-system restart (e.g. swsusp)
2201 */
2202 spin_unlock_irqrestore(&musb->lock, flags);
2203 return 0;
2204}
2205
2206#else
2207#define musb_suspend NULL
2208#define musb_resume NULL
2209#endif
2210
2211static struct platform_driver musb_driver = {
2212 .driver = {
2213 .name = (char *)musb_driver_name,
2214 .bus = &platform_bus_type,
2215 .owner = THIS_MODULE,
2216 },
2217 .remove = __devexit_p(musb_remove),
2218 .shutdown = musb_shutdown,
2219 .suspend = musb_suspend,
2220 .resume = musb_resume,
2221};
2222
2223/*-------------------------------------------------------------------------*/
2224
2225static int __init musb_init(void)
2226{
2227#ifdef CONFIG_USB_MUSB_HDRC_HCD
2228 if (usb_disabled())
2229 return 0;
2230#endif
2231
2232 pr_info("%s: version " MUSB_VERSION ", "
2233#ifdef CONFIG_MUSB_PIO_ONLY
2234 "pio"
2235#elif defined(CONFIG_USB_TI_CPPI_DMA)
2236 "cppi-dma"
2237#elif defined(CONFIG_USB_INVENTRA_DMA)
2238 "musb-dma"
2239#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2240 "tusb-omap-dma"
2241#else
2242 "?dma?"
2243#endif
2244 ", "
2245#ifdef CONFIG_USB_MUSB_OTG
2246 "otg (peripheral+host)"
2247#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2248 "peripheral"
2249#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2250 "host"
2251#endif
2252 ", debug=%d\n",
2253 musb_driver_name, debug);
2254 return platform_driver_probe(&musb_driver, musb_probe);
2255}
2256
2257/* make us init after usbcore and before usb
2258 * gadget and host-side drivers start to register
2259 */
2260subsys_initcall(musb_init);
2261
2262static void __exit musb_cleanup(void)
2263{
2264 platform_driver_unregister(&musb_driver);
2265}
2266module_exit(musb_cleanup);
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
new file mode 100644
index 000000000000..90035c12ab5f
--- /dev/null
+++ b/drivers/usb/musb/musb_core.h
@@ -0,0 +1,517 @@
1/*
2 * MUSB OTG driver defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_CORE_H__
36#define __MUSB_CORE_H__
37
38#include <linux/slab.h>
39#include <linux/list.h>
40#include <linux/interrupt.h>
41#include <linux/smp_lock.h>
42#include <linux/errno.h>
43#include <linux/clk.h>
44#include <linux/device.h>
45#include <linux/usb/ch9.h>
46#include <linux/usb/gadget.h>
47#include <linux/usb.h>
48#include <linux/usb/otg.h>
49#include <linux/usb/musb.h>
50
51struct musb;
52struct musb_hw_ep;
53struct musb_ep;
54
55
56#include "musb_debug.h"
57#include "musb_dma.h"
58
59#ifdef CONFIG_USB_MUSB_SOC
60/*
61 * Get core configuration from a header converted (by cfg_conv)
62 * from the Verilog config file generated by the core config utility
63 *
64 * For now we assume that header is provided along with other
65 * arch-specific files. Discrete chips will need a build tweak.
66 * So will using AHB IDs from silicon that provides them.
67 */
68#include <asm/arch/hdrc_cnf.h>
69#endif
70
71#include "musb_io.h"
72#include "musb_regs.h"
73
74#include "musb_gadget.h"
75#include "../core/hcd.h"
76#include "musb_host.h"
77
78
79
80#ifdef CONFIG_USB_MUSB_OTG
81
82#define is_peripheral_enabled(musb) ((musb)->board_mode != MUSB_HOST)
83#define is_host_enabled(musb) ((musb)->board_mode != MUSB_PERIPHERAL)
84#define is_otg_enabled(musb) ((musb)->board_mode == MUSB_OTG)
85
86/* NOTE: otg and peripheral-only state machines start at B_IDLE.
87 * OTG or host-only go to A_IDLE when ID is sensed.
88 */
89#define is_peripheral_active(m) (!(m)->is_host)
90#define is_host_active(m) ((m)->is_host)
91
92#else
93#define is_peripheral_enabled(musb) is_peripheral_capable()
94#define is_host_enabled(musb) is_host_capable()
95#define is_otg_enabled(musb) 0
96
97#define is_peripheral_active(musb) is_peripheral_capable()
98#define is_host_active(musb) is_host_capable()
99#endif
100
101#if defined(CONFIG_USB_MUSB_OTG) || defined(CONFIG_USB_MUSB_PERIPHERAL)
102/* for some reason, the "select USB_GADGET_MUSB_HDRC" doesn't always
103 * override that choice selection (often USB_GADGET_DUMMY_HCD).
104 */
105#ifndef CONFIG_USB_GADGET_MUSB_HDRC
106#error bogus Kconfig output ... select CONFIG_USB_GADGET_MUSB_HDRC
107#endif
108#endif /* need MUSB gadget selection */
109
110
111#ifdef CONFIG_PROC_FS
112#include <linux/fs.h>
113#define MUSB_CONFIG_PROC_FS
114#endif
115
116/****************************** PERIPHERAL ROLE *****************************/
117
118#ifdef CONFIG_USB_GADGET_MUSB_HDRC
119
120#define is_peripheral_capable() (1)
121
122extern irqreturn_t musb_g_ep0_irq(struct musb *);
123extern void musb_g_tx(struct musb *, u8);
124extern void musb_g_rx(struct musb *, u8);
125extern void musb_g_reset(struct musb *);
126extern void musb_g_suspend(struct musb *);
127extern void musb_g_resume(struct musb *);
128extern void musb_g_wakeup(struct musb *);
129extern void musb_g_disconnect(struct musb *);
130
131#else
132
133#define is_peripheral_capable() (0)
134
135static inline irqreturn_t musb_g_ep0_irq(struct musb *m) { return IRQ_NONE; }
136static inline void musb_g_reset(struct musb *m) {}
137static inline void musb_g_suspend(struct musb *m) {}
138static inline void musb_g_resume(struct musb *m) {}
139static inline void musb_g_wakeup(struct musb *m) {}
140static inline void musb_g_disconnect(struct musb *m) {}
141
142#endif
143
144/****************************** HOST ROLE ***********************************/
145
146#ifdef CONFIG_USB_MUSB_HDRC_HCD
147
148#define is_host_capable() (1)
149
150extern irqreturn_t musb_h_ep0_irq(struct musb *);
151extern void musb_host_tx(struct musb *, u8);
152extern void musb_host_rx(struct musb *, u8);
153
154#else
155
156#define is_host_capable() (0)
157
158static inline irqreturn_t musb_h_ep0_irq(struct musb *m) { return IRQ_NONE; }
159static inline void musb_host_tx(struct musb *m, u8 e) {}
160static inline void musb_host_rx(struct musb *m, u8 e) {}
161
162#endif
163
164
165/****************************** CONSTANTS ********************************/
166
167#ifndef MUSB_C_NUM_EPS
168#define MUSB_C_NUM_EPS ((u8)16)
169#endif
170
171#ifndef MUSB_MAX_END0_PACKET
172#define MUSB_MAX_END0_PACKET ((u16)MUSB_EP0_FIFOSIZE)
173#endif
174
175/* host side ep0 states */
176enum musb_h_ep0_state {
177 MUSB_EP0_IDLE,
178 MUSB_EP0_START, /* expect ack of setup */
179 MUSB_EP0_IN, /* expect IN DATA */
180 MUSB_EP0_OUT, /* expect ack of OUT DATA */
181 MUSB_EP0_STATUS, /* expect ack of STATUS */
182} __attribute__ ((packed));
183
184/* peripheral side ep0 states */
185enum musb_g_ep0_state {
186 MUSB_EP0_STAGE_SETUP, /* idle, waiting for setup */
187 MUSB_EP0_STAGE_TX, /* IN data */
188 MUSB_EP0_STAGE_RX, /* OUT data */
189 MUSB_EP0_STAGE_STATUSIN, /* (after OUT data) */
190 MUSB_EP0_STAGE_STATUSOUT, /* (after IN data) */
191 MUSB_EP0_STAGE_ACKWAIT, /* after zlp, before statusin */
192} __attribute__ ((packed));
193
194/* OTG protocol constants */
195#define OTG_TIME_A_WAIT_VRISE 100 /* msec (max) */
196#define OTG_TIME_A_WAIT_BCON 0 /* 0=infinite; min 1000 msec */
197#define OTG_TIME_A_IDLE_BDIS 200 /* msec (min) */
198
199/*************************** REGISTER ACCESS ********************************/
200
201/* Endpoint registers (other than dynfifo setup) can be accessed either
202 * directly with the "flat" model, or after setting up an index register.
203 */
204
205#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_ARCH_OMAP2430) \
206 || defined(CONFIG_ARCH_OMAP3430)
207/* REVISIT indexed access seemed to
208 * misbehave (on DaVinci) for at least peripheral IN ...
209 */
210#define MUSB_FLAT_REG
211#endif
212
213/* TUSB mapping: "flat" plus ep0 special cases */
214#if defined(CONFIG_USB_TUSB6010)
215#define musb_ep_select(_mbase, _epnum) \
216 musb_writeb((_mbase), MUSB_INDEX, (_epnum))
217#define MUSB_EP_OFFSET MUSB_TUSB_OFFSET
218
219/* "flat" mapping: each endpoint has its own i/o address */
220#elif defined(MUSB_FLAT_REG)
221#define musb_ep_select(_mbase, _epnum) (((void)(_mbase)), ((void)(_epnum)))
222#define MUSB_EP_OFFSET MUSB_FLAT_OFFSET
223
224/* "indexed" mapping: INDEX register controls register bank select */
225#else
226#define musb_ep_select(_mbase, _epnum) \
227 musb_writeb((_mbase), MUSB_INDEX, (_epnum))
228#define MUSB_EP_OFFSET MUSB_INDEXED_OFFSET
229#endif
230
231/****************************** FUNCTIONS ********************************/
232
233#define MUSB_HST_MODE(_musb)\
234 { (_musb)->is_host = true; }
235#define MUSB_DEV_MODE(_musb) \
236 { (_musb)->is_host = false; }
237
238#define test_devctl_hst_mode(_x) \
239 (musb_readb((_x)->mregs, MUSB_DEVCTL)&MUSB_DEVCTL_HM)
240
241#define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral")
242
243/******************************** TYPES *************************************/
244
245/*
246 * struct musb_hw_ep - endpoint hardware (bidirectional)
247 *
248 * Ordered slightly for better cacheline locality.
249 */
250struct musb_hw_ep {
251 struct musb *musb;
252 void __iomem *fifo;
253 void __iomem *regs;
254
255#ifdef CONFIG_USB_TUSB6010
256 void __iomem *conf;
257#endif
258
259 /* index in musb->endpoints[] */
260 u8 epnum;
261
262 /* hardware configuration, possibly dynamic */
263 bool is_shared_fifo;
264 bool tx_double_buffered;
265 bool rx_double_buffered;
266 u16 max_packet_sz_tx;
267 u16 max_packet_sz_rx;
268
269 struct dma_channel *tx_channel;
270 struct dma_channel *rx_channel;
271
272#ifdef CONFIG_USB_TUSB6010
273 /* TUSB has "asynchronous" and "synchronous" dma modes */
274 dma_addr_t fifo_async;
275 dma_addr_t fifo_sync;
276 void __iomem *fifo_sync_va;
277#endif
278
279#ifdef CONFIG_USB_MUSB_HDRC_HCD
280 void __iomem *target_regs;
281
282 /* currently scheduled peripheral endpoint */
283 struct musb_qh *in_qh;
284 struct musb_qh *out_qh;
285
286 u8 rx_reinit;
287 u8 tx_reinit;
288#endif
289
290#ifdef CONFIG_USB_GADGET_MUSB_HDRC
291 /* peripheral side */
292 struct musb_ep ep_in; /* TX */
293 struct musb_ep ep_out; /* RX */
294#endif
295};
296
297static inline struct usb_request *next_in_request(struct musb_hw_ep *hw_ep)
298{
299#ifdef CONFIG_USB_GADGET_MUSB_HDRC
300 return next_request(&hw_ep->ep_in);
301#else
302 return NULL;
303#endif
304}
305
306static inline struct usb_request *next_out_request(struct musb_hw_ep *hw_ep)
307{
308#ifdef CONFIG_USB_GADGET_MUSB_HDRC
309 return next_request(&hw_ep->ep_out);
310#else
311 return NULL;
312#endif
313}
314
315/*
316 * struct musb - Driver instance data.
317 */
318struct musb {
319 /* device lock */
320 spinlock_t lock;
321 struct clk *clock;
322 irqreturn_t (*isr)(int, void *);
323 struct work_struct irq_work;
324
325/* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
326#define MUSB_PORT_STAT_RESUME (1 << 31)
327
328 u32 port1_status;
329
330#ifdef CONFIG_USB_MUSB_HDRC_HCD
331 unsigned long rh_timer;
332
333 enum musb_h_ep0_state ep0_stage;
334
335 /* bulk traffic normally dedicates endpoint hardware, and each
336 * direction has its own ring of host side endpoints.
337 * we try to progress the transfer at the head of each endpoint's
338 * queue until it completes or NAKs too much; then we try the next
339 * endpoint.
340 */
341 struct musb_hw_ep *bulk_ep;
342
343 struct list_head control; /* of musb_qh */
344 struct list_head in_bulk; /* of musb_qh */
345 struct list_head out_bulk; /* of musb_qh */
346 struct musb_qh *periodic[32]; /* tree of interrupt+iso */
347#endif
348
349 /* called with IRQs blocked; ON/nonzero implies starting a session,
350 * and waiting at least a_wait_vrise_tmout.
351 */
352 void (*board_set_vbus)(struct musb *, int is_on);
353
354 struct dma_controller *dma_controller;
355
356 struct device *controller;
357 void __iomem *ctrl_base;
358 void __iomem *mregs;
359
360#ifdef CONFIG_USB_TUSB6010
361 dma_addr_t async;
362 dma_addr_t sync;
363 void __iomem *sync_va;
364#endif
365
366 /* passed down from chip/board specific irq handlers */
367 u8 int_usb;
368 u16 int_rx;
369 u16 int_tx;
370
371 struct otg_transceiver xceiv;
372
373 int nIrq;
374
375 struct musb_hw_ep endpoints[MUSB_C_NUM_EPS];
376#define control_ep endpoints
377
378#define VBUSERR_RETRY_COUNT 3
379 u16 vbuserr_retry;
380 u16 epmask;
381 u8 nr_endpoints;
382
383 u8 board_mode; /* enum musb_mode */
384 int (*board_set_power)(int state);
385
386 int (*set_clock)(struct clk *clk, int is_active);
387
388 u8 min_power; /* vbus for periph, in mA/2 */
389
390 bool is_host;
391
392 int a_wait_bcon; /* VBUS timeout in msecs */
393 unsigned long idle_timeout; /* Next timeout in jiffies */
394
395 /* active means connected and not suspended */
396 unsigned is_active:1;
397
398 unsigned is_multipoint:1;
399 unsigned ignore_disconnect:1; /* during bus resets */
400
401#ifdef C_MP_TX
402 unsigned bulk_split:1;
403#define can_bulk_split(musb,type) \
404 (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split)
405#else
406#define can_bulk_split(musb, type) 0
407#endif
408
409#ifdef C_MP_RX
410 unsigned bulk_combine:1;
411#define can_bulk_combine(musb,type) \
412 (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine)
413#else
414#define can_bulk_combine(musb, type) 0
415#endif
416
417#ifdef CONFIG_USB_GADGET_MUSB_HDRC
418 /* is_suspended means USB B_PERIPHERAL suspend */
419 unsigned is_suspended:1;
420
421 /* may_wakeup means remote wakeup is enabled */
422 unsigned may_wakeup:1;
423
424 /* is_self_powered is reported in device status and the
425 * config descriptor. is_bus_powered means B_PERIPHERAL
426 * draws some VBUS current; both can be true.
427 */
428 unsigned is_self_powered:1;
429 unsigned is_bus_powered:1;
430
431 unsigned set_address:1;
432 unsigned test_mode:1;
433 unsigned softconnect:1;
434
435 u8 address;
436 u8 test_mode_nr;
437 u16 ackpend; /* ep0 */
438 enum musb_g_ep0_state ep0_state;
439 struct usb_gadget g; /* the gadget */
440 struct usb_gadget_driver *gadget_driver; /* its driver */
441#endif
442
443#ifdef MUSB_CONFIG_PROC_FS
444 struct proc_dir_entry *proc_entry;
445#endif
446};
447
448static inline void musb_set_vbus(struct musb *musb, int is_on)
449{
450 musb->board_set_vbus(musb, is_on);
451}
452
453#ifdef CONFIG_USB_GADGET_MUSB_HDRC
454static inline struct musb *gadget_to_musb(struct usb_gadget *g)
455{
456 return container_of(g, struct musb, g);
457}
458#endif
459
460
461/***************************** Glue it together *****************************/
462
463extern const char musb_driver_name[];
464
465extern void musb_start(struct musb *musb);
466extern void musb_stop(struct musb *musb);
467
468extern void musb_write_fifo(struct musb_hw_ep *ep, u16 len, const u8 *src);
469extern void musb_read_fifo(struct musb_hw_ep *ep, u16 len, u8 *dst);
470
471extern void musb_load_testpacket(struct musb *);
472
473extern irqreturn_t musb_interrupt(struct musb *);
474
475extern void musb_platform_enable(struct musb *musb);
476extern void musb_platform_disable(struct musb *musb);
477
478extern void musb_hnp_stop(struct musb *musb);
479
480extern void musb_platform_set_mode(struct musb *musb, u8 musb_mode);
481
482#if defined(CONFIG_USB_TUSB6010) || \
483 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
484extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
485#else
486#define musb_platform_try_idle(x, y) do {} while (0)
487#endif
488
489#ifdef CONFIG_USB_TUSB6010
490extern int musb_platform_get_vbus_status(struct musb *musb);
491#else
492#define musb_platform_get_vbus_status(x) 0
493#endif
494
495extern int __init musb_platform_init(struct musb *musb);
496extern int musb_platform_exit(struct musb *musb);
497
498/*-------------------------- ProcFS definitions ---------------------*/
499
500struct proc_dir_entry;
501
502#if (MUSB_DEBUG > 0) && defined(MUSB_CONFIG_PROC_FS)
503extern struct proc_dir_entry *musb_debug_create(char *name, struct musb *data);
504extern void musb_debug_delete(char *name, struct musb *data);
505
506#else
507static inline struct proc_dir_entry *
508musb_debug_create(char *name, struct musb *data)
509{
510 return NULL;
511}
512static inline void musb_debug_delete(char *name, struct musb *data)
513{
514}
515#endif
516
517#endif /* __MUSB_CORE_H__ */
diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h
new file mode 100644
index 000000000000..3bdb311e820d
--- /dev/null
+++ b/drivers/usb/musb/musb_debug.h
@@ -0,0 +1,66 @@
1/*
2 * MUSB OTG driver debug defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_LINUX_DEBUG_H__
36#define __MUSB_LINUX_DEBUG_H__
37
38#define yprintk(facility, format, args...) \
39 do { printk(facility "%s %d: " format , \
40 __func__, __LINE__ , ## args); } while (0)
41#define WARNING(fmt, args...) yprintk(KERN_WARNING, fmt, ## args)
42#define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args)
43#define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
44
45#define xprintk(level, facility, format, args...) do { \
46 if (_dbg_level(level)) { \
47 printk(facility "%s %d: " format , \
48 __func__, __LINE__ , ## args); \
49 } } while (0)
50
51#if MUSB_DEBUG > 0
52extern unsigned debug;
53#else
54#define debug 0
55#endif
56
57static inline int _dbg_level(unsigned l)
58{
59 return debug >= l;
60}
61
62#define DBG(level, fmt, args...) xprintk(level, KERN_DEBUG, fmt, ## args)
63
64extern const char *otg_state_string(struct musb *);
65
66#endif /* __MUSB_LINUX_DEBUG_H__ */
diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h
new file mode 100644
index 000000000000..0a2c4e3602c1
--- /dev/null
+++ b/drivers/usb/musb/musb_dma.h
@@ -0,0 +1,172 @@
1/*
2 * MUSB OTG driver DMA controller abstraction
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_DMA_H__
36#define __MUSB_DMA_H__
37
38struct musb_hw_ep;
39
40/*
41 * DMA Controller Abstraction
42 *
43 * DMA Controllers are abstracted to allow use of a variety of different
44 * implementations of DMA, as allowed by the Inventra USB cores. On the
45 * host side, usbcore sets up the DMA mappings and flushes caches; on the
46 * peripheral side, the gadget controller driver does. Responsibilities
47 * of a DMA controller driver include:
48 *
49 * - Handling the details of moving multiple USB packets
50 * in cooperation with the Inventra USB core, including especially
51 * the correct RX side treatment of short packets and buffer-full
52 * states (both of which terminate transfers).
53 *
54 * - Knowing the correlation between dma channels and the
55 * Inventra core's local endpoint resources and data direction.
56 *
57 * - Maintaining a list of allocated/available channels.
58 *
59 * - Updating channel status on interrupts,
60 * whether shared with the Inventra core or separate.
61 */
62
63#define DMA_ADDR_INVALID (~(dma_addr_t)0)
64
65#ifndef CONFIG_MUSB_PIO_ONLY
66#define is_dma_capable() (1)
67#else
68#define is_dma_capable() (0)
69#endif
70
71#ifdef CONFIG_USB_TI_CPPI_DMA
72#define is_cppi_enabled() 1
73#else
74#define is_cppi_enabled() 0
75#endif
76
77#ifdef CONFIG_USB_TUSB_OMAP_DMA
78#define tusb_dma_omap() 1
79#else
80#define tusb_dma_omap() 0
81#endif
82
83/*
84 * DMA channel status ... updated by the dma controller driver whenever that
85 * status changes, and protected by the overall controller spinlock.
86 */
87enum dma_channel_status {
88 /* unallocated */
89 MUSB_DMA_STATUS_UNKNOWN,
90 /* allocated ... but not busy, no errors */
91 MUSB_DMA_STATUS_FREE,
92 /* busy ... transactions are active */
93 MUSB_DMA_STATUS_BUSY,
94 /* transaction(s) aborted due to ... dma or memory bus error */
95 MUSB_DMA_STATUS_BUS_ABORT,
96 /* transaction(s) aborted due to ... core error or USB fault */
97 MUSB_DMA_STATUS_CORE_ABORT
98};
99
100struct dma_controller;
101
102/**
103 * struct dma_channel - A DMA channel.
104 * @private_data: channel-private data
105 * @max_len: the maximum number of bytes the channel can move in one
106 * transaction (typically representing many USB maximum-sized packets)
107 * @actual_len: how many bytes have been transferred
108 * @status: current channel status (updated e.g. on interrupt)
109 * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
110 *
111 * channels are associated with an endpoint for the duration of at least
112 * one usb transfer.
113 */
114struct dma_channel {
115 void *private_data;
116 /* FIXME not void* private_data, but a dma_controller * */
117 size_t max_len;
118 size_t actual_len;
119 enum dma_channel_status status;
120 bool desired_mode;
121};
122
123/*
124 * dma_channel_status - return status of dma channel
125 * @c: the channel
126 *
127 * Returns the software's view of the channel status. If that status is BUSY
128 * then it's possible that the hardware has completed (or aborted) a transfer,
129 * so the driver needs to update that status.
130 */
131static inline enum dma_channel_status
132dma_channel_status(struct dma_channel *c)
133{
134 return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
135}
136
137/**
138 * struct dma_controller - A DMA Controller.
139 * @start: call this to start a DMA controller;
140 * return 0 on success, else negative errno
141 * @stop: call this to stop a DMA controller
142 * return 0 on success, else negative errno
143 * @channel_alloc: call this to allocate a DMA channel
144 * @channel_release: call this to release a DMA channel
145 * @channel_abort: call this to abort a pending DMA transaction,
146 * returning it to FREE (but allocated) state
147 *
148 * Controllers manage dma channels.
149 */
150struct dma_controller {
151 int (*start)(struct dma_controller *);
152 int (*stop)(struct dma_controller *);
153 struct dma_channel *(*channel_alloc)(struct dma_controller *,
154 struct musb_hw_ep *, u8 is_tx);
155 void (*channel_release)(struct dma_channel *);
156 int (*channel_program)(struct dma_channel *channel,
157 u16 maxpacket, u8 mode,
158 dma_addr_t dma_addr,
159 u32 length);
160 int (*channel_abort)(struct dma_channel *);
161};
162
163/* called after channel_program(), may indicate a fault */
164extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
165
166
167extern struct dma_controller *__init
168dma_controller_create(struct musb *, void __iomem *);
169
170extern void dma_controller_destroy(struct dma_controller *);
171
172#endif /* __MUSB_DMA_H__ */
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
new file mode 100644
index 000000000000..b3773f13ee0a
--- /dev/null
+++ b/drivers/usb/musb/musb_gadget.c
@@ -0,0 +1,2033 @@
1/*
2 * MUSB OTG driver peripheral support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/list.h>
37#include <linux/timer.h>
38#include <linux/module.h>
39#include <linux/smp.h>
40#include <linux/spinlock.h>
41#include <linux/delay.h>
42#include <linux/moduleparam.h>
43#include <linux/stat.h>
44#include <linux/dma-mapping.h>
45
46#include "musb_core.h"
47
48
49/* MUSB PERIPHERAL status 3-mar-2006:
50 *
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
52 * Minor glitches:
53 *
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
58 * clearing SENDSTALL?
59 *
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
63 * required.
64 *
65 * - TX/IN
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
71 *
72 * - RX/OUT
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
78 *
79 * - ISO not tested ... might work, but only weakly isochronous
80 *
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
84 *
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
89 */
90
91/* ----------------------------------------------------------------------- */
92
93/*
94 * Immediately complete a request.
95 *
96 * @param request the request to complete
97 * @param status the status to complete the request with
98 * Context: controller locked, IRQs blocked.
99 */
100void musb_g_giveback(
101 struct musb_ep *ep,
102 struct usb_request *request,
103 int status)
104__releases(ep->musb->lock)
105__acquires(ep->musb->lock)
106{
107 struct musb_request *req;
108 struct musb *musb;
109 int busy = ep->busy;
110
111 req = to_musb_request(request);
112
113 list_del(&request->list);
114 if (req->request.status == -EINPROGRESS)
115 req->request.status = status;
116 musb = req->musb;
117
118 ep->busy = 1;
119 spin_unlock(&musb->lock);
120 if (is_dma_capable()) {
121 if (req->mapped) {
122 dma_unmap_single(musb->controller,
123 req->request.dma,
124 req->request.length,
125 req->tx
126 ? DMA_TO_DEVICE
127 : DMA_FROM_DEVICE);
128 req->request.dma = DMA_ADDR_INVALID;
129 req->mapped = 0;
130 } else if (req->request.dma != DMA_ADDR_INVALID)
131 dma_sync_single_for_cpu(musb->controller,
132 req->request.dma,
133 req->request.length,
134 req->tx
135 ? DMA_TO_DEVICE
136 : DMA_FROM_DEVICE);
137 }
138 if (request->status == 0)
139 DBG(5, "%s done request %p, %d/%d\n",
140 ep->end_point.name, request,
141 req->request.actual, req->request.length);
142 else
143 DBG(2, "%s request %p, %d/%d fault %d\n",
144 ep->end_point.name, request,
145 req->request.actual, req->request.length,
146 request->status);
147 req->request.complete(&req->ep->end_point, &req->request);
148 spin_lock(&musb->lock);
149 ep->busy = busy;
150}
151
152/* ----------------------------------------------------------------------- */
153
154/*
155 * Abort requests queued to an endpoint using the status. Synchronous.
156 * caller locked controller and blocked irqs, and selected this ep.
157 */
158static void nuke(struct musb_ep *ep, const int status)
159{
160 struct musb_request *req = NULL;
161 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
162
163 ep->busy = 1;
164
165 if (is_dma_capable() && ep->dma) {
166 struct dma_controller *c = ep->musb->dma_controller;
167 int value;
168 if (ep->is_in) {
169 musb_writew(epio, MUSB_TXCSR,
170 0 | MUSB_TXCSR_FLUSHFIFO);
171 musb_writew(epio, MUSB_TXCSR,
172 0 | MUSB_TXCSR_FLUSHFIFO);
173 } else {
174 musb_writew(epio, MUSB_RXCSR,
175 0 | MUSB_RXCSR_FLUSHFIFO);
176 musb_writew(epio, MUSB_RXCSR,
177 0 | MUSB_RXCSR_FLUSHFIFO);
178 }
179
180 value = c->channel_abort(ep->dma);
181 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
182 c->channel_release(ep->dma);
183 ep->dma = NULL;
184 }
185
186 while (!list_empty(&(ep->req_list))) {
187 req = container_of(ep->req_list.next, struct musb_request,
188 request.list);
189 musb_g_giveback(ep, &req->request, status);
190 }
191}
192
193/* ----------------------------------------------------------------------- */
194
195/* Data transfers - pure PIO, pure DMA, or mixed mode */
196
197/*
198 * This assumes the separate CPPI engine is responding to DMA requests
199 * from the usb core ... sequenced a bit differently from mentor dma.
200 */
201
202static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
203{
204 if (can_bulk_split(musb, ep->type))
205 return ep->hw_ep->max_packet_sz_tx;
206 else
207 return ep->packet_sz;
208}
209
210
211#ifdef CONFIG_USB_INVENTRA_DMA
212
213/* Peripheral tx (IN) using Mentor DMA works as follows:
214 Only mode 0 is used for transfers <= wPktSize,
215 mode 1 is used for larger transfers,
216
217 One of the following happens:
218 - Host sends IN token which causes an endpoint interrupt
219 -> TxAvail
220 -> if DMA is currently busy, exit.
221 -> if queue is non-empty, txstate().
222
223 - Request is queued by the gadget driver.
224 -> if queue was previously empty, txstate()
225
226 txstate()
227 -> start
228 /\ -> setup DMA
229 | (data is transferred to the FIFO, then sent out when
230 | IN token(s) are recd from Host.
231 | -> DMA interrupt on completion
232 | calls TxAvail.
233 | -> stop DMA, ~DmaEenab,
234 | -> set TxPktRdy for last short pkt or zlp
235 | -> Complete Request
236 | -> Continue next request (call txstate)
237 |___________________________________|
238
239 * Non-Mentor DMA engines can of course work differently, such as by
240 * upleveling from irq-per-packet to irq-per-buffer.
241 */
242
243#endif
244
245/*
246 * An endpoint is transmitting data. This can be called either from
247 * the IRQ routine or from ep.queue() to kickstart a request on an
248 * endpoint.
249 *
250 * Context: controller locked, IRQs blocked, endpoint selected
251 */
252static void txstate(struct musb *musb, struct musb_request *req)
253{
254 u8 epnum = req->epnum;
255 struct musb_ep *musb_ep;
256 void __iomem *epio = musb->endpoints[epnum].regs;
257 struct usb_request *request;
258 u16 fifo_count = 0, csr;
259 int use_dma = 0;
260
261 musb_ep = req->ep;
262
263 /* we shouldn't get here while DMA is active ... but we do ... */
264 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
265 DBG(4, "dma pending...\n");
266 return;
267 }
268
269 /* read TXCSR before */
270 csr = musb_readw(epio, MUSB_TXCSR);
271
272 request = &req->request;
273 fifo_count = min(max_ep_writesize(musb, musb_ep),
274 (int)(request->length - request->actual));
275
276 if (csr & MUSB_TXCSR_TXPKTRDY) {
277 DBG(5, "%s old packet still ready , txcsr %03x\n",
278 musb_ep->end_point.name, csr);
279 return;
280 }
281
282 if (csr & MUSB_TXCSR_P_SENDSTALL) {
283 DBG(5, "%s stalling, txcsr %03x\n",
284 musb_ep->end_point.name, csr);
285 return;
286 }
287
288 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
289 epnum, musb_ep->packet_sz, fifo_count,
290 csr);
291
292#ifndef CONFIG_MUSB_PIO_ONLY
293 if (is_dma_capable() && musb_ep->dma) {
294 struct dma_controller *c = musb->dma_controller;
295
296 use_dma = (request->dma != DMA_ADDR_INVALID);
297
298 /* MUSB_TXCSR_P_ISO is still set correctly */
299
300#ifdef CONFIG_USB_INVENTRA_DMA
301 {
302 size_t request_size;
303
304 /* setup DMA, then program endpoint CSR */
305 request_size = min(request->length,
306 musb_ep->dma->max_len);
307 if (request_size <= musb_ep->packet_sz)
308 musb_ep->dma->desired_mode = 0;
309 else
310 musb_ep->dma->desired_mode = 1;
311
312 use_dma = use_dma && c->channel_program(
313 musb_ep->dma, musb_ep->packet_sz,
314 musb_ep->dma->desired_mode,
315 request->dma, request_size);
316 if (use_dma) {
317 if (musb_ep->dma->desired_mode == 0) {
318 /* ASSERT: DMAENAB is clear */
319 csr &= ~(MUSB_TXCSR_AUTOSET |
320 MUSB_TXCSR_DMAMODE);
321 csr |= (MUSB_TXCSR_DMAENAB |
322 MUSB_TXCSR_MODE);
323 /* against programming guide */
324 } else
325 csr |= (MUSB_TXCSR_AUTOSET
326 | MUSB_TXCSR_DMAENAB
327 | MUSB_TXCSR_DMAMODE
328 | MUSB_TXCSR_MODE);
329
330 csr &= ~MUSB_TXCSR_P_UNDERRUN;
331 musb_writew(epio, MUSB_TXCSR, csr);
332 }
333 }
334
335#elif defined(CONFIG_USB_TI_CPPI_DMA)
336 /* program endpoint CSR first, then setup DMA */
337 csr &= ~(MUSB_TXCSR_AUTOSET
338 | MUSB_TXCSR_DMAMODE
339 | MUSB_TXCSR_P_UNDERRUN
340 | MUSB_TXCSR_TXPKTRDY);
341 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_DMAENAB;
342 musb_writew(epio, MUSB_TXCSR,
343 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
344 | csr);
345
346 /* ensure writebuffer is empty */
347 csr = musb_readw(epio, MUSB_TXCSR);
348
349 /* NOTE host side sets DMAENAB later than this; both are
350 * OK since the transfer dma glue (between CPPI and Mentor
351 * fifos) just tells CPPI it could start. Data only moves
352 * to the USB TX fifo when both fifos are ready.
353 */
354
355 /* "mode" is irrelevant here; handle terminating ZLPs like
356 * PIO does, since the hardware RNDIS mode seems unreliable
357 * except for the last-packet-is-already-short case.
358 */
359 use_dma = use_dma && c->channel_program(
360 musb_ep->dma, musb_ep->packet_sz,
361 0,
362 request->dma,
363 request->length);
364 if (!use_dma) {
365 c->channel_release(musb_ep->dma);
366 musb_ep->dma = NULL;
367 /* ASSERT: DMAENAB clear */
368 csr &= ~(MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
369 /* invariant: prequest->buf is non-null */
370 }
371#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
372 use_dma = use_dma && c->channel_program(
373 musb_ep->dma, musb_ep->packet_sz,
374 request->zero,
375 request->dma,
376 request->length);
377#endif
378 }
379#endif
380
381 if (!use_dma) {
382 musb_write_fifo(musb_ep->hw_ep, fifo_count,
383 (u8 *) (request->buf + request->actual));
384 request->actual += fifo_count;
385 csr |= MUSB_TXCSR_TXPKTRDY;
386 csr &= ~MUSB_TXCSR_P_UNDERRUN;
387 musb_writew(epio, MUSB_TXCSR, csr);
388 }
389
390 /* host may already have the data when this message shows... */
391 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
392 musb_ep->end_point.name, use_dma ? "dma" : "pio",
393 request->actual, request->length,
394 musb_readw(epio, MUSB_TXCSR),
395 fifo_count,
396 musb_readw(epio, MUSB_TXMAXP));
397}
398
399/*
400 * FIFO state update (e.g. data ready).
401 * Called from IRQ, with controller locked.
402 */
403void musb_g_tx(struct musb *musb, u8 epnum)
404{
405 u16 csr;
406 struct usb_request *request;
407 u8 __iomem *mbase = musb->mregs;
408 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
409 void __iomem *epio = musb->endpoints[epnum].regs;
410 struct dma_channel *dma;
411
412 musb_ep_select(mbase, epnum);
413 request = next_request(musb_ep);
414
415 csr = musb_readw(epio, MUSB_TXCSR);
416 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
417
418 dma = is_dma_capable() ? musb_ep->dma : NULL;
419 do {
420 /* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX
421 * probably rates reporting as a host error
422 */
423 if (csr & MUSB_TXCSR_P_SENTSTALL) {
424 csr |= MUSB_TXCSR_P_WZC_BITS;
425 csr &= ~MUSB_TXCSR_P_SENTSTALL;
426 musb_writew(epio, MUSB_TXCSR, csr);
427 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
428 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
429 musb->dma_controller->channel_abort(dma);
430 }
431
432 if (request)
433 musb_g_giveback(musb_ep, request, -EPIPE);
434
435 break;
436 }
437
438 if (csr & MUSB_TXCSR_P_UNDERRUN) {
439 /* we NAKed, no big deal ... little reason to care */
440 csr |= MUSB_TXCSR_P_WZC_BITS;
441 csr &= ~(MUSB_TXCSR_P_UNDERRUN
442 | MUSB_TXCSR_TXPKTRDY);
443 musb_writew(epio, MUSB_TXCSR, csr);
444 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
445 }
446
447 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
448 /* SHOULD NOT HAPPEN ... has with cppi though, after
449 * changing SENDSTALL (and other cases); harmless?
450 */
451 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
452 break;
453 }
454
455 if (request) {
456 u8 is_dma = 0;
457
458 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
459 is_dma = 1;
460 csr |= MUSB_TXCSR_P_WZC_BITS;
461 csr &= ~(MUSB_TXCSR_DMAENAB
462 | MUSB_TXCSR_P_UNDERRUN
463 | MUSB_TXCSR_TXPKTRDY);
464 musb_writew(epio, MUSB_TXCSR, csr);
465 /* ensure writebuffer is empty */
466 csr = musb_readw(epio, MUSB_TXCSR);
467 request->actual += musb_ep->dma->actual_len;
468 DBG(4, "TXCSR%d %04x, dma off, "
469 "len %zu, req %p\n",
470 epnum, csr,
471 musb_ep->dma->actual_len,
472 request);
473 }
474
475 if (is_dma || request->actual == request->length) {
476
477 /* First, maybe a terminating short packet.
478 * Some DMA engines might handle this by
479 * themselves.
480 */
481 if ((request->zero
482 && request->length
483 && (request->length
484 % musb_ep->packet_sz)
485 == 0)
486#ifdef CONFIG_USB_INVENTRA_DMA
487 || (is_dma &&
488 ((!dma->desired_mode) ||
489 (request->actual &
490 (musb_ep->packet_sz - 1))))
491#endif
492 ) {
493 /* on dma completion, fifo may not
494 * be available yet ...
495 */
496 if (csr & MUSB_TXCSR_TXPKTRDY)
497 break;
498
499 DBG(4, "sending zero pkt\n");
500 musb_writew(epio, MUSB_TXCSR,
501 MUSB_TXCSR_MODE
502 | MUSB_TXCSR_TXPKTRDY);
503 request->zero = 0;
504 }
505
506 /* ... or if not, then complete it */
507 musb_g_giveback(musb_ep, request, 0);
508
509 /* kickstart next transfer if appropriate;
510 * the packet that just completed might not
511 * be transmitted for hours or days.
512 * REVISIT for double buffering...
513 * FIXME revisit for stalls too...
514 */
515 musb_ep_select(mbase, epnum);
516 csr = musb_readw(epio, MUSB_TXCSR);
517 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
518 break;
519 request = musb_ep->desc
520 ? next_request(musb_ep)
521 : NULL;
522 if (!request) {
523 DBG(4, "%s idle now\n",
524 musb_ep->end_point.name);
525 break;
526 }
527 }
528
529 txstate(musb, to_musb_request(request));
530 }
531
532 } while (0);
533}
534
535/* ------------------------------------------------------------ */
536
537#ifdef CONFIG_USB_INVENTRA_DMA
538
539/* Peripheral rx (OUT) using Mentor DMA works as follows:
540 - Only mode 0 is used.
541
542 - Request is queued by the gadget class driver.
543 -> if queue was previously empty, rxstate()
544
545 - Host sends OUT token which causes an endpoint interrupt
546 /\ -> RxReady
547 | -> if request queued, call rxstate
548 | /\ -> setup DMA
549 | | -> DMA interrupt on completion
550 | | -> RxReady
551 | | -> stop DMA
552 | | -> ack the read
553 | | -> if data recd = max expected
554 | | by the request, or host
555 | | sent a short packet,
556 | | complete the request,
557 | | and start the next one.
558 | |_____________________________________|
559 | else just wait for the host
560 | to send the next OUT token.
561 |__________________________________________________|
562
563 * Non-Mentor DMA engines can of course work differently.
564 */
565
566#endif
567
568/*
569 * Context: controller locked, IRQs blocked, endpoint selected
570 */
571static void rxstate(struct musb *musb, struct musb_request *req)
572{
573 u16 csr = 0;
574 const u8 epnum = req->epnum;
575 struct usb_request *request = &req->request;
576 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
577 void __iomem *epio = musb->endpoints[epnum].regs;
578 u16 fifo_count = 0;
579 u16 len = musb_ep->packet_sz;
580
581 csr = musb_readw(epio, MUSB_RXCSR);
582
583 if (is_cppi_enabled() && musb_ep->dma) {
584 struct dma_controller *c = musb->dma_controller;
585 struct dma_channel *channel = musb_ep->dma;
586
587 /* NOTE: CPPI won't actually stop advancing the DMA
588 * queue after short packet transfers, so this is almost
589 * always going to run as IRQ-per-packet DMA so that
590 * faults will be handled correctly.
591 */
592 if (c->channel_program(channel,
593 musb_ep->packet_sz,
594 !request->short_not_ok,
595 request->dma + request->actual,
596 request->length - request->actual)) {
597
598 /* make sure that if an rxpkt arrived after the irq,
599 * the cppi engine will be ready to take it as soon
600 * as DMA is enabled
601 */
602 csr &= ~(MUSB_RXCSR_AUTOCLEAR
603 | MUSB_RXCSR_DMAMODE);
604 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
605 musb_writew(epio, MUSB_RXCSR, csr);
606 return;
607 }
608 }
609
610 if (csr & MUSB_RXCSR_RXPKTRDY) {
611 len = musb_readw(epio, MUSB_RXCOUNT);
612 if (request->actual < request->length) {
613#ifdef CONFIG_USB_INVENTRA_DMA
614 if (is_dma_capable() && musb_ep->dma) {
615 struct dma_controller *c;
616 struct dma_channel *channel;
617 int use_dma = 0;
618
619 c = musb->dma_controller;
620 channel = musb_ep->dma;
621
622 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
623 * mode 0 only. So we do not get endpoint interrupts due to DMA
624 * completion. We only get interrupts from DMA controller.
625 *
626 * We could operate in DMA mode 1 if we knew the size of the tranfer
627 * in advance. For mass storage class, request->length = what the host
628 * sends, so that'd work. But for pretty much everything else,
629 * request->length is routinely more than what the host sends. For
630 * most these gadgets, end of is signified either by a short packet,
631 * or filling the last byte of the buffer. (Sending extra data in
632 * that last pckate should trigger an overflow fault.) But in mode 1,
633 * we don't get DMA completion interrrupt for short packets.
634 *
635 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
636 * to get endpoint interrupt on every DMA req, but that didn't seem
637 * to work reliably.
638 *
639 * REVISIT an updated g_file_storage can set req->short_not_ok, which
640 * then becomes usable as a runtime "use mode 1" hint...
641 */
642
643 csr |= MUSB_RXCSR_DMAENAB;
644#ifdef USE_MODE1
645 csr |= MUSB_RXCSR_AUTOCLEAR;
646 /* csr |= MUSB_RXCSR_DMAMODE; */
647
648 /* this special sequence (enabling and then
649 * disabling MUSB_RXCSR_DMAMODE) is required
650 * to get DMAReq to activate
651 */
652 musb_writew(epio, MUSB_RXCSR,
653 csr | MUSB_RXCSR_DMAMODE);
654#endif
655 musb_writew(epio, MUSB_RXCSR, csr);
656
657 if (request->actual < request->length) {
658 int transfer_size = 0;
659#ifdef USE_MODE1
660 transfer_size = min(request->length,
661 channel->max_len);
662#else
663 transfer_size = len;
664#endif
665 if (transfer_size <= musb_ep->packet_sz)
666 musb_ep->dma->desired_mode = 0;
667 else
668 musb_ep->dma->desired_mode = 1;
669
670 use_dma = c->channel_program(
671 channel,
672 musb_ep->packet_sz,
673 channel->desired_mode,
674 request->dma
675 + request->actual,
676 transfer_size);
677 }
678
679 if (use_dma)
680 return;
681 }
682#endif /* Mentor's DMA */
683
684 fifo_count = request->length - request->actual;
685 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
686 musb_ep->end_point.name,
687 len, fifo_count,
688 musb_ep->packet_sz);
689
690 fifo_count = min(len, fifo_count);
691
692#ifdef CONFIG_USB_TUSB_OMAP_DMA
693 if (tusb_dma_omap() && musb_ep->dma) {
694 struct dma_controller *c = musb->dma_controller;
695 struct dma_channel *channel = musb_ep->dma;
696 u32 dma_addr = request->dma + request->actual;
697 int ret;
698
699 ret = c->channel_program(channel,
700 musb_ep->packet_sz,
701 channel->desired_mode,
702 dma_addr,
703 fifo_count);
704 if (ret)
705 return;
706 }
707#endif
708
709 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
710 (request->buf + request->actual));
711 request->actual += fifo_count;
712
713 /* REVISIT if we left anything in the fifo, flush
714 * it and report -EOVERFLOW
715 */
716
717 /* ack the read! */
718 csr |= MUSB_RXCSR_P_WZC_BITS;
719 csr &= ~MUSB_RXCSR_RXPKTRDY;
720 musb_writew(epio, MUSB_RXCSR, csr);
721 }
722 }
723
724 /* reach the end or short packet detected */
725 if (request->actual == request->length || len < musb_ep->packet_sz)
726 musb_g_giveback(musb_ep, request, 0);
727}
728
729/*
730 * Data ready for a request; called from IRQ
731 */
732void musb_g_rx(struct musb *musb, u8 epnum)
733{
734 u16 csr;
735 struct usb_request *request;
736 void __iomem *mbase = musb->mregs;
737 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
738 void __iomem *epio = musb->endpoints[epnum].regs;
739 struct dma_channel *dma;
740
741 musb_ep_select(mbase, epnum);
742
743 request = next_request(musb_ep);
744
745 csr = musb_readw(epio, MUSB_RXCSR);
746 dma = is_dma_capable() ? musb_ep->dma : NULL;
747
748 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
749 csr, dma ? " (dma)" : "", request);
750
751 if (csr & MUSB_RXCSR_P_SENTSTALL) {
752 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
753 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
754 (void) musb->dma_controller->channel_abort(dma);
755 request->actual += musb_ep->dma->actual_len;
756 }
757
758 csr |= MUSB_RXCSR_P_WZC_BITS;
759 csr &= ~MUSB_RXCSR_P_SENTSTALL;
760 musb_writew(epio, MUSB_RXCSR, csr);
761
762 if (request)
763 musb_g_giveback(musb_ep, request, -EPIPE);
764 goto done;
765 }
766
767 if (csr & MUSB_RXCSR_P_OVERRUN) {
768 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
769 csr &= ~MUSB_RXCSR_P_OVERRUN;
770 musb_writew(epio, MUSB_RXCSR, csr);
771
772 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
773 if (request && request->status == -EINPROGRESS)
774 request->status = -EOVERFLOW;
775 }
776 if (csr & MUSB_RXCSR_INCOMPRX) {
777 /* REVISIT not necessarily an error */
778 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
779 }
780
781 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
782 /* "should not happen"; likely RXPKTRDY pending for DMA */
783 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
784 "%s busy, csr %04x\n",
785 musb_ep->end_point.name, csr);
786 goto done;
787 }
788
789 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
790 csr &= ~(MUSB_RXCSR_AUTOCLEAR
791 | MUSB_RXCSR_DMAENAB
792 | MUSB_RXCSR_DMAMODE);
793 musb_writew(epio, MUSB_RXCSR,
794 MUSB_RXCSR_P_WZC_BITS | csr);
795
796 request->actual += musb_ep->dma->actual_len;
797
798 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
799 epnum, csr,
800 musb_readw(epio, MUSB_RXCSR),
801 musb_ep->dma->actual_len, request);
802
803#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
804 /* Autoclear doesn't clear RxPktRdy for short packets */
805 if ((dma->desired_mode == 0)
806 || (dma->actual_len
807 & (musb_ep->packet_sz - 1))) {
808 /* ack the read! */
809 csr &= ~MUSB_RXCSR_RXPKTRDY;
810 musb_writew(epio, MUSB_RXCSR, csr);
811 }
812
813 /* incomplete, and not short? wait for next IN packet */
814 if ((request->actual < request->length)
815 && (musb_ep->dma->actual_len
816 == musb_ep->packet_sz))
817 goto done;
818#endif
819 musb_g_giveback(musb_ep, request, 0);
820
821 request = next_request(musb_ep);
822 if (!request)
823 goto done;
824
825 /* don't start more i/o till the stall clears */
826 musb_ep_select(mbase, epnum);
827 csr = musb_readw(epio, MUSB_RXCSR);
828 if (csr & MUSB_RXCSR_P_SENDSTALL)
829 goto done;
830 }
831
832
833 /* analyze request if the ep is hot */
834 if (request)
835 rxstate(musb, to_musb_request(request));
836 else
837 DBG(3, "packet waiting for %s%s request\n",
838 musb_ep->desc ? "" : "inactive ",
839 musb_ep->end_point.name);
840
841done:
842 return;
843}
844
845/* ------------------------------------------------------------ */
846
847static int musb_gadget_enable(struct usb_ep *ep,
848 const struct usb_endpoint_descriptor *desc)
849{
850 unsigned long flags;
851 struct musb_ep *musb_ep;
852 struct musb_hw_ep *hw_ep;
853 void __iomem *regs;
854 struct musb *musb;
855 void __iomem *mbase;
856 u8 epnum;
857 u16 csr;
858 unsigned tmp;
859 int status = -EINVAL;
860
861 if (!ep || !desc)
862 return -EINVAL;
863
864 musb_ep = to_musb_ep(ep);
865 hw_ep = musb_ep->hw_ep;
866 regs = hw_ep->regs;
867 musb = musb_ep->musb;
868 mbase = musb->mregs;
869 epnum = musb_ep->current_epnum;
870
871 spin_lock_irqsave(&musb->lock, flags);
872
873 if (musb_ep->desc) {
874 status = -EBUSY;
875 goto fail;
876 }
877 musb_ep->type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
878
879 /* check direction and (later) maxpacket size against endpoint */
880 if ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != epnum)
881 goto fail;
882
883 /* REVISIT this rules out high bandwidth periodic transfers */
884 tmp = le16_to_cpu(desc->wMaxPacketSize);
885 if (tmp & ~0x07ff)
886 goto fail;
887 musb_ep->packet_sz = tmp;
888
889 /* enable the interrupts for the endpoint, set the endpoint
890 * packet size (or fail), set the mode, clear the fifo
891 */
892 musb_ep_select(mbase, epnum);
893 if (desc->bEndpointAddress & USB_DIR_IN) {
894 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
895
896 if (hw_ep->is_shared_fifo)
897 musb_ep->is_in = 1;
898 if (!musb_ep->is_in)
899 goto fail;
900 if (tmp > hw_ep->max_packet_sz_tx)
901 goto fail;
902
903 int_txe |= (1 << epnum);
904 musb_writew(mbase, MUSB_INTRTXE, int_txe);
905
906 /* REVISIT if can_bulk_split(), use by updating "tmp";
907 * likewise high bandwidth periodic tx
908 */
909 musb_writew(regs, MUSB_TXMAXP, tmp);
910
911 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
912 if (musb_readw(regs, MUSB_TXCSR)
913 & MUSB_TXCSR_FIFONOTEMPTY)
914 csr |= MUSB_TXCSR_FLUSHFIFO;
915 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
916 csr |= MUSB_TXCSR_P_ISO;
917
918 /* set twice in case of double buffering */
919 musb_writew(regs, MUSB_TXCSR, csr);
920 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
921 musb_writew(regs, MUSB_TXCSR, csr);
922
923 } else {
924 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
925
926 if (hw_ep->is_shared_fifo)
927 musb_ep->is_in = 0;
928 if (musb_ep->is_in)
929 goto fail;
930 if (tmp > hw_ep->max_packet_sz_rx)
931 goto fail;
932
933 int_rxe |= (1 << epnum);
934 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
935
936 /* REVISIT if can_bulk_combine() use by updating "tmp"
937 * likewise high bandwidth periodic rx
938 */
939 musb_writew(regs, MUSB_RXMAXP, tmp);
940
941 /* force shared fifo to OUT-only mode */
942 if (hw_ep->is_shared_fifo) {
943 csr = musb_readw(regs, MUSB_TXCSR);
944 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
945 musb_writew(regs, MUSB_TXCSR, csr);
946 }
947
948 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
949 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
950 csr |= MUSB_RXCSR_P_ISO;
951 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
952 csr |= MUSB_RXCSR_DISNYET;
953
954 /* set twice in case of double buffering */
955 musb_writew(regs, MUSB_RXCSR, csr);
956 musb_writew(regs, MUSB_RXCSR, csr);
957 }
958
959 /* NOTE: all the I/O code _should_ work fine without DMA, in case
960 * for some reason you run out of channels here.
961 */
962 if (is_dma_capable() && musb->dma_controller) {
963 struct dma_controller *c = musb->dma_controller;
964
965 musb_ep->dma = c->channel_alloc(c, hw_ep,
966 (desc->bEndpointAddress & USB_DIR_IN));
967 } else
968 musb_ep->dma = NULL;
969
970 musb_ep->desc = desc;
971 musb_ep->busy = 0;
972 status = 0;
973
974 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
975 musb_driver_name, musb_ep->end_point.name,
976 ({ char *s; switch (musb_ep->type) {
977 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
978 case USB_ENDPOINT_XFER_INT: s = "int"; break;
979 default: s = "iso"; break;
980 }; s; }),
981 musb_ep->is_in ? "IN" : "OUT",
982 musb_ep->dma ? "dma, " : "",
983 musb_ep->packet_sz);
984
985 schedule_work(&musb->irq_work);
986
987fail:
988 spin_unlock_irqrestore(&musb->lock, flags);
989 return status;
990}
991
992/*
993 * Disable an endpoint flushing all requests queued.
994 */
995static int musb_gadget_disable(struct usb_ep *ep)
996{
997 unsigned long flags;
998 struct musb *musb;
999 u8 epnum;
1000 struct musb_ep *musb_ep;
1001 void __iomem *epio;
1002 int status = 0;
1003
1004 musb_ep = to_musb_ep(ep);
1005 musb = musb_ep->musb;
1006 epnum = musb_ep->current_epnum;
1007 epio = musb->endpoints[epnum].regs;
1008
1009 spin_lock_irqsave(&musb->lock, flags);
1010 musb_ep_select(musb->mregs, epnum);
1011
1012 /* zero the endpoint sizes */
1013 if (musb_ep->is_in) {
1014 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1015 int_txe &= ~(1 << epnum);
1016 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1017 musb_writew(epio, MUSB_TXMAXP, 0);
1018 } else {
1019 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1020 int_rxe &= ~(1 << epnum);
1021 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1022 musb_writew(epio, MUSB_RXMAXP, 0);
1023 }
1024
1025 musb_ep->desc = NULL;
1026
1027 /* abort all pending DMA and requests */
1028 nuke(musb_ep, -ESHUTDOWN);
1029
1030 schedule_work(&musb->irq_work);
1031
1032 spin_unlock_irqrestore(&(musb->lock), flags);
1033
1034 DBG(2, "%s\n", musb_ep->end_point.name);
1035
1036 return status;
1037}
1038
1039/*
1040 * Allocate a request for an endpoint.
1041 * Reused by ep0 code.
1042 */
1043struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1044{
1045 struct musb_ep *musb_ep = to_musb_ep(ep);
1046 struct musb_request *request = NULL;
1047
1048 request = kzalloc(sizeof *request, gfp_flags);
1049 if (request) {
1050 INIT_LIST_HEAD(&request->request.list);
1051 request->request.dma = DMA_ADDR_INVALID;
1052 request->epnum = musb_ep->current_epnum;
1053 request->ep = musb_ep;
1054 }
1055
1056 return &request->request;
1057}
1058
1059/*
1060 * Free a request
1061 * Reused by ep0 code.
1062 */
1063void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1064{
1065 kfree(to_musb_request(req));
1066}
1067
1068static LIST_HEAD(buffers);
1069
1070struct free_record {
1071 struct list_head list;
1072 struct device *dev;
1073 unsigned bytes;
1074 dma_addr_t dma;
1075};
1076
1077/*
1078 * Context: controller locked, IRQs blocked.
1079 */
1080static void musb_ep_restart(struct musb *musb, struct musb_request *req)
1081{
1082 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1083 req->tx ? "TX/IN" : "RX/OUT",
1084 &req->request, req->request.length, req->epnum);
1085
1086 musb_ep_select(musb->mregs, req->epnum);
1087 if (req->tx)
1088 txstate(musb, req);
1089 else
1090 rxstate(musb, req);
1091}
1092
1093static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1094 gfp_t gfp_flags)
1095{
1096 struct musb_ep *musb_ep;
1097 struct musb_request *request;
1098 struct musb *musb;
1099 int status = 0;
1100 unsigned long lockflags;
1101
1102 if (!ep || !req)
1103 return -EINVAL;
1104 if (!req->buf)
1105 return -ENODATA;
1106
1107 musb_ep = to_musb_ep(ep);
1108 musb = musb_ep->musb;
1109
1110 request = to_musb_request(req);
1111 request->musb = musb;
1112
1113 if (request->ep != musb_ep)
1114 return -EINVAL;
1115
1116 DBG(4, "<== to %s request=%p\n", ep->name, req);
1117
1118 /* request is mine now... */
1119 request->request.actual = 0;
1120 request->request.status = -EINPROGRESS;
1121 request->epnum = musb_ep->current_epnum;
1122 request->tx = musb_ep->is_in;
1123
1124 if (is_dma_capable() && musb_ep->dma) {
1125 if (request->request.dma == DMA_ADDR_INVALID) {
1126 request->request.dma = dma_map_single(
1127 musb->controller,
1128 request->request.buf,
1129 request->request.length,
1130 request->tx
1131 ? DMA_TO_DEVICE
1132 : DMA_FROM_DEVICE);
1133 request->mapped = 1;
1134 } else {
1135 dma_sync_single_for_device(musb->controller,
1136 request->request.dma,
1137 request->request.length,
1138 request->tx
1139 ? DMA_TO_DEVICE
1140 : DMA_FROM_DEVICE);
1141 request->mapped = 0;
1142 }
1143 } else if (!req->buf) {
1144 return -ENODATA;
1145 } else
1146 request->mapped = 0;
1147
1148 spin_lock_irqsave(&musb->lock, lockflags);
1149
1150 /* don't queue if the ep is down */
1151 if (!musb_ep->desc) {
1152 DBG(4, "req %p queued to %s while ep %s\n",
1153 req, ep->name, "disabled");
1154 status = -ESHUTDOWN;
1155 goto cleanup;
1156 }
1157
1158 /* add request to the list */
1159 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1160
1161 /* it this is the head of the queue, start i/o ... */
1162 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1163 musb_ep_restart(musb, request);
1164
1165cleanup:
1166 spin_unlock_irqrestore(&musb->lock, lockflags);
1167 return status;
1168}
1169
1170static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1171{
1172 struct musb_ep *musb_ep = to_musb_ep(ep);
1173 struct usb_request *r;
1174 unsigned long flags;
1175 int status = 0;
1176 struct musb *musb = musb_ep->musb;
1177
1178 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1179 return -EINVAL;
1180
1181 spin_lock_irqsave(&musb->lock, flags);
1182
1183 list_for_each_entry(r, &musb_ep->req_list, list) {
1184 if (r == request)
1185 break;
1186 }
1187 if (r != request) {
1188 DBG(3, "request %p not queued to %s\n", request, ep->name);
1189 status = -EINVAL;
1190 goto done;
1191 }
1192
1193 /* if the hardware doesn't have the request, easy ... */
1194 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1195 musb_g_giveback(musb_ep, request, -ECONNRESET);
1196
1197 /* ... else abort the dma transfer ... */
1198 else if (is_dma_capable() && musb_ep->dma) {
1199 struct dma_controller *c = musb->dma_controller;
1200
1201 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1202 if (c->channel_abort)
1203 status = c->channel_abort(musb_ep->dma);
1204 else
1205 status = -EBUSY;
1206 if (status == 0)
1207 musb_g_giveback(musb_ep, request, -ECONNRESET);
1208 } else {
1209 /* NOTE: by sticking to easily tested hardware/driver states,
1210 * we leave counting of in-flight packets imprecise.
1211 */
1212 musb_g_giveback(musb_ep, request, -ECONNRESET);
1213 }
1214
1215done:
1216 spin_unlock_irqrestore(&musb->lock, flags);
1217 return status;
1218}
1219
1220/*
1221 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1222 * data but will queue requests.
1223 *
1224 * exported to ep0 code
1225 */
1226int musb_gadget_set_halt(struct usb_ep *ep, int value)
1227{
1228 struct musb_ep *musb_ep = to_musb_ep(ep);
1229 u8 epnum = musb_ep->current_epnum;
1230 struct musb *musb = musb_ep->musb;
1231 void __iomem *epio = musb->endpoints[epnum].regs;
1232 void __iomem *mbase;
1233 unsigned long flags;
1234 u16 csr;
1235 struct musb_request *request = NULL;
1236 int status = 0;
1237
1238 if (!ep)
1239 return -EINVAL;
1240 mbase = musb->mregs;
1241
1242 spin_lock_irqsave(&musb->lock, flags);
1243
1244 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1245 status = -EINVAL;
1246 goto done;
1247 }
1248
1249 musb_ep_select(mbase, epnum);
1250
1251 /* cannot portably stall with non-empty FIFO */
1252 request = to_musb_request(next_request(musb_ep));
1253 if (value && musb_ep->is_in) {
1254 csr = musb_readw(epio, MUSB_TXCSR);
1255 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1256 DBG(3, "%s fifo busy, cannot halt\n", ep->name);
1257 spin_unlock_irqrestore(&musb->lock, flags);
1258 return -EAGAIN;
1259 }
1260
1261 }
1262
1263 /* set/clear the stall and toggle bits */
1264 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1265 if (musb_ep->is_in) {
1266 csr = musb_readw(epio, MUSB_TXCSR);
1267 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
1268 csr |= MUSB_TXCSR_FLUSHFIFO;
1269 csr |= MUSB_TXCSR_P_WZC_BITS
1270 | MUSB_TXCSR_CLRDATATOG;
1271 if (value)
1272 csr |= MUSB_TXCSR_P_SENDSTALL;
1273 else
1274 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1275 | MUSB_TXCSR_P_SENTSTALL);
1276 csr &= ~MUSB_TXCSR_TXPKTRDY;
1277 musb_writew(epio, MUSB_TXCSR, csr);
1278 } else {
1279 csr = musb_readw(epio, MUSB_RXCSR);
1280 csr |= MUSB_RXCSR_P_WZC_BITS
1281 | MUSB_RXCSR_FLUSHFIFO
1282 | MUSB_RXCSR_CLRDATATOG;
1283 if (value)
1284 csr |= MUSB_RXCSR_P_SENDSTALL;
1285 else
1286 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1287 | MUSB_RXCSR_P_SENTSTALL);
1288 musb_writew(epio, MUSB_RXCSR, csr);
1289 }
1290
1291done:
1292
1293 /* maybe start the first request in the queue */
1294 if (!musb_ep->busy && !value && request) {
1295 DBG(3, "restarting the request\n");
1296 musb_ep_restart(musb, request);
1297 }
1298
1299 spin_unlock_irqrestore(&musb->lock, flags);
1300 return status;
1301}
1302
1303static int musb_gadget_fifo_status(struct usb_ep *ep)
1304{
1305 struct musb_ep *musb_ep = to_musb_ep(ep);
1306 void __iomem *epio = musb_ep->hw_ep->regs;
1307 int retval = -EINVAL;
1308
1309 if (musb_ep->desc && !musb_ep->is_in) {
1310 struct musb *musb = musb_ep->musb;
1311 int epnum = musb_ep->current_epnum;
1312 void __iomem *mbase = musb->mregs;
1313 unsigned long flags;
1314
1315 spin_lock_irqsave(&musb->lock, flags);
1316
1317 musb_ep_select(mbase, epnum);
1318 /* FIXME return zero unless RXPKTRDY is set */
1319 retval = musb_readw(epio, MUSB_RXCOUNT);
1320
1321 spin_unlock_irqrestore(&musb->lock, flags);
1322 }
1323 return retval;
1324}
1325
1326static void musb_gadget_fifo_flush(struct usb_ep *ep)
1327{
1328 struct musb_ep *musb_ep = to_musb_ep(ep);
1329 struct musb *musb = musb_ep->musb;
1330 u8 epnum = musb_ep->current_epnum;
1331 void __iomem *epio = musb->endpoints[epnum].regs;
1332 void __iomem *mbase;
1333 unsigned long flags;
1334 u16 csr, int_txe;
1335
1336 mbase = musb->mregs;
1337
1338 spin_lock_irqsave(&musb->lock, flags);
1339 musb_ep_select(mbase, (u8) epnum);
1340
1341 /* disable interrupts */
1342 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1343 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1344
1345 if (musb_ep->is_in) {
1346 csr = musb_readw(epio, MUSB_TXCSR);
1347 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1348 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1349 musb_writew(epio, MUSB_TXCSR, csr);
1350 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1351 musb_writew(epio, MUSB_TXCSR, csr);
1352 }
1353 } else {
1354 csr = musb_readw(epio, MUSB_RXCSR);
1355 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1356 musb_writew(epio, MUSB_RXCSR, csr);
1357 musb_writew(epio, MUSB_RXCSR, csr);
1358 }
1359
1360 /* re-enable interrupt */
1361 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1362 spin_unlock_irqrestore(&musb->lock, flags);
1363}
1364
1365static const struct usb_ep_ops musb_ep_ops = {
1366 .enable = musb_gadget_enable,
1367 .disable = musb_gadget_disable,
1368 .alloc_request = musb_alloc_request,
1369 .free_request = musb_free_request,
1370 .queue = musb_gadget_queue,
1371 .dequeue = musb_gadget_dequeue,
1372 .set_halt = musb_gadget_set_halt,
1373 .fifo_status = musb_gadget_fifo_status,
1374 .fifo_flush = musb_gadget_fifo_flush
1375};
1376
1377/* ----------------------------------------------------------------------- */
1378
1379static int musb_gadget_get_frame(struct usb_gadget *gadget)
1380{
1381 struct musb *musb = gadget_to_musb(gadget);
1382
1383 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1384}
1385
1386static int musb_gadget_wakeup(struct usb_gadget *gadget)
1387{
1388 struct musb *musb = gadget_to_musb(gadget);
1389 void __iomem *mregs = musb->mregs;
1390 unsigned long flags;
1391 int status = -EINVAL;
1392 u8 power, devctl;
1393 int retries;
1394
1395 spin_lock_irqsave(&musb->lock, flags);
1396
1397 switch (musb->xceiv.state) {
1398 case OTG_STATE_B_PERIPHERAL:
1399 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1400 * that's part of the standard usb 1.1 state machine, and
1401 * doesn't affect OTG transitions.
1402 */
1403 if (musb->may_wakeup && musb->is_suspended)
1404 break;
1405 goto done;
1406 case OTG_STATE_B_IDLE:
1407 /* Start SRP ... OTG not required. */
1408 devctl = musb_readb(mregs, MUSB_DEVCTL);
1409 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1410 devctl |= MUSB_DEVCTL_SESSION;
1411 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1412 devctl = musb_readb(mregs, MUSB_DEVCTL);
1413 retries = 100;
1414 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1415 devctl = musb_readb(mregs, MUSB_DEVCTL);
1416 if (retries-- < 1)
1417 break;
1418 }
1419 retries = 10000;
1420 while (devctl & MUSB_DEVCTL_SESSION) {
1421 devctl = musb_readb(mregs, MUSB_DEVCTL);
1422 if (retries-- < 1)
1423 break;
1424 }
1425
1426 /* Block idling for at least 1s */
1427 musb_platform_try_idle(musb,
1428 jiffies + msecs_to_jiffies(1 * HZ));
1429
1430 status = 0;
1431 goto done;
1432 default:
1433 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1434 goto done;
1435 }
1436
1437 status = 0;
1438
1439 power = musb_readb(mregs, MUSB_POWER);
1440 power |= MUSB_POWER_RESUME;
1441 musb_writeb(mregs, MUSB_POWER, power);
1442 DBG(2, "issue wakeup\n");
1443
1444 /* FIXME do this next chunk in a timer callback, no udelay */
1445 mdelay(2);
1446
1447 power = musb_readb(mregs, MUSB_POWER);
1448 power &= ~MUSB_POWER_RESUME;
1449 musb_writeb(mregs, MUSB_POWER, power);
1450done:
1451 spin_unlock_irqrestore(&musb->lock, flags);
1452 return status;
1453}
1454
1455static int
1456musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1457{
1458 struct musb *musb = gadget_to_musb(gadget);
1459
1460 musb->is_self_powered = !!is_selfpowered;
1461 return 0;
1462}
1463
1464static void musb_pullup(struct musb *musb, int is_on)
1465{
1466 u8 power;
1467
1468 power = musb_readb(musb->mregs, MUSB_POWER);
1469 if (is_on)
1470 power |= MUSB_POWER_SOFTCONN;
1471 else
1472 power &= ~MUSB_POWER_SOFTCONN;
1473
1474 /* FIXME if on, HdrcStart; if off, HdrcStop */
1475
1476 DBG(3, "gadget %s D+ pullup %s\n",
1477 musb->gadget_driver->function, is_on ? "on" : "off");
1478 musb_writeb(musb->mregs, MUSB_POWER, power);
1479}
1480
1481#if 0
1482static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1483{
1484 DBG(2, "<= %s =>\n", __func__);
1485
1486 /*
1487 * FIXME iff driver's softconnect flag is set (as it is during probe,
1488 * though that can clear it), just musb_pullup().
1489 */
1490
1491 return -EINVAL;
1492}
1493#endif
1494
1495static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1496{
1497 struct musb *musb = gadget_to_musb(gadget);
1498
1499 if (!musb->xceiv.set_power)
1500 return -EOPNOTSUPP;
1501 return otg_set_power(&musb->xceiv, mA);
1502}
1503
1504static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1505{
1506 struct musb *musb = gadget_to_musb(gadget);
1507 unsigned long flags;
1508
1509 is_on = !!is_on;
1510
1511 /* NOTE: this assumes we are sensing vbus; we'd rather
1512 * not pullup unless the B-session is active.
1513 */
1514 spin_lock_irqsave(&musb->lock, flags);
1515 if (is_on != musb->softconnect) {
1516 musb->softconnect = is_on;
1517 musb_pullup(musb, is_on);
1518 }
1519 spin_unlock_irqrestore(&musb->lock, flags);
1520 return 0;
1521}
1522
1523static const struct usb_gadget_ops musb_gadget_operations = {
1524 .get_frame = musb_gadget_get_frame,
1525 .wakeup = musb_gadget_wakeup,
1526 .set_selfpowered = musb_gadget_set_self_powered,
1527 /* .vbus_session = musb_gadget_vbus_session, */
1528 .vbus_draw = musb_gadget_vbus_draw,
1529 .pullup = musb_gadget_pullup,
1530};
1531
1532/* ----------------------------------------------------------------------- */
1533
1534/* Registration */
1535
1536/* Only this registration code "knows" the rule (from USB standards)
1537 * about there being only one external upstream port. It assumes
1538 * all peripheral ports are external...
1539 */
1540static struct musb *the_gadget;
1541
1542static void musb_gadget_release(struct device *dev)
1543{
1544 /* kref_put(WHAT) */
1545 dev_dbg(dev, "%s\n", __func__);
1546}
1547
1548
1549static void __init
1550init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1551{
1552 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1553
1554 memset(ep, 0, sizeof *ep);
1555
1556 ep->current_epnum = epnum;
1557 ep->musb = musb;
1558 ep->hw_ep = hw_ep;
1559 ep->is_in = is_in;
1560
1561 INIT_LIST_HEAD(&ep->req_list);
1562
1563 sprintf(ep->name, "ep%d%s", epnum,
1564 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1565 is_in ? "in" : "out"));
1566 ep->end_point.name = ep->name;
1567 INIT_LIST_HEAD(&ep->end_point.ep_list);
1568 if (!epnum) {
1569 ep->end_point.maxpacket = 64;
1570 ep->end_point.ops = &musb_g_ep0_ops;
1571 musb->g.ep0 = &ep->end_point;
1572 } else {
1573 if (is_in)
1574 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1575 else
1576 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1577 ep->end_point.ops = &musb_ep_ops;
1578 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1579 }
1580}
1581
1582/*
1583 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1584 * to the rest of the driver state.
1585 */
1586static inline void __init musb_g_init_endpoints(struct musb *musb)
1587{
1588 u8 epnum;
1589 struct musb_hw_ep *hw_ep;
1590 unsigned count = 0;
1591
1592 /* intialize endpoint list just once */
1593 INIT_LIST_HEAD(&(musb->g.ep_list));
1594
1595 for (epnum = 0, hw_ep = musb->endpoints;
1596 epnum < musb->nr_endpoints;
1597 epnum++, hw_ep++) {
1598 if (hw_ep->is_shared_fifo /* || !epnum */) {
1599 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1600 count++;
1601 } else {
1602 if (hw_ep->max_packet_sz_tx) {
1603 init_peripheral_ep(musb, &hw_ep->ep_in,
1604 epnum, 1);
1605 count++;
1606 }
1607 if (hw_ep->max_packet_sz_rx) {
1608 init_peripheral_ep(musb, &hw_ep->ep_out,
1609 epnum, 0);
1610 count++;
1611 }
1612 }
1613 }
1614}
1615
1616/* called once during driver setup to initialize and link into
1617 * the driver model; memory is zeroed.
1618 */
1619int __init musb_gadget_setup(struct musb *musb)
1620{
1621 int status;
1622
1623 /* REVISIT minor race: if (erroneously) setting up two
1624 * musb peripherals at the same time, only the bus lock
1625 * is probably held.
1626 */
1627 if (the_gadget)
1628 return -EBUSY;
1629 the_gadget = musb;
1630
1631 musb->g.ops = &musb_gadget_operations;
1632 musb->g.is_dualspeed = 1;
1633 musb->g.speed = USB_SPEED_UNKNOWN;
1634
1635 /* this "gadget" abstracts/virtualizes the controller */
1636 strcpy(musb->g.dev.bus_id, "gadget");
1637 musb->g.dev.parent = musb->controller;
1638 musb->g.dev.dma_mask = musb->controller->dma_mask;
1639 musb->g.dev.release = musb_gadget_release;
1640 musb->g.name = musb_driver_name;
1641
1642 if (is_otg_enabled(musb))
1643 musb->g.is_otg = 1;
1644
1645 musb_g_init_endpoints(musb);
1646
1647 musb->is_active = 0;
1648 musb_platform_try_idle(musb, 0);
1649
1650 status = device_register(&musb->g.dev);
1651 if (status != 0)
1652 the_gadget = NULL;
1653 return status;
1654}
1655
1656void musb_gadget_cleanup(struct musb *musb)
1657{
1658 if (musb != the_gadget)
1659 return;
1660
1661 device_unregister(&musb->g.dev);
1662 the_gadget = NULL;
1663}
1664
1665/*
1666 * Register the gadget driver. Used by gadget drivers when
1667 * registering themselves with the controller.
1668 *
1669 * -EINVAL something went wrong (not driver)
1670 * -EBUSY another gadget is already using the controller
1671 * -ENOMEM no memeory to perform the operation
1672 *
1673 * @param driver the gadget driver
1674 * @return <0 if error, 0 if everything is fine
1675 */
1676int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1677{
1678 int retval;
1679 unsigned long flags;
1680 struct musb *musb = the_gadget;
1681
1682 if (!driver
1683 || driver->speed != USB_SPEED_HIGH
1684 || !driver->bind
1685 || !driver->setup)
1686 return -EINVAL;
1687
1688 /* driver must be initialized to support peripheral mode */
1689 if (!musb || !(musb->board_mode == MUSB_OTG
1690 || musb->board_mode != MUSB_OTG)) {
1691 DBG(1, "%s, no dev??\n", __func__);
1692 return -ENODEV;
1693 }
1694
1695 DBG(3, "registering driver %s\n", driver->function);
1696 spin_lock_irqsave(&musb->lock, flags);
1697
1698 if (musb->gadget_driver) {
1699 DBG(1, "%s is already bound to %s\n",
1700 musb_driver_name,
1701 musb->gadget_driver->driver.name);
1702 retval = -EBUSY;
1703 } else {
1704 musb->gadget_driver = driver;
1705 musb->g.dev.driver = &driver->driver;
1706 driver->driver.bus = NULL;
1707 musb->softconnect = 1;
1708 retval = 0;
1709 }
1710
1711 spin_unlock_irqrestore(&musb->lock, flags);
1712
1713 if (retval == 0)
1714 retval = driver->bind(&musb->g);
1715 if (retval != 0) {
1716 DBG(3, "bind to driver %s failed --> %d\n",
1717 driver->driver.name, retval);
1718 musb->gadget_driver = NULL;
1719 musb->g.dev.driver = NULL;
1720 }
1721
1722 /* start peripheral and/or OTG engines */
1723 if (retval == 0) {
1724 spin_lock_irqsave(&musb->lock, flags);
1725
1726 /* REVISIT always use otg_set_peripheral(), handling
1727 * issues including the root hub one below ...
1728 */
1729 musb->xceiv.gadget = &musb->g;
1730 musb->xceiv.state = OTG_STATE_B_IDLE;
1731 musb->is_active = 1;
1732
1733 /* FIXME this ignores the softconnect flag. Drivers are
1734 * allowed hold the peripheral inactive until for example
1735 * userspace hooks up printer hardware or DSP codecs, so
1736 * hosts only see fully functional devices.
1737 */
1738
1739 if (!is_otg_enabled(musb))
1740 musb_start(musb);
1741
1742 spin_unlock_irqrestore(&musb->lock, flags);
1743
1744 if (is_otg_enabled(musb)) {
1745 DBG(3, "OTG startup...\n");
1746
1747 /* REVISIT: funcall to other code, which also
1748 * handles power budgeting ... this way also
1749 * ensures HdrcStart is indirectly called.
1750 */
1751 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1752 if (retval < 0) {
1753 DBG(1, "add_hcd failed, %d\n", retval);
1754 spin_lock_irqsave(&musb->lock, flags);
1755 musb->xceiv.gadget = NULL;
1756 musb->xceiv.state = OTG_STATE_UNDEFINED;
1757 musb->gadget_driver = NULL;
1758 musb->g.dev.driver = NULL;
1759 spin_unlock_irqrestore(&musb->lock, flags);
1760 }
1761 }
1762 }
1763
1764 return retval;
1765}
1766EXPORT_SYMBOL(usb_gadget_register_driver);
1767
1768static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1769{
1770 int i;
1771 struct musb_hw_ep *hw_ep;
1772
1773 /* don't disconnect if it's not connected */
1774 if (musb->g.speed == USB_SPEED_UNKNOWN)
1775 driver = NULL;
1776 else
1777 musb->g.speed = USB_SPEED_UNKNOWN;
1778
1779 /* deactivate the hardware */
1780 if (musb->softconnect) {
1781 musb->softconnect = 0;
1782 musb_pullup(musb, 0);
1783 }
1784 musb_stop(musb);
1785
1786 /* killing any outstanding requests will quiesce the driver;
1787 * then report disconnect
1788 */
1789 if (driver) {
1790 for (i = 0, hw_ep = musb->endpoints;
1791 i < musb->nr_endpoints;
1792 i++, hw_ep++) {
1793 musb_ep_select(musb->mregs, i);
1794 if (hw_ep->is_shared_fifo /* || !epnum */) {
1795 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1796 } else {
1797 if (hw_ep->max_packet_sz_tx)
1798 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1799 if (hw_ep->max_packet_sz_rx)
1800 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1801 }
1802 }
1803
1804 spin_unlock(&musb->lock);
1805 driver->disconnect(&musb->g);
1806 spin_lock(&musb->lock);
1807 }
1808}
1809
1810/*
1811 * Unregister the gadget driver. Used by gadget drivers when
1812 * unregistering themselves from the controller.
1813 *
1814 * @param driver the gadget driver to unregister
1815 */
1816int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1817{
1818 unsigned long flags;
1819 int retval = 0;
1820 struct musb *musb = the_gadget;
1821
1822 if (!driver || !driver->unbind || !musb)
1823 return -EINVAL;
1824
1825 /* REVISIT always use otg_set_peripheral() here too;
1826 * this needs to shut down the OTG engine.
1827 */
1828
1829 spin_lock_irqsave(&musb->lock, flags);
1830
1831#ifdef CONFIG_USB_MUSB_OTG
1832 musb_hnp_stop(musb);
1833#endif
1834
1835 if (musb->gadget_driver == driver) {
1836
1837 (void) musb_gadget_vbus_draw(&musb->g, 0);
1838
1839 musb->xceiv.state = OTG_STATE_UNDEFINED;
1840 stop_activity(musb, driver);
1841
1842 DBG(3, "unregistering driver %s\n", driver->function);
1843 spin_unlock_irqrestore(&musb->lock, flags);
1844 driver->unbind(&musb->g);
1845 spin_lock_irqsave(&musb->lock, flags);
1846
1847 musb->gadget_driver = NULL;
1848 musb->g.dev.driver = NULL;
1849
1850 musb->is_active = 0;
1851 musb_platform_try_idle(musb, 0);
1852 } else
1853 retval = -EINVAL;
1854 spin_unlock_irqrestore(&musb->lock, flags);
1855
1856 if (is_otg_enabled(musb) && retval == 0) {
1857 usb_remove_hcd(musb_to_hcd(musb));
1858 /* FIXME we need to be able to register another
1859 * gadget driver here and have everything work;
1860 * that currently misbehaves.
1861 */
1862 }
1863
1864 return retval;
1865}
1866EXPORT_SYMBOL(usb_gadget_unregister_driver);
1867
1868
1869/* ----------------------------------------------------------------------- */
1870
1871/* lifecycle operations called through plat_uds.c */
1872
1873void musb_g_resume(struct musb *musb)
1874{
1875 musb->is_suspended = 0;
1876 switch (musb->xceiv.state) {
1877 case OTG_STATE_B_IDLE:
1878 break;
1879 case OTG_STATE_B_WAIT_ACON:
1880 case OTG_STATE_B_PERIPHERAL:
1881 musb->is_active = 1;
1882 if (musb->gadget_driver && musb->gadget_driver->resume) {
1883 spin_unlock(&musb->lock);
1884 musb->gadget_driver->resume(&musb->g);
1885 spin_lock(&musb->lock);
1886 }
1887 break;
1888 default:
1889 WARNING("unhandled RESUME transition (%s)\n",
1890 otg_state_string(musb));
1891 }
1892}
1893
1894/* called when SOF packets stop for 3+ msec */
1895void musb_g_suspend(struct musb *musb)
1896{
1897 u8 devctl;
1898
1899 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1900 DBG(3, "devctl %02x\n", devctl);
1901
1902 switch (musb->xceiv.state) {
1903 case OTG_STATE_B_IDLE:
1904 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1905 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
1906 break;
1907 case OTG_STATE_B_PERIPHERAL:
1908 musb->is_suspended = 1;
1909 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1910 spin_unlock(&musb->lock);
1911 musb->gadget_driver->suspend(&musb->g);
1912 spin_lock(&musb->lock);
1913 }
1914 break;
1915 default:
1916 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1917 * A_PERIPHERAL may need care too
1918 */
1919 WARNING("unhandled SUSPEND transition (%s)\n",
1920 otg_state_string(musb));
1921 }
1922}
1923
1924/* Called during SRP */
1925void musb_g_wakeup(struct musb *musb)
1926{
1927 musb_gadget_wakeup(&musb->g);
1928}
1929
1930/* called when VBUS drops below session threshold, and in other cases */
1931void musb_g_disconnect(struct musb *musb)
1932{
1933 void __iomem *mregs = musb->mregs;
1934 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1935
1936 DBG(3, "devctl %02x\n", devctl);
1937
1938 /* clear HR */
1939 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1940
1941 /* don't draw vbus until new b-default session */
1942 (void) musb_gadget_vbus_draw(&musb->g, 0);
1943
1944 musb->g.speed = USB_SPEED_UNKNOWN;
1945 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1946 spin_unlock(&musb->lock);
1947 musb->gadget_driver->disconnect(&musb->g);
1948 spin_lock(&musb->lock);
1949 }
1950
1951 switch (musb->xceiv.state) {
1952 default:
1953#ifdef CONFIG_USB_MUSB_OTG
1954 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1955 otg_state_string(musb));
1956 musb->xceiv.state = OTG_STATE_A_IDLE;
1957 break;
1958 case OTG_STATE_A_PERIPHERAL:
1959 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
1960 break;
1961 case OTG_STATE_B_WAIT_ACON:
1962 case OTG_STATE_B_HOST:
1963#endif
1964 case OTG_STATE_B_PERIPHERAL:
1965 case OTG_STATE_B_IDLE:
1966 musb->xceiv.state = OTG_STATE_B_IDLE;
1967 break;
1968 case OTG_STATE_B_SRP_INIT:
1969 break;
1970 }
1971
1972 musb->is_active = 0;
1973}
1974
1975void musb_g_reset(struct musb *musb)
1976__releases(musb->lock)
1977__acquires(musb->lock)
1978{
1979 void __iomem *mbase = musb->mregs;
1980 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
1981 u8 power;
1982
1983 DBG(3, "<== %s addr=%x driver '%s'\n",
1984 (devctl & MUSB_DEVCTL_BDEVICE)
1985 ? "B-Device" : "A-Device",
1986 musb_readb(mbase, MUSB_FADDR),
1987 musb->gadget_driver
1988 ? musb->gadget_driver->driver.name
1989 : NULL
1990 );
1991
1992 /* report disconnect, if we didn't already (flushing EP state) */
1993 if (musb->g.speed != USB_SPEED_UNKNOWN)
1994 musb_g_disconnect(musb);
1995
1996 /* clear HR */
1997 else if (devctl & MUSB_DEVCTL_HR)
1998 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
1999
2000
2001 /* what speed did we negotiate? */
2002 power = musb_readb(mbase, MUSB_POWER);
2003 musb->g.speed = (power & MUSB_POWER_HSMODE)
2004 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2005
2006 /* start in USB_STATE_DEFAULT */
2007 musb->is_active = 1;
2008 musb->is_suspended = 0;
2009 MUSB_DEV_MODE(musb);
2010 musb->address = 0;
2011 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2012
2013 musb->may_wakeup = 0;
2014 musb->g.b_hnp_enable = 0;
2015 musb->g.a_alt_hnp_support = 0;
2016 musb->g.a_hnp_support = 0;
2017
2018 /* Normal reset, as B-Device;
2019 * or else after HNP, as A-Device
2020 */
2021 if (devctl & MUSB_DEVCTL_BDEVICE) {
2022 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
2023 musb->g.is_a_peripheral = 0;
2024 } else if (is_otg_enabled(musb)) {
2025 musb->xceiv.state = OTG_STATE_A_PERIPHERAL;
2026 musb->g.is_a_peripheral = 1;
2027 } else
2028 WARN_ON(1);
2029
2030 /* start with default limits on VBUS power draw */
2031 (void) musb_gadget_vbus_draw(&musb->g,
2032 is_otg_enabled(musb) ? 8 : 100);
2033}
diff --git a/drivers/usb/musb/musb_gadget.h b/drivers/usb/musb/musb_gadget.h
new file mode 100644
index 000000000000..59502da9f739
--- /dev/null
+++ b/drivers/usb/musb/musb_gadget.h
@@ -0,0 +1,108 @@
1/*
2 * MUSB OTG driver peripheral defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_GADGET_H
36#define __MUSB_GADGET_H
37
38struct musb_request {
39 struct usb_request request;
40 struct musb_ep *ep;
41 struct musb *musb;
42 u8 tx; /* endpoint direction */
43 u8 epnum;
44 u8 mapped;
45};
46
47static inline struct musb_request *to_musb_request(struct usb_request *req)
48{
49 return req ? container_of(req, struct musb_request, request) : NULL;
50}
51
52extern struct usb_request *
53musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
54extern void musb_free_request(struct usb_ep *ep, struct usb_request *req);
55
56
57/*
58 * struct musb_ep - peripheral side view of endpoint rx or tx side
59 */
60struct musb_ep {
61 /* stuff towards the head is basically write-once. */
62 struct usb_ep end_point;
63 char name[12];
64 struct musb_hw_ep *hw_ep;
65 struct musb *musb;
66 u8 current_epnum;
67
68 /* ... when enabled/disabled ... */
69 u8 type;
70 u8 is_in;
71 u16 packet_sz;
72 const struct usb_endpoint_descriptor *desc;
73 struct dma_channel *dma;
74
75 /* later things are modified based on usage */
76 struct list_head req_list;
77
78 /* true if lock must be dropped but req_list may not be advanced */
79 u8 busy;
80};
81
82static inline struct musb_ep *to_musb_ep(struct usb_ep *ep)
83{
84 return ep ? container_of(ep, struct musb_ep, end_point) : NULL;
85}
86
87static inline struct usb_request *next_request(struct musb_ep *ep)
88{
89 struct list_head *queue = &ep->req_list;
90
91 if (list_empty(queue))
92 return NULL;
93 return container_of(queue->next, struct usb_request, list);
94}
95
96extern void musb_g_tx(struct musb *musb, u8 epnum);
97extern void musb_g_rx(struct musb *musb, u8 epnum);
98
99extern const struct usb_ep_ops musb_g_ep0_ops;
100
101extern int musb_gadget_setup(struct musb *);
102extern void musb_gadget_cleanup(struct musb *);
103
104extern void musb_g_giveback(struct musb_ep *, struct usb_request *, int);
105
106extern int musb_gadget_set_halt(struct usb_ep *ep, int value);
107
108#endif /* __MUSB_GADGET_H */
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
new file mode 100644
index 000000000000..48d7d3ccb243
--- /dev/null
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -0,0 +1,981 @@
1/*
2 * MUSB OTG peripheral driver ep0 handling
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/list.h>
37#include <linux/timer.h>
38#include <linux/spinlock.h>
39#include <linux/init.h>
40#include <linux/device.h>
41#include <linux/interrupt.h>
42
43#include "musb_core.h"
44
45/* ep0 is always musb->endpoints[0].ep_in */
46#define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
47
48/*
49 * locking note: we use only the controller lock, for simpler correctness.
50 * It's always held with IRQs blocked.
51 *
52 * It protects the ep0 request queue as well as ep0_state, not just the
53 * controller and indexed registers. And that lock stays held unless it
54 * needs to be dropped to allow reentering this driver ... like upcalls to
55 * the gadget driver, or adjusting endpoint halt status.
56 */
57
58static char *decode_ep0stage(u8 stage)
59{
60 switch (stage) {
61 case MUSB_EP0_STAGE_SETUP: return "idle";
62 case MUSB_EP0_STAGE_TX: return "in";
63 case MUSB_EP0_STAGE_RX: return "out";
64 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
65 case MUSB_EP0_STAGE_STATUSIN: return "in/status";
66 case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
67 default: return "?";
68 }
69}
70
71/* handle a standard GET_STATUS request
72 * Context: caller holds controller lock
73 */
74static int service_tx_status_request(
75 struct musb *musb,
76 const struct usb_ctrlrequest *ctrlrequest)
77{
78 void __iomem *mbase = musb->mregs;
79 int handled = 1;
80 u8 result[2], epnum = 0;
81 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
82
83 result[1] = 0;
84
85 switch (recip) {
86 case USB_RECIP_DEVICE:
87 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
88 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
89#ifdef CONFIG_USB_MUSB_OTG
90 if (musb->g.is_otg) {
91 result[0] |= musb->g.b_hnp_enable
92 << USB_DEVICE_B_HNP_ENABLE;
93 result[0] |= musb->g.a_alt_hnp_support
94 << USB_DEVICE_A_ALT_HNP_SUPPORT;
95 result[0] |= musb->g.a_hnp_support
96 << USB_DEVICE_A_HNP_SUPPORT;
97 }
98#endif
99 break;
100
101 case USB_RECIP_INTERFACE:
102 result[0] = 0;
103 break;
104
105 case USB_RECIP_ENDPOINT: {
106 int is_in;
107 struct musb_ep *ep;
108 u16 tmp;
109 void __iomem *regs;
110
111 epnum = (u8) ctrlrequest->wIndex;
112 if (!epnum) {
113 result[0] = 0;
114 break;
115 }
116
117 is_in = epnum & USB_DIR_IN;
118 if (is_in) {
119 epnum &= 0x0f;
120 ep = &musb->endpoints[epnum].ep_in;
121 } else {
122 ep = &musb->endpoints[epnum].ep_out;
123 }
124 regs = musb->endpoints[epnum].regs;
125
126 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
127 handled = -EINVAL;
128 break;
129 }
130
131 musb_ep_select(mbase, epnum);
132 if (is_in)
133 tmp = musb_readw(regs, MUSB_TXCSR)
134 & MUSB_TXCSR_P_SENDSTALL;
135 else
136 tmp = musb_readw(regs, MUSB_RXCSR)
137 & MUSB_RXCSR_P_SENDSTALL;
138 musb_ep_select(mbase, 0);
139
140 result[0] = tmp ? 1 : 0;
141 } break;
142
143 default:
144 /* class, vendor, etc ... delegate */
145 handled = 0;
146 break;
147 }
148
149 /* fill up the fifo; caller updates csr0 */
150 if (handled > 0) {
151 u16 len = le16_to_cpu(ctrlrequest->wLength);
152
153 if (len > 2)
154 len = 2;
155 musb_write_fifo(&musb->endpoints[0], len, result);
156 }
157
158 return handled;
159}
160
161/*
162 * handle a control-IN request, the end0 buffer contains the current request
163 * that is supposed to be a standard control request. Assumes the fifo to
164 * be at least 2 bytes long.
165 *
166 * @return 0 if the request was NOT HANDLED,
167 * < 0 when error
168 * > 0 when the request is processed
169 *
170 * Context: caller holds controller lock
171 */
172static int
173service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
174{
175 int handled = 0; /* not handled */
176
177 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
178 == USB_TYPE_STANDARD) {
179 switch (ctrlrequest->bRequest) {
180 case USB_REQ_GET_STATUS:
181 handled = service_tx_status_request(musb,
182 ctrlrequest);
183 break;
184
185 /* case USB_REQ_SYNC_FRAME: */
186
187 default:
188 break;
189 }
190 }
191 return handled;
192}
193
194/*
195 * Context: caller holds controller lock
196 */
197static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
198{
199 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
200 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
201}
202
203/*
204 * Tries to start B-device HNP negotiation if enabled via sysfs
205 */
206static inline void musb_try_b_hnp_enable(struct musb *musb)
207{
208 void __iomem *mbase = musb->mregs;
209 u8 devctl;
210
211 DBG(1, "HNP: Setting HR\n");
212 devctl = musb_readb(mbase, MUSB_DEVCTL);
213 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
214}
215
216/*
217 * Handle all control requests with no DATA stage, including standard
218 * requests such as:
219 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
220 * always delegated to the gadget driver
221 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
222 * always handled here, except for class/vendor/... features
223 *
224 * Context: caller holds controller lock
225 */
226static int
227service_zero_data_request(struct musb *musb,
228 struct usb_ctrlrequest *ctrlrequest)
229__releases(musb->lock)
230__acquires(musb->lock)
231{
232 int handled = -EINVAL;
233 void __iomem *mbase = musb->mregs;
234 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
235
236 /* the gadget driver handles everything except what we MUST handle */
237 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
238 == USB_TYPE_STANDARD) {
239 switch (ctrlrequest->bRequest) {
240 case USB_REQ_SET_ADDRESS:
241 /* change it after the status stage */
242 musb->set_address = true;
243 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
244 handled = 1;
245 break;
246
247 case USB_REQ_CLEAR_FEATURE:
248 switch (recip) {
249 case USB_RECIP_DEVICE:
250 if (ctrlrequest->wValue
251 != USB_DEVICE_REMOTE_WAKEUP)
252 break;
253 musb->may_wakeup = 0;
254 handled = 1;
255 break;
256 case USB_RECIP_INTERFACE:
257 break;
258 case USB_RECIP_ENDPOINT:{
259 const u8 num = ctrlrequest->wIndex & 0x0f;
260 struct musb_ep *musb_ep;
261
262 if (num == 0
263 || num >= MUSB_C_NUM_EPS
264 || ctrlrequest->wValue
265 != USB_ENDPOINT_HALT)
266 break;
267
268 if (ctrlrequest->wIndex & USB_DIR_IN)
269 musb_ep = &musb->endpoints[num].ep_in;
270 else
271 musb_ep = &musb->endpoints[num].ep_out;
272 if (!musb_ep->desc)
273 break;
274
275 /* REVISIT do it directly, no locking games */
276 spin_unlock(&musb->lock);
277 musb_gadget_set_halt(&musb_ep->end_point, 0);
278 spin_lock(&musb->lock);
279
280 /* select ep0 again */
281 musb_ep_select(mbase, 0);
282 handled = 1;
283 } break;
284 default:
285 /* class, vendor, etc ... delegate */
286 handled = 0;
287 break;
288 }
289 break;
290
291 case USB_REQ_SET_FEATURE:
292 switch (recip) {
293 case USB_RECIP_DEVICE:
294 handled = 1;
295 switch (ctrlrequest->wValue) {
296 case USB_DEVICE_REMOTE_WAKEUP:
297 musb->may_wakeup = 1;
298 break;
299 case USB_DEVICE_TEST_MODE:
300 if (musb->g.speed != USB_SPEED_HIGH)
301 goto stall;
302 if (ctrlrequest->wIndex & 0xff)
303 goto stall;
304
305 switch (ctrlrequest->wIndex >> 8) {
306 case 1:
307 pr_debug("TEST_J\n");
308 /* TEST_J */
309 musb->test_mode_nr =
310 MUSB_TEST_J;
311 break;
312 case 2:
313 /* TEST_K */
314 pr_debug("TEST_K\n");
315 musb->test_mode_nr =
316 MUSB_TEST_K;
317 break;
318 case 3:
319 /* TEST_SE0_NAK */
320 pr_debug("TEST_SE0_NAK\n");
321 musb->test_mode_nr =
322 MUSB_TEST_SE0_NAK;
323 break;
324 case 4:
325 /* TEST_PACKET */
326 pr_debug("TEST_PACKET\n");
327 musb->test_mode_nr =
328 MUSB_TEST_PACKET;
329 break;
330 default:
331 goto stall;
332 }
333
334 /* enter test mode after irq */
335 if (handled > 0)
336 musb->test_mode = true;
337 break;
338#ifdef CONFIG_USB_MUSB_OTG
339 case USB_DEVICE_B_HNP_ENABLE:
340 if (!musb->g.is_otg)
341 goto stall;
342 musb->g.b_hnp_enable = 1;
343 musb_try_b_hnp_enable(musb);
344 break;
345 case USB_DEVICE_A_HNP_SUPPORT:
346 if (!musb->g.is_otg)
347 goto stall;
348 musb->g.a_hnp_support = 1;
349 break;
350 case USB_DEVICE_A_ALT_HNP_SUPPORT:
351 if (!musb->g.is_otg)
352 goto stall;
353 musb->g.a_alt_hnp_support = 1;
354 break;
355#endif
356stall:
357 default:
358 handled = -EINVAL;
359 break;
360 }
361 break;
362
363 case USB_RECIP_INTERFACE:
364 break;
365
366 case USB_RECIP_ENDPOINT:{
367 const u8 epnum =
368 ctrlrequest->wIndex & 0x0f;
369 struct musb_ep *musb_ep;
370 struct musb_hw_ep *ep;
371 void __iomem *regs;
372 int is_in;
373 u16 csr;
374
375 if (epnum == 0
376 || epnum >= MUSB_C_NUM_EPS
377 || ctrlrequest->wValue
378 != USB_ENDPOINT_HALT)
379 break;
380
381 ep = musb->endpoints + epnum;
382 regs = ep->regs;
383 is_in = ctrlrequest->wIndex & USB_DIR_IN;
384 if (is_in)
385 musb_ep = &ep->ep_in;
386 else
387 musb_ep = &ep->ep_out;
388 if (!musb_ep->desc)
389 break;
390
391 musb_ep_select(mbase, epnum);
392 if (is_in) {
393 csr = musb_readw(regs,
394 MUSB_TXCSR);
395 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
396 csr |= MUSB_TXCSR_FLUSHFIFO;
397 csr |= MUSB_TXCSR_P_SENDSTALL
398 | MUSB_TXCSR_CLRDATATOG
399 | MUSB_TXCSR_P_WZC_BITS;
400 musb_writew(regs, MUSB_TXCSR,
401 csr);
402 } else {
403 csr = musb_readw(regs,
404 MUSB_RXCSR);
405 csr |= MUSB_RXCSR_P_SENDSTALL
406 | MUSB_RXCSR_FLUSHFIFO
407 | MUSB_RXCSR_CLRDATATOG
408 | MUSB_TXCSR_P_WZC_BITS;
409 musb_writew(regs, MUSB_RXCSR,
410 csr);
411 }
412
413 /* select ep0 again */
414 musb_ep_select(mbase, 0);
415 handled = 1;
416 } break;
417
418 default:
419 /* class, vendor, etc ... delegate */
420 handled = 0;
421 break;
422 }
423 break;
424 default:
425 /* delegate SET_CONFIGURATION, etc */
426 handled = 0;
427 }
428 } else
429 handled = 0;
430 return handled;
431}
432
433/* we have an ep0out data packet
434 * Context: caller holds controller lock
435 */
436static void ep0_rxstate(struct musb *musb)
437{
438 void __iomem *regs = musb->control_ep->regs;
439 struct usb_request *req;
440 u16 tmp;
441
442 req = next_ep0_request(musb);
443
444 /* read packet and ack; or stall because of gadget driver bug:
445 * should have provided the rx buffer before setup() returned.
446 */
447 if (req) {
448 void *buf = req->buf + req->actual;
449 unsigned len = req->length - req->actual;
450
451 /* read the buffer */
452 tmp = musb_readb(regs, MUSB_COUNT0);
453 if (tmp > len) {
454 req->status = -EOVERFLOW;
455 tmp = len;
456 }
457 musb_read_fifo(&musb->endpoints[0], tmp, buf);
458 req->actual += tmp;
459 tmp = MUSB_CSR0_P_SVDRXPKTRDY;
460 if (tmp < 64 || req->actual == req->length) {
461 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
462 tmp |= MUSB_CSR0_P_DATAEND;
463 } else
464 req = NULL;
465 } else
466 tmp = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
467
468
469 /* Completion handler may choose to stall, e.g. because the
470 * message just received holds invalid data.
471 */
472 if (req) {
473 musb->ackpend = tmp;
474 musb_g_ep0_giveback(musb, req);
475 if (!musb->ackpend)
476 return;
477 musb->ackpend = 0;
478 }
479 musb_writew(regs, MUSB_CSR0, tmp);
480}
481
482/*
483 * transmitting to the host (IN), this code might be called from IRQ
484 * and from kernel thread.
485 *
486 * Context: caller holds controller lock
487 */
488static void ep0_txstate(struct musb *musb)
489{
490 void __iomem *regs = musb->control_ep->regs;
491 struct usb_request *request = next_ep0_request(musb);
492 u16 csr = MUSB_CSR0_TXPKTRDY;
493 u8 *fifo_src;
494 u8 fifo_count;
495
496 if (!request) {
497 /* WARN_ON(1); */
498 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
499 return;
500 }
501
502 /* load the data */
503 fifo_src = (u8 *) request->buf + request->actual;
504 fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
505 request->length - request->actual);
506 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
507 request->actual += fifo_count;
508
509 /* update the flags */
510 if (fifo_count < MUSB_MAX_END0_PACKET
511 || request->actual == request->length) {
512 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
513 csr |= MUSB_CSR0_P_DATAEND;
514 } else
515 request = NULL;
516
517 /* report completions as soon as the fifo's loaded; there's no
518 * win in waiting till this last packet gets acked. (other than
519 * very precise fault reporting, needed by USB TMC; possible with
520 * this hardware, but not usable from portable gadget drivers.)
521 */
522 if (request) {
523 musb->ackpend = csr;
524 musb_g_ep0_giveback(musb, request);
525 if (!musb->ackpend)
526 return;
527 musb->ackpend = 0;
528 }
529
530 /* send it out, triggering a "txpktrdy cleared" irq */
531 musb_writew(regs, MUSB_CSR0, csr);
532}
533
534/*
535 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
536 * Fields are left in USB byte-order.
537 *
538 * Context: caller holds controller lock.
539 */
540static void
541musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
542{
543 struct usb_request *r;
544 void __iomem *regs = musb->control_ep->regs;
545
546 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
547
548 /* NOTE: earlier 2.6 versions changed setup packets to host
549 * order, but now USB packets always stay in USB byte order.
550 */
551 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
552 req->bRequestType,
553 req->bRequest,
554 le16_to_cpu(req->wValue),
555 le16_to_cpu(req->wIndex),
556 le16_to_cpu(req->wLength));
557
558 /* clean up any leftover transfers */
559 r = next_ep0_request(musb);
560 if (r)
561 musb_g_ep0_giveback(musb, r);
562
563 /* For zero-data requests we want to delay the STATUS stage to
564 * avoid SETUPEND errors. If we read data (OUT), delay accepting
565 * packets until there's a buffer to store them in.
566 *
567 * If we write data, the controller acts happier if we enable
568 * the TX FIFO right away, and give the controller a moment
569 * to switch modes...
570 */
571 musb->set_address = false;
572 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
573 if (req->wLength == 0) {
574 if (req->bRequestType & USB_DIR_IN)
575 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
576 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
577 } else if (req->bRequestType & USB_DIR_IN) {
578 musb->ep0_state = MUSB_EP0_STAGE_TX;
579 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
580 while ((musb_readw(regs, MUSB_CSR0)
581 & MUSB_CSR0_RXPKTRDY) != 0)
582 cpu_relax();
583 musb->ackpend = 0;
584 } else
585 musb->ep0_state = MUSB_EP0_STAGE_RX;
586}
587
588static int
589forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
590__releases(musb->lock)
591__acquires(musb->lock)
592{
593 int retval;
594 if (!musb->gadget_driver)
595 return -EOPNOTSUPP;
596 spin_unlock(&musb->lock);
597 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
598 spin_lock(&musb->lock);
599 return retval;
600}
601
602/*
603 * Handle peripheral ep0 interrupt
604 *
605 * Context: irq handler; we won't re-enter the driver that way.
606 */
607irqreturn_t musb_g_ep0_irq(struct musb *musb)
608{
609 u16 csr;
610 u16 len;
611 void __iomem *mbase = musb->mregs;
612 void __iomem *regs = musb->endpoints[0].regs;
613 irqreturn_t retval = IRQ_NONE;
614
615 musb_ep_select(mbase, 0); /* select ep0 */
616 csr = musb_readw(regs, MUSB_CSR0);
617 len = musb_readb(regs, MUSB_COUNT0);
618
619 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
620 csr, len,
621 musb_readb(mbase, MUSB_FADDR),
622 decode_ep0stage(musb->ep0_state));
623
624 /* I sent a stall.. need to acknowledge it now.. */
625 if (csr & MUSB_CSR0_P_SENTSTALL) {
626 musb_writew(regs, MUSB_CSR0,
627 csr & ~MUSB_CSR0_P_SENTSTALL);
628 retval = IRQ_HANDLED;
629 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
630 csr = musb_readw(regs, MUSB_CSR0);
631 }
632
633 /* request ended "early" */
634 if (csr & MUSB_CSR0_P_SETUPEND) {
635 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
636 retval = IRQ_HANDLED;
637 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
638 csr = musb_readw(regs, MUSB_CSR0);
639 /* NOTE: request may need completion */
640 }
641
642 /* docs from Mentor only describe tx, rx, and idle/setup states.
643 * we need to handle nuances around status stages, and also the
644 * case where status and setup stages come back-to-back ...
645 */
646 switch (musb->ep0_state) {
647
648 case MUSB_EP0_STAGE_TX:
649 /* irq on clearing txpktrdy */
650 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
651 ep0_txstate(musb);
652 retval = IRQ_HANDLED;
653 }
654 break;
655
656 case MUSB_EP0_STAGE_RX:
657 /* irq on set rxpktrdy */
658 if (csr & MUSB_CSR0_RXPKTRDY) {
659 ep0_rxstate(musb);
660 retval = IRQ_HANDLED;
661 }
662 break;
663
664 case MUSB_EP0_STAGE_STATUSIN:
665 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
666
667 /* update address (if needed) only @ the end of the
668 * status phase per usb spec, which also guarantees
669 * we get 10 msec to receive this irq... until this
670 * is done we won't see the next packet.
671 */
672 if (musb->set_address) {
673 musb->set_address = false;
674 musb_writeb(mbase, MUSB_FADDR, musb->address);
675 }
676
677 /* enter test mode if needed (exit by reset) */
678 else if (musb->test_mode) {
679 DBG(1, "entering TESTMODE\n");
680
681 if (MUSB_TEST_PACKET == musb->test_mode_nr)
682 musb_load_testpacket(musb);
683
684 musb_writeb(mbase, MUSB_TESTMODE,
685 musb->test_mode_nr);
686 }
687 /* FALLTHROUGH */
688
689 case MUSB_EP0_STAGE_STATUSOUT:
690 /* end of sequence #1: write to host (TX state) */
691 {
692 struct usb_request *req;
693
694 req = next_ep0_request(musb);
695 if (req)
696 musb_g_ep0_giveback(musb, req);
697 }
698 retval = IRQ_HANDLED;
699 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
700 /* FALLTHROUGH */
701
702 case MUSB_EP0_STAGE_SETUP:
703 if (csr & MUSB_CSR0_RXPKTRDY) {
704 struct usb_ctrlrequest setup;
705 int handled = 0;
706
707 if (len != 8) {
708 ERR("SETUP packet len %d != 8 ?\n", len);
709 break;
710 }
711 musb_read_setup(musb, &setup);
712 retval = IRQ_HANDLED;
713
714 /* sometimes the RESET won't be reported */
715 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
716 u8 power;
717
718 printk(KERN_NOTICE "%s: peripheral reset "
719 "irq lost!\n",
720 musb_driver_name);
721 power = musb_readb(mbase, MUSB_POWER);
722 musb->g.speed = (power & MUSB_POWER_HSMODE)
723 ? USB_SPEED_HIGH : USB_SPEED_FULL;
724
725 }
726
727 switch (musb->ep0_state) {
728
729 /* sequence #3 (no data stage), includes requests
730 * we can't forward (notably SET_ADDRESS and the
731 * device/endpoint feature set/clear operations)
732 * plus SET_CONFIGURATION and others we must
733 */
734 case MUSB_EP0_STAGE_ACKWAIT:
735 handled = service_zero_data_request(
736 musb, &setup);
737
738 /* status stage might be immediate */
739 if (handled > 0) {
740 musb->ackpend |= MUSB_CSR0_P_DATAEND;
741 musb->ep0_state =
742 MUSB_EP0_STAGE_STATUSIN;
743 }
744 break;
745
746 /* sequence #1 (IN to host), includes GET_STATUS
747 * requests that we can't forward, GET_DESCRIPTOR
748 * and others that we must
749 */
750 case MUSB_EP0_STAGE_TX:
751 handled = service_in_request(musb, &setup);
752 if (handled > 0) {
753 musb->ackpend = MUSB_CSR0_TXPKTRDY
754 | MUSB_CSR0_P_DATAEND;
755 musb->ep0_state =
756 MUSB_EP0_STAGE_STATUSOUT;
757 }
758 break;
759
760 /* sequence #2 (OUT from host), always forward */
761 default: /* MUSB_EP0_STAGE_RX */
762 break;
763 }
764
765 DBG(3, "handled %d, csr %04x, ep0stage %s\n",
766 handled, csr,
767 decode_ep0stage(musb->ep0_state));
768
769 /* unless we need to delegate this to the gadget
770 * driver, we know how to wrap this up: csr0 has
771 * not yet been written.
772 */
773 if (handled < 0)
774 goto stall;
775 else if (handled > 0)
776 goto finish;
777
778 handled = forward_to_driver(musb, &setup);
779 if (handled < 0) {
780 musb_ep_select(mbase, 0);
781stall:
782 DBG(3, "stall (%d)\n", handled);
783 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
784 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
785finish:
786 musb_writew(regs, MUSB_CSR0,
787 musb->ackpend);
788 musb->ackpend = 0;
789 }
790 }
791 break;
792
793 case MUSB_EP0_STAGE_ACKWAIT:
794 /* This should not happen. But happens with tusb6010 with
795 * g_file_storage and high speed. Do nothing.
796 */
797 retval = IRQ_HANDLED;
798 break;
799
800 default:
801 /* "can't happen" */
802 WARN_ON(1);
803 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
804 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
805 break;
806 }
807
808 return retval;
809}
810
811
812static int
813musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
814{
815 /* always enabled */
816 return -EINVAL;
817}
818
819static int musb_g_ep0_disable(struct usb_ep *e)
820{
821 /* always enabled */
822 return -EINVAL;
823}
824
825static int
826musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
827{
828 struct musb_ep *ep;
829 struct musb_request *req;
830 struct musb *musb;
831 int status;
832 unsigned long lockflags;
833 void __iomem *regs;
834
835 if (!e || !r)
836 return -EINVAL;
837
838 ep = to_musb_ep(e);
839 musb = ep->musb;
840 regs = musb->control_ep->regs;
841
842 req = to_musb_request(r);
843 req->musb = musb;
844 req->request.actual = 0;
845 req->request.status = -EINPROGRESS;
846 req->tx = ep->is_in;
847
848 spin_lock_irqsave(&musb->lock, lockflags);
849
850 if (!list_empty(&ep->req_list)) {
851 status = -EBUSY;
852 goto cleanup;
853 }
854
855 switch (musb->ep0_state) {
856 case MUSB_EP0_STAGE_RX: /* control-OUT data */
857 case MUSB_EP0_STAGE_TX: /* control-IN data */
858 case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
859 status = 0;
860 break;
861 default:
862 DBG(1, "ep0 request queued in state %d\n",
863 musb->ep0_state);
864 status = -EINVAL;
865 goto cleanup;
866 }
867
868 /* add request to the list */
869 list_add_tail(&(req->request.list), &(ep->req_list));
870
871 DBG(3, "queue to %s (%s), length=%d\n",
872 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
873 req->request.length);
874
875 musb_ep_select(musb->mregs, 0);
876
877 /* sequence #1, IN ... start writing the data */
878 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
879 ep0_txstate(musb);
880
881 /* sequence #3, no-data ... issue IN status */
882 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
883 if (req->request.length)
884 status = -EINVAL;
885 else {
886 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
887 musb_writew(regs, MUSB_CSR0,
888 musb->ackpend | MUSB_CSR0_P_DATAEND);
889 musb->ackpend = 0;
890 musb_g_ep0_giveback(ep->musb, r);
891 }
892
893 /* else for sequence #2 (OUT), caller provides a buffer
894 * before the next packet arrives. deferred responses
895 * (after SETUP is acked) are racey.
896 */
897 } else if (musb->ackpend) {
898 musb_writew(regs, MUSB_CSR0, musb->ackpend);
899 musb->ackpend = 0;
900 }
901
902cleanup:
903 spin_unlock_irqrestore(&musb->lock, lockflags);
904 return status;
905}
906
907static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
908{
909 /* we just won't support this */
910 return -EINVAL;
911}
912
913static int musb_g_ep0_halt(struct usb_ep *e, int value)
914{
915 struct musb_ep *ep;
916 struct musb *musb;
917 void __iomem *base, *regs;
918 unsigned long flags;
919 int status;
920 u16 csr;
921
922 if (!e || !value)
923 return -EINVAL;
924
925 ep = to_musb_ep(e);
926 musb = ep->musb;
927 base = musb->mregs;
928 regs = musb->control_ep->regs;
929 status = 0;
930
931 spin_lock_irqsave(&musb->lock, flags);
932
933 if (!list_empty(&ep->req_list)) {
934 status = -EBUSY;
935 goto cleanup;
936 }
937
938 musb_ep_select(base, 0);
939 csr = musb->ackpend;
940
941 switch (musb->ep0_state) {
942
943 /* Stalls are usually issued after parsing SETUP packet, either
944 * directly in irq context from setup() or else later.
945 */
946 case MUSB_EP0_STAGE_TX: /* control-IN data */
947 case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
948 case MUSB_EP0_STAGE_RX: /* control-OUT data */
949 csr = musb_readw(regs, MUSB_CSR0);
950 /* FALLTHROUGH */
951
952 /* It's also OK to issue stalls during callbacks when a non-empty
953 * DATA stage buffer has been read (or even written).
954 */
955 case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
956 case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
957
958 csr |= MUSB_CSR0_P_SENDSTALL;
959 musb_writew(regs, MUSB_CSR0, csr);
960 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
961 musb->ackpend = 0;
962 break;
963 default:
964 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
965 status = -EINVAL;
966 }
967
968cleanup:
969 spin_unlock_irqrestore(&musb->lock, flags);
970 return status;
971}
972
973const struct usb_ep_ops musb_g_ep0_ops = {
974 .enable = musb_g_ep0_enable,
975 .disable = musb_g_ep0_disable,
976 .alloc_request = musb_alloc_request,
977 .free_request = musb_free_request,
978 .queue = musb_g_ep0_queue,
979 .dequeue = musb_g_ep0_dequeue,
980 .set_halt = musb_g_ep0_halt,
981};
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
new file mode 100644
index 000000000000..8b4be012669a
--- /dev/null
+++ b/drivers/usb/musb/musb_host.c
@@ -0,0 +1,2170 @@
1/*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#include <linux/module.h>
36#include <linux/kernel.h>
37#include <linux/delay.h>
38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/errno.h>
41#include <linux/init.h>
42#include <linux/list.h>
43
44#include "musb_core.h"
45#include "musb_host.h"
46
47
48/* MUSB HOST status 22-mar-2006
49 *
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
52 *
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
59 *
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
64 *
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
66 *
67 * - Still no traffic scheduling code to make NAKing for bulk or control
68 * transfers unable to starve other requests; or to make efficient use
69 * of hardware with periodic transfers. (Note that network drivers
70 * commonly post bulk reads that stay pending for a long time; these
71 * would make very visible trouble.)
72 *
73 * - Not tested with HNP, but some SRP paths seem to behave.
74 *
75 * NOTE 24-August-2006:
76 *
77 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
78 * extra endpoint for periodic use enabling hub + keybd + mouse. That
79 * mostly works, except that with "usbnet" it's easy to trigger cases
80 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
81 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
82 * although ARP RX wins. (That test was done with a full speed link.)
83 */
84
85
86/*
87 * NOTE on endpoint usage:
88 *
89 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
90 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
91 *
92 * (Yes, bulk _could_ use more of the endpoints than that, and would even
93 * benefit from it ... one remote device may easily be NAKing while others
94 * need to perform transfers in that same direction. The same thing could
95 * be done in software though, assuming dma cooperates.)
96 *
97 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
98 * So far that scheduling is both dumb and optimistic: the endpoint will be
99 * "claimed" until its software queue is no longer refilled. No multiplexing
100 * of transfers between endpoints, or anything clever.
101 */
102
103
104static void musb_ep_program(struct musb *musb, u8 epnum,
105 struct urb *urb, unsigned int nOut,
106 u8 *buf, u32 len);
107
108/*
109 * Clear TX fifo. Needed to avoid BABBLE errors.
110 */
111static inline void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
112{
113 void __iomem *epio = ep->regs;
114 u16 csr;
115 int retries = 1000;
116
117 csr = musb_readw(epio, MUSB_TXCSR);
118 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
119 DBG(5, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
120 csr |= MUSB_TXCSR_FLUSHFIFO;
121 musb_writew(epio, MUSB_TXCSR, csr);
122 csr = musb_readw(epio, MUSB_TXCSR);
123 if (retries-- < 1) {
124 ERR("Could not flush host TX fifo: csr: %04x\n", csr);
125 return;
126 }
127 mdelay(1);
128 }
129}
130
131/*
132 * Start transmit. Caller is responsible for locking shared resources.
133 * musb must be locked.
134 */
135static inline void musb_h_tx_start(struct musb_hw_ep *ep)
136{
137 u16 txcsr;
138
139 /* NOTE: no locks here; caller should lock and select EP */
140 if (ep->epnum) {
141 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
142 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
143 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
144 } else {
145 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
146 musb_writew(ep->regs, MUSB_CSR0, txcsr);
147 }
148
149}
150
151static inline void cppi_host_txdma_start(struct musb_hw_ep *ep)
152{
153 u16 txcsr;
154
155 /* NOTE: no locks here; caller should lock and select EP */
156 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
157 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
158 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
159}
160
161/*
162 * Start the URB at the front of an endpoint's queue
163 * end must be claimed from the caller.
164 *
165 * Context: controller locked, irqs blocked
166 */
167static void
168musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
169{
170 u16 frame;
171 u32 len;
172 void *buf;
173 void __iomem *mbase = musb->mregs;
174 struct urb *urb = next_urb(qh);
175 struct musb_hw_ep *hw_ep = qh->hw_ep;
176 unsigned pipe = urb->pipe;
177 u8 address = usb_pipedevice(pipe);
178 int epnum = hw_ep->epnum;
179
180 /* initialize software qh state */
181 qh->offset = 0;
182 qh->segsize = 0;
183
184 /* gather right source of data */
185 switch (qh->type) {
186 case USB_ENDPOINT_XFER_CONTROL:
187 /* control transfers always start with SETUP */
188 is_in = 0;
189 hw_ep->out_qh = qh;
190 musb->ep0_stage = MUSB_EP0_START;
191 buf = urb->setup_packet;
192 len = 8;
193 break;
194 case USB_ENDPOINT_XFER_ISOC:
195 qh->iso_idx = 0;
196 qh->frame = 0;
197 buf = urb->transfer_buffer + urb->iso_frame_desc[0].offset;
198 len = urb->iso_frame_desc[0].length;
199 break;
200 default: /* bulk, interrupt */
201 buf = urb->transfer_buffer;
202 len = urb->transfer_buffer_length;
203 }
204
205 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
206 qh, urb, address, qh->epnum,
207 is_in ? "in" : "out",
208 ({char *s; switch (qh->type) {
209 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
210 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
211 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
212 default: s = "-intr"; break;
213 }; s; }),
214 epnum, buf, len);
215
216 /* Configure endpoint */
217 if (is_in || hw_ep->is_shared_fifo)
218 hw_ep->in_qh = qh;
219 else
220 hw_ep->out_qh = qh;
221 musb_ep_program(musb, epnum, urb, !is_in, buf, len);
222
223 /* transmit may have more work: start it when it is time */
224 if (is_in)
225 return;
226
227 /* determine if the time is right for a periodic transfer */
228 switch (qh->type) {
229 case USB_ENDPOINT_XFER_ISOC:
230 case USB_ENDPOINT_XFER_INT:
231 DBG(3, "check whether there's still time for periodic Tx\n");
232 qh->iso_idx = 0;
233 frame = musb_readw(mbase, MUSB_FRAME);
234 /* FIXME this doesn't implement that scheduling policy ...
235 * or handle framecounter wrapping
236 */
237 if ((urb->transfer_flags & URB_ISO_ASAP)
238 || (frame >= urb->start_frame)) {
239 /* REVISIT the SOF irq handler shouldn't duplicate
240 * this code; and we don't init urb->start_frame...
241 */
242 qh->frame = 0;
243 goto start;
244 } else {
245 qh->frame = urb->start_frame;
246 /* enable SOF interrupt so we can count down */
247 DBG(1, "SOF for %d\n", epnum);
248#if 1 /* ifndef CONFIG_ARCH_DAVINCI */
249 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
250#endif
251 }
252 break;
253 default:
254start:
255 DBG(4, "Start TX%d %s\n", epnum,
256 hw_ep->tx_channel ? "dma" : "pio");
257
258 if (!hw_ep->tx_channel)
259 musb_h_tx_start(hw_ep);
260 else if (is_cppi_enabled() || tusb_dma_omap())
261 cppi_host_txdma_start(hw_ep);
262 }
263}
264
265/* caller owns controller lock, irqs are blocked */
266static void
267__musb_giveback(struct musb *musb, struct urb *urb, int status)
268__releases(musb->lock)
269__acquires(musb->lock)
270{
271 DBG(({ int level; switch (urb->status) {
272 case 0:
273 level = 4;
274 break;
275 /* common/boring faults */
276 case -EREMOTEIO:
277 case -ESHUTDOWN:
278 case -ECONNRESET:
279 case -EPIPE:
280 level = 3;
281 break;
282 default:
283 level = 2;
284 break;
285 }; level; }),
286 "complete %p (%d), dev%d ep%d%s, %d/%d\n",
287 urb, urb->status,
288 usb_pipedevice(urb->pipe),
289 usb_pipeendpoint(urb->pipe),
290 usb_pipein(urb->pipe) ? "in" : "out",
291 urb->actual_length, urb->transfer_buffer_length
292 );
293
294 spin_unlock(&musb->lock);
295 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
296 spin_lock(&musb->lock);
297}
298
299/* for bulk/interrupt endpoints only */
300static inline void
301musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb)
302{
303 struct usb_device *udev = urb->dev;
304 u16 csr;
305 void __iomem *epio = ep->regs;
306 struct musb_qh *qh;
307
308 /* FIXME: the current Mentor DMA code seems to have
309 * problems getting toggle correct.
310 */
311
312 if (is_in || ep->is_shared_fifo)
313 qh = ep->in_qh;
314 else
315 qh = ep->out_qh;
316
317 if (!is_in) {
318 csr = musb_readw(epio, MUSB_TXCSR);
319 usb_settoggle(udev, qh->epnum, 1,
320 (csr & MUSB_TXCSR_H_DATATOGGLE)
321 ? 1 : 0);
322 } else {
323 csr = musb_readw(epio, MUSB_RXCSR);
324 usb_settoggle(udev, qh->epnum, 0,
325 (csr & MUSB_RXCSR_H_DATATOGGLE)
326 ? 1 : 0);
327 }
328}
329
330/* caller owns controller lock, irqs are blocked */
331static struct musb_qh *
332musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
333{
334 int is_in;
335 struct musb_hw_ep *ep = qh->hw_ep;
336 struct musb *musb = ep->musb;
337 int ready = qh->is_ready;
338
339 if (ep->is_shared_fifo)
340 is_in = 1;
341 else
342 is_in = usb_pipein(urb->pipe);
343
344 /* save toggle eagerly, for paranoia */
345 switch (qh->type) {
346 case USB_ENDPOINT_XFER_BULK:
347 case USB_ENDPOINT_XFER_INT:
348 musb_save_toggle(ep, is_in, urb);
349 break;
350 case USB_ENDPOINT_XFER_ISOC:
351 if (status == 0 && urb->error_count)
352 status = -EXDEV;
353 break;
354 }
355
356 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
357
358 qh->is_ready = 0;
359 __musb_giveback(musb, urb, status);
360 qh->is_ready = ready;
361
362 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
363 * invalidate qh as soon as list_empty(&hep->urb_list)
364 */
365 if (list_empty(&qh->hep->urb_list)) {
366 struct list_head *head;
367
368 if (is_in)
369 ep->rx_reinit = 1;
370 else
371 ep->tx_reinit = 1;
372
373 /* clobber old pointers to this qh */
374 if (is_in || ep->is_shared_fifo)
375 ep->in_qh = NULL;
376 else
377 ep->out_qh = NULL;
378 qh->hep->hcpriv = NULL;
379
380 switch (qh->type) {
381
382 case USB_ENDPOINT_XFER_ISOC:
383 case USB_ENDPOINT_XFER_INT:
384 /* this is where periodic bandwidth should be
385 * de-allocated if it's tracked and allocated;
386 * and where we'd update the schedule tree...
387 */
388 musb->periodic[ep->epnum] = NULL;
389 kfree(qh);
390 qh = NULL;
391 break;
392
393 case USB_ENDPOINT_XFER_CONTROL:
394 case USB_ENDPOINT_XFER_BULK:
395 /* fifo policy for these lists, except that NAKing
396 * should rotate a qh to the end (for fairness).
397 */
398 head = qh->ring.prev;
399 list_del(&qh->ring);
400 kfree(qh);
401 qh = first_qh(head);
402 break;
403 }
404 }
405 return qh;
406}
407
408/*
409 * Advance this hardware endpoint's queue, completing the specified urb and
410 * advancing to either the next urb queued to that qh, or else invalidating
411 * that qh and advancing to the next qh scheduled after the current one.
412 *
413 * Context: caller owns controller lock, irqs are blocked
414 */
415static void
416musb_advance_schedule(struct musb *musb, struct urb *urb,
417 struct musb_hw_ep *hw_ep, int is_in)
418{
419 struct musb_qh *qh;
420
421 if (is_in || hw_ep->is_shared_fifo)
422 qh = hw_ep->in_qh;
423 else
424 qh = hw_ep->out_qh;
425
426 if (urb->status == -EINPROGRESS)
427 qh = musb_giveback(qh, urb, 0);
428 else
429 qh = musb_giveback(qh, urb, urb->status);
430
431 if (qh && qh->is_ready && !list_empty(&qh->hep->urb_list)) {
432 DBG(4, "... next ep%d %cX urb %p\n",
433 hw_ep->epnum, is_in ? 'R' : 'T',
434 next_urb(qh));
435 musb_start_urb(musb, is_in, qh);
436 }
437}
438
439static inline u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
440{
441 /* we don't want fifo to fill itself again;
442 * ignore dma (various models),
443 * leave toggle alone (may not have been saved yet)
444 */
445 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
446 csr &= ~(MUSB_RXCSR_H_REQPKT
447 | MUSB_RXCSR_H_AUTOREQ
448 | MUSB_RXCSR_AUTOCLEAR);
449
450 /* write 2x to allow double buffering */
451 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
452 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
453
454 /* flush writebuffer */
455 return musb_readw(hw_ep->regs, MUSB_RXCSR);
456}
457
458/*
459 * PIO RX for a packet (or part of it).
460 */
461static bool
462musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
463{
464 u16 rx_count;
465 u8 *buf;
466 u16 csr;
467 bool done = false;
468 u32 length;
469 int do_flush = 0;
470 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
471 void __iomem *epio = hw_ep->regs;
472 struct musb_qh *qh = hw_ep->in_qh;
473 int pipe = urb->pipe;
474 void *buffer = urb->transfer_buffer;
475
476 /* musb_ep_select(mbase, epnum); */
477 rx_count = musb_readw(epio, MUSB_RXCOUNT);
478 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
479 urb->transfer_buffer, qh->offset,
480 urb->transfer_buffer_length);
481
482 /* unload FIFO */
483 if (usb_pipeisoc(pipe)) {
484 int status = 0;
485 struct usb_iso_packet_descriptor *d;
486
487 if (iso_err) {
488 status = -EILSEQ;
489 urb->error_count++;
490 }
491
492 d = urb->iso_frame_desc + qh->iso_idx;
493 buf = buffer + d->offset;
494 length = d->length;
495 if (rx_count > length) {
496 if (status == 0) {
497 status = -EOVERFLOW;
498 urb->error_count++;
499 }
500 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
501 do_flush = 1;
502 } else
503 length = rx_count;
504 urb->actual_length += length;
505 d->actual_length = length;
506
507 d->status = status;
508
509 /* see if we are done */
510 done = (++qh->iso_idx >= urb->number_of_packets);
511 } else {
512 /* non-isoch */
513 buf = buffer + qh->offset;
514 length = urb->transfer_buffer_length - qh->offset;
515 if (rx_count > length) {
516 if (urb->status == -EINPROGRESS)
517 urb->status = -EOVERFLOW;
518 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
519 do_flush = 1;
520 } else
521 length = rx_count;
522 urb->actual_length += length;
523 qh->offset += length;
524
525 /* see if we are done */
526 done = (urb->actual_length == urb->transfer_buffer_length)
527 || (rx_count < qh->maxpacket)
528 || (urb->status != -EINPROGRESS);
529 if (done
530 && (urb->status == -EINPROGRESS)
531 && (urb->transfer_flags & URB_SHORT_NOT_OK)
532 && (urb->actual_length
533 < urb->transfer_buffer_length))
534 urb->status = -EREMOTEIO;
535 }
536
537 musb_read_fifo(hw_ep, length, buf);
538
539 csr = musb_readw(epio, MUSB_RXCSR);
540 csr |= MUSB_RXCSR_H_WZC_BITS;
541 if (unlikely(do_flush))
542 musb_h_flush_rxfifo(hw_ep, csr);
543 else {
544 /* REVISIT this assumes AUTOCLEAR is never set */
545 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
546 if (!done)
547 csr |= MUSB_RXCSR_H_REQPKT;
548 musb_writew(epio, MUSB_RXCSR, csr);
549 }
550
551 return done;
552}
553
554/* we don't always need to reinit a given side of an endpoint...
555 * when we do, use tx/rx reinit routine and then construct a new CSR
556 * to address data toggle, NYET, and DMA or PIO.
557 *
558 * it's possible that driver bugs (especially for DMA) or aborting a
559 * transfer might have left the endpoint busier than it should be.
560 * the busy/not-empty tests are basically paranoia.
561 */
562static void
563musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
564{
565 u16 csr;
566
567 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
568 * That always uses tx_reinit since ep0 repurposes TX register
569 * offsets; the initial SETUP packet is also a kind of OUT.
570 */
571
572 /* if programmed for Tx, put it in RX mode */
573 if (ep->is_shared_fifo) {
574 csr = musb_readw(ep->regs, MUSB_TXCSR);
575 if (csr & MUSB_TXCSR_MODE) {
576 musb_h_tx_flush_fifo(ep);
577 musb_writew(ep->regs, MUSB_TXCSR,
578 MUSB_TXCSR_FRCDATATOG);
579 }
580 /* clear mode (and everything else) to enable Rx */
581 musb_writew(ep->regs, MUSB_TXCSR, 0);
582
583 /* scrub all previous state, clearing toggle */
584 } else {
585 csr = musb_readw(ep->regs, MUSB_RXCSR);
586 if (csr & MUSB_RXCSR_RXPKTRDY)
587 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
588 musb_readw(ep->regs, MUSB_RXCOUNT));
589
590 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
591 }
592
593 /* target addr and (for multipoint) hub addr/port */
594 if (musb->is_multipoint) {
595 musb_writeb(ep->target_regs, MUSB_RXFUNCADDR,
596 qh->addr_reg);
597 musb_writeb(ep->target_regs, MUSB_RXHUBADDR,
598 qh->h_addr_reg);
599 musb_writeb(ep->target_regs, MUSB_RXHUBPORT,
600 qh->h_port_reg);
601 } else
602 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
603
604 /* protocol/endpoint, interval/NAKlimit, i/o size */
605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
607 /* NOTE: bulk combining rewrites high bits of maxpacket */
608 musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket);
609
610 ep->rx_reinit = 0;
611}
612
613
614/*
615 * Program an HDRC endpoint as per the given URB
616 * Context: irqs blocked, controller lock held
617 */
618static void musb_ep_program(struct musb *musb, u8 epnum,
619 struct urb *urb, unsigned int is_out,
620 u8 *buf, u32 len)
621{
622 struct dma_controller *dma_controller;
623 struct dma_channel *dma_channel;
624 u8 dma_ok;
625 void __iomem *mbase = musb->mregs;
626 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
627 void __iomem *epio = hw_ep->regs;
628 struct musb_qh *qh;
629 u16 packet_sz;
630
631 if (!is_out || hw_ep->is_shared_fifo)
632 qh = hw_ep->in_qh;
633 else
634 qh = hw_ep->out_qh;
635
636 packet_sz = qh->maxpacket;
637
638 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
639 "h_addr%02x h_port%02x bytes %d\n",
640 is_out ? "-->" : "<--",
641 epnum, urb, urb->dev->speed,
642 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
643 qh->h_addr_reg, qh->h_port_reg,
644 len);
645
646 musb_ep_select(mbase, epnum);
647
648 /* candidate for DMA? */
649 dma_controller = musb->dma_controller;
650 if (is_dma_capable() && epnum && dma_controller) {
651 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
652 if (!dma_channel) {
653 dma_channel = dma_controller->channel_alloc(
654 dma_controller, hw_ep, is_out);
655 if (is_out)
656 hw_ep->tx_channel = dma_channel;
657 else
658 hw_ep->rx_channel = dma_channel;
659 }
660 } else
661 dma_channel = NULL;
662
663 /* make sure we clear DMAEnab, autoSet bits from previous run */
664
665 /* OUT/transmit/EP0 or IN/receive? */
666 if (is_out) {
667 u16 csr;
668 u16 int_txe;
669 u16 load_count;
670
671 csr = musb_readw(epio, MUSB_TXCSR);
672
673 /* disable interrupt in case we flush */
674 int_txe = musb_readw(mbase, MUSB_INTRTXE);
675 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
676
677 /* general endpoint setup */
678 if (epnum) {
679 /* ASSERT: TXCSR_DMAENAB was already cleared */
680
681 /* flush all old state, set default */
682 musb_h_tx_flush_fifo(hw_ep);
683 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
684 | MUSB_TXCSR_DMAMODE
685 | MUSB_TXCSR_FRCDATATOG
686 | MUSB_TXCSR_H_RXSTALL
687 | MUSB_TXCSR_H_ERROR
688 | MUSB_TXCSR_TXPKTRDY
689 );
690 csr |= MUSB_TXCSR_MODE;
691
692 if (usb_gettoggle(urb->dev,
693 qh->epnum, 1))
694 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
695 | MUSB_TXCSR_H_DATATOGGLE;
696 else
697 csr |= MUSB_TXCSR_CLRDATATOG;
698
699 /* twice in case of double packet buffering */
700 musb_writew(epio, MUSB_TXCSR, csr);
701 /* REVISIT may need to clear FLUSHFIFO ... */
702 musb_writew(epio, MUSB_TXCSR, csr);
703 csr = musb_readw(epio, MUSB_TXCSR);
704 } else {
705 /* endpoint 0: just flush */
706 musb_writew(epio, MUSB_CSR0,
707 csr | MUSB_CSR0_FLUSHFIFO);
708 musb_writew(epio, MUSB_CSR0,
709 csr | MUSB_CSR0_FLUSHFIFO);
710 }
711
712 /* target addr and (for multipoint) hub addr/port */
713 if (musb->is_multipoint) {
714 musb_writeb(mbase,
715 MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
716 qh->addr_reg);
717 musb_writeb(mbase,
718 MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
719 qh->h_addr_reg);
720 musb_writeb(mbase,
721 MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
722 qh->h_port_reg);
723/* FIXME if !epnum, do the same for RX ... */
724 } else
725 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
726
727 /* protocol/endpoint/interval/NAKlimit */
728 if (epnum) {
729 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
730 if (can_bulk_split(musb, qh->type))
731 musb_writew(epio, MUSB_TXMAXP,
732 packet_sz
733 | ((hw_ep->max_packet_sz_tx /
734 packet_sz) - 1) << 11);
735 else
736 musb_writew(epio, MUSB_TXMAXP,
737 packet_sz);
738 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
739 } else {
740 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
741 if (musb->is_multipoint)
742 musb_writeb(epio, MUSB_TYPE0,
743 qh->type_reg);
744 }
745
746 if (can_bulk_split(musb, qh->type))
747 load_count = min((u32) hw_ep->max_packet_sz_tx,
748 len);
749 else
750 load_count = min((u32) packet_sz, len);
751
752#ifdef CONFIG_USB_INVENTRA_DMA
753 if (dma_channel) {
754
755 /* clear previous state */
756 csr = musb_readw(epio, MUSB_TXCSR);
757 csr &= ~(MUSB_TXCSR_AUTOSET
758 | MUSB_TXCSR_DMAMODE
759 | MUSB_TXCSR_DMAENAB);
760 csr |= MUSB_TXCSR_MODE;
761 musb_writew(epio, MUSB_TXCSR,
762 csr | MUSB_TXCSR_MODE);
763
764 qh->segsize = min(len, dma_channel->max_len);
765
766 if (qh->segsize <= packet_sz)
767 dma_channel->desired_mode = 0;
768 else
769 dma_channel->desired_mode = 1;
770
771
772 if (dma_channel->desired_mode == 0) {
773 csr &= ~(MUSB_TXCSR_AUTOSET
774 | MUSB_TXCSR_DMAMODE);
775 csr |= (MUSB_TXCSR_DMAENAB);
776 /* against programming guide */
777 } else
778 csr |= (MUSB_TXCSR_AUTOSET
779 | MUSB_TXCSR_DMAENAB
780 | MUSB_TXCSR_DMAMODE);
781
782 musb_writew(epio, MUSB_TXCSR, csr);
783
784 dma_ok = dma_controller->channel_program(
785 dma_channel, packet_sz,
786 dma_channel->desired_mode,
787 urb->transfer_dma,
788 qh->segsize);
789 if (dma_ok) {
790 load_count = 0;
791 } else {
792 dma_controller->channel_release(dma_channel);
793 if (is_out)
794 hw_ep->tx_channel = NULL;
795 else
796 hw_ep->rx_channel = NULL;
797 dma_channel = NULL;
798 }
799 }
800#endif
801
802 /* candidate for DMA */
803 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
804
805 /* program endpoint CSRs first, then setup DMA.
806 * assume CPPI setup succeeds.
807 * defer enabling dma.
808 */
809 csr = musb_readw(epio, MUSB_TXCSR);
810 csr &= ~(MUSB_TXCSR_AUTOSET
811 | MUSB_TXCSR_DMAMODE
812 | MUSB_TXCSR_DMAENAB);
813 csr |= MUSB_TXCSR_MODE;
814 musb_writew(epio, MUSB_TXCSR,
815 csr | MUSB_TXCSR_MODE);
816
817 dma_channel->actual_len = 0L;
818 qh->segsize = len;
819
820 /* TX uses "rndis" mode automatically, but needs help
821 * to identify the zero-length-final-packet case.
822 */
823 dma_ok = dma_controller->channel_program(
824 dma_channel, packet_sz,
825 (urb->transfer_flags
826 & URB_ZERO_PACKET)
827 == URB_ZERO_PACKET,
828 urb->transfer_dma,
829 qh->segsize);
830 if (dma_ok) {
831 load_count = 0;
832 } else {
833 dma_controller->channel_release(dma_channel);
834 hw_ep->tx_channel = NULL;
835 dma_channel = NULL;
836
837 /* REVISIT there's an error path here that
838 * needs handling: can't do dma, but
839 * there's no pio buffer address...
840 */
841 }
842 }
843
844 if (load_count) {
845 /* ASSERT: TXCSR_DMAENAB was already cleared */
846
847 /* PIO to load FIFO */
848 qh->segsize = load_count;
849 musb_write_fifo(hw_ep, load_count, buf);
850 csr = musb_readw(epio, MUSB_TXCSR);
851 csr &= ~(MUSB_TXCSR_DMAENAB
852 | MUSB_TXCSR_DMAMODE
853 | MUSB_TXCSR_AUTOSET);
854 /* write CSR */
855 csr |= MUSB_TXCSR_MODE;
856
857 if (epnum)
858 musb_writew(epio, MUSB_TXCSR, csr);
859 }
860
861 /* re-enable interrupt */
862 musb_writew(mbase, MUSB_INTRTXE, int_txe);
863
864 /* IN/receive */
865 } else {
866 u16 csr;
867
868 if (hw_ep->rx_reinit) {
869 musb_rx_reinit(musb, qh, hw_ep);
870
871 /* init new state: toggle and NYET, maybe DMA later */
872 if (usb_gettoggle(urb->dev, qh->epnum, 0))
873 csr = MUSB_RXCSR_H_WR_DATATOGGLE
874 | MUSB_RXCSR_H_DATATOGGLE;
875 else
876 csr = 0;
877 if (qh->type == USB_ENDPOINT_XFER_INT)
878 csr |= MUSB_RXCSR_DISNYET;
879
880 } else {
881 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
882
883 if (csr & (MUSB_RXCSR_RXPKTRDY
884 | MUSB_RXCSR_DMAENAB
885 | MUSB_RXCSR_H_REQPKT))
886 ERR("broken !rx_reinit, ep%d csr %04x\n",
887 hw_ep->epnum, csr);
888
889 /* scrub any stale state, leaving toggle alone */
890 csr &= MUSB_RXCSR_DISNYET;
891 }
892
893 /* kick things off */
894
895 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
896 /* candidate for DMA */
897 if (dma_channel) {
898 dma_channel->actual_len = 0L;
899 qh->segsize = len;
900
901 /* AUTOREQ is in a DMA register */
902 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
903 csr = musb_readw(hw_ep->regs,
904 MUSB_RXCSR);
905
906 /* unless caller treats short rx transfers as
907 * errors, we dare not queue multiple transfers.
908 */
909 dma_ok = dma_controller->channel_program(
910 dma_channel, packet_sz,
911 !(urb->transfer_flags
912 & URB_SHORT_NOT_OK),
913 urb->transfer_dma,
914 qh->segsize);
915 if (!dma_ok) {
916 dma_controller->channel_release(
917 dma_channel);
918 hw_ep->rx_channel = NULL;
919 dma_channel = NULL;
920 } else
921 csr |= MUSB_RXCSR_DMAENAB;
922 }
923 }
924
925 csr |= MUSB_RXCSR_H_REQPKT;
926 DBG(7, "RXCSR%d := %04x\n", epnum, csr);
927 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
928 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
929 }
930}
931
932
933/*
934 * Service the default endpoint (ep0) as host.
935 * Return true until it's time to start the status stage.
936 */
937static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
938{
939 bool more = false;
940 u8 *fifo_dest = NULL;
941 u16 fifo_count = 0;
942 struct musb_hw_ep *hw_ep = musb->control_ep;
943 struct musb_qh *qh = hw_ep->in_qh;
944 struct usb_ctrlrequest *request;
945
946 switch (musb->ep0_stage) {
947 case MUSB_EP0_IN:
948 fifo_dest = urb->transfer_buffer + urb->actual_length;
949 fifo_count = min(len, ((u16) (urb->transfer_buffer_length
950 - urb->actual_length)));
951 if (fifo_count < len)
952 urb->status = -EOVERFLOW;
953
954 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
955
956 urb->actual_length += fifo_count;
957 if (len < qh->maxpacket) {
958 /* always terminate on short read; it's
959 * rarely reported as an error.
960 */
961 } else if (urb->actual_length <
962 urb->transfer_buffer_length)
963 more = true;
964 break;
965 case MUSB_EP0_START:
966 request = (struct usb_ctrlrequest *) urb->setup_packet;
967
968 if (!request->wLength) {
969 DBG(4, "start no-DATA\n");
970 break;
971 } else if (request->bRequestType & USB_DIR_IN) {
972 DBG(4, "start IN-DATA\n");
973 musb->ep0_stage = MUSB_EP0_IN;
974 more = true;
975 break;
976 } else {
977 DBG(4, "start OUT-DATA\n");
978 musb->ep0_stage = MUSB_EP0_OUT;
979 more = true;
980 }
981 /* FALLTHROUGH */
982 case MUSB_EP0_OUT:
983 fifo_count = min(qh->maxpacket, ((u16)
984 (urb->transfer_buffer_length
985 - urb->actual_length)));
986
987 if (fifo_count) {
988 fifo_dest = (u8 *) (urb->transfer_buffer
989 + urb->actual_length);
990 DBG(3, "Sending %d bytes to %p\n",
991 fifo_count, fifo_dest);
992 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
993
994 urb->actual_length += fifo_count;
995 more = true;
996 }
997 break;
998 default:
999 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1000 break;
1001 }
1002
1003 return more;
1004}
1005
1006/*
1007 * Handle default endpoint interrupt as host. Only called in IRQ time
1008 * from the LinuxIsr() interrupt service routine.
1009 *
1010 * called with controller irqlocked
1011 */
1012irqreturn_t musb_h_ep0_irq(struct musb *musb)
1013{
1014 struct urb *urb;
1015 u16 csr, len;
1016 int status = 0;
1017 void __iomem *mbase = musb->mregs;
1018 struct musb_hw_ep *hw_ep = musb->control_ep;
1019 void __iomem *epio = hw_ep->regs;
1020 struct musb_qh *qh = hw_ep->in_qh;
1021 bool complete = false;
1022 irqreturn_t retval = IRQ_NONE;
1023
1024 /* ep0 only has one queue, "in" */
1025 urb = next_urb(qh);
1026
1027 musb_ep_select(mbase, 0);
1028 csr = musb_readw(epio, MUSB_CSR0);
1029 len = (csr & MUSB_CSR0_RXPKTRDY)
1030 ? musb_readb(epio, MUSB_COUNT0)
1031 : 0;
1032
1033 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1034 csr, qh, len, urb, musb->ep0_stage);
1035
1036 /* if we just did status stage, we are done */
1037 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1038 retval = IRQ_HANDLED;
1039 complete = true;
1040 }
1041
1042 /* prepare status */
1043 if (csr & MUSB_CSR0_H_RXSTALL) {
1044 DBG(6, "STALLING ENDPOINT\n");
1045 status = -EPIPE;
1046
1047 } else if (csr & MUSB_CSR0_H_ERROR) {
1048 DBG(2, "no response, csr0 %04x\n", csr);
1049 status = -EPROTO;
1050
1051 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1052 DBG(2, "control NAK timeout\n");
1053
1054 /* NOTE: this code path would be a good place to PAUSE a
1055 * control transfer, if another one is queued, so that
1056 * ep0 is more likely to stay busy.
1057 *
1058 * if (qh->ring.next != &musb->control), then
1059 * we have a candidate... NAKing is *NOT* an error
1060 */
1061 musb_writew(epio, MUSB_CSR0, 0);
1062 retval = IRQ_HANDLED;
1063 }
1064
1065 if (status) {
1066 DBG(6, "aborting\n");
1067 retval = IRQ_HANDLED;
1068 if (urb)
1069 urb->status = status;
1070 complete = true;
1071
1072 /* use the proper sequence to abort the transfer */
1073 if (csr & MUSB_CSR0_H_REQPKT) {
1074 csr &= ~MUSB_CSR0_H_REQPKT;
1075 musb_writew(epio, MUSB_CSR0, csr);
1076 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1077 musb_writew(epio, MUSB_CSR0, csr);
1078 } else {
1079 csr |= MUSB_CSR0_FLUSHFIFO;
1080 musb_writew(epio, MUSB_CSR0, csr);
1081 musb_writew(epio, MUSB_CSR0, csr);
1082 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1083 musb_writew(epio, MUSB_CSR0, csr);
1084 }
1085
1086 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1087
1088 /* clear it */
1089 musb_writew(epio, MUSB_CSR0, 0);
1090 }
1091
1092 if (unlikely(!urb)) {
1093 /* stop endpoint since we have no place for its data, this
1094 * SHOULD NEVER HAPPEN! */
1095 ERR("no URB for end 0\n");
1096
1097 musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO);
1098 musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO);
1099 musb_writew(epio, MUSB_CSR0, 0);
1100
1101 goto done;
1102 }
1103
1104 if (!complete) {
1105 /* call common logic and prepare response */
1106 if (musb_h_ep0_continue(musb, len, urb)) {
1107 /* more packets required */
1108 csr = (MUSB_EP0_IN == musb->ep0_stage)
1109 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1110 } else {
1111 /* data transfer complete; perform status phase */
1112 if (usb_pipeout(urb->pipe)
1113 || !urb->transfer_buffer_length)
1114 csr = MUSB_CSR0_H_STATUSPKT
1115 | MUSB_CSR0_H_REQPKT;
1116 else
1117 csr = MUSB_CSR0_H_STATUSPKT
1118 | MUSB_CSR0_TXPKTRDY;
1119
1120 /* flag status stage */
1121 musb->ep0_stage = MUSB_EP0_STATUS;
1122
1123 DBG(5, "ep0 STATUS, csr %04x\n", csr);
1124
1125 }
1126 musb_writew(epio, MUSB_CSR0, csr);
1127 retval = IRQ_HANDLED;
1128 } else
1129 musb->ep0_stage = MUSB_EP0_IDLE;
1130
1131 /* call completion handler if done */
1132 if (complete)
1133 musb_advance_schedule(musb, urb, hw_ep, 1);
1134done:
1135 return retval;
1136}
1137
1138
1139#ifdef CONFIG_USB_INVENTRA_DMA
1140
1141/* Host side TX (OUT) using Mentor DMA works as follows:
1142 submit_urb ->
1143 - if queue was empty, Program Endpoint
1144 - ... which starts DMA to fifo in mode 1 or 0
1145
1146 DMA Isr (transfer complete) -> TxAvail()
1147 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1148 only in musb_cleanup_urb)
1149 - TxPktRdy has to be set in mode 0 or for
1150 short packets in mode 1.
1151*/
1152
1153#endif
1154
1155/* Service a Tx-Available or dma completion irq for the endpoint */
1156void musb_host_tx(struct musb *musb, u8 epnum)
1157{
1158 int pipe;
1159 bool done = false;
1160 u16 tx_csr;
1161 size_t wLength = 0;
1162 u8 *buf = NULL;
1163 struct urb *urb;
1164 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1165 void __iomem *epio = hw_ep->regs;
1166 struct musb_qh *qh = hw_ep->out_qh;
1167 u32 status = 0;
1168 void __iomem *mbase = musb->mregs;
1169 struct dma_channel *dma;
1170
1171 urb = next_urb(qh);
1172
1173 musb_ep_select(mbase, epnum);
1174 tx_csr = musb_readw(epio, MUSB_TXCSR);
1175
1176 /* with CPPI, DMA sometimes triggers "extra" irqs */
1177 if (!urb) {
1178 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1179 goto finish;
1180 }
1181
1182 pipe = urb->pipe;
1183 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1184 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1185 dma ? ", dma" : "");
1186
1187 /* check for errors */
1188 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1189 /* dma was disabled, fifo flushed */
1190 DBG(3, "TX end %d stall\n", epnum);
1191
1192 /* stall; record URB status */
1193 status = -EPIPE;
1194
1195 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1196 /* (NON-ISO) dma was disabled, fifo flushed */
1197 DBG(3, "TX 3strikes on ep=%d\n", epnum);
1198
1199 status = -ETIMEDOUT;
1200
1201 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1202 DBG(6, "TX end=%d device not responding\n", epnum);
1203
1204 /* NOTE: this code path would be a good place to PAUSE a
1205 * transfer, if there's some other (nonperiodic) tx urb
1206 * that could use this fifo. (dma complicates it...)
1207 *
1208 * if (bulk && qh->ring.next != &musb->out_bulk), then
1209 * we have a candidate... NAKing is *NOT* an error
1210 */
1211 musb_ep_select(mbase, epnum);
1212 musb_writew(epio, MUSB_TXCSR,
1213 MUSB_TXCSR_H_WZC_BITS
1214 | MUSB_TXCSR_TXPKTRDY);
1215 goto finish;
1216 }
1217
1218 if (status) {
1219 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1220 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1221 (void) musb->dma_controller->channel_abort(dma);
1222 }
1223
1224 /* do the proper sequence to abort the transfer in the
1225 * usb core; the dma engine should already be stopped.
1226 */
1227 musb_h_tx_flush_fifo(hw_ep);
1228 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1229 | MUSB_TXCSR_DMAENAB
1230 | MUSB_TXCSR_H_ERROR
1231 | MUSB_TXCSR_H_RXSTALL
1232 | MUSB_TXCSR_H_NAKTIMEOUT
1233 );
1234
1235 musb_ep_select(mbase, epnum);
1236 musb_writew(epio, MUSB_TXCSR, tx_csr);
1237 /* REVISIT may need to clear FLUSHFIFO ... */
1238 musb_writew(epio, MUSB_TXCSR, tx_csr);
1239 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1240
1241 done = true;
1242 }
1243
1244 /* second cppi case */
1245 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1246 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1247 goto finish;
1248
1249 }
1250
1251 /* REVISIT this looks wrong... */
1252 if (!status || dma || usb_pipeisoc(pipe)) {
1253 if (dma)
1254 wLength = dma->actual_len;
1255 else
1256 wLength = qh->segsize;
1257 qh->offset += wLength;
1258
1259 if (usb_pipeisoc(pipe)) {
1260 struct usb_iso_packet_descriptor *d;
1261
1262 d = urb->iso_frame_desc + qh->iso_idx;
1263 d->actual_length = qh->segsize;
1264 if (++qh->iso_idx >= urb->number_of_packets) {
1265 done = true;
1266 } else {
1267 d++;
1268 buf = urb->transfer_buffer + d->offset;
1269 wLength = d->length;
1270 }
1271 } else if (dma) {
1272 done = true;
1273 } else {
1274 /* see if we need to send more data, or ZLP */
1275 if (qh->segsize < qh->maxpacket)
1276 done = true;
1277 else if (qh->offset == urb->transfer_buffer_length
1278 && !(urb->transfer_flags
1279 & URB_ZERO_PACKET))
1280 done = true;
1281 if (!done) {
1282 buf = urb->transfer_buffer
1283 + qh->offset;
1284 wLength = urb->transfer_buffer_length
1285 - qh->offset;
1286 }
1287 }
1288 }
1289
1290 /* urb->status != -EINPROGRESS means request has been faulted,
1291 * so we must abort this transfer after cleanup
1292 */
1293 if (urb->status != -EINPROGRESS) {
1294 done = true;
1295 if (status == 0)
1296 status = urb->status;
1297 }
1298
1299 if (done) {
1300 /* set status */
1301 urb->status = status;
1302 urb->actual_length = qh->offset;
1303 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1304
1305 } else if (!(tx_csr & MUSB_TXCSR_DMAENAB)) {
1306 /* WARN_ON(!buf); */
1307
1308 /* REVISIT: some docs say that when hw_ep->tx_double_buffered,
1309 * (and presumably, fifo is not half-full) we should write TWO
1310 * packets before updating TXCSR ... other docs disagree ...
1311 */
1312 /* PIO: start next packet in this URB */
1313 wLength = min(qh->maxpacket, (u16) wLength);
1314 musb_write_fifo(hw_ep, wLength, buf);
1315 qh->segsize = wLength;
1316
1317 musb_ep_select(mbase, epnum);
1318 musb_writew(epio, MUSB_TXCSR,
1319 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1320 } else
1321 DBG(1, "not complete, but dma enabled?\n");
1322
1323finish:
1324 return;
1325}
1326
1327
1328#ifdef CONFIG_USB_INVENTRA_DMA
1329
1330/* Host side RX (IN) using Mentor DMA works as follows:
1331 submit_urb ->
1332 - if queue was empty, ProgramEndpoint
1333 - first IN token is sent out (by setting ReqPkt)
1334 LinuxIsr -> RxReady()
1335 /\ => first packet is received
1336 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1337 | -> DMA Isr (transfer complete) -> RxReady()
1338 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1339 | - if urb not complete, send next IN token (ReqPkt)
1340 | | else complete urb.
1341 | |
1342 ---------------------------
1343 *
1344 * Nuances of mode 1:
1345 * For short packets, no ack (+RxPktRdy) is sent automatically
1346 * (even if AutoClear is ON)
1347 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1348 * automatically => major problem, as collecting the next packet becomes
1349 * difficult. Hence mode 1 is not used.
1350 *
1351 * REVISIT
1352 * All we care about at this driver level is that
1353 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1354 * (b) termination conditions are: short RX, or buffer full;
1355 * (c) fault modes include
1356 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1357 * (and that endpoint's dma queue stops immediately)
1358 * - overflow (full, PLUS more bytes in the terminal packet)
1359 *
1360 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1361 * thus be a great candidate for using mode 1 ... for all but the
1362 * last packet of one URB's transfer.
1363 */
1364
1365#endif
1366
1367/*
1368 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1369 * and high-bandwidth IN transfer cases.
1370 */
1371void musb_host_rx(struct musb *musb, u8 epnum)
1372{
1373 struct urb *urb;
1374 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1375 void __iomem *epio = hw_ep->regs;
1376 struct musb_qh *qh = hw_ep->in_qh;
1377 size_t xfer_len;
1378 void __iomem *mbase = musb->mregs;
1379 int pipe;
1380 u16 rx_csr, val;
1381 bool iso_err = false;
1382 bool done = false;
1383 u32 status;
1384 struct dma_channel *dma;
1385
1386 musb_ep_select(mbase, epnum);
1387
1388 urb = next_urb(qh);
1389 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1390 status = 0;
1391 xfer_len = 0;
1392
1393 rx_csr = musb_readw(epio, MUSB_RXCSR);
1394 val = rx_csr;
1395
1396 if (unlikely(!urb)) {
1397 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1398 * usbtest #11 (unlinks) triggers it regularly, sometimes
1399 * with fifo full. (Only with DMA??)
1400 */
1401 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1402 musb_readw(epio, MUSB_RXCOUNT));
1403 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1404 return;
1405 }
1406
1407 pipe = urb->pipe;
1408
1409 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1410 epnum, rx_csr, urb->actual_length,
1411 dma ? dma->actual_len : 0);
1412
1413 /* check for errors, concurrent stall & unlink is not really
1414 * handled yet! */
1415 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1416 DBG(3, "RX end %d STALL\n", epnum);
1417
1418 /* stall; record URB status */
1419 status = -EPIPE;
1420
1421 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1422 DBG(3, "end %d RX proto error\n", epnum);
1423
1424 status = -EPROTO;
1425 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1426
1427 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1428
1429 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1430 /* NOTE this code path would be a good place to PAUSE a
1431 * transfer, if there's some other (nonperiodic) rx urb
1432 * that could use this fifo. (dma complicates it...)
1433 *
1434 * if (bulk && qh->ring.next != &musb->in_bulk), then
1435 * we have a candidate... NAKing is *NOT* an error
1436 */
1437 DBG(6, "RX end %d NAK timeout\n", epnum);
1438 musb_ep_select(mbase, epnum);
1439 musb_writew(epio, MUSB_RXCSR,
1440 MUSB_RXCSR_H_WZC_BITS
1441 | MUSB_RXCSR_H_REQPKT);
1442
1443 goto finish;
1444 } else {
1445 DBG(4, "RX end %d ISO data error\n", epnum);
1446 /* packet error reported later */
1447 iso_err = true;
1448 }
1449 }
1450
1451 /* faults abort the transfer */
1452 if (status) {
1453 /* clean up dma and collect transfer count */
1454 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1455 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1456 (void) musb->dma_controller->channel_abort(dma);
1457 xfer_len = dma->actual_len;
1458 }
1459 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1460 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1461 done = true;
1462 goto finish;
1463 }
1464
1465 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1466 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1467 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1468 goto finish;
1469 }
1470
1471 /* thorough shutdown for now ... given more precise fault handling
1472 * and better queueing support, we might keep a DMA pipeline going
1473 * while processing this irq for earlier completions.
1474 */
1475
1476 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1477
1478#ifndef CONFIG_USB_INVENTRA_DMA
1479 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1480 /* REVISIT this happened for a while on some short reads...
1481 * the cleanup still needs investigation... looks bad...
1482 * and also duplicates dma cleanup code above ... plus,
1483 * shouldn't this be the "half full" double buffer case?
1484 */
1485 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1486 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1487 (void) musb->dma_controller->channel_abort(dma);
1488 xfer_len = dma->actual_len;
1489 done = true;
1490 }
1491
1492 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1493 xfer_len, dma ? ", dma" : "");
1494 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1495
1496 musb_ep_select(mbase, epnum);
1497 musb_writew(epio, MUSB_RXCSR,
1498 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1499 }
1500#endif
1501 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1502 xfer_len = dma->actual_len;
1503
1504 val &= ~(MUSB_RXCSR_DMAENAB
1505 | MUSB_RXCSR_H_AUTOREQ
1506 | MUSB_RXCSR_AUTOCLEAR
1507 | MUSB_RXCSR_RXPKTRDY);
1508 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1509
1510#ifdef CONFIG_USB_INVENTRA_DMA
1511 /* done if urb buffer is full or short packet is recd */
1512 done = (urb->actual_length + xfer_len >=
1513 urb->transfer_buffer_length
1514 || dma->actual_len < qh->maxpacket);
1515
1516 /* send IN token for next packet, without AUTOREQ */
1517 if (!done) {
1518 val |= MUSB_RXCSR_H_REQPKT;
1519 musb_writew(epio, MUSB_RXCSR,
1520 MUSB_RXCSR_H_WZC_BITS | val);
1521 }
1522
1523 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1524 done ? "off" : "reset",
1525 musb_readw(epio, MUSB_RXCSR),
1526 musb_readw(epio, MUSB_RXCOUNT));
1527#else
1528 done = true;
1529#endif
1530 } else if (urb->status == -EINPROGRESS) {
1531 /* if no errors, be sure a packet is ready for unloading */
1532 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1533 status = -EPROTO;
1534 ERR("Rx interrupt with no errors or packet!\n");
1535
1536 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1537
1538/* SCRUB (RX) */
1539 /* do the proper sequence to abort the transfer */
1540 musb_ep_select(mbase, epnum);
1541 val &= ~MUSB_RXCSR_H_REQPKT;
1542 musb_writew(epio, MUSB_RXCSR, val);
1543 goto finish;
1544 }
1545
1546 /* we are expecting IN packets */
1547#ifdef CONFIG_USB_INVENTRA_DMA
1548 if (dma) {
1549 struct dma_controller *c;
1550 u16 rx_count;
1551 int ret;
1552
1553 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1554
1555 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1556 epnum, rx_count,
1557 urb->transfer_dma
1558 + urb->actual_length,
1559 qh->offset,
1560 urb->transfer_buffer_length);
1561
1562 c = musb->dma_controller;
1563
1564 dma->desired_mode = 0;
1565#ifdef USE_MODE1
1566 /* because of the issue below, mode 1 will
1567 * only rarely behave with correct semantics.
1568 */
1569 if ((urb->transfer_flags &
1570 URB_SHORT_NOT_OK)
1571 && (urb->transfer_buffer_length -
1572 urb->actual_length)
1573 > qh->maxpacket)
1574 dma->desired_mode = 1;
1575#endif
1576
1577/* Disadvantage of using mode 1:
1578 * It's basically usable only for mass storage class; essentially all
1579 * other protocols also terminate transfers on short packets.
1580 *
1581 * Details:
1582 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1583 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1584 * to use the extra IN token to grab the last packet using mode 0, then
1585 * the problem is that you cannot be sure when the device will send the
1586 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1587 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1588 * transfer, while sometimes it is recd just a little late so that if you
1589 * try to configure for mode 0 soon after the mode 1 transfer is
1590 * completed, you will find rxcount 0. Okay, so you might think why not
1591 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1592 */
1593
1594 val = musb_readw(epio, MUSB_RXCSR);
1595 val &= ~MUSB_RXCSR_H_REQPKT;
1596
1597 if (dma->desired_mode == 0)
1598 val &= ~MUSB_RXCSR_H_AUTOREQ;
1599 else
1600 val |= MUSB_RXCSR_H_AUTOREQ;
1601 val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
1602
1603 musb_writew(epio, MUSB_RXCSR,
1604 MUSB_RXCSR_H_WZC_BITS | val);
1605
1606 /* REVISIT if when actual_length != 0,
1607 * transfer_buffer_length needs to be
1608 * adjusted first...
1609 */
1610 ret = c->channel_program(
1611 dma, qh->maxpacket,
1612 dma->desired_mode,
1613 urb->transfer_dma
1614 + urb->actual_length,
1615 (dma->desired_mode == 0)
1616 ? rx_count
1617 : urb->transfer_buffer_length);
1618
1619 if (!ret) {
1620 c->channel_release(dma);
1621 hw_ep->rx_channel = NULL;
1622 dma = NULL;
1623 /* REVISIT reset CSR */
1624 }
1625 }
1626#endif /* Mentor DMA */
1627
1628 if (!dma) {
1629 done = musb_host_packet_rx(musb, urb,
1630 epnum, iso_err);
1631 DBG(6, "read %spacket\n", done ? "last " : "");
1632 }
1633 }
1634
1635 if (dma && usb_pipeisoc(pipe)) {
1636 struct usb_iso_packet_descriptor *d;
1637 int iso_stat = status;
1638
1639 d = urb->iso_frame_desc + qh->iso_idx;
1640 d->actual_length += xfer_len;
1641 if (iso_err) {
1642 iso_stat = -EILSEQ;
1643 urb->error_count++;
1644 }
1645 d->status = iso_stat;
1646 }
1647
1648finish:
1649 urb->actual_length += xfer_len;
1650 qh->offset += xfer_len;
1651 if (done) {
1652 if (urb->status == -EINPROGRESS)
1653 urb->status = status;
1654 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1655 }
1656}
1657
1658/* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1659 * the software schedule associates multiple such nodes with a given
1660 * host side hardware endpoint + direction; scheduling may activate
1661 * that hardware endpoint.
1662 */
1663static int musb_schedule(
1664 struct musb *musb,
1665 struct musb_qh *qh,
1666 int is_in)
1667{
1668 int idle;
1669 int best_diff;
1670 int best_end, epnum;
1671 struct musb_hw_ep *hw_ep = NULL;
1672 struct list_head *head = NULL;
1673
1674 /* use fixed hardware for control and bulk */
1675 switch (qh->type) {
1676 case USB_ENDPOINT_XFER_CONTROL:
1677 head = &musb->control;
1678 hw_ep = musb->control_ep;
1679 break;
1680 case USB_ENDPOINT_XFER_BULK:
1681 hw_ep = musb->bulk_ep;
1682 if (is_in)
1683 head = &musb->in_bulk;
1684 else
1685 head = &musb->out_bulk;
1686 break;
1687 }
1688 if (head) {
1689 idle = list_empty(head);
1690 list_add_tail(&qh->ring, head);
1691 goto success;
1692 }
1693
1694 /* else, periodic transfers get muxed to other endpoints */
1695
1696 /* FIXME this doesn't consider direction, so it can only
1697 * work for one half of the endpoint hardware, and assumes
1698 * the previous cases handled all non-shared endpoints...
1699 */
1700
1701 /* we know this qh hasn't been scheduled, so all we need to do
1702 * is choose which hardware endpoint to put it on ...
1703 *
1704 * REVISIT what we really want here is a regular schedule tree
1705 * like e.g. OHCI uses, but for now musb->periodic is just an
1706 * array of the _single_ logical endpoint associated with a
1707 * given physical one (identity mapping logical->physical).
1708 *
1709 * that simplistic approach makes TT scheduling a lot simpler;
1710 * there is none, and thus none of its complexity...
1711 */
1712 best_diff = 4096;
1713 best_end = -1;
1714
1715 for (epnum = 1; epnum < musb->nr_endpoints; epnum++) {
1716 int diff;
1717
1718 if (musb->periodic[epnum])
1719 continue;
1720 hw_ep = &musb->endpoints[epnum];
1721 if (hw_ep == musb->bulk_ep)
1722 continue;
1723
1724 if (is_in)
1725 diff = hw_ep->max_packet_sz_rx - qh->maxpacket;
1726 else
1727 diff = hw_ep->max_packet_sz_tx - qh->maxpacket;
1728
1729 if (diff > 0 && best_diff > diff) {
1730 best_diff = diff;
1731 best_end = epnum;
1732 }
1733 }
1734 if (best_end < 0)
1735 return -ENOSPC;
1736
1737 idle = 1;
1738 hw_ep = musb->endpoints + best_end;
1739 musb->periodic[best_end] = qh;
1740 DBG(4, "qh %p periodic slot %d\n", qh, best_end);
1741success:
1742 qh->hw_ep = hw_ep;
1743 qh->hep->hcpriv = qh;
1744 if (idle)
1745 musb_start_urb(musb, is_in, qh);
1746 return 0;
1747}
1748
1749static int musb_urb_enqueue(
1750 struct usb_hcd *hcd,
1751 struct urb *urb,
1752 gfp_t mem_flags)
1753{
1754 unsigned long flags;
1755 struct musb *musb = hcd_to_musb(hcd);
1756 struct usb_host_endpoint *hep = urb->ep;
1757 struct musb_qh *qh = hep->hcpriv;
1758 struct usb_endpoint_descriptor *epd = &hep->desc;
1759 int ret;
1760 unsigned type_reg;
1761 unsigned interval;
1762
1763 /* host role must be active */
1764 if (!is_host_active(musb) || !musb->is_active)
1765 return -ENODEV;
1766
1767 spin_lock_irqsave(&musb->lock, flags);
1768 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1769 spin_unlock_irqrestore(&musb->lock, flags);
1770 if (ret)
1771 return ret;
1772
1773 /* DMA mapping was already done, if needed, and this urb is on
1774 * hep->urb_list ... so there's little to do unless hep wasn't
1775 * yet scheduled onto a live qh.
1776 *
1777 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1778 * disabled, testing for empty qh->ring and avoiding qh setup costs
1779 * except for the first urb queued after a config change.
1780 */
1781 if (qh) {
1782 urb->hcpriv = qh;
1783 return 0;
1784 }
1785
1786 /* Allocate and initialize qh, minimizing the work done each time
1787 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1788 *
1789 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1790 * for bugs in other kernel code to break this driver...
1791 */
1792 qh = kzalloc(sizeof *qh, mem_flags);
1793 if (!qh) {
1794 usb_hcd_unlink_urb_from_ep(hcd, urb);
1795 return -ENOMEM;
1796 }
1797
1798 qh->hep = hep;
1799 qh->dev = urb->dev;
1800 INIT_LIST_HEAD(&qh->ring);
1801 qh->is_ready = 1;
1802
1803 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1804
1805 /* no high bandwidth support yet */
1806 if (qh->maxpacket & ~0x7ff) {
1807 ret = -EMSGSIZE;
1808 goto done;
1809 }
1810
1811 qh->epnum = epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
1812 qh->type = epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1813
1814 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1815 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1816
1817 /* precompute rxtype/txtype/type0 register */
1818 type_reg = (qh->type << 4) | qh->epnum;
1819 switch (urb->dev->speed) {
1820 case USB_SPEED_LOW:
1821 type_reg |= 0xc0;
1822 break;
1823 case USB_SPEED_FULL:
1824 type_reg |= 0x80;
1825 break;
1826 default:
1827 type_reg |= 0x40;
1828 }
1829 qh->type_reg = type_reg;
1830
1831 /* precompute rxinterval/txinterval register */
1832 interval = min((u8)16, epd->bInterval); /* log encoding */
1833 switch (qh->type) {
1834 case USB_ENDPOINT_XFER_INT:
1835 /* fullspeed uses linear encoding */
1836 if (USB_SPEED_FULL == urb->dev->speed) {
1837 interval = epd->bInterval;
1838 if (!interval)
1839 interval = 1;
1840 }
1841 /* FALLTHROUGH */
1842 case USB_ENDPOINT_XFER_ISOC:
1843 /* iso always uses log encoding */
1844 break;
1845 default:
1846 /* REVISIT we actually want to use NAK limits, hinting to the
1847 * transfer scheduling logic to try some other qh, e.g. try
1848 * for 2 msec first:
1849 *
1850 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
1851 *
1852 * The downside of disabling this is that transfer scheduling
1853 * gets VERY unfair for nonperiodic transfers; a misbehaving
1854 * peripheral could make that hurt. Or for reads, one that's
1855 * perfectly normal: network and other drivers keep reads
1856 * posted at all times, having one pending for a week should
1857 * be perfectly safe.
1858 *
1859 * The upside of disabling it is avoidng transfer scheduling
1860 * code to put this aside for while.
1861 */
1862 interval = 0;
1863 }
1864 qh->intv_reg = interval;
1865
1866 /* precompute addressing for external hub/tt ports */
1867 if (musb->is_multipoint) {
1868 struct usb_device *parent = urb->dev->parent;
1869
1870 if (parent != hcd->self.root_hub) {
1871 qh->h_addr_reg = (u8) parent->devnum;
1872
1873 /* set up tt info if needed */
1874 if (urb->dev->tt) {
1875 qh->h_port_reg = (u8) urb->dev->ttport;
1876 qh->h_addr_reg |= 0x80;
1877 }
1878 }
1879 }
1880
1881 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
1882 * until we get real dma queues (with an entry for each urb/buffer),
1883 * we only have work to do in the former case.
1884 */
1885 spin_lock_irqsave(&musb->lock, flags);
1886 if (hep->hcpriv) {
1887 /* some concurrent activity submitted another urb to hep...
1888 * odd, rare, error prone, but legal.
1889 */
1890 kfree(qh);
1891 ret = 0;
1892 } else
1893 ret = musb_schedule(musb, qh,
1894 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
1895
1896 if (ret == 0) {
1897 urb->hcpriv = qh;
1898 /* FIXME set urb->start_frame for iso/intr, it's tested in
1899 * musb_start_urb(), but otherwise only konicawc cares ...
1900 */
1901 }
1902 spin_unlock_irqrestore(&musb->lock, flags);
1903
1904done:
1905 if (ret != 0) {
1906 usb_hcd_unlink_urb_from_ep(hcd, urb);
1907 kfree(qh);
1908 }
1909 return ret;
1910}
1911
1912
1913/*
1914 * abort a transfer that's at the head of a hardware queue.
1915 * called with controller locked, irqs blocked
1916 * that hardware queue advances to the next transfer, unless prevented
1917 */
1918static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in)
1919{
1920 struct musb_hw_ep *ep = qh->hw_ep;
1921 void __iomem *epio = ep->regs;
1922 unsigned hw_end = ep->epnum;
1923 void __iomem *regs = ep->musb->mregs;
1924 u16 csr;
1925 int status = 0;
1926
1927 musb_ep_select(regs, hw_end);
1928
1929 if (is_dma_capable()) {
1930 struct dma_channel *dma;
1931
1932 dma = is_in ? ep->rx_channel : ep->tx_channel;
1933 if (dma) {
1934 status = ep->musb->dma_controller->channel_abort(dma);
1935 DBG(status ? 1 : 3,
1936 "abort %cX%d DMA for urb %p --> %d\n",
1937 is_in ? 'R' : 'T', ep->epnum,
1938 urb, status);
1939 urb->actual_length += dma->actual_len;
1940 }
1941 }
1942
1943 /* turn off DMA requests, discard state, stop polling ... */
1944 if (is_in) {
1945 /* giveback saves bulk toggle */
1946 csr = musb_h_flush_rxfifo(ep, 0);
1947
1948 /* REVISIT we still get an irq; should likely clear the
1949 * endpoint's irq status here to avoid bogus irqs.
1950 * clearing that status is platform-specific...
1951 */
1952 } else {
1953 musb_h_tx_flush_fifo(ep);
1954 csr = musb_readw(epio, MUSB_TXCSR);
1955 csr &= ~(MUSB_TXCSR_AUTOSET
1956 | MUSB_TXCSR_DMAENAB
1957 | MUSB_TXCSR_H_RXSTALL
1958 | MUSB_TXCSR_H_NAKTIMEOUT
1959 | MUSB_TXCSR_H_ERROR
1960 | MUSB_TXCSR_TXPKTRDY);
1961 musb_writew(epio, MUSB_TXCSR, csr);
1962 /* REVISIT may need to clear FLUSHFIFO ... */
1963 musb_writew(epio, MUSB_TXCSR, csr);
1964 /* flush cpu writebuffer */
1965 csr = musb_readw(epio, MUSB_TXCSR);
1966 }
1967 if (status == 0)
1968 musb_advance_schedule(ep->musb, urb, ep, is_in);
1969 return status;
1970}
1971
1972static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1973{
1974 struct musb *musb = hcd_to_musb(hcd);
1975 struct musb_qh *qh;
1976 struct list_head *sched;
1977 unsigned long flags;
1978 int ret;
1979
1980 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
1981 usb_pipedevice(urb->pipe),
1982 usb_pipeendpoint(urb->pipe),
1983 usb_pipein(urb->pipe) ? "in" : "out");
1984
1985 spin_lock_irqsave(&musb->lock, flags);
1986 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1987 if (ret)
1988 goto done;
1989
1990 qh = urb->hcpriv;
1991 if (!qh)
1992 goto done;
1993
1994 /* Any URB not actively programmed into endpoint hardware can be
1995 * immediately given back. Such an URB must be at the head of its
1996 * endpoint queue, unless someday we get real DMA queues. And even
1997 * then, it might not be known to the hardware...
1998 *
1999 * Otherwise abort current transfer, pending dma, etc.; urb->status
2000 * has already been updated. This is a synchronous abort; it'd be
2001 * OK to hold off until after some IRQ, though.
2002 */
2003 if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list)
2004 ret = -EINPROGRESS;
2005 else {
2006 switch (qh->type) {
2007 case USB_ENDPOINT_XFER_CONTROL:
2008 sched = &musb->control;
2009 break;
2010 case USB_ENDPOINT_XFER_BULK:
2011 if (usb_pipein(urb->pipe))
2012 sched = &musb->in_bulk;
2013 else
2014 sched = &musb->out_bulk;
2015 break;
2016 default:
2017 /* REVISIT when we get a schedule tree, periodic
2018 * transfers won't always be at the head of a
2019 * singleton queue...
2020 */
2021 sched = NULL;
2022 break;
2023 }
2024 }
2025
2026 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2027 if (ret < 0 || (sched && qh != first_qh(sched))) {
2028 int ready = qh->is_ready;
2029
2030 ret = 0;
2031 qh->is_ready = 0;
2032 __musb_giveback(musb, urb, 0);
2033 qh->is_ready = ready;
2034 } else
2035 ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2036done:
2037 spin_unlock_irqrestore(&musb->lock, flags);
2038 return ret;
2039}
2040
2041/* disable an endpoint */
2042static void
2043musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2044{
2045 u8 epnum = hep->desc.bEndpointAddress;
2046 unsigned long flags;
2047 struct musb *musb = hcd_to_musb(hcd);
2048 u8 is_in = epnum & USB_DIR_IN;
2049 struct musb_qh *qh = hep->hcpriv;
2050 struct urb *urb, *tmp;
2051 struct list_head *sched;
2052
2053 if (!qh)
2054 return;
2055
2056 spin_lock_irqsave(&musb->lock, flags);
2057
2058 switch (qh->type) {
2059 case USB_ENDPOINT_XFER_CONTROL:
2060 sched = &musb->control;
2061 break;
2062 case USB_ENDPOINT_XFER_BULK:
2063 if (is_in)
2064 sched = &musb->in_bulk;
2065 else
2066 sched = &musb->out_bulk;
2067 break;
2068 default:
2069 /* REVISIT when we get a schedule tree, periodic transfers
2070 * won't always be at the head of a singleton queue...
2071 */
2072 sched = NULL;
2073 break;
2074 }
2075
2076 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2077
2078 /* kick first urb off the hardware, if needed */
2079 qh->is_ready = 0;
2080 if (!sched || qh == first_qh(sched)) {
2081 urb = next_urb(qh);
2082
2083 /* make software (then hardware) stop ASAP */
2084 if (!urb->unlinked)
2085 urb->status = -ESHUTDOWN;
2086
2087 /* cleanup */
2088 musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2089 } else
2090 urb = NULL;
2091
2092 /* then just nuke all the others */
2093 list_for_each_entry_safe_from(urb, tmp, &hep->urb_list, urb_list)
2094 musb_giveback(qh, urb, -ESHUTDOWN);
2095
2096 spin_unlock_irqrestore(&musb->lock, flags);
2097}
2098
2099static int musb_h_get_frame_number(struct usb_hcd *hcd)
2100{
2101 struct musb *musb = hcd_to_musb(hcd);
2102
2103 return musb_readw(musb->mregs, MUSB_FRAME);
2104}
2105
2106static int musb_h_start(struct usb_hcd *hcd)
2107{
2108 struct musb *musb = hcd_to_musb(hcd);
2109
2110 /* NOTE: musb_start() is called when the hub driver turns
2111 * on port power, or when (OTG) peripheral starts.
2112 */
2113 hcd->state = HC_STATE_RUNNING;
2114 musb->port1_status = 0;
2115 return 0;
2116}
2117
2118static void musb_h_stop(struct usb_hcd *hcd)
2119{
2120 musb_stop(hcd_to_musb(hcd));
2121 hcd->state = HC_STATE_HALT;
2122}
2123
2124static int musb_bus_suspend(struct usb_hcd *hcd)
2125{
2126 struct musb *musb = hcd_to_musb(hcd);
2127
2128 if (musb->xceiv.state == OTG_STATE_A_SUSPEND)
2129 return 0;
2130
2131 if (is_host_active(musb) && musb->is_active) {
2132 WARNING("trying to suspend as %s is_active=%i\n",
2133 otg_state_string(musb), musb->is_active);
2134 return -EBUSY;
2135 } else
2136 return 0;
2137}
2138
2139static int musb_bus_resume(struct usb_hcd *hcd)
2140{
2141 /* resuming child port does the work */
2142 return 0;
2143}
2144
2145const struct hc_driver musb_hc_driver = {
2146 .description = "musb-hcd",
2147 .product_desc = "MUSB HDRC host driver",
2148 .hcd_priv_size = sizeof(struct musb),
2149 .flags = HCD_USB2 | HCD_MEMORY,
2150
2151 /* not using irq handler or reset hooks from usbcore, since
2152 * those must be shared with peripheral code for OTG configs
2153 */
2154
2155 .start = musb_h_start,
2156 .stop = musb_h_stop,
2157
2158 .get_frame_number = musb_h_get_frame_number,
2159
2160 .urb_enqueue = musb_urb_enqueue,
2161 .urb_dequeue = musb_urb_dequeue,
2162 .endpoint_disable = musb_h_disable,
2163
2164 .hub_status_data = musb_hub_status_data,
2165 .hub_control = musb_hub_control,
2166 .bus_suspend = musb_bus_suspend,
2167 .bus_resume = musb_bus_resume,
2168 /* .start_port_reset = NULL, */
2169 /* .hub_irq_enable = NULL, */
2170};
diff --git a/drivers/usb/musb/musb_host.h b/drivers/usb/musb/musb_host.h
new file mode 100644
index 000000000000..77bcdb9d5b32
--- /dev/null
+++ b/drivers/usb/musb/musb_host.h
@@ -0,0 +1,110 @@
1/*
2 * MUSB OTG driver host defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef _MUSB_HOST_H
36#define _MUSB_HOST_H
37
38static inline struct usb_hcd *musb_to_hcd(struct musb *musb)
39{
40 return container_of((void *) musb, struct usb_hcd, hcd_priv);
41}
42
43static inline struct musb *hcd_to_musb(struct usb_hcd *hcd)
44{
45 return (struct musb *) (hcd->hcd_priv);
46}
47
48/* stored in "usb_host_endpoint.hcpriv" for scheduled endpoints */
49struct musb_qh {
50 struct usb_host_endpoint *hep; /* usbcore info */
51 struct usb_device *dev;
52 struct musb_hw_ep *hw_ep; /* current binding */
53
54 struct list_head ring; /* of musb_qh */
55 /* struct musb_qh *next; */ /* for periodic tree */
56
57 unsigned offset; /* in urb->transfer_buffer */
58 unsigned segsize; /* current xfer fragment */
59
60 u8 type_reg; /* {rx,tx} type register */
61 u8 intv_reg; /* {rx,tx} interval register */
62 u8 addr_reg; /* device address register */
63 u8 h_addr_reg; /* hub address register */
64 u8 h_port_reg; /* hub port register */
65
66 u8 is_ready; /* safe to modify hw_ep */
67 u8 type; /* XFERTYPE_* */
68 u8 epnum;
69 u16 maxpacket;
70 u16 frame; /* for periodic schedule */
71 unsigned iso_idx; /* in urb->iso_frame_desc[] */
72};
73
74/* map from control or bulk queue head to the first qh on that ring */
75static inline struct musb_qh *first_qh(struct list_head *q)
76{
77 if (list_empty(q))
78 return NULL;
79 return list_entry(q->next, struct musb_qh, ring);
80}
81
82
83extern void musb_root_disconnect(struct musb *musb);
84
85struct usb_hcd;
86
87extern int musb_hub_status_data(struct usb_hcd *hcd, char *buf);
88extern int musb_hub_control(struct usb_hcd *hcd,
89 u16 typeReq, u16 wValue, u16 wIndex,
90 char *buf, u16 wLength);
91
92extern const struct hc_driver musb_hc_driver;
93
94static inline struct urb *next_urb(struct musb_qh *qh)
95{
96#ifdef CONFIG_USB_MUSB_HDRC_HCD
97 struct list_head *queue;
98
99 if (!qh)
100 return NULL;
101 queue = &qh->hep->urb_list;
102 if (list_empty(queue))
103 return NULL;
104 return list_entry(queue->next, struct urb, urb_list);
105#else
106 return NULL;
107#endif
108}
109
110#endif /* _MUSB_HOST_H */
diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
new file mode 100644
index 000000000000..6bbedae83af8
--- /dev/null
+++ b/drivers/usb/musb/musb_io.h
@@ -0,0 +1,115 @@
1/*
2 * MUSB OTG driver register I/O
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_LINUX_PLATFORM_ARCH_H__
36#define __MUSB_LINUX_PLATFORM_ARCH_H__
37
38#include <linux/io.h>
39
40#ifndef CONFIG_ARM
41static inline void readsl(const void __iomem *addr, void *buf, int len)
42 { insl((unsigned long)addr, buf, len); }
43static inline void readsw(const void __iomem *addr, void *buf, int len)
44 { insw((unsigned long)addr, buf, len); }
45static inline void readsb(const void __iomem *addr, void *buf, int len)
46 { insb((unsigned long)addr, buf, len); }
47
48static inline void writesl(const void __iomem *addr, const void *buf, int len)
49 { outsl((unsigned long)addr, buf, len); }
50static inline void writesw(const void __iomem *addr, const void *buf, int len)
51 { outsw((unsigned long)addr, buf, len); }
52static inline void writesb(const void __iomem *addr, const void *buf, int len)
53 { outsb((unsigned long)addr, buf, len); }
54
55#endif
56
57/* NOTE: these offsets are all in bytes */
58
59static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
60 { return __raw_readw(addr + offset); }
61
62static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
63 { return __raw_readl(addr + offset); }
64
65
66static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
67 { __raw_writew(data, addr + offset); }
68
69static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
70 { __raw_writel(data, addr + offset); }
71
72
73#ifdef CONFIG_USB_TUSB6010
74
75/*
76 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
77 */
78static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
79{
80 u16 tmp;
81 u8 val;
82
83 tmp = __raw_readw(addr + (offset & ~1));
84 if (offset & 1)
85 val = (tmp >> 8);
86 else
87 val = tmp & 0xff;
88
89 return val;
90}
91
92static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
93{
94 u16 tmp;
95
96 tmp = __raw_readw(addr + (offset & ~1));
97 if (offset & 1)
98 tmp = (data << 8) | (tmp & 0xff);
99 else
100 tmp = (tmp & 0xff00) | data;
101
102 __raw_writew(tmp, addr + (offset & ~1));
103}
104
105#else
106
107static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
108 { return __raw_readb(addr + offset); }
109
110static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
111 { __raw_writeb(data, addr + offset); }
112
113#endif /* CONFIG_USB_TUSB6010 */
114
115#endif
diff --git a/drivers/usb/musb/musb_procfs.c b/drivers/usb/musb/musb_procfs.c
new file mode 100644
index 000000000000..55e6b78bdccc
--- /dev/null
+++ b/drivers/usb/musb/musb_procfs.c
@@ -0,0 +1,830 @@
1/*
2 * MUSB OTG driver debug support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/proc_fs.h>
37#include <linux/seq_file.h>
38#include <linux/uaccess.h> /* FIXME remove procfs writes */
39#include <asm/arch/hardware.h>
40
41#include "musb_core.h"
42
43#include "davinci.h"
44
45#ifdef CONFIG_USB_MUSB_HDRC_HCD
46
47static int dump_qh(struct musb_qh *qh, char *buf, unsigned max)
48{
49 int count;
50 int tmp;
51 struct usb_host_endpoint *hep = qh->hep;
52 struct urb *urb;
53
54 count = snprintf(buf, max, " qh %p dev%d ep%d%s max%d\n",
55 qh, qh->dev->devnum, qh->epnum,
56 ({ char *s; switch (qh->type) {
57 case USB_ENDPOINT_XFER_BULK:
58 s = "-bulk"; break;
59 case USB_ENDPOINT_XFER_INT:
60 s = "-int"; break;
61 case USB_ENDPOINT_XFER_CONTROL:
62 s = ""; break;
63 default:
64 s = "iso"; break;
65 }; s; }),
66 qh->maxpacket);
67 if (count <= 0)
68 return 0;
69 buf += count;
70 max -= count;
71
72 list_for_each_entry(urb, &hep->urb_list, urb_list) {
73 tmp = snprintf(buf, max, "\t%s urb %p %d/%d\n",
74 usb_pipein(urb->pipe) ? "in" : "out",
75 urb, urb->actual_length,
76 urb->transfer_buffer_length);
77 if (tmp <= 0)
78 break;
79 tmp = min(tmp, (int)max);
80 count += tmp;
81 buf += tmp;
82 max -= tmp;
83 }
84 return count;
85}
86
87static int
88dump_queue(struct list_head *q, char *buf, unsigned max)
89{
90 int count = 0;
91 struct musb_qh *qh;
92
93 list_for_each_entry(qh, q, ring) {
94 int tmp;
95
96 tmp = dump_qh(qh, buf, max);
97 if (tmp <= 0)
98 break;
99 tmp = min(tmp, (int)max);
100 count += tmp;
101 buf += tmp;
102 max -= tmp;
103 }
104 return count;
105}
106
107#endif /* HCD */
108
109#ifdef CONFIG_USB_GADGET_MUSB_HDRC
110static int dump_ep(struct musb_ep *ep, char *buffer, unsigned max)
111{
112 char *buf = buffer;
113 int code = 0;
114 void __iomem *regs = ep->hw_ep->regs;
115 char *mode = "1buf";
116
117 if (ep->is_in) {
118 if (ep->hw_ep->tx_double_buffered)
119 mode = "2buf";
120 } else {
121 if (ep->hw_ep->rx_double_buffered)
122 mode = "2buf";
123 }
124
125 do {
126 struct usb_request *req;
127
128 code = snprintf(buf, max,
129 "\n%s (hw%d): %s%s, csr %04x maxp %04x\n",
130 ep->name, ep->current_epnum,
131 mode, ep->dma ? " dma" : "",
132 musb_readw(regs,
133 (ep->is_in || !ep->current_epnum)
134 ? MUSB_TXCSR
135 : MUSB_RXCSR),
136 musb_readw(regs, ep->is_in
137 ? MUSB_TXMAXP
138 : MUSB_RXMAXP)
139 );
140 if (code <= 0)
141 break;
142 code = min(code, (int) max);
143 buf += code;
144 max -= code;
145
146 if (is_cppi_enabled() && ep->current_epnum) {
147 unsigned cppi = ep->current_epnum - 1;
148 void __iomem *base = ep->musb->ctrl_base;
149 unsigned off1 = cppi << 2;
150 void __iomem *ram = base;
151 char tmp[16];
152
153 if (ep->is_in) {
154 ram += DAVINCI_TXCPPI_STATERAM_OFFSET(cppi);
155 tmp[0] = 0;
156 } else {
157 ram += DAVINCI_RXCPPI_STATERAM_OFFSET(cppi);
158 snprintf(tmp, sizeof tmp, "%d left, ",
159 musb_readl(base,
160 DAVINCI_RXCPPI_BUFCNT0_REG + off1));
161 }
162
163 code = snprintf(buf, max, "%cX DMA%d: %s"
164 "%08x %08x, %08x %08x; "
165 "%08x %08x %08x .. %08x\n",
166 ep->is_in ? 'T' : 'R',
167 ep->current_epnum - 1, tmp,
168 musb_readl(ram, 0 * 4),
169 musb_readl(ram, 1 * 4),
170 musb_readl(ram, 2 * 4),
171 musb_readl(ram, 3 * 4),
172 musb_readl(ram, 4 * 4),
173 musb_readl(ram, 5 * 4),
174 musb_readl(ram, 6 * 4),
175 musb_readl(ram, 7 * 4));
176 if (code <= 0)
177 break;
178 code = min(code, (int) max);
179 buf += code;
180 max -= code;
181 }
182
183 if (list_empty(&ep->req_list)) {
184 code = snprintf(buf, max, "\t(queue empty)\n");
185 if (code <= 0)
186 break;
187 code = min(code, (int) max);
188 buf += code;
189 max -= code;
190 break;
191 }
192 list_for_each_entry(req, &ep->req_list, list) {
193 code = snprintf(buf, max, "\treq %p, %s%s%d/%d\n",
194 req,
195 req->zero ? "zero, " : "",
196 req->short_not_ok ? "!short, " : "",
197 req->actual, req->length);
198 if (code <= 0)
199 break;
200 code = min(code, (int) max);
201 buf += code;
202 max -= code;
203 }
204 } while (0);
205 return buf - buffer;
206}
207#endif
208
209static int
210dump_end_info(struct musb *musb, u8 epnum, char *aBuffer, unsigned max)
211{
212 int code = 0;
213 char *buf = aBuffer;
214 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
215
216 do {
217 musb_ep_select(musb->mregs, epnum);
218#ifdef CONFIG_USB_MUSB_HDRC_HCD
219 if (is_host_active(musb)) {
220 int dump_rx, dump_tx;
221 void __iomem *regs = hw_ep->regs;
222
223 /* TEMPORARY (!) until we have a real periodic
224 * schedule tree ...
225 */
226 if (!epnum) {
227 /* control is shared, uses RX queue
228 * but (mostly) shadowed tx registers
229 */
230 dump_tx = !list_empty(&musb->control);
231 dump_rx = 0;
232 } else if (hw_ep == musb->bulk_ep) {
233 dump_tx = !list_empty(&musb->out_bulk);
234 dump_rx = !list_empty(&musb->in_bulk);
235 } else if (musb->periodic[epnum]) {
236 struct usb_host_endpoint *hep;
237
238 hep = musb->periodic[epnum]->hep;
239 dump_rx = hep->desc.bEndpointAddress
240 & USB_ENDPOINT_DIR_MASK;
241 dump_tx = !dump_rx;
242 } else
243 break;
244 /* END TEMPORARY */
245
246
247 if (dump_rx) {
248 code = snprintf(buf, max,
249 "\nRX%d: %s rxcsr %04x interval %02x "
250 "max %04x type %02x; "
251 "dev %d hub %d port %d"
252 "\n",
253 epnum,
254 hw_ep->rx_double_buffered
255 ? "2buf" : "1buf",
256 musb_readw(regs, MUSB_RXCSR),
257 musb_readb(regs, MUSB_RXINTERVAL),
258 musb_readw(regs, MUSB_RXMAXP),
259 musb_readb(regs, MUSB_RXTYPE),
260 /* FIXME: assumes multipoint */
261 musb_readb(musb->mregs,
262 MUSB_BUSCTL_OFFSET(epnum,
263 MUSB_RXFUNCADDR)),
264 musb_readb(musb->mregs,
265 MUSB_BUSCTL_OFFSET(epnum,
266 MUSB_RXHUBADDR)),
267 musb_readb(musb->mregs,
268 MUSB_BUSCTL_OFFSET(epnum,
269 MUSB_RXHUBPORT))
270 );
271 if (code <= 0)
272 break;
273 code = min(code, (int) max);
274 buf += code;
275 max -= code;
276
277 if (is_cppi_enabled()
278 && epnum
279 && hw_ep->rx_channel) {
280 unsigned cppi = epnum - 1;
281 unsigned off1 = cppi << 2;
282 void __iomem *base;
283 void __iomem *ram;
284 char tmp[16];
285
286 base = musb->ctrl_base;
287 ram = DAVINCI_RXCPPI_STATERAM_OFFSET(
288 cppi) + base;
289 snprintf(tmp, sizeof tmp, "%d left, ",
290 musb_readl(base,
291 DAVINCI_RXCPPI_BUFCNT0_REG
292 + off1));
293
294 code = snprintf(buf, max,
295 " rx dma%d: %s"
296 "%08x %08x, %08x %08x; "
297 "%08x %08x %08x .. %08x\n",
298 cppi, tmp,
299 musb_readl(ram, 0 * 4),
300 musb_readl(ram, 1 * 4),
301 musb_readl(ram, 2 * 4),
302 musb_readl(ram, 3 * 4),
303 musb_readl(ram, 4 * 4),
304 musb_readl(ram, 5 * 4),
305 musb_readl(ram, 6 * 4),
306 musb_readl(ram, 7 * 4));
307 if (code <= 0)
308 break;
309 code = min(code, (int) max);
310 buf += code;
311 max -= code;
312 }
313
314 if (hw_ep == musb->bulk_ep
315 && !list_empty(
316 &musb->in_bulk)) {
317 code = dump_queue(&musb->in_bulk,
318 buf, max);
319 if (code <= 0)
320 break;
321 code = min(code, (int) max);
322 buf += code;
323 max -= code;
324 } else if (musb->periodic[epnum]) {
325 code = dump_qh(musb->periodic[epnum],
326 buf, max);
327 if (code <= 0)
328 break;
329 code = min(code, (int) max);
330 buf += code;
331 max -= code;
332 }
333 }
334
335 if (dump_tx) {
336 code = snprintf(buf, max,
337 "\nTX%d: %s txcsr %04x interval %02x "
338 "max %04x type %02x; "
339 "dev %d hub %d port %d"
340 "\n",
341 epnum,
342 hw_ep->tx_double_buffered
343 ? "2buf" : "1buf",
344 musb_readw(regs, MUSB_TXCSR),
345 musb_readb(regs, MUSB_TXINTERVAL),
346 musb_readw(regs, MUSB_TXMAXP),
347 musb_readb(regs, MUSB_TXTYPE),
348 /* FIXME: assumes multipoint */
349 musb_readb(musb->mregs,
350 MUSB_BUSCTL_OFFSET(epnum,
351 MUSB_TXFUNCADDR)),
352 musb_readb(musb->mregs,
353 MUSB_BUSCTL_OFFSET(epnum,
354 MUSB_TXHUBADDR)),
355 musb_readb(musb->mregs,
356 MUSB_BUSCTL_OFFSET(epnum,
357 MUSB_TXHUBPORT))
358 );
359 if (code <= 0)
360 break;
361 code = min(code, (int) max);
362 buf += code;
363 max -= code;
364
365 if (is_cppi_enabled()
366 && epnum
367 && hw_ep->tx_channel) {
368 unsigned cppi = epnum - 1;
369 void __iomem *base;
370 void __iomem *ram;
371
372 base = musb->ctrl_base;
373 ram = DAVINCI_RXCPPI_STATERAM_OFFSET(
374 cppi) + base;
375 code = snprintf(buf, max,
376 " tx dma%d: "
377 "%08x %08x, %08x %08x; "
378 "%08x %08x %08x .. %08x\n",
379 cppi,
380 musb_readl(ram, 0 * 4),
381 musb_readl(ram, 1 * 4),
382 musb_readl(ram, 2 * 4),
383 musb_readl(ram, 3 * 4),
384 musb_readl(ram, 4 * 4),
385 musb_readl(ram, 5 * 4),
386 musb_readl(ram, 6 * 4),
387 musb_readl(ram, 7 * 4));
388 if (code <= 0)
389 break;
390 code = min(code, (int) max);
391 buf += code;
392 max -= code;
393 }
394
395 if (hw_ep == musb->control_ep
396 && !list_empty(
397 &musb->control)) {
398 code = dump_queue(&musb->control,
399 buf, max);
400 if (code <= 0)
401 break;
402 code = min(code, (int) max);
403 buf += code;
404 max -= code;
405 } else if (hw_ep == musb->bulk_ep
406 && !list_empty(
407 &musb->out_bulk)) {
408 code = dump_queue(&musb->out_bulk,
409 buf, max);
410 if (code <= 0)
411 break;
412 code = min(code, (int) max);
413 buf += code;
414 max -= code;
415 } else if (musb->periodic[epnum]) {
416 code = dump_qh(musb->periodic[epnum],
417 buf, max);
418 if (code <= 0)
419 break;
420 code = min(code, (int) max);
421 buf += code;
422 max -= code;
423 }
424 }
425 }
426#endif
427#ifdef CONFIG_USB_GADGET_MUSB_HDRC
428 if (is_peripheral_active(musb)) {
429 code = 0;
430
431 if (hw_ep->ep_in.desc || !epnum) {
432 code = dump_ep(&hw_ep->ep_in, buf, max);
433 if (code <= 0)
434 break;
435 code = min(code, (int) max);
436 buf += code;
437 max -= code;
438 }
439 if (hw_ep->ep_out.desc) {
440 code = dump_ep(&hw_ep->ep_out, buf, max);
441 if (code <= 0)
442 break;
443 code = min(code, (int) max);
444 buf += code;
445 max -= code;
446 }
447 }
448#endif
449 } while (0);
450
451 return buf - aBuffer;
452}
453
454/* Dump the current status and compile options.
455 * @param musb the device driver instance
456 * @param buffer where to dump the status; it must be big enough to hold the
457 * result otherwise "BAD THINGS HAPPENS(TM)".
458 */
459static int dump_header_stats(struct musb *musb, char *buffer)
460{
461 int code, count = 0;
462 const void __iomem *mbase = musb->mregs;
463
464 *buffer = 0;
465 count = sprintf(buffer, "Status: %sHDRC, Mode=%s "
466 "(Power=%02x, DevCtl=%02x)\n",
467 (musb->is_multipoint ? "M" : ""), MUSB_MODE(musb),
468 musb_readb(mbase, MUSB_POWER),
469 musb_readb(mbase, MUSB_DEVCTL));
470 if (count <= 0)
471 return 0;
472 buffer += count;
473
474 code = sprintf(buffer, "OTG state: %s; %sactive\n",
475 otg_state_string(musb),
476 musb->is_active ? "" : "in");
477 if (code <= 0)
478 goto done;
479 buffer += code;
480 count += code;
481
482 code = sprintf(buffer,
483 "Options: "
484#ifdef CONFIG_MUSB_PIO_ONLY
485 "pio"
486#elif defined(CONFIG_USB_TI_CPPI_DMA)
487 "cppi-dma"
488#elif defined(CONFIG_USB_INVENTRA_DMA)
489 "musb-dma"
490#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
491 "tusb-omap-dma"
492#else
493 "?dma?"
494#endif
495 ", "
496#ifdef CONFIG_USB_MUSB_OTG
497 "otg (peripheral+host)"
498#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
499 "peripheral"
500#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
501 "host"
502#endif
503 ", debug=%d [eps=%d]\n",
504 debug,
505 musb->nr_endpoints);
506 if (code <= 0)
507 goto done;
508 count += code;
509 buffer += code;
510
511#ifdef CONFIG_USB_GADGET_MUSB_HDRC
512 code = sprintf(buffer, "Peripheral address: %02x\n",
513 musb_readb(musb->ctrl_base, MUSB_FADDR));
514 if (code <= 0)
515 goto done;
516 buffer += code;
517 count += code;
518#endif
519
520#ifdef CONFIG_USB_MUSB_HDRC_HCD
521 code = sprintf(buffer, "Root port status: %08x\n",
522 musb->port1_status);
523 if (code <= 0)
524 goto done;
525 buffer += code;
526 count += code;
527#endif
528
529#ifdef CONFIG_ARCH_DAVINCI
530 code = sprintf(buffer,
531 "DaVinci: ctrl=%02x stat=%1x phy=%03x\n"
532 "\trndis=%05x auto=%04x intsrc=%08x intmsk=%08x"
533 "\n",
534 musb_readl(musb->ctrl_base, DAVINCI_USB_CTRL_REG),
535 musb_readl(musb->ctrl_base, DAVINCI_USB_STAT_REG),
536 __raw_readl((void __force __iomem *)
537 IO_ADDRESS(USBPHY_CTL_PADDR)),
538 musb_readl(musb->ctrl_base, DAVINCI_RNDIS_REG),
539 musb_readl(musb->ctrl_base, DAVINCI_AUTOREQ_REG),
540 musb_readl(musb->ctrl_base,
541 DAVINCI_USB_INT_SOURCE_REG),
542 musb_readl(musb->ctrl_base,
543 DAVINCI_USB_INT_MASK_REG));
544 if (code <= 0)
545 goto done;
546 count += code;
547 buffer += code;
548#endif /* DAVINCI */
549
550#ifdef CONFIG_USB_TUSB6010
551 code = sprintf(buffer,
552 "TUSB6010: devconf %08x, phy enable %08x drive %08x"
553 "\n\totg %03x timer %08x"
554 "\n\tprcm conf %08x mgmt %08x; int src %08x mask %08x"
555 "\n",
556 musb_readl(musb->ctrl_base, TUSB_DEV_CONF),
557 musb_readl(musb->ctrl_base, TUSB_PHY_OTG_CTRL_ENABLE),
558 musb_readl(musb->ctrl_base, TUSB_PHY_OTG_CTRL),
559 musb_readl(musb->ctrl_base, TUSB_DEV_OTG_STAT),
560 musb_readl(musb->ctrl_base, TUSB_DEV_OTG_TIMER),
561 musb_readl(musb->ctrl_base, TUSB_PRCM_CONF),
562 musb_readl(musb->ctrl_base, TUSB_PRCM_MNGMT),
563 musb_readl(musb->ctrl_base, TUSB_INT_SRC),
564 musb_readl(musb->ctrl_base, TUSB_INT_MASK));
565 if (code <= 0)
566 goto done;
567 count += code;
568 buffer += code;
569#endif /* DAVINCI */
570
571 if (is_cppi_enabled() && musb->dma_controller) {
572 code = sprintf(buffer,
573 "CPPI: txcr=%d txsrc=%01x txena=%01x; "
574 "rxcr=%d rxsrc=%01x rxena=%01x "
575 "\n",
576 musb_readl(musb->ctrl_base,
577 DAVINCI_TXCPPI_CTRL_REG),
578 musb_readl(musb->ctrl_base,
579 DAVINCI_TXCPPI_RAW_REG),
580 musb_readl(musb->ctrl_base,
581 DAVINCI_TXCPPI_INTENAB_REG),
582 musb_readl(musb->ctrl_base,
583 DAVINCI_RXCPPI_CTRL_REG),
584 musb_readl(musb->ctrl_base,
585 DAVINCI_RXCPPI_RAW_REG),
586 musb_readl(musb->ctrl_base,
587 DAVINCI_RXCPPI_INTENAB_REG));
588 if (code <= 0)
589 goto done;
590 count += code;
591 buffer += code;
592 }
593
594#ifdef CONFIG_USB_GADGET_MUSB_HDRC
595 if (is_peripheral_enabled(musb)) {
596 code = sprintf(buffer, "Gadget driver: %s\n",
597 musb->gadget_driver
598 ? musb->gadget_driver->driver.name
599 : "(none)");
600 if (code <= 0)
601 goto done;
602 count += code;
603 buffer += code;
604 }
605#endif
606
607done:
608 return count;
609}
610
611/* Write to ProcFS
612 *
613 * C soft-connect
614 * c soft-disconnect
615 * I enable HS
616 * i disable HS
617 * s stop session
618 * F force session (OTG-unfriendly)
619 * E rElinquish bus (OTG)
620 * H request host mode
621 * h cancel host request
622 * T start sending TEST_PACKET
623 * D<num> set/query the debug level
624 */
625static int musb_proc_write(struct file *file, const char __user *buffer,
626 unsigned long count, void *data)
627{
628 char cmd;
629 u8 reg;
630 struct musb *musb = (struct musb *)data;
631 void __iomem *mbase = musb->mregs;
632
633 /* MOD_INC_USE_COUNT; */
634
635 if (unlikely(copy_from_user(&cmd, buffer, 1)))
636 return -EFAULT;
637
638 switch (cmd) {
639 case 'C':
640 if (mbase) {
641 reg = musb_readb(mbase, MUSB_POWER)
642 | MUSB_POWER_SOFTCONN;
643 musb_writeb(mbase, MUSB_POWER, reg);
644 }
645 break;
646
647 case 'c':
648 if (mbase) {
649 reg = musb_readb(mbase, MUSB_POWER)
650 & ~MUSB_POWER_SOFTCONN;
651 musb_writeb(mbase, MUSB_POWER, reg);
652 }
653 break;
654
655 case 'I':
656 if (mbase) {
657 reg = musb_readb(mbase, MUSB_POWER)
658 | MUSB_POWER_HSENAB;
659 musb_writeb(mbase, MUSB_POWER, reg);
660 }
661 break;
662
663 case 'i':
664 if (mbase) {
665 reg = musb_readb(mbase, MUSB_POWER)
666 & ~MUSB_POWER_HSENAB;
667 musb_writeb(mbase, MUSB_POWER, reg);
668 }
669 break;
670
671 case 'F':
672 reg = musb_readb(mbase, MUSB_DEVCTL);
673 reg |= MUSB_DEVCTL_SESSION;
674 musb_writeb(mbase, MUSB_DEVCTL, reg);
675 break;
676
677 case 'H':
678 if (mbase) {
679 reg = musb_readb(mbase, MUSB_DEVCTL);
680 reg |= MUSB_DEVCTL_HR;
681 musb_writeb(mbase, MUSB_DEVCTL, reg);
682 /* MUSB_HST_MODE( ((struct musb*)data) ); */
683 /* WARNING("Host Mode\n"); */
684 }
685 break;
686
687 case 'h':
688 if (mbase) {
689 reg = musb_readb(mbase, MUSB_DEVCTL);
690 reg &= ~MUSB_DEVCTL_HR;
691 musb_writeb(mbase, MUSB_DEVCTL, reg);
692 }
693 break;
694
695 case 'T':
696 if (mbase) {
697 musb_load_testpacket(musb);
698 musb_writeb(mbase, MUSB_TESTMODE,
699 MUSB_TEST_PACKET);
700 }
701 break;
702
703#if (MUSB_DEBUG > 0)
704 /* set/read debug level */
705 case 'D':{
706 if (count > 1) {
707 char digits[8], *p = digits;
708 int i = 0, level = 0, sign = 1;
709 int len = min(count - 1, (unsigned long)8);
710
711 if (copy_from_user(&digits, &buffer[1], len))
712 return -EFAULT;
713
714 /* optional sign */
715 if (*p == '-') {
716 len -= 1;
717 sign = -sign;
718 p++;
719 }
720
721 /* read it */
722 while (i++ < len && *p > '0' && *p < '9') {
723 level = level * 10 + (*p - '0');
724 p++;
725 }
726
727 level *= sign;
728 DBG(1, "debug level %d\n", level);
729 debug = level;
730 }
731 }
732 break;
733
734
735 case '?':
736 INFO("?: you are seeing it\n");
737 INFO("C/c: soft connect enable/disable\n");
738 INFO("I/i: hispeed enable/disable\n");
739 INFO("F: force session start\n");
740 INFO("H: host mode\n");
741 INFO("T: start sending TEST_PACKET\n");
742 INFO("D: set/read dbug level\n");
743 break;
744#endif
745
746 default:
747 ERR("Command %c not implemented\n", cmd);
748 break;
749 }
750
751 musb_platform_try_idle(musb, 0);
752
753 return count;
754}
755
756static int musb_proc_read(char *page, char **start,
757 off_t off, int count, int *eof, void *data)
758{
759 char *buffer = page;
760 int code = 0;
761 unsigned long flags;
762 struct musb *musb = data;
763 unsigned epnum;
764
765 count -= off;
766 count -= 1; /* for NUL at end */
767 if (count <= 0)
768 return -EINVAL;
769
770 spin_lock_irqsave(&musb->lock, flags);
771
772 code = dump_header_stats(musb, buffer);
773 if (code > 0) {
774 buffer += code;
775 count -= code;
776 }
777
778 /* generate the report for the end points */
779 /* REVISIT ... not unless something's connected! */
780 for (epnum = 0; count >= 0 && epnum < musb->nr_endpoints;
781 epnum++) {
782 code = dump_end_info(musb, epnum, buffer, count);
783 if (code > 0) {
784 buffer += code;
785 count -= code;
786 }
787 }
788
789 musb_platform_try_idle(musb, 0);
790
791 spin_unlock_irqrestore(&musb->lock, flags);
792 *eof = 1;
793
794 return buffer - page;
795}
796
797void __devexit musb_debug_delete(char *name, struct musb *musb)
798{
799 if (musb->proc_entry)
800 remove_proc_entry(name, NULL);
801}
802
803struct proc_dir_entry *__init
804musb_debug_create(char *name, struct musb *data)
805{
806 struct proc_dir_entry *pde;
807
808 /* FIXME convert everything to seq_file; then later, debugfs */
809
810 if (!name)
811 return NULL;
812
813 pde = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUSR, NULL);
814 data->proc_entry = pde;
815 if (pde) {
816 pde->data = data;
817 /* pde->owner = THIS_MODULE; */
818
819 pde->read_proc = musb_proc_read;
820 pde->write_proc = musb_proc_write;
821
822 pde->size = 0;
823
824 pr_debug("Registered /proc/%s\n", name);
825 } else {
826 pr_debug("Cannot create a valid proc file entry");
827 }
828
829 return pde;
830}
diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
new file mode 100644
index 000000000000..9c228661aa5a
--- /dev/null
+++ b/drivers/usb/musb/musb_regs.h
@@ -0,0 +1,300 @@
1/*
2 * MUSB OTG driver register defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_REGS_H__
36#define __MUSB_REGS_H__
37
38#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
39
40/*
41 * Common USB registers
42 */
43
44#define MUSB_FADDR 0x00 /* 8-bit */
45#define MUSB_POWER 0x01 /* 8-bit */
46
47#define MUSB_INTRTX 0x02 /* 16-bit */
48#define MUSB_INTRRX 0x04
49#define MUSB_INTRTXE 0x06
50#define MUSB_INTRRXE 0x08
51#define MUSB_INTRUSB 0x0A /* 8 bit */
52#define MUSB_INTRUSBE 0x0B /* 8 bit */
53#define MUSB_FRAME 0x0C
54#define MUSB_INDEX 0x0E /* 8 bit */
55#define MUSB_TESTMODE 0x0F /* 8 bit */
56
57/* Get offset for a given FIFO from musb->mregs */
58#ifdef CONFIG_USB_TUSB6010
59#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
60#else
61#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
62#endif
63
64/*
65 * Additional Control Registers
66 */
67
68#define MUSB_DEVCTL 0x60 /* 8 bit */
69
70/* These are always controlled through the INDEX register */
71#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
72#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
73#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
74#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
75
76/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
77#define MUSB_HWVERS 0x6C /* 8 bit */
78
79#define MUSB_EPINFO 0x78 /* 8 bit */
80#define MUSB_RAMINFO 0x79 /* 8 bit */
81#define MUSB_LINKINFO 0x7a /* 8 bit */
82#define MUSB_VPLEN 0x7b /* 8 bit */
83#define MUSB_HS_EOF1 0x7c /* 8 bit */
84#define MUSB_FS_EOF1 0x7d /* 8 bit */
85#define MUSB_LS_EOF1 0x7e /* 8 bit */
86
87/* Offsets to endpoint registers */
88#define MUSB_TXMAXP 0x00
89#define MUSB_TXCSR 0x02
90#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
91#define MUSB_RXMAXP 0x04
92#define MUSB_RXCSR 0x06
93#define MUSB_RXCOUNT 0x08
94#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
95#define MUSB_TXTYPE 0x0A
96#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
97#define MUSB_TXINTERVAL 0x0B
98#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
99#define MUSB_RXTYPE 0x0C
100#define MUSB_RXINTERVAL 0x0D
101#define MUSB_FIFOSIZE 0x0F
102#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
103
104/* Offsets to endpoint registers in indexed model (using INDEX register) */
105#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
106 (0x10 + (_offset))
107
108/* Offsets to endpoint registers in flat models */
109#define MUSB_FLAT_OFFSET(_epnum, _offset) \
110 (0x100 + (0x10*(_epnum)) + (_offset))
111
112#ifdef CONFIG_USB_TUSB6010
113/* TUSB6010 EP0 configuration register is special */
114#define MUSB_TUSB_OFFSET(_epnum, _offset) \
115 (0x10 + _offset)
116#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
117#endif
118
119/* "bus control"/target registers, for host side multipoint (external hubs) */
120#define MUSB_TXFUNCADDR 0x00
121#define MUSB_TXHUBADDR 0x02
122#define MUSB_TXHUBPORT 0x03
123
124#define MUSB_RXFUNCADDR 0x04
125#define MUSB_RXHUBADDR 0x06
126#define MUSB_RXHUBPORT 0x07
127
128#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
129 (0x80 + (8*(_epnum)) + (_offset))
130
131/*
132 * MUSB Register bits
133 */
134
135/* POWER */
136#define MUSB_POWER_ISOUPDATE 0x80
137#define MUSB_POWER_SOFTCONN 0x40
138#define MUSB_POWER_HSENAB 0x20
139#define MUSB_POWER_HSMODE 0x10
140#define MUSB_POWER_RESET 0x08
141#define MUSB_POWER_RESUME 0x04
142#define MUSB_POWER_SUSPENDM 0x02
143#define MUSB_POWER_ENSUSPEND 0x01
144
145/* INTRUSB */
146#define MUSB_INTR_SUSPEND 0x01
147#define MUSB_INTR_RESUME 0x02
148#define MUSB_INTR_RESET 0x04
149#define MUSB_INTR_BABBLE 0x04
150#define MUSB_INTR_SOF 0x08
151#define MUSB_INTR_CONNECT 0x10
152#define MUSB_INTR_DISCONNECT 0x20
153#define MUSB_INTR_SESSREQ 0x40
154#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
155
156/* DEVCTL */
157#define MUSB_DEVCTL_BDEVICE 0x80
158#define MUSB_DEVCTL_FSDEV 0x40
159#define MUSB_DEVCTL_LSDEV 0x20
160#define MUSB_DEVCTL_VBUS 0x18
161#define MUSB_DEVCTL_VBUS_SHIFT 3
162#define MUSB_DEVCTL_HM 0x04
163#define MUSB_DEVCTL_HR 0x02
164#define MUSB_DEVCTL_SESSION 0x01
165
166/* TESTMODE */
167#define MUSB_TEST_FORCE_HOST 0x80
168#define MUSB_TEST_FIFO_ACCESS 0x40
169#define MUSB_TEST_FORCE_FS 0x20
170#define MUSB_TEST_FORCE_HS 0x10
171#define MUSB_TEST_PACKET 0x08
172#define MUSB_TEST_K 0x04
173#define MUSB_TEST_J 0x02
174#define MUSB_TEST_SE0_NAK 0x01
175
176/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
177#define MUSB_FIFOSZ_DPB 0x10
178/* Allocation size (8, 16, 32, ... 4096) */
179#define MUSB_FIFOSZ_SIZE 0x0f
180
181/* CSR0 */
182#define MUSB_CSR0_FLUSHFIFO 0x0100
183#define MUSB_CSR0_TXPKTRDY 0x0002
184#define MUSB_CSR0_RXPKTRDY 0x0001
185
186/* CSR0 in Peripheral mode */
187#define MUSB_CSR0_P_SVDSETUPEND 0x0080
188#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
189#define MUSB_CSR0_P_SENDSTALL 0x0020
190#define MUSB_CSR0_P_SETUPEND 0x0010
191#define MUSB_CSR0_P_DATAEND 0x0008
192#define MUSB_CSR0_P_SENTSTALL 0x0004
193
194/* CSR0 in Host mode */
195#define MUSB_CSR0_H_DIS_PING 0x0800
196#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
197#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
198#define MUSB_CSR0_H_NAKTIMEOUT 0x0080
199#define MUSB_CSR0_H_STATUSPKT 0x0040
200#define MUSB_CSR0_H_REQPKT 0x0020
201#define MUSB_CSR0_H_ERROR 0x0010
202#define MUSB_CSR0_H_SETUPPKT 0x0008
203#define MUSB_CSR0_H_RXSTALL 0x0004
204
205/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
206#define MUSB_CSR0_P_WZC_BITS \
207 (MUSB_CSR0_P_SENTSTALL)
208#define MUSB_CSR0_H_WZC_BITS \
209 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
210 | MUSB_CSR0_RXPKTRDY)
211
212/* TxType/RxType */
213#define MUSB_TYPE_SPEED 0xc0
214#define MUSB_TYPE_SPEED_SHIFT 6
215#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
216#define MUSB_TYPE_PROTO_SHIFT 4
217#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
218
219/* CONFIGDATA */
220#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
221#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
222#define MUSB_CONFIGDATA_BIGENDIAN 0x20
223#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
224#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
225#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
226#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
227#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
228
229/* TXCSR in Peripheral and Host mode */
230#define MUSB_TXCSR_AUTOSET 0x8000
231#define MUSB_TXCSR_MODE 0x2000
232#define MUSB_TXCSR_DMAENAB 0x1000
233#define MUSB_TXCSR_FRCDATATOG 0x0800
234#define MUSB_TXCSR_DMAMODE 0x0400
235#define MUSB_TXCSR_CLRDATATOG 0x0040
236#define MUSB_TXCSR_FLUSHFIFO 0x0008
237#define MUSB_TXCSR_FIFONOTEMPTY 0x0002
238#define MUSB_TXCSR_TXPKTRDY 0x0001
239
240/* TXCSR in Peripheral mode */
241#define MUSB_TXCSR_P_ISO 0x4000
242#define MUSB_TXCSR_P_INCOMPTX 0x0080
243#define MUSB_TXCSR_P_SENTSTALL 0x0020
244#define MUSB_TXCSR_P_SENDSTALL 0x0010
245#define MUSB_TXCSR_P_UNDERRUN 0x0004
246
247/* TXCSR in Host mode */
248#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
249#define MUSB_TXCSR_H_DATATOGGLE 0x0100
250#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
251#define MUSB_TXCSR_H_RXSTALL 0x0020
252#define MUSB_TXCSR_H_ERROR 0x0004
253
254/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
255#define MUSB_TXCSR_P_WZC_BITS \
256 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
257 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
258#define MUSB_TXCSR_H_WZC_BITS \
259 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
260 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
261
262/* RXCSR in Peripheral and Host mode */
263#define MUSB_RXCSR_AUTOCLEAR 0x8000
264#define MUSB_RXCSR_DMAENAB 0x2000
265#define MUSB_RXCSR_DISNYET 0x1000
266#define MUSB_RXCSR_PID_ERR 0x1000
267#define MUSB_RXCSR_DMAMODE 0x0800
268#define MUSB_RXCSR_INCOMPRX 0x0100
269#define MUSB_RXCSR_CLRDATATOG 0x0080
270#define MUSB_RXCSR_FLUSHFIFO 0x0010
271#define MUSB_RXCSR_DATAERROR 0x0008
272#define MUSB_RXCSR_FIFOFULL 0x0002
273#define MUSB_RXCSR_RXPKTRDY 0x0001
274
275/* RXCSR in Peripheral mode */
276#define MUSB_RXCSR_P_ISO 0x4000
277#define MUSB_RXCSR_P_SENTSTALL 0x0040
278#define MUSB_RXCSR_P_SENDSTALL 0x0020
279#define MUSB_RXCSR_P_OVERRUN 0x0004
280
281/* RXCSR in Host mode */
282#define MUSB_RXCSR_H_AUTOREQ 0x4000
283#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
284#define MUSB_RXCSR_H_DATATOGGLE 0x0200
285#define MUSB_RXCSR_H_RXSTALL 0x0040
286#define MUSB_RXCSR_H_REQPKT 0x0020
287#define MUSB_RXCSR_H_ERROR 0x0004
288
289/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
290#define MUSB_RXCSR_P_WZC_BITS \
291 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
292 | MUSB_RXCSR_RXPKTRDY)
293#define MUSB_RXCSR_H_WZC_BITS \
294 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
295 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
296
297/* HUBADDR */
298#define MUSB_HUBADDR_MULTI_TT 0x80
299
300#endif /* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
new file mode 100644
index 000000000000..e0e9ce584175
--- /dev/null
+++ b/drivers/usb/musb/musb_virthub.c
@@ -0,0 +1,425 @@
1/*
2 * MUSB OTG driver virtual root hub support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#include <linux/module.h>
36#include <linux/kernel.h>
37#include <linux/sched.h>
38#include <linux/slab.h>
39#include <linux/errno.h>
40#include <linux/init.h>
41#include <linux/time.h>
42#include <linux/timer.h>
43
44#include <asm/unaligned.h>
45
46#include "musb_core.h"
47
48
49static void musb_port_suspend(struct musb *musb, bool do_suspend)
50{
51 u8 power;
52 void __iomem *mbase = musb->mregs;
53
54 if (!is_host_active(musb))
55 return;
56
57 /* NOTE: this doesn't necessarily put PHY into low power mode,
58 * turning off its clock; that's a function of PHY integration and
59 * MUSB_POWER_ENSUSPEND. PHY may need a clock (sigh) to detect
60 * SE0 changing to connect (J) or wakeup (K) states.
61 */
62 power = musb_readb(mbase, MUSB_POWER);
63 if (do_suspend) {
64 int retries = 10000;
65
66 power &= ~MUSB_POWER_RESUME;
67 power |= MUSB_POWER_SUSPENDM;
68 musb_writeb(mbase, MUSB_POWER, power);
69
70 /* Needed for OPT A tests */
71 power = musb_readb(mbase, MUSB_POWER);
72 while (power & MUSB_POWER_SUSPENDM) {
73 power = musb_readb(mbase, MUSB_POWER);
74 if (retries-- < 1)
75 break;
76 }
77
78 DBG(3, "Root port suspended, power %02x\n", power);
79
80 musb->port1_status |= USB_PORT_STAT_SUSPEND;
81 switch (musb->xceiv.state) {
82 case OTG_STATE_A_HOST:
83 musb->xceiv.state = OTG_STATE_A_SUSPEND;
84 musb->is_active = is_otg_enabled(musb)
85 && musb->xceiv.host->b_hnp_enable;
86 musb_platform_try_idle(musb, 0);
87 break;
88#ifdef CONFIG_USB_MUSB_OTG
89 case OTG_STATE_B_HOST:
90 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
91 musb->is_active = is_otg_enabled(musb)
92 && musb->xceiv.host->b_hnp_enable;
93 musb_platform_try_idle(musb, 0);
94 break;
95#endif
96 default:
97 DBG(1, "bogus rh suspend? %s\n",
98 otg_state_string(musb));
99 }
100 } else if (power & MUSB_POWER_SUSPENDM) {
101 power &= ~MUSB_POWER_SUSPENDM;
102 power |= MUSB_POWER_RESUME;
103 musb_writeb(mbase, MUSB_POWER, power);
104
105 DBG(3, "Root port resuming, power %02x\n", power);
106
107 /* later, GetPortStatus will stop RESUME signaling */
108 musb->port1_status |= MUSB_PORT_STAT_RESUME;
109 musb->rh_timer = jiffies + msecs_to_jiffies(20);
110 }
111}
112
113static void musb_port_reset(struct musb *musb, bool do_reset)
114{
115 u8 power;
116 void __iomem *mbase = musb->mregs;
117
118#ifdef CONFIG_USB_MUSB_OTG
119 if (musb->xceiv.state == OTG_STATE_B_IDLE) {
120 DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n");
121 musb->port1_status &= ~USB_PORT_STAT_RESET;
122 return;
123 }
124#endif
125
126 if (!is_host_active(musb))
127 return;
128
129 /* NOTE: caller guarantees it will turn off the reset when
130 * the appropriate amount of time has passed
131 */
132 power = musb_readb(mbase, MUSB_POWER);
133 if (do_reset) {
134
135 /*
136 * If RESUME is set, we must make sure it stays minimum 20 ms.
137 * Then we must clear RESUME and wait a bit to let musb start
138 * generating SOFs. If we don't do this, OPT HS A 6.8 tests
139 * fail with "Error! Did not receive an SOF before suspend
140 * detected".
141 */
142 if (power & MUSB_POWER_RESUME) {
143 while (time_before(jiffies, musb->rh_timer))
144 msleep(1);
145 musb_writeb(mbase, MUSB_POWER,
146 power & ~MUSB_POWER_RESUME);
147 msleep(1);
148 }
149
150 musb->ignore_disconnect = true;
151 power &= 0xf0;
152 musb_writeb(mbase, MUSB_POWER,
153 power | MUSB_POWER_RESET);
154
155 musb->port1_status |= USB_PORT_STAT_RESET;
156 musb->port1_status &= ~USB_PORT_STAT_ENABLE;
157 musb->rh_timer = jiffies + msecs_to_jiffies(50);
158 } else {
159 DBG(4, "root port reset stopped\n");
160 musb_writeb(mbase, MUSB_POWER,
161 power & ~MUSB_POWER_RESET);
162
163 musb->ignore_disconnect = false;
164
165 power = musb_readb(mbase, MUSB_POWER);
166 if (power & MUSB_POWER_HSMODE) {
167 DBG(4, "high-speed device connected\n");
168 musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;
169 }
170
171 musb->port1_status &= ~USB_PORT_STAT_RESET;
172 musb->port1_status |= USB_PORT_STAT_ENABLE
173 | (USB_PORT_STAT_C_RESET << 16)
174 | (USB_PORT_STAT_C_ENABLE << 16);
175 usb_hcd_poll_rh_status(musb_to_hcd(musb));
176
177 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
178 }
179}
180
181void musb_root_disconnect(struct musb *musb)
182{
183 musb->port1_status = (1 << USB_PORT_FEAT_POWER)
184 | (1 << USB_PORT_FEAT_C_CONNECTION);
185
186 usb_hcd_poll_rh_status(musb_to_hcd(musb));
187 musb->is_active = 0;
188
189 switch (musb->xceiv.state) {
190 case OTG_STATE_A_HOST:
191 case OTG_STATE_A_SUSPEND:
192 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
193 musb->is_active = 0;
194 break;
195 case OTG_STATE_A_WAIT_VFALL:
196 musb->xceiv.state = OTG_STATE_B_IDLE;
197 break;
198 default:
199 DBG(1, "host disconnect (%s)\n", otg_state_string(musb));
200 }
201}
202
203
204/*---------------------------------------------------------------------*/
205
206/* Caller may or may not hold musb->lock */
207int musb_hub_status_data(struct usb_hcd *hcd, char *buf)
208{
209 struct musb *musb = hcd_to_musb(hcd);
210 int retval = 0;
211
212 /* called in_irq() via usb_hcd_poll_rh_status() */
213 if (musb->port1_status & 0xffff0000) {
214 *buf = 0x02;
215 retval = 1;
216 }
217 return retval;
218}
219
220int musb_hub_control(
221 struct usb_hcd *hcd,
222 u16 typeReq,
223 u16 wValue,
224 u16 wIndex,
225 char *buf,
226 u16 wLength)
227{
228 struct musb *musb = hcd_to_musb(hcd);
229 u32 temp;
230 int retval = 0;
231 unsigned long flags;
232
233 spin_lock_irqsave(&musb->lock, flags);
234
235 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))) {
236 spin_unlock_irqrestore(&musb->lock, flags);
237 return -ESHUTDOWN;
238 }
239
240 /* hub features: always zero, setting is a NOP
241 * port features: reported, sometimes updated when host is active
242 * no indicators
243 */
244 switch (typeReq) {
245 case ClearHubFeature:
246 case SetHubFeature:
247 switch (wValue) {
248 case C_HUB_OVER_CURRENT:
249 case C_HUB_LOCAL_POWER:
250 break;
251 default:
252 goto error;
253 }
254 break;
255 case ClearPortFeature:
256 if ((wIndex & 0xff) != 1)
257 goto error;
258
259 switch (wValue) {
260 case USB_PORT_FEAT_ENABLE:
261 break;
262 case USB_PORT_FEAT_SUSPEND:
263 musb_port_suspend(musb, false);
264 break;
265 case USB_PORT_FEAT_POWER:
266 if (!(is_otg_enabled(musb) && hcd->self.is_b_host))
267 musb_set_vbus(musb, 0);
268 break;
269 case USB_PORT_FEAT_C_CONNECTION:
270 case USB_PORT_FEAT_C_ENABLE:
271 case USB_PORT_FEAT_C_OVER_CURRENT:
272 case USB_PORT_FEAT_C_RESET:
273 case USB_PORT_FEAT_C_SUSPEND:
274 break;
275 default:
276 goto error;
277 }
278 DBG(5, "clear feature %d\n", wValue);
279 musb->port1_status &= ~(1 << wValue);
280 break;
281 case GetHubDescriptor:
282 {
283 struct usb_hub_descriptor *desc = (void *)buf;
284
285 desc->bDescLength = 9;
286 desc->bDescriptorType = 0x29;
287 desc->bNbrPorts = 1;
288 desc->wHubCharacteristics = __constant_cpu_to_le16(
289 0x0001 /* per-port power switching */
290 | 0x0010 /* no overcurrent reporting */
291 );
292 desc->bPwrOn2PwrGood = 5; /* msec/2 */
293 desc->bHubContrCurrent = 0;
294
295 /* workaround bogus struct definition */
296 desc->DeviceRemovable[0] = 0x02; /* port 1 */
297 desc->DeviceRemovable[1] = 0xff;
298 }
299 break;
300 case GetHubStatus:
301 temp = 0;
302 *(__le32 *) buf = cpu_to_le32(temp);
303 break;
304 case GetPortStatus:
305 if (wIndex != 1)
306 goto error;
307
308 /* finish RESET signaling? */
309 if ((musb->port1_status & USB_PORT_STAT_RESET)
310 && time_after_eq(jiffies, musb->rh_timer))
311 musb_port_reset(musb, false);
312
313 /* finish RESUME signaling? */
314 if ((musb->port1_status & MUSB_PORT_STAT_RESUME)
315 && time_after_eq(jiffies, musb->rh_timer)) {
316 u8 power;
317
318 power = musb_readb(musb->mregs, MUSB_POWER);
319 power &= ~MUSB_POWER_RESUME;
320 DBG(4, "root port resume stopped, power %02x\n",
321 power);
322 musb_writeb(musb->mregs, MUSB_POWER, power);
323
324 /* ISSUE: DaVinci (RTL 1.300) disconnects after
325 * resume of high speed peripherals (but not full
326 * speed ones).
327 */
328
329 musb->is_active = 1;
330 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
331 | MUSB_PORT_STAT_RESUME);
332 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
333 usb_hcd_poll_rh_status(musb_to_hcd(musb));
334 /* NOTE: it might really be A_WAIT_BCON ... */
335 musb->xceiv.state = OTG_STATE_A_HOST;
336 }
337
338 put_unaligned(cpu_to_le32(musb->port1_status
339 & ~MUSB_PORT_STAT_RESUME),
340 (__le32 *) buf);
341
342 /* port change status is more interesting */
343 DBG(get_unaligned((u16 *)(buf+2)) ? 2 : 5, "port status %08x\n",
344 musb->port1_status);
345 break;
346 case SetPortFeature:
347 if ((wIndex & 0xff) != 1)
348 goto error;
349
350 switch (wValue) {
351 case USB_PORT_FEAT_POWER:
352 /* NOTE: this controller has a strange state machine
353 * that involves "requesting sessions" according to
354 * magic side effects from incompletely-described
355 * rules about startup...
356 *
357 * This call is what really starts the host mode; be
358 * very careful about side effects if you reorder any
359 * initialization logic, e.g. for OTG, or change any
360 * logic relating to VBUS power-up.
361 */
362 if (!(is_otg_enabled(musb) && hcd->self.is_b_host))
363 musb_start(musb);
364 break;
365 case USB_PORT_FEAT_RESET:
366 musb_port_reset(musb, true);
367 break;
368 case USB_PORT_FEAT_SUSPEND:
369 musb_port_suspend(musb, true);
370 break;
371 case USB_PORT_FEAT_TEST:
372 if (unlikely(is_host_active(musb)))
373 goto error;
374
375 wIndex >>= 8;
376 switch (wIndex) {
377 case 1:
378 pr_debug("TEST_J\n");
379 temp = MUSB_TEST_J;
380 break;
381 case 2:
382 pr_debug("TEST_K\n");
383 temp = MUSB_TEST_K;
384 break;
385 case 3:
386 pr_debug("TEST_SE0_NAK\n");
387 temp = MUSB_TEST_SE0_NAK;
388 break;
389 case 4:
390 pr_debug("TEST_PACKET\n");
391 temp = MUSB_TEST_PACKET;
392 musb_load_testpacket(musb);
393 break;
394 case 5:
395 pr_debug("TEST_FORCE_ENABLE\n");
396 temp = MUSB_TEST_FORCE_HOST
397 | MUSB_TEST_FORCE_HS;
398
399 musb_writeb(musb->mregs, MUSB_DEVCTL,
400 MUSB_DEVCTL_SESSION);
401 break;
402 case 6:
403 pr_debug("TEST_FIFO_ACCESS\n");
404 temp = MUSB_TEST_FIFO_ACCESS;
405 break;
406 default:
407 goto error;
408 }
409 musb_writeb(musb->mregs, MUSB_TESTMODE, temp);
410 break;
411 default:
412 goto error;
413 }
414 DBG(5, "set feature %d\n", wValue);
415 musb->port1_status |= 1 << wValue;
416 break;
417
418 default:
419error:
420 /* "protocol stall" on error */
421 retval = -EPIPE;
422 }
423 spin_unlock_irqrestore(&musb->lock, flags);
424 return retval;
425}
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
new file mode 100644
index 000000000000..9ba8fb7fcd24
--- /dev/null
+++ b/drivers/usb/musb/musbhsdma.c
@@ -0,0 +1,433 @@
1/*
2 * MUSB OTG driver - support for Mentor's DMA controller
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33#include <linux/device.h>
34#include <linux/interrupt.h>
35#include <linux/platform_device.h>
36#include "musb_core.h"
37
38#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
39#include "omap2430.h"
40#endif
41
42#define MUSB_HSDMA_BASE 0x200
43#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
44#define MUSB_HSDMA_CONTROL 0x4
45#define MUSB_HSDMA_ADDRESS 0x8
46#define MUSB_HSDMA_COUNT 0xc
47
48#define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
49 (MUSB_HSDMA_BASE + (_bChannel << 4) + _offset)
50
51/* control register (16-bit): */
52#define MUSB_HSDMA_ENABLE_SHIFT 0
53#define MUSB_HSDMA_TRANSMIT_SHIFT 1
54#define MUSB_HSDMA_MODE1_SHIFT 2
55#define MUSB_HSDMA_IRQENABLE_SHIFT 3
56#define MUSB_HSDMA_ENDPOINT_SHIFT 4
57#define MUSB_HSDMA_BUSERROR_SHIFT 8
58#define MUSB_HSDMA_BURSTMODE_SHIFT 9
59#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
60#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
61#define MUSB_HSDMA_BURSTMODE_INCR4 1
62#define MUSB_HSDMA_BURSTMODE_INCR8 2
63#define MUSB_HSDMA_BURSTMODE_INCR16 3
64
65#define MUSB_HSDMA_CHANNELS 8
66
67struct musb_dma_controller;
68
69struct musb_dma_channel {
70 struct dma_channel Channel;
71 struct musb_dma_controller *controller;
72 u32 dwStartAddress;
73 u32 len;
74 u16 wMaxPacketSize;
75 u8 bIndex;
76 u8 epnum;
77 u8 transmit;
78};
79
80struct musb_dma_controller {
81 struct dma_controller Controller;
82 struct musb_dma_channel aChannel[MUSB_HSDMA_CHANNELS];
83 void *pDmaPrivate;
84 void __iomem *pCoreBase;
85 u8 bChannelCount;
86 u8 bmUsedChannels;
87 u8 irq;
88};
89
90static int dma_controller_start(struct dma_controller *c)
91{
92 /* nothing to do */
93 return 0;
94}
95
96static void dma_channel_release(struct dma_channel *pChannel);
97
98static int dma_controller_stop(struct dma_controller *c)
99{
100 struct musb_dma_controller *controller =
101 container_of(c, struct musb_dma_controller, Controller);
102 struct musb *musb = (struct musb *) controller->pDmaPrivate;
103 struct dma_channel *pChannel;
104 u8 bBit;
105
106 if (controller->bmUsedChannels != 0) {
107 dev_err(musb->controller,
108 "Stopping DMA controller while channel active\n");
109
110 for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
111 if (controller->bmUsedChannels & (1 << bBit)) {
112 pChannel = &controller->aChannel[bBit].Channel;
113 dma_channel_release(pChannel);
114
115 if (!controller->bmUsedChannels)
116 break;
117 }
118 }
119 }
120 return 0;
121}
122
123static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
124 struct musb_hw_ep *hw_ep, u8 transmit)
125{
126 u8 bBit;
127 struct dma_channel *pChannel = NULL;
128 struct musb_dma_channel *pImplChannel = NULL;
129 struct musb_dma_controller *controller =
130 container_of(c, struct musb_dma_controller, Controller);
131
132 for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
133 if (!(controller->bmUsedChannels & (1 << bBit))) {
134 controller->bmUsedChannels |= (1 << bBit);
135 pImplChannel = &(controller->aChannel[bBit]);
136 pImplChannel->controller = controller;
137 pImplChannel->bIndex = bBit;
138 pImplChannel->epnum = hw_ep->epnum;
139 pImplChannel->transmit = transmit;
140 pChannel = &(pImplChannel->Channel);
141 pChannel->private_data = pImplChannel;
142 pChannel->status = MUSB_DMA_STATUS_FREE;
143 pChannel->max_len = 0x10000;
144 /* Tx => mode 1; Rx => mode 0 */
145 pChannel->desired_mode = transmit;
146 pChannel->actual_len = 0;
147 break;
148 }
149 }
150 return pChannel;
151}
152
153static void dma_channel_release(struct dma_channel *pChannel)
154{
155 struct musb_dma_channel *pImplChannel =
156 (struct musb_dma_channel *) pChannel->private_data;
157
158 pChannel->actual_len = 0;
159 pImplChannel->dwStartAddress = 0;
160 pImplChannel->len = 0;
161
162 pImplChannel->controller->bmUsedChannels &=
163 ~(1 << pImplChannel->bIndex);
164
165 pChannel->status = MUSB_DMA_STATUS_UNKNOWN;
166}
167
168static void configure_channel(struct dma_channel *pChannel,
169 u16 packet_sz, u8 mode,
170 dma_addr_t dma_addr, u32 len)
171{
172 struct musb_dma_channel *pImplChannel =
173 (struct musb_dma_channel *) pChannel->private_data;
174 struct musb_dma_controller *controller = pImplChannel->controller;
175 void __iomem *mbase = controller->pCoreBase;
176 u8 bChannel = pImplChannel->bIndex;
177 u16 csr = 0;
178
179 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
180 pChannel, packet_sz, dma_addr, len, mode);
181
182 if (mode) {
183 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
184 BUG_ON(len < packet_sz);
185
186 if (packet_sz >= 64) {
187 csr |= MUSB_HSDMA_BURSTMODE_INCR16
188 << MUSB_HSDMA_BURSTMODE_SHIFT;
189 } else if (packet_sz >= 32) {
190 csr |= MUSB_HSDMA_BURSTMODE_INCR8
191 << MUSB_HSDMA_BURSTMODE_SHIFT;
192 } else if (packet_sz >= 16) {
193 csr |= MUSB_HSDMA_BURSTMODE_INCR4
194 << MUSB_HSDMA_BURSTMODE_SHIFT;
195 }
196 }
197
198 csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
199 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
200 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
201 | (pImplChannel->transmit
202 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
203 : 0);
204
205 /* address/count */
206 musb_writel(mbase,
207 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
208 dma_addr);
209 musb_writel(mbase,
210 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
211 len);
212
213 /* control (this should start things) */
214 musb_writew(mbase,
215 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
216 csr);
217}
218
219static int dma_channel_program(struct dma_channel *pChannel,
220 u16 packet_sz, u8 mode,
221 dma_addr_t dma_addr, u32 len)
222{
223 struct musb_dma_channel *pImplChannel =
224 (struct musb_dma_channel *) pChannel->private_data;
225
226 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
227 pImplChannel->epnum,
228 pImplChannel->transmit ? "Tx" : "Rx",
229 packet_sz, dma_addr, len, mode);
230
231 BUG_ON(pChannel->status == MUSB_DMA_STATUS_UNKNOWN ||
232 pChannel->status == MUSB_DMA_STATUS_BUSY);
233
234 pChannel->actual_len = 0;
235 pImplChannel->dwStartAddress = dma_addr;
236 pImplChannel->len = len;
237 pImplChannel->wMaxPacketSize = packet_sz;
238 pChannel->status = MUSB_DMA_STATUS_BUSY;
239
240 if ((mode == 1) && (len >= packet_sz))
241 configure_channel(pChannel, packet_sz, 1, dma_addr, len);
242 else
243 configure_channel(pChannel, packet_sz, 0, dma_addr, len);
244
245 return true;
246}
247
248static int dma_channel_abort(struct dma_channel *pChannel)
249{
250 struct musb_dma_channel *pImplChannel =
251 (struct musb_dma_channel *) pChannel->private_data;
252 u8 bChannel = pImplChannel->bIndex;
253 void __iomem *mbase = pImplChannel->controller->pCoreBase;
254 u16 csr;
255
256 if (pChannel->status == MUSB_DMA_STATUS_BUSY) {
257 if (pImplChannel->transmit) {
258
259 csr = musb_readw(mbase,
260 MUSB_EP_OFFSET(pImplChannel->epnum,
261 MUSB_TXCSR));
262 csr &= ~(MUSB_TXCSR_AUTOSET |
263 MUSB_TXCSR_DMAENAB |
264 MUSB_TXCSR_DMAMODE);
265 musb_writew(mbase,
266 MUSB_EP_OFFSET(pImplChannel->epnum,
267 MUSB_TXCSR),
268 csr);
269 } else {
270 csr = musb_readw(mbase,
271 MUSB_EP_OFFSET(pImplChannel->epnum,
272 MUSB_RXCSR));
273 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
274 MUSB_RXCSR_DMAENAB |
275 MUSB_RXCSR_DMAMODE);
276 musb_writew(mbase,
277 MUSB_EP_OFFSET(pImplChannel->epnum,
278 MUSB_RXCSR),
279 csr);
280 }
281
282 musb_writew(mbase,
283 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
284 0);
285 musb_writel(mbase,
286 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
287 0);
288 musb_writel(mbase,
289 MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
290 0);
291
292 pChannel->status = MUSB_DMA_STATUS_FREE;
293 }
294 return 0;
295}
296
297static irqreturn_t dma_controller_irq(int irq, void *private_data)
298{
299 struct musb_dma_controller *controller =
300 (struct musb_dma_controller *)private_data;
301 struct musb_dma_channel *pImplChannel;
302 struct musb *musb = controller->pDmaPrivate;
303 void __iomem *mbase = controller->pCoreBase;
304 struct dma_channel *pChannel;
305 u8 bChannel;
306 u16 csr;
307 u32 dwAddress;
308 u8 int_hsdma;
309 irqreturn_t retval = IRQ_NONE;
310 unsigned long flags;
311
312 spin_lock_irqsave(&musb->lock, flags);
313
314 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
315 if (!int_hsdma)
316 goto done;
317
318 for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) {
319 if (int_hsdma & (1 << bChannel)) {
320 pImplChannel = (struct musb_dma_channel *)
321 &(controller->aChannel[bChannel]);
322 pChannel = &pImplChannel->Channel;
323
324 csr = musb_readw(mbase,
325 MUSB_HSDMA_CHANNEL_OFFSET(bChannel,
326 MUSB_HSDMA_CONTROL));
327
328 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT))
329 pImplChannel->Channel.status =
330 MUSB_DMA_STATUS_BUS_ABORT;
331 else {
332 u8 devctl;
333
334 dwAddress = musb_readl(mbase,
335 MUSB_HSDMA_CHANNEL_OFFSET(
336 bChannel,
337 MUSB_HSDMA_ADDRESS));
338 pChannel->actual_len = dwAddress
339 - pImplChannel->dwStartAddress;
340
341 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
342 pChannel, pImplChannel->dwStartAddress,
343 dwAddress, pChannel->actual_len,
344 pImplChannel->len,
345 (pChannel->actual_len
346 < pImplChannel->len) ?
347 "=> reconfig 0" : "=> complete");
348
349 devctl = musb_readb(mbase, MUSB_DEVCTL);
350
351 pChannel->status = MUSB_DMA_STATUS_FREE;
352
353 /* completed */
354 if ((devctl & MUSB_DEVCTL_HM)
355 && (pImplChannel->transmit)
356 && ((pChannel->desired_mode == 0)
357 || (pChannel->actual_len &
358 (pImplChannel->wMaxPacketSize - 1)))
359 ) {
360 /* Send out the packet */
361 musb_ep_select(mbase,
362 pImplChannel->epnum);
363 musb_writew(mbase, MUSB_EP_OFFSET(
364 pImplChannel->epnum,
365 MUSB_TXCSR),
366 MUSB_TXCSR_TXPKTRDY);
367 } else
368 musb_dma_completion(
369 musb,
370 pImplChannel->epnum,
371 pImplChannel->transmit);
372 }
373 }
374 }
375 retval = IRQ_HANDLED;
376done:
377 spin_unlock_irqrestore(&musb->lock, flags);
378 return retval;
379}
380
381void dma_controller_destroy(struct dma_controller *c)
382{
383 struct musb_dma_controller *controller;
384
385 controller = container_of(c, struct musb_dma_controller, Controller);
386 if (!controller)
387 return;
388
389 if (controller->irq)
390 free_irq(controller->irq, c);
391
392 kfree(controller);
393}
394
395struct dma_controller *__init
396dma_controller_create(struct musb *musb, void __iomem *pCoreBase)
397{
398 struct musb_dma_controller *controller;
399 struct device *dev = musb->controller;
400 struct platform_device *pdev = to_platform_device(dev);
401 int irq = platform_get_irq(pdev, 1);
402
403 if (irq == 0) {
404 dev_err(dev, "No DMA interrupt line!\n");
405 return NULL;
406 }
407
408 controller = kzalloc(sizeof(struct musb_dma_controller), GFP_KERNEL);
409 if (!controller)
410 return NULL;
411
412 controller->bChannelCount = MUSB_HSDMA_CHANNELS;
413 controller->pDmaPrivate = musb;
414 controller->pCoreBase = pCoreBase;
415
416 controller->Controller.start = dma_controller_start;
417 controller->Controller.stop = dma_controller_stop;
418 controller->Controller.channel_alloc = dma_channel_allocate;
419 controller->Controller.channel_release = dma_channel_release;
420 controller->Controller.channel_program = dma_channel_program;
421 controller->Controller.channel_abort = dma_channel_abort;
422
423 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
424 musb->controller->bus_id, &controller->Controller)) {
425 dev_err(dev, "request_irq %d failed!\n", irq);
426 dma_controller_destroy(&controller->Controller);
427 return NULL;
428 }
429
430 controller->irq = irq;
431
432 return &controller->Controller;
433}
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
new file mode 100644
index 000000000000..298b22e6ad0d
--- /dev/null
+++ b/drivers/usb/musb/omap2430.c
@@ -0,0 +1,324 @@
1/*
2 * Copyright (C) 2005-2007 by Texas Instruments
3 * Some code has been taken from tusb6010.c
4 * Copyrights for that are attributable to:
5 * Copyright (C) 2006 Nokia Corporation
6 * Jarkko Nikula <jarkko.nikula@nokia.com>
7 * Tony Lindgren <tony@atomide.com>
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/init.h>
33#include <linux/list.h>
34#include <linux/clk.h>
35#include <linux/io.h>
36
37#include <asm/mach-types.h>
38#include <asm/arch/hardware.h>
39#include <asm/arch/mux.h>
40
41#include "musb_core.h"
42#include "omap2430.h"
43
44#ifdef CONFIG_ARCH_OMAP3430
45#define get_cpu_rev() 2
46#endif
47
48#define MUSB_TIMEOUT_A_WAIT_BCON 1100
49
50static struct timer_list musb_idle_timer;
51
52static void musb_do_idle(unsigned long _musb)
53{
54 struct musb *musb = (void *)_musb;
55 unsigned long flags;
56 u8 power;
57 u8 devctl;
58
59 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
60
61 spin_lock_irqsave(&musb->lock, flags);
62
63 switch (musb->xceiv.state) {
64 case OTG_STATE_A_WAIT_BCON:
65 devctl &= ~MUSB_DEVCTL_SESSION;
66 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
67
68 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
69 if (devctl & MUSB_DEVCTL_BDEVICE) {
70 musb->xceiv.state = OTG_STATE_B_IDLE;
71 MUSB_DEV_MODE(musb);
72 } else {
73 musb->xceiv.state = OTG_STATE_A_IDLE;
74 MUSB_HST_MODE(musb);
75 }
76 break;
77#ifdef CONFIG_USB_MUSB_HDRC_HCD
78 case OTG_STATE_A_SUSPEND:
79 /* finish RESUME signaling? */
80 if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
81 power = musb_readb(musb->mregs, MUSB_POWER);
82 power &= ~MUSB_POWER_RESUME;
83 DBG(1, "root port resume stopped, power %02x\n", power);
84 musb_writeb(musb->mregs, MUSB_POWER, power);
85 musb->is_active = 1;
86 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
87 | MUSB_PORT_STAT_RESUME);
88 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
89 usb_hcd_poll_rh_status(musb_to_hcd(musb));
90 /* NOTE: it might really be A_WAIT_BCON ... */
91 musb->xceiv.state = OTG_STATE_A_HOST;
92 }
93 break;
94#endif
95#ifdef CONFIG_USB_MUSB_HDRC_HCD
96 case OTG_STATE_A_HOST:
97 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
98 if (devctl & MUSB_DEVCTL_BDEVICE)
99 musb->xceiv.state = OTG_STATE_B_IDLE;
100 else
101 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
102#endif
103 default:
104 break;
105 }
106 spin_unlock_irqrestore(&musb->lock, flags);
107}
108
109
110void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
111{
112 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
113 static unsigned long last_timer;
114
115 if (timeout == 0)
116 timeout = default_timeout;
117
118 /* Never idle if active, or when VBUS timeout is not set as host */
119 if (musb->is_active || ((musb->a_wait_bcon == 0)
120 && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
121 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
122 del_timer(&musb_idle_timer);
123 last_timer = jiffies;
124 return;
125 }
126
127 if (time_after(last_timer, timeout)) {
128 if (!timer_pending(&musb_idle_timer))
129 last_timer = timeout;
130 else {
131 DBG(4, "Longer idle timer already pending, ignoring\n");
132 return;
133 }
134 }
135 last_timer = timeout;
136
137 DBG(4, "%s inactive, for idle timer for %lu ms\n",
138 otg_state_string(musb),
139 (unsigned long)jiffies_to_msecs(timeout - jiffies));
140 mod_timer(&musb_idle_timer, timeout);
141}
142
143void musb_platform_enable(struct musb *musb)
144{
145}
146void musb_platform_disable(struct musb *musb)
147{
148}
149static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
150{
151}
152
153static void omap_set_vbus(struct musb *musb, int is_on)
154{
155 u8 devctl;
156 /* HDRC controls CPEN, but beware current surges during device
157 * connect. They can trigger transient overcurrent conditions
158 * that must be ignored.
159 */
160
161 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
162
163 if (is_on) {
164 musb->is_active = 1;
165 musb->xceiv.default_a = 1;
166 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
167 devctl |= MUSB_DEVCTL_SESSION;
168
169 MUSB_HST_MODE(musb);
170 } else {
171 musb->is_active = 0;
172
173 /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
174 * jumping right to B_IDLE...
175 */
176
177 musb->xceiv.default_a = 0;
178 musb->xceiv.state = OTG_STATE_B_IDLE;
179 devctl &= ~MUSB_DEVCTL_SESSION;
180
181 MUSB_DEV_MODE(musb);
182 }
183 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
184
185 DBG(1, "VBUS %s, devctl %02x "
186 /* otg %3x conf %08x prcm %08x */ "\n",
187 otg_state_string(musb),
188 musb_readb(musb->mregs, MUSB_DEVCTL));
189}
190static int omap_set_power(struct otg_transceiver *x, unsigned mA)
191{
192 return 0;
193}
194
195static int musb_platform_resume(struct musb *musb);
196
197void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
198{
199 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
200
201 devctl |= MUSB_DEVCTL_SESSION;
202 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
203
204 switch (musb_mode) {
205 case MUSB_HOST:
206 otg_set_host(&musb->xceiv, musb->xceiv.host);
207 break;
208 case MUSB_PERIPHERAL:
209 otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
210 break;
211 case MUSB_OTG:
212 break;
213 }
214}
215
216int __init musb_platform_init(struct musb *musb)
217{
218 u32 l;
219
220#if defined(CONFIG_ARCH_OMAP2430)
221 omap_cfg_reg(AE5_2430_USB0HS_STP);
222#endif
223
224 musb_platform_resume(musb);
225
226 l = omap_readl(OTG_SYSCONFIG);
227 l &= ~ENABLEWAKEUP; /* disable wakeup */
228 l &= ~NOSTDBY; /* remove possible nostdby */
229 l |= SMARTSTDBY; /* enable smart standby */
230 l &= ~AUTOIDLE; /* disable auto idle */
231 l &= ~NOIDLE; /* remove possible noidle */
232 l |= SMARTIDLE; /* enable smart idle */
233 l |= AUTOIDLE; /* enable auto idle */
234 omap_writel(l, OTG_SYSCONFIG);
235
236 l = omap_readl(OTG_INTERFSEL);
237 l |= ULPI_12PIN;
238 omap_writel(l, OTG_INTERFSEL);
239
240 pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
241 "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
242 omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG),
243 omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL),
244 omap_readl(OTG_SIMENABLE));
245
246 omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
247
248 if (is_host_enabled(musb))
249 musb->board_set_vbus = omap_set_vbus;
250 if (is_peripheral_enabled(musb))
251 musb->xceiv.set_power = omap_set_power;
252 musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
253
254 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
255
256 return 0;
257}
258
259int musb_platform_suspend(struct musb *musb)
260{
261 u32 l;
262
263 if (!musb->clock)
264 return 0;
265
266 /* in any role */
267 l = omap_readl(OTG_FORCESTDBY);
268 l |= ENABLEFORCE; /* enable MSTANDBY */
269 omap_writel(l, OTG_FORCESTDBY);
270
271 l = omap_readl(OTG_SYSCONFIG);
272 l |= ENABLEWAKEUP; /* enable wakeup */
273 omap_writel(l, OTG_SYSCONFIG);
274
275 if (musb->xceiv.set_suspend)
276 musb->xceiv.set_suspend(&musb->xceiv, 1);
277
278 if (musb->set_clock)
279 musb->set_clock(musb->clock, 0);
280 else
281 clk_disable(musb->clock);
282
283 return 0;
284}
285
286static int musb_platform_resume(struct musb *musb)
287{
288 u32 l;
289
290 if (!musb->clock)
291 return 0;
292
293 if (musb->xceiv.set_suspend)
294 musb->xceiv.set_suspend(&musb->xceiv, 0);
295
296 if (musb->set_clock)
297 musb->set_clock(musb->clock, 1);
298 else
299 clk_enable(musb->clock);
300
301 l = omap_readl(OTG_SYSCONFIG);
302 l &= ~ENABLEWAKEUP; /* disable wakeup */
303 omap_writel(l, OTG_SYSCONFIG);
304
305 l = omap_readl(OTG_FORCESTDBY);
306 l &= ~ENABLEFORCE; /* disable MSTANDBY */
307 omap_writel(l, OTG_FORCESTDBY);
308
309 return 0;
310}
311
312
313int musb_platform_exit(struct musb *musb)
314{
315
316 omap_vbus_power(musb, 0 /*off*/, 1);
317
318 musb_platform_suspend(musb);
319
320 clk_put(musb->clock);
321 musb->clock = 0;
322
323 return 0;
324}
diff --git a/drivers/usb/musb/omap2430.h b/drivers/usb/musb/omap2430.h
new file mode 100644
index 000000000000..786a62071f72
--- /dev/null
+++ b/drivers/usb/musb/omap2430.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * The Inventra Controller Driver for Linux is free software; you
5 * can redistribute it and/or modify it under the terms of the GNU
6 * General Public License version 2 as published by the Free Software
7 * Foundation.
8 */
9
10#ifndef __MUSB_OMAP243X_H__
11#define __MUSB_OMAP243X_H__
12
13#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
14#include <asm/arch/hardware.h>
15#include <asm/arch/usb.h>
16
17/*
18 * OMAP2430-specific definitions
19 */
20
21#define MENTOR_BASE_OFFSET 0
22#if defined(CONFIG_ARCH_OMAP2430)
23#define OMAP_HSOTG_BASE (OMAP243X_HS_BASE)
24#elif defined(CONFIG_ARCH_OMAP3430)
25#define OMAP_HSOTG_BASE (OMAP34XX_HSUSB_OTG_BASE)
26#endif
27#define OMAP_HSOTG(offset) (OMAP_HSOTG_BASE + 0x400 + (offset))
28#define OTG_REVISION OMAP_HSOTG(0x0)
29#define OTG_SYSCONFIG OMAP_HSOTG(0x4)
30# define MIDLEMODE 12 /* bit position */
31# define FORCESTDBY (0 << MIDLEMODE)
32# define NOSTDBY (1 << MIDLEMODE)
33# define SMARTSTDBY (2 << MIDLEMODE)
34# define SIDLEMODE 3 /* bit position */
35# define FORCEIDLE (0 << SIDLEMODE)
36# define NOIDLE (1 << SIDLEMODE)
37# define SMARTIDLE (2 << SIDLEMODE)
38# define ENABLEWAKEUP (1 << 2)
39# define SOFTRST (1 << 1)
40# define AUTOIDLE (1 << 0)
41#define OTG_SYSSTATUS OMAP_HSOTG(0x8)
42# define RESETDONE (1 << 0)
43#define OTG_INTERFSEL OMAP_HSOTG(0xc)
44# define EXTCP (1 << 2)
45# define PHYSEL 0 /* bit position */
46# define UTMI_8BIT (0 << PHYSEL)
47# define ULPI_12PIN (1 << PHYSEL)
48# define ULPI_8PIN (2 << PHYSEL)
49#define OTG_SIMENABLE OMAP_HSOTG(0x10)
50# define TM1 (1 << 0)
51#define OTG_FORCESTDBY OMAP_HSOTG(0x14)
52# define ENABLEFORCE (1 << 0)
53
54#endif /* CONFIG_ARCH_OMAP2430 */
55
56#endif /* __MUSB_OMAP243X_H__ */
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
new file mode 100644
index 000000000000..b73b036f3d77
--- /dev/null
+++ b/drivers/usb/musb/tusb6010.c
@@ -0,0 +1,1151 @@
1/*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Jarkko Nikula <jarkko.nikula@nokia.com>
6 * Tony Lindgren <tony@atomide.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Notes:
13 * - Driver assumes that interface to external host (main CPU) is
14 * configured for NOR FLASH interface instead of VLYNQ serial
15 * interface.
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/usb.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25
26#include "musb_core.h"
27
28static void tusb_source_power(struct musb *musb, int is_on);
29
30#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
31#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
32
33/*
34 * Checks the revision. We need to use the DMA register as 3.0 does not
35 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
36 */
37u8 tusb_get_revision(struct musb *musb)
38{
39 void __iomem *tbase = musb->ctrl_base;
40 u32 die_id;
41 u8 rev;
42
43 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
44 if (TUSB_REV_MAJOR(rev) == 3) {
45 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
46 TUSB_DIDR1_HI));
47 if (die_id >= TUSB_DIDR1_HI_REV_31)
48 rev |= 1;
49 }
50
51 return rev;
52}
53
54static int __init tusb_print_revision(struct musb *musb)
55{
56 void __iomem *tbase = musb->ctrl_base;
57 u8 rev;
58
59 rev = tusb_get_revision(musb);
60
61 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
62 "prcm",
63 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
64 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
65 "int",
66 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
67 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
68 "gpio",
69 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
70 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
71 "dma",
72 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
73 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
74 "dieid",
75 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
76 "rev",
77 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
78
79 return tusb_get_revision(musb);
80}
81
82#define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
83 | TUSB_PHY_OTG_CTRL_TESTM0)
84
85/*
86 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
87 * Disables power detection in PHY for the duration of idle.
88 */
89static void tusb_wbus_quirk(struct musb *musb, int enabled)
90{
91 void __iomem *tbase = musb->ctrl_base;
92 static u32 phy_otg_ctrl, phy_otg_ena;
93 u32 tmp;
94
95 if (enabled) {
96 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
97 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
98 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
99 | phy_otg_ena | WBUS_QUIRK_MASK;
100 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
101 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
102 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
103 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
104 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
105 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
106 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
107 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
108 & TUSB_PHY_OTG_CTRL_TESTM2) {
109 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
110 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
111 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
112 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
113 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
114 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
115 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
116 phy_otg_ctrl = 0;
117 phy_otg_ena = 0;
118 }
119}
120
121/*
122 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
123 * so both loading and unloading FIFOs need explicit byte counts.
124 */
125
126static inline void
127tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
128{
129 u32 val;
130 int i;
131
132 if (len > 4) {
133 for (i = 0; i < (len >> 2); i++) {
134 memcpy(&val, buf, 4);
135 musb_writel(fifo, 0, val);
136 buf += 4;
137 }
138 len %= 4;
139 }
140 if (len > 0) {
141 /* Write the rest 1 - 3 bytes to FIFO */
142 memcpy(&val, buf, len);
143 musb_writel(fifo, 0, val);
144 }
145}
146
147static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
148 void __iomem *buf, u16 len)
149{
150 u32 val;
151 int i;
152
153 if (len > 4) {
154 for (i = 0; i < (len >> 2); i++) {
155 val = musb_readl(fifo, 0);
156 memcpy(buf, &val, 4);
157 buf += 4;
158 }
159 len %= 4;
160 }
161 if (len > 0) {
162 /* Read the rest 1 - 3 bytes from FIFO */
163 val = musb_readl(fifo, 0);
164 memcpy(buf, &val, len);
165 }
166}
167
168void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
169{
170 void __iomem *ep_conf = hw_ep->conf;
171 void __iomem *fifo = hw_ep->fifo;
172 u8 epnum = hw_ep->epnum;
173
174 prefetch(buf);
175
176 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
177 'T', epnum, fifo, len, buf);
178
179 if (epnum)
180 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
181 TUSB_EP_CONFIG_XFR_SIZE(len));
182 else
183 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
184 TUSB_EP0_CONFIG_XFR_SIZE(len));
185
186 if (likely((0x01 & (unsigned long) buf) == 0)) {
187
188 /* Best case is 32bit-aligned destination address */
189 if ((0x02 & (unsigned long) buf) == 0) {
190 if (len >= 4) {
191 writesl(fifo, buf, len >> 2);
192 buf += (len & ~0x03);
193 len &= 0x03;
194 }
195 } else {
196 if (len >= 2) {
197 u32 val;
198 int i;
199
200 /* Cannot use writesw, fifo is 32-bit */
201 for (i = 0; i < (len >> 2); i++) {
202 val = (u32)(*(u16 *)buf);
203 buf += 2;
204 val |= (*(u16 *)buf) << 16;
205 buf += 2;
206 musb_writel(fifo, 0, val);
207 }
208 len &= 0x03;
209 }
210 }
211 }
212
213 if (len > 0)
214 tusb_fifo_write_unaligned(fifo, buf, len);
215}
216
217void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
218{
219 void __iomem *ep_conf = hw_ep->conf;
220 void __iomem *fifo = hw_ep->fifo;
221 u8 epnum = hw_ep->epnum;
222
223 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
224 'R', epnum, fifo, len, buf);
225
226 if (epnum)
227 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
228 TUSB_EP_CONFIG_XFR_SIZE(len));
229 else
230 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
231
232 if (likely((0x01 & (unsigned long) buf) == 0)) {
233
234 /* Best case is 32bit-aligned destination address */
235 if ((0x02 & (unsigned long) buf) == 0) {
236 if (len >= 4) {
237 readsl(fifo, buf, len >> 2);
238 buf += (len & ~0x03);
239 len &= 0x03;
240 }
241 } else {
242 if (len >= 2) {
243 u32 val;
244 int i;
245
246 /* Cannot use readsw, fifo is 32-bit */
247 for (i = 0; i < (len >> 2); i++) {
248 val = musb_readl(fifo, 0);
249 *(u16 *)buf = (u16)(val & 0xffff);
250 buf += 2;
251 *(u16 *)buf = (u16)(val >> 16);
252 buf += 2;
253 }
254 len &= 0x03;
255 }
256 }
257 }
258
259 if (len > 0)
260 tusb_fifo_read_unaligned(fifo, buf, len);
261}
262
263#ifdef CONFIG_USB_GADGET_MUSB_HDRC
264
265/* This is used by gadget drivers, and OTG transceiver logic, allowing
266 * at most mA current to be drawn from VBUS during a Default-B session
267 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
268 * mode), or low power Default-B sessions, something else supplies power.
269 * Caller must take care of locking.
270 */
271static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
272{
273 struct musb *musb = container_of(x, struct musb, xceiv);
274 void __iomem *tbase = musb->ctrl_base;
275 u32 reg;
276
277 /*
278 * Keep clock active when enabled. Note that this is not tied to
279 * drawing VBUS, as with OTG mA can be less than musb->min_power.
280 */
281 if (musb->set_clock) {
282 if (mA)
283 musb->set_clock(musb->clock, 1);
284 else
285 musb->set_clock(musb->clock, 0);
286 }
287
288 /* tps65030 seems to consume max 100mA, with maybe 60mA available
289 * (measured on one board) for things other than tps and tusb.
290 *
291 * Boards sharing the CPU clock with CLKIN will need to prevent
292 * certain idle sleep states while the USB link is active.
293 *
294 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
295 * The actual current usage would be very board-specific. For now,
296 * it's simpler to just use an aggregate (also board-specific).
297 */
298 if (x->default_a || mA < (musb->min_power << 1))
299 mA = 0;
300
301 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
302 if (mA) {
303 musb->is_bus_powered = 1;
304 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
305 } else {
306 musb->is_bus_powered = 0;
307 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
308 }
309 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
310
311 DBG(2, "draw max %d mA VBUS\n", mA);
312 return 0;
313}
314
315#else
316#define tusb_draw_power NULL
317#endif
318
319/* workaround for issue 13: change clock during chip idle
320 * (to be fixed in rev3 silicon) ... symptoms include disconnect
321 * or looping suspend/resume cycles
322 */
323static void tusb_set_clock_source(struct musb *musb, unsigned mode)
324{
325 void __iomem *tbase = musb->ctrl_base;
326 u32 reg;
327
328 reg = musb_readl(tbase, TUSB_PRCM_CONF);
329 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
330
331 /* 0 = refclk (clkin, XI)
332 * 1 = PHY 60 MHz (internal PLL)
333 * 2 = not supported
334 * 3 = what?
335 */
336 if (mode > 0)
337 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
338
339 musb_writel(tbase, TUSB_PRCM_CONF, reg);
340
341 /* FIXME tusb6010_platform_retime(mode == 0); */
342}
343
344/*
345 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
346 * Other code ensures that we idle unless we're connected _and_ the
347 * USB link is not suspended ... and tells us the relevant wakeup
348 * events. SW_EN for voltage is handled separately.
349 */
350void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
351{
352 void __iomem *tbase = musb->ctrl_base;
353 u32 reg;
354
355 if ((wakeup_enables & TUSB_PRCM_WBUS)
356 && (tusb_get_revision(musb) == TUSB_REV_30))
357 tusb_wbus_quirk(musb, 1);
358
359 tusb_set_clock_source(musb, 0);
360
361 wakeup_enables |= TUSB_PRCM_WNORCS;
362 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
363
364 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
365 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
366 * Presumably that's mostly to save power, hence WID is immaterial ...
367 */
368
369 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
370 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
371 if (is_host_active(musb)) {
372 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
373 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
374 } else {
375 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
376 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
377 }
378 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
379 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
380
381 DBG(6, "idle, wake on %02x\n", wakeup_enables);
382}
383
384/*
385 * Updates cable VBUS status. Caller must take care of locking.
386 */
387int musb_platform_get_vbus_status(struct musb *musb)
388{
389 void __iomem *tbase = musb->ctrl_base;
390 u32 otg_stat, prcm_mngmt;
391 int ret = 0;
392
393 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
394 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
395
396 /* Temporarily enable VBUS detection if it was disabled for
397 * suspend mode. Unless it's enabled otg_stat and devctl will
398 * not show correct VBUS state.
399 */
400 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
401 u32 tmp = prcm_mngmt;
402 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
403 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
404 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
405 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
406 }
407
408 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
409 ret = 1;
410
411 return ret;
412}
413
414static struct timer_list musb_idle_timer;
415
416static void musb_do_idle(unsigned long _musb)
417{
418 struct musb *musb = (void *)_musb;
419 unsigned long flags;
420
421 spin_lock_irqsave(&musb->lock, flags);
422
423 switch (musb->xceiv.state) {
424 case OTG_STATE_A_WAIT_BCON:
425 if ((musb->a_wait_bcon != 0)
426 && (musb->idle_timeout == 0
427 || time_after(jiffies, musb->idle_timeout))) {
428 DBG(4, "Nothing connected %s, turning off VBUS\n",
429 otg_state_string(musb));
430 }
431 /* FALLTHROUGH */
432 case OTG_STATE_A_IDLE:
433 tusb_source_power(musb, 0);
434 default:
435 break;
436 }
437
438 if (!musb->is_active) {
439 u32 wakeups;
440
441 /* wait until khubd handles port change status */
442 if (is_host_active(musb) && (musb->port1_status >> 16))
443 goto done;
444
445#ifdef CONFIG_USB_GADGET_MUSB_HDRC
446 if (is_peripheral_enabled(musb) && !musb->gadget_driver)
447 wakeups = 0;
448 else {
449 wakeups = TUSB_PRCM_WHOSTDISCON
450 | TUSB_PRCM_WBUS
451 | TUSB_PRCM_WVBUS;
452 if (is_otg_enabled(musb))
453 wakeups |= TUSB_PRCM_WID;
454 }
455#else
456 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
457#endif
458 tusb_allow_idle(musb, wakeups);
459 }
460done:
461 spin_unlock_irqrestore(&musb->lock, flags);
462}
463
464/*
465 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
466 * like "disconnected" or "suspended". We'll be woken out of it by
467 * connect, resume, or disconnect.
468 *
469 * Needs to be called as the last function everywhere where there is
470 * register access to TUSB6010 because of NOR flash wake-up.
471 * Caller should own controller spinlock.
472 *
473 * Delay because peripheral enables D+ pullup 3msec after SE0, and
474 * we don't want to treat that full speed J as a wakeup event.
475 * ... peripherals must draw only suspend current after 10 msec.
476 */
477void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
478{
479 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
480 static unsigned long last_timer;
481
482 if (timeout == 0)
483 timeout = default_timeout;
484
485 /* Never idle if active, or when VBUS timeout is not set as host */
486 if (musb->is_active || ((musb->a_wait_bcon == 0)
487 && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
488 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
489 del_timer(&musb_idle_timer);
490 last_timer = jiffies;
491 return;
492 }
493
494 if (time_after(last_timer, timeout)) {
495 if (!timer_pending(&musb_idle_timer))
496 last_timer = timeout;
497 else {
498 DBG(4, "Longer idle timer already pending, ignoring\n");
499 return;
500 }
501 }
502 last_timer = timeout;
503
504 DBG(4, "%s inactive, for idle timer for %lu ms\n",
505 otg_state_string(musb),
506 (unsigned long)jiffies_to_msecs(timeout - jiffies));
507 mod_timer(&musb_idle_timer, timeout);
508}
509
510/* ticks of 60 MHz clock */
511#define DEVCLOCK 60000000
512#define OTG_TIMER_MS(msecs) ((msecs) \
513 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
514 | TUSB_DEV_OTG_TIMER_ENABLE) \
515 : 0)
516
517static void tusb_source_power(struct musb *musb, int is_on)
518{
519 void __iomem *tbase = musb->ctrl_base;
520 u32 conf, prcm, timer;
521 u8 devctl;
522
523 /* HDRC controls CPEN, but beware current surges during device
524 * connect. They can trigger transient overcurrent conditions
525 * that must be ignored.
526 */
527
528 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
529 conf = musb_readl(tbase, TUSB_DEV_CONF);
530 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
531
532 if (is_on) {
533 if (musb->set_clock)
534 musb->set_clock(musb->clock, 1);
535 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
536 musb->xceiv.default_a = 1;
537 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
538 devctl |= MUSB_DEVCTL_SESSION;
539
540 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
541 MUSB_HST_MODE(musb);
542 } else {
543 u32 otg_stat;
544
545 timer = 0;
546
547 /* If ID pin is grounded, we want to be a_idle */
548 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
549 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
550 switch (musb->xceiv.state) {
551 case OTG_STATE_A_WAIT_VRISE:
552 case OTG_STATE_A_WAIT_BCON:
553 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
554 break;
555 case OTG_STATE_A_WAIT_VFALL:
556 musb->xceiv.state = OTG_STATE_A_IDLE;
557 break;
558 default:
559 musb->xceiv.state = OTG_STATE_A_IDLE;
560 }
561 musb->is_active = 0;
562 musb->xceiv.default_a = 1;
563 MUSB_HST_MODE(musb);
564 } else {
565 musb->is_active = 0;
566 musb->xceiv.default_a = 0;
567 musb->xceiv.state = OTG_STATE_B_IDLE;
568 MUSB_DEV_MODE(musb);
569 }
570
571 devctl &= ~MUSB_DEVCTL_SESSION;
572 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
573 if (musb->set_clock)
574 musb->set_clock(musb->clock, 0);
575 }
576 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
577
578 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
579 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
580 musb_writel(tbase, TUSB_DEV_CONF, conf);
581 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
582
583 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
584 otg_state_string(musb),
585 musb_readb(musb->mregs, MUSB_DEVCTL),
586 musb_readl(tbase, TUSB_DEV_OTG_STAT),
587 conf, prcm);
588}
589
590/*
591 * Sets the mode to OTG, peripheral or host by changing the ID detection.
592 * Caller must take care of locking.
593 *
594 * Note that if a mini-A cable is plugged in the ID line will stay down as
595 * the weak ID pull-up is not able to pull the ID up.
596 *
597 * REVISIT: It would be possible to add support for changing between host
598 * and peripheral modes in non-OTG configurations by reconfiguring hardware
599 * and then setting musb->board_mode. For now, only support OTG mode.
600 */
601void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
602{
603 void __iomem *tbase = musb->ctrl_base;
604 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
605
606 if (musb->board_mode != MUSB_OTG) {
607 ERR("Changing mode currently only supported in OTG mode\n");
608 return;
609 }
610
611 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
612 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
613 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
614 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
615
616 switch (musb_mode) {
617
618#ifdef CONFIG_USB_MUSB_HDRC_HCD
619 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
620 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
621 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
622 dev_conf |= TUSB_DEV_CONF_ID_SEL;
623 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
624 break;
625#endif
626
627#ifdef CONFIG_USB_GADGET_MUSB_HDRC
628 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
629 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
630 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
631 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
632 break;
633#endif
634
635#ifdef CONFIG_USB_MUSB_OTG
636 case MUSB_OTG: /* Use PHY ID detection */
637 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
638 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
639 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
640 break;
641#endif
642
643 default:
644 DBG(2, "Trying to set unknown mode %i\n", musb_mode);
645 }
646
647 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
648 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
649 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
650 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
651 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
652
653 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
654 if ((musb_mode == MUSB_PERIPHERAL) &&
655 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
656 INFO("Cannot be peripheral with mini-A cable "
657 "otg_stat: %08x\n", otg_stat);
658}
659
660static inline unsigned long
661tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
662{
663 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
664 unsigned long idle_timeout = 0;
665
666 /* ID pin */
667 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
668 int default_a;
669
670 if (is_otg_enabled(musb))
671 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
672 else
673 default_a = is_host_enabled(musb);
674 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
675 musb->xceiv.default_a = default_a;
676 tusb_source_power(musb, default_a);
677
678 /* Don't allow idling immediately */
679 if (default_a)
680 idle_timeout = jiffies + (HZ * 3);
681 }
682
683 /* VBUS state change */
684 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
685
686 /* B-dev state machine: no vbus ~= disconnect */
687 if ((is_otg_enabled(musb) && !musb->xceiv.default_a)
688 || !is_host_enabled(musb)) {
689#ifdef CONFIG_USB_MUSB_HDRC_HCD
690 /* ? musb_root_disconnect(musb); */
691 musb->port1_status &=
692 ~(USB_PORT_STAT_CONNECTION
693 | USB_PORT_STAT_ENABLE
694 | USB_PORT_STAT_LOW_SPEED
695 | USB_PORT_STAT_HIGH_SPEED
696 | USB_PORT_STAT_TEST
697 );
698#endif
699
700 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
701 DBG(1, "Forcing disconnect (no interrupt)\n");
702 if (musb->xceiv.state != OTG_STATE_B_IDLE) {
703 /* INTR_DISCONNECT can hide... */
704 musb->xceiv.state = OTG_STATE_B_IDLE;
705 musb->int_usb |= MUSB_INTR_DISCONNECT;
706 }
707 musb->is_active = 0;
708 }
709 DBG(2, "vbus change, %s, otg %03x\n",
710 otg_state_string(musb), otg_stat);
711 idle_timeout = jiffies + (1 * HZ);
712 schedule_work(&musb->irq_work);
713
714 } else /* A-dev state machine */ {
715 DBG(2, "vbus change, %s, otg %03x\n",
716 otg_state_string(musb), otg_stat);
717
718 switch (musb->xceiv.state) {
719 case OTG_STATE_A_IDLE:
720 DBG(2, "Got SRP, turning on VBUS\n");
721 musb_set_vbus(musb, 1);
722
723 /* CONNECT can wake if a_wait_bcon is set */
724 if (musb->a_wait_bcon != 0)
725 musb->is_active = 0;
726 else
727 musb->is_active = 1;
728
729 /*
730 * OPT FS A TD.4.6 needs few seconds for
731 * A_WAIT_VRISE
732 */
733 idle_timeout = jiffies + (2 * HZ);
734
735 break;
736 case OTG_STATE_A_WAIT_VRISE:
737 /* ignore; A-session-valid < VBUS_VALID/2,
738 * we monitor this with the timer
739 */
740 break;
741 case OTG_STATE_A_WAIT_VFALL:
742 /* REVISIT this irq triggers during short
743 * spikes caused by enumeration ...
744 */
745 if (musb->vbuserr_retry) {
746 musb->vbuserr_retry--;
747 tusb_source_power(musb, 1);
748 } else {
749 musb->vbuserr_retry
750 = VBUSERR_RETRY_COUNT;
751 tusb_source_power(musb, 0);
752 }
753 break;
754 default:
755 break;
756 }
757 }
758 }
759
760 /* OTG timer expiration */
761 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
762 u8 devctl;
763
764 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
765
766 switch (musb->xceiv.state) {
767 case OTG_STATE_A_WAIT_VRISE:
768 /* VBUS has probably been valid for a while now,
769 * but may well have bounced out of range a bit
770 */
771 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
772 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
773 if ((devctl & MUSB_DEVCTL_VBUS)
774 != MUSB_DEVCTL_VBUS) {
775 DBG(2, "devctl %02x\n", devctl);
776 break;
777 }
778 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
779 musb->is_active = 0;
780 idle_timeout = jiffies
781 + msecs_to_jiffies(musb->a_wait_bcon);
782 } else {
783 /* REVISIT report overcurrent to hub? */
784 ERR("vbus too slow, devctl %02x\n", devctl);
785 tusb_source_power(musb, 0);
786 }
787 break;
788 case OTG_STATE_A_WAIT_BCON:
789 if (musb->a_wait_bcon != 0)
790 idle_timeout = jiffies
791 + msecs_to_jiffies(musb->a_wait_bcon);
792 break;
793 case OTG_STATE_A_SUSPEND:
794 break;
795 case OTG_STATE_B_WAIT_ACON:
796 break;
797 default:
798 break;
799 }
800 }
801 schedule_work(&musb->irq_work);
802
803 return idle_timeout;
804}
805
806static irqreturn_t tusb_interrupt(int irq, void *__hci)
807{
808 struct musb *musb = __hci;
809 void __iomem *tbase = musb->ctrl_base;
810 unsigned long flags, idle_timeout = 0;
811 u32 int_mask, int_src;
812
813 spin_lock_irqsave(&musb->lock, flags);
814
815 /* Mask all interrupts to allow using both edge and level GPIO irq */
816 int_mask = musb_readl(tbase, TUSB_INT_MASK);
817 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
818
819 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
820 DBG(3, "TUSB IRQ %08x\n", int_src);
821
822 musb->int_usb = (u8) int_src;
823
824 /* Acknowledge wake-up source interrupts */
825 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
826 u32 reg;
827 u32 i;
828
829 if (tusb_get_revision(musb) == TUSB_REV_30)
830 tusb_wbus_quirk(musb, 0);
831
832 /* there are issues re-locking the PLL on wakeup ... */
833
834 /* work around issue 8 */
835 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
836 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
837 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
838 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
839 if (reg == i)
840 break;
841 DBG(6, "TUSB NOR not ready\n");
842 }
843
844 /* work around issue 13 (2nd half) */
845 tusb_set_clock_source(musb, 1);
846
847 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
848 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
849 if (reg & ~TUSB_PRCM_WNORCS) {
850 musb->is_active = 1;
851 schedule_work(&musb->irq_work);
852 }
853 DBG(3, "wake %sactive %02x\n",
854 musb->is_active ? "" : "in", reg);
855
856 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
857 }
858
859 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
860 del_timer(&musb_idle_timer);
861
862 /* OTG state change reports (annoyingly) not issued by Mentor core */
863 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
864 | TUSB_INT_SRC_OTG_TIMEOUT
865 | TUSB_INT_SRC_ID_STATUS_CHNG))
866 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
867
868 /* TX dma callback must be handled here, RX dma callback is
869 * handled in tusb_omap_dma_cb.
870 */
871 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
872 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
873 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
874
875 DBG(3, "DMA IRQ %08x\n", dma_src);
876 real_dma_src = ~real_dma_src & dma_src;
877 if (tusb_dma_omap() && real_dma_src) {
878 int tx_source = (real_dma_src & 0xffff);
879 int i;
880
881 for (i = 1; i <= 15; i++) {
882 if (tx_source & (1 << i)) {
883 DBG(3, "completing ep%i %s\n", i, "tx");
884 musb_dma_completion(musb, i, 1);
885 }
886 }
887 }
888 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
889 }
890
891 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
892 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
893 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
894
895 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
896 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
897 musb->int_tx = (musb_src & 0xffff);
898 } else {
899 musb->int_rx = 0;
900 musb->int_tx = 0;
901 }
902
903 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
904 musb_interrupt(musb);
905
906 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
907 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
908 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
909
910 musb_platform_try_idle(musb, idle_timeout);
911
912 musb_writel(tbase, TUSB_INT_MASK, int_mask);
913 spin_unlock_irqrestore(&musb->lock, flags);
914
915 return IRQ_HANDLED;
916}
917
918static int dma_off;
919
920/*
921 * Enables TUSB6010. Caller must take care of locking.
922 * REVISIT:
923 * - Check what is unnecessary in MGC_HdrcStart()
924 */
925void musb_platform_enable(struct musb *musb)
926{
927 void __iomem *tbase = musb->ctrl_base;
928
929 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
930 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
931 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
932
933 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
934 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
935 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
936 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
937
938 /* Clear all subsystem interrups */
939 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
940 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
941 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
942
943 /* Acknowledge pending interrupt(s) */
944 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
945
946 /* Only 0 clock cycles for minimum interrupt de-assertion time and
947 * interrupt polarity active low seems to work reliably here */
948 musb_writel(tbase, TUSB_INT_CTRL_CONF,
949 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
950
951 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
952
953 /* maybe force into the Default-A OTG state machine */
954 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
955 & TUSB_DEV_OTG_STAT_ID_STATUS))
956 musb_writel(tbase, TUSB_INT_SRC_SET,
957 TUSB_INT_SRC_ID_STATUS_CHNG);
958
959 if (is_dma_capable() && dma_off)
960 printk(KERN_WARNING "%s %s: dma not reactivated\n",
961 __FILE__, __func__);
962 else
963 dma_off = 1;
964}
965
966/*
967 * Disables TUSB6010. Caller must take care of locking.
968 */
969void musb_platform_disable(struct musb *musb)
970{
971 void __iomem *tbase = musb->ctrl_base;
972
973 /* FIXME stop DMA, IRQs, timers, ... */
974
975 /* disable all IRQs */
976 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
977 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
978 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
979 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
980
981 del_timer(&musb_idle_timer);
982
983 if (is_dma_capable() && !dma_off) {
984 printk(KERN_WARNING "%s %s: dma still active\n",
985 __FILE__, __func__);
986 dma_off = 1;
987 }
988}
989
990/*
991 * Sets up TUSB6010 CPU interface specific signals and registers
992 * Note: Settings optimized for OMAP24xx
993 */
994static void __init tusb_setup_cpu_interface(struct musb *musb)
995{
996 void __iomem *tbase = musb->ctrl_base;
997
998 /*
999 * Disable GPIO[5:0] pullups (used as output DMA requests)
1000 * Don't disable GPIO[7:6] as they are needed for wake-up.
1001 */
1002 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1003
1004 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1005 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1006
1007 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1008 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1009
1010 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1011 * de-assertion time 2 system clocks p 62 */
1012 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1013 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1014 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1015 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1016
1017 /* Set 0 wait count for synchronous burst access */
1018 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1019}
1020
1021static int __init tusb_start(struct musb *musb)
1022{
1023 void __iomem *tbase = musb->ctrl_base;
1024 int ret = 0;
1025 unsigned long flags;
1026 u32 reg;
1027
1028 if (musb->board_set_power)
1029 ret = musb->board_set_power(1);
1030 if (ret != 0) {
1031 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1032 return ret;
1033 }
1034
1035 spin_lock_irqsave(&musb->lock, flags);
1036
1037 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1038 TUSB_PROD_TEST_RESET_VAL) {
1039 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1040 goto err;
1041 }
1042
1043 ret = tusb_print_revision(musb);
1044 if (ret < 2) {
1045 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1046 ret);
1047 goto err;
1048 }
1049
1050 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1051 * NOR FLASH interface is used */
1052 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1053
1054 /* Select PHY free running 60MHz as a system clock */
1055 tusb_set_clock_source(musb, 1);
1056
1057 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1058 * power saving, enable VBus detect and session end comparators,
1059 * enable IDpullup, enable VBus charging */
1060 musb_writel(tbase, TUSB_PRCM_MNGMT,
1061 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1062 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1063 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1064 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1065 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1066 tusb_setup_cpu_interface(musb);
1067
1068 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1069 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1070 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1071 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1072
1073 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1074 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1075 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1076
1077 spin_unlock_irqrestore(&musb->lock, flags);
1078
1079 return 0;
1080
1081err:
1082 spin_unlock_irqrestore(&musb->lock, flags);
1083
1084 if (musb->board_set_power)
1085 musb->board_set_power(0);
1086
1087 return -ENODEV;
1088}
1089
1090int __init musb_platform_init(struct musb *musb)
1091{
1092 struct platform_device *pdev;
1093 struct resource *mem;
1094 void __iomem *sync;
1095 int ret;
1096
1097 pdev = to_platform_device(musb->controller);
1098
1099 /* dma address for async dma */
1100 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1101 musb->async = mem->start;
1102
1103 /* dma address for sync dma */
1104 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1105 if (!mem) {
1106 pr_debug("no sync dma resource?\n");
1107 return -ENODEV;
1108 }
1109 musb->sync = mem->start;
1110
1111 sync = ioremap(mem->start, mem->end - mem->start + 1);
1112 if (!sync) {
1113 pr_debug("ioremap for sync failed\n");
1114 return -ENOMEM;
1115 }
1116 musb->sync_va = sync;
1117
1118 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1119 * FIFOs at 0x600, TUSB at 0x800
1120 */
1121 musb->mregs += TUSB_BASE_OFFSET;
1122
1123 ret = tusb_start(musb);
1124 if (ret) {
1125 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1126 ret);
1127 return -ENODEV;
1128 }
1129 musb->isr = tusb_interrupt;
1130
1131 if (is_host_enabled(musb))
1132 musb->board_set_vbus = tusb_source_power;
1133 if (is_peripheral_enabled(musb))
1134 musb->xceiv.set_power = tusb_draw_power;
1135
1136 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1137
1138 return ret;
1139}
1140
1141int musb_platform_exit(struct musb *musb)
1142{
1143 del_timer_sync(&musb_idle_timer);
1144
1145 if (musb->board_set_power)
1146 musb->board_set_power(0);
1147
1148 iounmap(musb->sync_va);
1149
1150 return 0;
1151}
diff --git a/drivers/usb/musb/tusb6010.h b/drivers/usb/musb/tusb6010.h
new file mode 100644
index 000000000000..db6dad0750ae
--- /dev/null
+++ b/drivers/usb/musb/tusb6010.h
@@ -0,0 +1,402 @@
1/*
2 * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Jarkko Nikula <jarkko.nikula@nokia.com>
6 * Tony Lindgren <tony@atomide.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __TUSB6010_H__
14#define __TUSB6010_H__
15
16extern u8 tusb_get_revision(struct musb *musb);
17
18#ifdef CONFIG_USB_TUSB6010
19#define musb_in_tusb() 1
20#else
21#define musb_in_tusb() 0
22#endif
23
24#ifdef CONFIG_USB_TUSB_OMAP_DMA
25#define tusb_dma_omap() 1
26#else
27#define tusb_dma_omap() 0
28#endif
29
30/* VLYNQ control register. 32-bit at offset 0x000 */
31#define TUSB_VLYNQ_CTRL 0x004
32
33/* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
34#define TUSB_BASE_OFFSET 0x400
35
36/* FIFO registers 32-bit at offset 0x600 */
37#define TUSB_FIFO_BASE 0x600
38
39/* Device System & Control registers. 32-bit at offset 0x800 */
40#define TUSB_SYS_REG_BASE 0x800
41
42#define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
43#define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16)
44#define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15)
45#define TUSB_DEV_CONF_SOFT_ID (1 << 1)
46#define TUSB_DEV_CONF_ID_SEL (1 << 0)
47
48#define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
49#define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
50#define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24)
51#define TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP (1 << 23)
52#define TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN (1 << 19)
53#define TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN (1 << 18)
54#define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17)
55#define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16)
56#define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15)
57#define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14)
58#define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13)
59#define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12)
60#define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11)
61#define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10)
62#define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9)
63#define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7)
64#define TUSB_PHY_OTG_CTRL_PD (1 << 6)
65#define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5)
66#define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4)
67#define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3)
68#define TUSB_PHY_OTG_CTRL_RESET (1 << 2)
69#define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1)
70#define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0)
71
72/*OTG status register */
73#define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
74#define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8)
75#define TUSB_DEV_OTG_STAT_SESS_END (1 << 7)
76#define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6)
77#define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5)
78#define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4)
79#define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3)
80#define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2)
81#define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0)
82#define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1)
83#define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0)
84
85#define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
86# define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31)
87# define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
88#define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
89
90/* PRCM configuration register */
91#define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
92#define TUSB_PRCM_CONF_SFW_CPEN (1 << 24)
93#define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16)
94
95/* PRCM management register */
96#define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
97#define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25)
98#define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24)
99#define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20)
100#define TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN (1 << 19)
101#define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18)
102#define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17)
103#define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
104#define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
105#define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8)
106#define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4)
107#define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3)
108#define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2)
109#define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1)
110#define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0)
111
112/* Wake-up source clear and mask registers */
113#define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
114#define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
115#define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
116#define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13)
117#define TUSB_PRCM_WGPIO_7 (1 << 12)
118#define TUSB_PRCM_WGPIO_6 (1 << 11)
119#define TUSB_PRCM_WGPIO_5 (1 << 10)
120#define TUSB_PRCM_WGPIO_4 (1 << 9)
121#define TUSB_PRCM_WGPIO_3 (1 << 8)
122#define TUSB_PRCM_WGPIO_2 (1 << 7)
123#define TUSB_PRCM_WGPIO_1 (1 << 6)
124#define TUSB_PRCM_WGPIO_0 (1 << 5)
125#define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */
126#define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */
127#define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */
128#define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */
129#define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */
130
131#define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
132#define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
133#define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
134#define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
135#define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
136#define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
137#define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
138#define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
139#define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
140#define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
141#define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
142#define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
143#define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
144#define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
145#define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
146#define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
147
148/* NOR flash interrupt source registers */
149#define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
150#define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
151#define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
152#define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
153#define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24)
154#define TUSB_INT_SRC_USB_IP_CORE (1 << 17)
155#define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16)
156#define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15)
157#define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14)
158#define TUSB_INT_SRC_DEV_WAKEUP (1 << 13)
159#define TUSB_INT_SRC_DEV_READY (1 << 12)
160#define TUSB_INT_SRC_USB_IP_TX (1 << 9)
161#define TUSB_INT_SRC_USB_IP_RX (1 << 8)
162#define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7)
163#define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6)
164#define TUSB_INT_SRC_USB_IP_DISCON (1 << 5)
165#define TUSB_INT_SRC_USB_IP_CONN (1 << 4)
166#define TUSB_INT_SRC_USB_IP_SOF (1 << 3)
167#define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2)
168#define TUSB_INT_SRC_USB_IP_RESUME (1 << 1)
169#define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0)
170
171/* NOR flash interrupt registers reserved bits. Must be written as 0 */
172#define TUSB_INT_MASK_RESERVED_17 (0x3fff << 17)
173#define TUSB_INT_MASK_RESERVED_13 (1 << 13)
174#define TUSB_INT_MASK_RESERVED_8 (0xf << 8)
175#define TUSB_INT_SRC_RESERVED_26 (0x1f << 26)
176#define TUSB_INT_SRC_RESERVED_18 (0x3f << 18)
177#define TUSB_INT_SRC_RESERVED_10 (0x03 << 10)
178
179/* Reserved bits for NOR flash interrupt mask and clear register */
180#define TUSB_INT_MASK_RESERVED_BITS (TUSB_INT_MASK_RESERVED_17 | \
181 TUSB_INT_MASK_RESERVED_13 | \
182 TUSB_INT_MASK_RESERVED_8)
183
184/* Reserved bits for NOR flash interrupt status register */
185#define TUSB_INT_SRC_RESERVED_BITS (TUSB_INT_SRC_RESERVED_26 | \
186 TUSB_INT_SRC_RESERVED_18 | \
187 TUSB_INT_SRC_RESERVED_10)
188
189#define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
190#define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
191#define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
192#define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
193#define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
194#define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
195
196/* Offsets from each ep base register */
197#define TUSB_EP_TX_OFFSET 0x10c /* EP_IN in docs */
198#define TUSB_EP_RX_OFFSET 0x14c /* EP_OUT in docs */
199#define TUSB_EP_MAX_PACKET_SIZE_OFFSET 0x188
200
201#define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
202#define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
203#define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
204
205/* Device System & Control register bitfields */
206#define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18)
207#define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
208#define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16)
209#define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
210#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
211#define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20)
212#define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16)
213#define TUSB_EP0_CONFIG_SW_EN (1 << 8)
214#define TUSB_EP0_CONFIG_DIR_TX (1 << 7)
215#define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
216#define TUSB_EP_CONFIG_SW_EN (1 << 31)
217#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
218#define TUSB_PROD_TEST_RESET_VAL 0xa596
219#define TUSB_EP_FIFO(ep) (TUSB_FIFO_BASE + (ep) * 0x20)
220
221#define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
222#define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)
223#define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf)
224#define TUSB_DIDR1_HI_REV_20 0
225#define TUSB_DIDR1_HI_REV_30 1
226#define TUSB_DIDR1_HI_REV_31 2
227
228#define TUSB_REV_10 0x10
229#define TUSB_REV_20 0x20
230#define TUSB_REV_30 0x30
231#define TUSB_REV_31 0x31
232
233/*----------------------------------------------------------------------------*/
234
235#ifdef CONFIG_USB_TUSB6010
236
237/* configuration parameters specific to this silicon */
238
239/* Number of Tx endpoints. Legal values are 1 - 16 (this value includes EP0) */
240#define MUSB_C_NUM_EPT 16
241
242/* Number of Rx endpoints. Legal values are 1 - 16 (this value includes EP0) */
243#define MUSB_C_NUM_EPR 16
244
245/* Endpoint 1 to 15 direction types. C_EP1_DEF is defined if either Tx endpoint
246 * 1 or Rx endpoint 1 are used.
247 */
248#define MUSB_C_EP1_DEF
249
250/* C_EP1_TX_DEF is defined if Tx endpoint 1 is used */
251#define MUSB_C_EP1_TX_DEF
252
253/* C_EP1_RX_DEF is defined if Rx endpoint 1 is used */
254#define MUSB_C_EP1_RX_DEF
255
256/* C_EP1_TOR_DEF is defined if Tx endpoint 1 and Rx endpoint 1 share a FIFO */
257/* #define C_EP1_TOR_DEF */
258
259/* C_EP1_TAR_DEF is defined if both Tx endpoint 1 and Rx endpoint 1 are used
260 * and do not share a FIFO.
261 */
262#define MUSB_C_EP1_TAR_DEF
263
264/* Similarly for all other used endpoints */
265#define MUSB_C_EP2_DEF
266#define MUSB_C_EP2_TX_DEF
267#define MUSB_C_EP2_RX_DEF
268#define MUSB_C_EP2_TAR_DEF
269#define MUSB_C_EP3_DEF
270#define MUSB_C_EP3_TX_DEF
271#define MUSB_C_EP3_RX_DEF
272#define MUSB_C_EP3_TAR_DEF
273#define MUSB_C_EP4_DEF
274#define MUSB_C_EP4_TX_DEF
275#define MUSB_C_EP4_RX_DEF
276#define MUSB_C_EP4_TAR_DEF
277
278/* Endpoint 1 to 15 FIFO address bits. Legal values are 3 to 13 - corresponding
279 * to FIFO sizes of 8 to 8192 bytes. If an Tx endpoint shares a FIFO with an Rx
280 * endpoint then the Rx FIFO size must be the same as the Tx FIFO size. All
281 * endpoints 1 to 15 must be defined, unused endpoints should be set to 2.
282 */
283#define MUSB_C_EP1T_BITS 5
284#define MUSB_C_EP1R_BITS 5
285#define MUSB_C_EP2T_BITS 5
286#define MUSB_C_EP2R_BITS 5
287#define MUSB_C_EP3T_BITS 3
288#define MUSB_C_EP3R_BITS 3
289#define MUSB_C_EP4T_BITS 3
290#define MUSB_C_EP4R_BITS 3
291
292#define MUSB_C_EP5T_BITS 2
293#define MUSB_C_EP5R_BITS 2
294#define MUSB_C_EP6T_BITS 2
295#define MUSB_C_EP6R_BITS 2
296#define MUSB_C_EP7T_BITS 2
297#define MUSB_C_EP7R_BITS 2
298#define MUSB_C_EP8T_BITS 2
299#define MUSB_C_EP8R_BITS 2
300#define MUSB_C_EP9T_BITS 2
301#define MUSB_C_EP9R_BITS 2
302#define MUSB_C_EP10T_BITS 2
303#define MUSB_C_EP10R_BITS 2
304#define MUSB_C_EP11T_BITS 2
305#define MUSB_C_EP11R_BITS 2
306#define MUSB_C_EP12T_BITS 2
307#define MUSB_C_EP12R_BITS 2
308#define MUSB_C_EP13T_BITS 2
309#define MUSB_C_EP13R_BITS 2
310#define MUSB_C_EP14T_BITS 2
311#define MUSB_C_EP14R_BITS 2
312#define MUSB_C_EP15T_BITS 2
313#define MUSB_C_EP15R_BITS 2
314
315/* Define the following constant if the USB2.0 Transceiver Macrocell data width
316 * is 16-bits.
317 */
318/* #define C_UTM_16 */
319
320/* Define this constant if the CPU uses big-endian byte ordering. */
321/* #define C_BIGEND */
322
323/* Define the following constant if any Tx endpoint is required to support
324 * multiple bulk packets.
325 */
326/* #define C_MP_TX */
327
328/* Define the following constant if any Rx endpoint is required to support
329 * multiple bulk packets.
330 */
331/* #define C_MP_RX */
332
333/* Define the following constant if any Tx endpoint is required to support high
334 * bandwidth ISO.
335 */
336/* #define C_HB_TX */
337
338/* Define the following constant if any Rx endpoint is required to support high
339 * bandwidth ISO.
340 */
341/* #define C_HB_RX */
342
343/* Define the following constant if software connect/disconnect control is
344 * required.
345 */
346#define MUSB_C_SOFT_CON
347
348/* Define the following constant if Vendor Control Registers are required. */
349/* #define C_VEND_REG */
350
351/* Vendor control register widths. */
352#define MUSB_C_VCTL_BITS 4
353#define MUSB_C_VSTAT_BITS 8
354
355/* Define the following constant to include a DMA controller. */
356/* #define C_DMA */
357
358/* Define the following constant if 2 or more DMA channels are required. */
359/* #define C_DMA2 */
360
361/* Define the following constant if 3 or more DMA channels are required. */
362/* #define C_DMA3 */
363
364/* Define the following constant if 4 or more DMA channels are required. */
365/* #define C_DMA4 */
366
367/* Define the following constant if 5 or more DMA channels are required. */
368/* #define C_DMA5 */
369
370/* Define the following constant if 6 or more DMA channels are required. */
371/* #define C_DMA6 */
372
373/* Define the following constant if 7 or more DMA channels are required. */
374/* #define C_DMA7 */
375
376/* Define the following constant if 8 or more DMA channels are required. */
377/* #define C_DMA8 */
378
379/* Enable Dynamic FIFO Sizing */
380#define MUSB_C_DYNFIFO_DEF
381
382/* Derived constants. The following constants are derived from the previous
383 * configuration constants
384 */
385
386/* Total number of endpoints. Legal values are 2 - 16. This must be equal to
387 * the larger of C_NUM_EPT, C_NUM_EPR
388 */
389/* #define MUSB_C_NUM_EPS 5 */
390
391/* C_EPMAX_BITS is equal to the largest endpoint FIFO word address bits */
392#define MUSB_C_EPMAX_BITS 11
393
394/* C_RAM_BITS is the number of address bits required to address the RAM (32-bit
395 * addresses). It is defined as log2 of the sum of 2** of all the endpoint FIFO
396 * dword address bits (rounded up).
397 */
398#define MUSB_C_RAM_BITS 12
399
400#endif /* CONFIG_USB_TUSB6010 */
401
402#endif /* __TUSB6010_H__ */
diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
new file mode 100644
index 000000000000..52f7f29cebda
--- /dev/null
+++ b/drivers/usb/musb/tusb6010_omap.c
@@ -0,0 +1,719 @@
1/*
2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/init.h>
15#include <linux/usb.h>
16#include <linux/platform_device.h>
17#include <linux/dma-mapping.h>
18#include <asm/arch/dma.h>
19#include <asm/arch/mux.h>
20
21#include "musb_core.h"
22
23#define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
24
25#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
26
27struct tusb_omap_dma_ch {
28 struct musb *musb;
29 void __iomem *tbase;
30 unsigned long phys_offset;
31 int epnum;
32 u8 tx;
33 struct musb_hw_ep *hw_ep;
34
35 int ch;
36 s8 dmareq;
37 s8 sync_dev;
38
39 struct tusb_omap_dma *tusb_dma;
40
41 void __iomem *dma_addr;
42
43 u32 len;
44 u16 packet_sz;
45 u16 transfer_packet_sz;
46 u32 transfer_len;
47 u32 completed_len;
48};
49
50struct tusb_omap_dma {
51 struct dma_controller controller;
52 struct musb *musb;
53 void __iomem *tbase;
54
55 int ch;
56 s8 dmareq;
57 s8 sync_dev;
58 unsigned multichannel:1;
59};
60
61static int tusb_omap_dma_start(struct dma_controller *c)
62{
63 struct tusb_omap_dma *tusb_dma;
64
65 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
66
67 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
68
69 return 0;
70}
71
72static int tusb_omap_dma_stop(struct dma_controller *c)
73{
74 struct tusb_omap_dma *tusb_dma;
75
76 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
77
78 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
79
80 return 0;
81}
82
83/*
84 * Allocate dmareq0 to the current channel unless it's already taken
85 */
86static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
87{
88 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
89
90 if (reg != 0) {
91 DBG(3, "ep%i dmareq0 is busy for ep%i\n",
92 chdat->epnum, reg & 0xf);
93 return -EAGAIN;
94 }
95
96 if (chdat->tx)
97 reg = (1 << 4) | chdat->epnum;
98 else
99 reg = chdat->epnum;
100
101 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
102
103 return 0;
104}
105
106static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
107{
108 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
109
110 if ((reg & 0xf) != chdat->epnum) {
111 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
112 chdat->epnum, reg & 0xf);
113 return;
114 }
115 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
116}
117
118/*
119 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
120 * musb_gadget.c.
121 */
122static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
123{
124 struct dma_channel *channel = (struct dma_channel *)data;
125 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
126 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
127 struct musb *musb = chdat->musb;
128 struct musb_hw_ep *hw_ep = chdat->hw_ep;
129 void __iomem *ep_conf = hw_ep->conf;
130 void __iomem *mbase = musb->mregs;
131 unsigned long remaining, flags, pio;
132 int ch;
133
134 spin_lock_irqsave(&musb->lock, flags);
135
136 if (tusb_dma->multichannel)
137 ch = chdat->ch;
138 else
139 ch = tusb_dma->ch;
140
141 if (ch_status != OMAP_DMA_BLOCK_IRQ)
142 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
143
144 DBG(3, "ep%i %s dma callback ch: %i status: %x\n",
145 chdat->epnum, chdat->tx ? "tx" : "rx",
146 ch, ch_status);
147
148 if (chdat->tx)
149 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
150 else
151 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
152
153 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
154
155 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
156 if (unlikely(remaining > chdat->transfer_len)) {
157 DBG(2, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
158 chdat->tx ? "tx" : "rx", chdat->ch,
159 remaining);
160 remaining = 0;
161 }
162
163 channel->actual_len = chdat->transfer_len - remaining;
164 pio = chdat->len - channel->actual_len;
165
166 DBG(3, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
167
168 /* Transfer remaining 1 - 31 bytes */
169 if (pio > 0 && pio < 32) {
170 u8 *buf;
171
172 DBG(3, "Using PIO for remaining %lu bytes\n", pio);
173 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
174 if (chdat->tx) {
175 dma_cache_maint(phys_to_virt((u32)chdat->dma_addr),
176 chdat->transfer_len, DMA_TO_DEVICE);
177 musb_write_fifo(hw_ep, pio, buf);
178 } else {
179 musb_read_fifo(hw_ep, pio, buf);
180 dma_cache_maint(phys_to_virt((u32)chdat->dma_addr),
181 chdat->transfer_len, DMA_FROM_DEVICE);
182 }
183 channel->actual_len += pio;
184 }
185
186 if (!tusb_dma->multichannel)
187 tusb_omap_free_shared_dmareq(chdat);
188
189 channel->status = MUSB_DMA_STATUS_FREE;
190
191 /* Handle only RX callbacks here. TX callbacks must be handled based
192 * on the TUSB DMA status interrupt.
193 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
194 * interrupt for RX and TX.
195 */
196 if (!chdat->tx)
197 musb_dma_completion(musb, chdat->epnum, chdat->tx);
198
199 /* We must terminate short tx transfers manually by setting TXPKTRDY.
200 * REVISIT: This same problem may occur with other MUSB dma as well.
201 * Easy to test with g_ether by pinging the MUSB board with ping -s54.
202 */
203 if ((chdat->transfer_len < chdat->packet_sz)
204 || (chdat->transfer_len % chdat->packet_sz != 0)) {
205 u16 csr;
206
207 if (chdat->tx) {
208 DBG(3, "terminating short tx packet\n");
209 musb_ep_select(mbase, chdat->epnum);
210 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
211 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
212 | MUSB_TXCSR_P_WZC_BITS;
213 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
214 }
215 }
216
217 spin_unlock_irqrestore(&musb->lock, flags);
218}
219
220static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
221 u8 rndis_mode, dma_addr_t dma_addr, u32 len)
222{
223 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
224 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
225 struct musb *musb = chdat->musb;
226 struct musb_hw_ep *hw_ep = chdat->hw_ep;
227 void __iomem *mbase = musb->mregs;
228 void __iomem *ep_conf = hw_ep->conf;
229 dma_addr_t fifo = hw_ep->fifo_sync;
230 struct omap_dma_channel_params dma_params;
231 u32 dma_remaining;
232 int src_burst, dst_burst;
233 u16 csr;
234 int ch;
235 s8 dmareq;
236 s8 sync_dev;
237
238 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
239 return false;
240
241 /*
242 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
243 * register which will cause missed DMA interrupt. We could try to
244 * use a timer for the callback, but it is unsafe as the XFR_SIZE
245 * register is corrupt, and we won't know if the DMA worked.
246 */
247 if (dma_addr & 0x2)
248 return false;
249
250 /*
251 * Because of HW issue #10, it seems like mixing sync DMA and async
252 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
253 * using the channel for DMA.
254 */
255 if (chdat->tx)
256 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
257 else
258 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
259
260 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
261 if (dma_remaining) {
262 DBG(2, "Busy %s dma ch%i, not using: %08x\n",
263 chdat->tx ? "tx" : "rx", chdat->ch,
264 dma_remaining);
265 return false;
266 }
267
268 chdat->transfer_len = len & ~0x1f;
269
270 if (len < packet_sz)
271 chdat->transfer_packet_sz = chdat->transfer_len;
272 else
273 chdat->transfer_packet_sz = packet_sz;
274
275 if (tusb_dma->multichannel) {
276 ch = chdat->ch;
277 dmareq = chdat->dmareq;
278 sync_dev = chdat->sync_dev;
279 } else {
280 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
281 DBG(3, "could not get dma for ep%i\n", chdat->epnum);
282 return false;
283 }
284 if (tusb_dma->ch < 0) {
285 /* REVISIT: This should get blocked earlier, happens
286 * with MSC ErrorRecoveryTest
287 */
288 WARN_ON(1);
289 return false;
290 }
291
292 ch = tusb_dma->ch;
293 dmareq = tusb_dma->dmareq;
294 sync_dev = tusb_dma->sync_dev;
295 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
296 }
297
298 chdat->packet_sz = packet_sz;
299 chdat->len = len;
300 channel->actual_len = 0;
301 chdat->dma_addr = (void __iomem *)dma_addr;
302 channel->status = MUSB_DMA_STATUS_BUSY;
303
304 /* Since we're recycling dma areas, we need to clean or invalidate */
305 if (chdat->tx)
306 dma_cache_maint(phys_to_virt(dma_addr), len, DMA_TO_DEVICE);
307 else
308 dma_cache_maint(phys_to_virt(dma_addr), len, DMA_FROM_DEVICE);
309
310 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
311 if ((dma_addr & 0x3) == 0) {
312 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
313 dma_params.elem_count = 8; /* Elements in frame */
314 } else {
315 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
316 dma_params.elem_count = 16; /* Elements in frame */
317 fifo = hw_ep->fifo_async;
318 }
319
320 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
321
322 DBG(3, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
323 chdat->epnum, chdat->tx ? "tx" : "rx",
324 ch, dma_addr, chdat->transfer_len, len,
325 chdat->transfer_packet_sz, packet_sz);
326
327 /*
328 * Prepare omap DMA for transfer
329 */
330 if (chdat->tx) {
331 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
332 dma_params.src_start = (unsigned long)dma_addr;
333 dma_params.src_ei = 0;
334 dma_params.src_fi = 0;
335
336 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
337 dma_params.dst_start = (unsigned long)fifo;
338 dma_params.dst_ei = 1;
339 dma_params.dst_fi = -31; /* Loop 32 byte window */
340
341 dma_params.trigger = sync_dev;
342 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
343 dma_params.src_or_dst_synch = 0; /* Dest sync */
344
345 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
346 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
347 } else {
348 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
349 dma_params.src_start = (unsigned long)fifo;
350 dma_params.src_ei = 1;
351 dma_params.src_fi = -31; /* Loop 32 byte window */
352
353 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
354 dma_params.dst_start = (unsigned long)dma_addr;
355 dma_params.dst_ei = 0;
356 dma_params.dst_fi = 0;
357
358 dma_params.trigger = sync_dev;
359 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
360 dma_params.src_or_dst_synch = 1; /* Source sync */
361
362 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
363 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
364 }
365
366 DBG(3, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
367 chdat->epnum, chdat->tx ? "tx" : "rx",
368 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
369 ((dma_addr & 0x3) == 0) ? "sync" : "async",
370 dma_params.src_start, dma_params.dst_start);
371
372 omap_set_dma_params(ch, &dma_params);
373 omap_set_dma_src_burst_mode(ch, src_burst);
374 omap_set_dma_dest_burst_mode(ch, dst_burst);
375 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
376
377 /*
378 * Prepare MUSB for DMA transfer
379 */
380 if (chdat->tx) {
381 musb_ep_select(mbase, chdat->epnum);
382 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
383 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
384 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
385 csr &= ~MUSB_TXCSR_P_UNDERRUN;
386 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
387 } else {
388 musb_ep_select(mbase, chdat->epnum);
389 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
390 csr |= MUSB_RXCSR_DMAENAB;
391 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
392 musb_writew(hw_ep->regs, MUSB_RXCSR,
393 csr | MUSB_RXCSR_P_WZC_BITS);
394 }
395
396 /*
397 * Start DMA transfer
398 */
399 omap_start_dma(ch);
400
401 if (chdat->tx) {
402 /* Send transfer_packet_sz packets at a time */
403 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
404 chdat->transfer_packet_sz);
405
406 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
407 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
408 } else {
409 /* Receive transfer_packet_sz packets at a time */
410 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
411 chdat->transfer_packet_sz << 16);
412
413 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
414 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
415 }
416
417 return true;
418}
419
420static int tusb_omap_dma_abort(struct dma_channel *channel)
421{
422 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
423 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
424
425 if (!tusb_dma->multichannel) {
426 if (tusb_dma->ch >= 0) {
427 omap_stop_dma(tusb_dma->ch);
428 omap_free_dma(tusb_dma->ch);
429 tusb_dma->ch = -1;
430 }
431
432 tusb_dma->dmareq = -1;
433 tusb_dma->sync_dev = -1;
434 }
435
436 channel->status = MUSB_DMA_STATUS_FREE;
437
438 return 0;
439}
440
441static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
442{
443 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
444 int i, dmareq_nr = -1;
445
446 const int sync_dev[6] = {
447 OMAP24XX_DMA_EXT_DMAREQ0,
448 OMAP24XX_DMA_EXT_DMAREQ1,
449 OMAP242X_DMA_EXT_DMAREQ2,
450 OMAP242X_DMA_EXT_DMAREQ3,
451 OMAP242X_DMA_EXT_DMAREQ4,
452 OMAP242X_DMA_EXT_DMAREQ5,
453 };
454
455 for (i = 0; i < MAX_DMAREQ; i++) {
456 int cur = (reg & (0xf << (i * 5))) >> (i * 5);
457 if (cur == 0) {
458 dmareq_nr = i;
459 break;
460 }
461 }
462
463 if (dmareq_nr == -1)
464 return -EAGAIN;
465
466 reg |= (chdat->epnum << (dmareq_nr * 5));
467 if (chdat->tx)
468 reg |= ((1 << 4) << (dmareq_nr * 5));
469 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
470
471 chdat->dmareq = dmareq_nr;
472 chdat->sync_dev = sync_dev[chdat->dmareq];
473
474 return 0;
475}
476
477static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
478{
479 u32 reg;
480
481 if (!chdat || chdat->dmareq < 0)
482 return;
483
484 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
485 reg &= ~(0x1f << (chdat->dmareq * 5));
486 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
487
488 chdat->dmareq = -1;
489 chdat->sync_dev = -1;
490}
491
492static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
493
494static struct dma_channel *
495tusb_omap_dma_allocate(struct dma_controller *c,
496 struct musb_hw_ep *hw_ep,
497 u8 tx)
498{
499 int ret, i;
500 const char *dev_name;
501 struct tusb_omap_dma *tusb_dma;
502 struct musb *musb;
503 void __iomem *tbase;
504 struct dma_channel *channel = NULL;
505 struct tusb_omap_dma_ch *chdat = NULL;
506 u32 reg;
507
508 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
509 musb = tusb_dma->musb;
510 tbase = musb->ctrl_base;
511
512 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
513 if (tx)
514 reg &= ~(1 << hw_ep->epnum);
515 else
516 reg &= ~(1 << (hw_ep->epnum + 15));
517 musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
518
519 /* REVISIT: Why does dmareq5 not work? */
520 if (hw_ep->epnum == 0) {
521 DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
522 return NULL;
523 }
524
525 for (i = 0; i < MAX_DMAREQ; i++) {
526 struct dma_channel *ch = dma_channel_pool[i];
527 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
528 ch->status = MUSB_DMA_STATUS_FREE;
529 channel = ch;
530 chdat = ch->private_data;
531 break;
532 }
533 }
534
535 if (!channel)
536 return NULL;
537
538 if (tx) {
539 chdat->tx = 1;
540 dev_name = "TUSB transmit";
541 } else {
542 chdat->tx = 0;
543 dev_name = "TUSB receive";
544 }
545
546 chdat->musb = tusb_dma->musb;
547 chdat->tbase = tusb_dma->tbase;
548 chdat->hw_ep = hw_ep;
549 chdat->epnum = hw_ep->epnum;
550 chdat->dmareq = -1;
551 chdat->completed_len = 0;
552 chdat->tusb_dma = tusb_dma;
553
554 channel->max_len = 0x7fffffff;
555 channel->desired_mode = 0;
556 channel->actual_len = 0;
557
558 if (tusb_dma->multichannel) {
559 ret = tusb_omap_dma_allocate_dmareq(chdat);
560 if (ret != 0)
561 goto free_dmareq;
562
563 ret = omap_request_dma(chdat->sync_dev, dev_name,
564 tusb_omap_dma_cb, channel, &chdat->ch);
565 if (ret != 0)
566 goto free_dmareq;
567 } else if (tusb_dma->ch == -1) {
568 tusb_dma->dmareq = 0;
569 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0;
570
571 /* Callback data gets set later in the shared dmareq case */
572 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared",
573 tusb_omap_dma_cb, NULL, &tusb_dma->ch);
574 if (ret != 0)
575 goto free_dmareq;
576
577 chdat->dmareq = -1;
578 chdat->ch = -1;
579 }
580
581 DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
582 chdat->epnum,
583 chdat->tx ? "tx" : "rx",
584 chdat->ch >= 0 ? "dedicated" : "shared",
585 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch,
586 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq,
587 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev);
588
589 return channel;
590
591free_dmareq:
592 tusb_omap_dma_free_dmareq(chdat);
593
594 DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum);
595 channel->status = MUSB_DMA_STATUS_UNKNOWN;
596
597 return NULL;
598}
599
600static void tusb_omap_dma_release(struct dma_channel *channel)
601{
602 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
603 struct musb *musb = chdat->musb;
604 void __iomem *tbase = musb->ctrl_base;
605 u32 reg;
606
607 DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch);
608
609 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
610 if (chdat->tx)
611 reg |= (1 << chdat->epnum);
612 else
613 reg |= (1 << (chdat->epnum + 15));
614 musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
615
616 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR);
617 if (chdat->tx)
618 reg |= (1 << chdat->epnum);
619 else
620 reg |= (1 << (chdat->epnum + 15));
621 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg);
622
623 channel->status = MUSB_DMA_STATUS_UNKNOWN;
624
625 if (chdat->ch >= 0) {
626 omap_stop_dma(chdat->ch);
627 omap_free_dma(chdat->ch);
628 chdat->ch = -1;
629 }
630
631 if (chdat->dmareq >= 0)
632 tusb_omap_dma_free_dmareq(chdat);
633
634 channel = NULL;
635}
636
637void dma_controller_destroy(struct dma_controller *c)
638{
639 struct tusb_omap_dma *tusb_dma;
640 int i;
641
642 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
643 for (i = 0; i < MAX_DMAREQ; i++) {
644 struct dma_channel *ch = dma_channel_pool[i];
645 if (ch) {
646 kfree(ch->private_data);
647 kfree(ch);
648 }
649 }
650
651 if (!tusb_dma->multichannel && tusb_dma && tusb_dma->ch >= 0)
652 omap_free_dma(tusb_dma->ch);
653
654 kfree(tusb_dma);
655}
656
657struct dma_controller *__init
658dma_controller_create(struct musb *musb, void __iomem *base)
659{
660 void __iomem *tbase = musb->ctrl_base;
661 struct tusb_omap_dma *tusb_dma;
662 int i;
663
664 /* REVISIT: Get dmareq lines used from board-*.c */
665
666 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
667 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
668
669 musb_writel(tbase, TUSB_DMA_REQ_CONF,
670 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
671 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
672 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
673
674 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
675 if (!tusb_dma)
676 goto cleanup;
677
678 tusb_dma->musb = musb;
679 tusb_dma->tbase = musb->ctrl_base;
680
681 tusb_dma->ch = -1;
682 tusb_dma->dmareq = -1;
683 tusb_dma->sync_dev = -1;
684
685 tusb_dma->controller.start = tusb_omap_dma_start;
686 tusb_dma->controller.stop = tusb_omap_dma_stop;
687 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
688 tusb_dma->controller.channel_release = tusb_omap_dma_release;
689 tusb_dma->controller.channel_program = tusb_omap_dma_program;
690 tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
691
692 if (tusb_get_revision(musb) >= TUSB_REV_30)
693 tusb_dma->multichannel = 1;
694
695 for (i = 0; i < MAX_DMAREQ; i++) {
696 struct dma_channel *ch;
697 struct tusb_omap_dma_ch *chdat;
698
699 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
700 if (!ch)
701 goto cleanup;
702
703 dma_channel_pool[i] = ch;
704
705 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
706 if (!chdat)
707 goto cleanup;
708
709 ch->status = MUSB_DMA_STATUS_UNKNOWN;
710 ch->private_data = chdat;
711 }
712
713 return &tusb_dma->controller;
714
715cleanup:
716 dma_controller_destroy(&tusb_dma->controller);
717
718 return NULL;
719}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 08:08:05 -0500