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path: root/drivers/usb/renesas_usbhs/common.h
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Diffstat (limited to 'drivers/usb/renesas_usbhs/common.h')
-rw-r--r--drivers/usb/renesas_usbhs/common.h35
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h
index 06d7239a044d..b410463a1212 100644
--- a/drivers/usb/renesas_usbhs/common.h
+++ b/drivers/usb/renesas_usbhs/common.h
@@ -36,6 +36,12 @@ struct usbhs_priv;
36#define CFIFO 0x0014 36#define CFIFO 0x0014
37#define CFIFOSEL 0x0020 37#define CFIFOSEL 0x0020
38#define CFIFOCTR 0x0022 38#define CFIFOCTR 0x0022
39#define D0FIFO 0x0100
40#define D0FIFOSEL 0x0028
41#define D0FIFOCTR 0x002A
42#define D1FIFO 0x0120
43#define D1FIFOSEL 0x002C
44#define D1FIFOCTR 0x002E
39#define INTENB0 0x0030 45#define INTENB0 0x0030
40#define INTENB1 0x0032 46#define INTENB1 0x0032
41#define BRDYENB 0x0036 47#define BRDYENB 0x0036
@@ -60,6 +66,30 @@ struct usbhs_priv;
60#define PIPEMAXP 0x006C 66#define PIPEMAXP 0x006C
61#define PIPEPERI 0x006E 67#define PIPEPERI 0x006E
62#define PIPEnCTR 0x0070 68#define PIPEnCTR 0x0070
69#define PIPE1TRE 0x0090
70#define PIPE1TRN 0x0092
71#define PIPE2TRE 0x0094
72#define PIPE2TRN 0x0096
73#define PIPE3TRE 0x0098
74#define PIPE3TRN 0x009A
75#define PIPE4TRE 0x009C
76#define PIPE4TRN 0x009E
77#define PIPE5TRE 0x00A0
78#define PIPE5TRN 0x00A2
79#define PIPEBTRE 0x00A4
80#define PIPEBTRN 0x00A6
81#define PIPECTRE 0x00A8
82#define PIPECTRN 0x00AA
83#define PIPEDTRE 0x00AC
84#define PIPEDTRN 0x00AE
85#define PIPEETRE 0x00B0
86#define PIPEETRN 0x00B2
87#define PIPEFTRE 0x00B4
88#define PIPEFTRN 0x00B6
89#define PIPE9TRE 0x00B8
90#define PIPE9TRN 0x00BA
91#define PIPEATRE 0x00BC
92#define PIPEATRN 0x00BE
63 93
64/* SYSCFG */ 94/* SYSCFG */
65#define SCKE (1 << 10) /* USB Module Clock Enable */ 95#define SCKE (1 << 10) /* USB Module Clock Enable */
@@ -78,6 +108,7 @@ struct usbhs_priv;
78#define RHST_HIGH_SPEED 3 /* High-speed connection */ 108#define RHST_HIGH_SPEED 3 /* High-speed connection */
79 109
80/* CFIFOSEL */ 110/* CFIFOSEL */
111#define DREQE (1 << 12) /* DMA Transfer Request Enable */
81#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */ 112#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
82 113
83/* CFIFOCTR */ 114/* CFIFOCTR */
@@ -164,6 +195,10 @@ struct usbhs_priv;
164 195
165#define CCPL (1 << 2) /* Control Transfer End Enable */ 196#define CCPL (1 << 2) /* Control Transfer End Enable */
166 197
198/* PIPEnTRE */
199#define TRENB (1 << 9) /* Transaction Counter Enable */
200#define TRCLR (1 << 8) /* Transaction Counter Clear */
201
167/* FRMNUM */ 202/* FRMNUM */
168#define FRNM_MASK (0x7FF) 203#define FRNM_MASK (0x7FF)
169 204