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-rw-r--r--drivers/usb/musb/Kconfig35
-rw-r--r--drivers/usb/musb/Makefile7
-rw-r--r--drivers/usb/musb/am35x.c17
-rw-r--r--drivers/usb/musb/blackfin.c16
-rw-r--r--drivers/usb/musb/cppi_dma.c34
-rw-r--r--drivers/usb/musb/da8xx.c21
-rw-r--r--drivers/usb/musb/davinci.c13
-rw-r--r--drivers/usb/musb/musb_core.c151
-rw-r--r--drivers/usb/musb/musb_debug.h14
-rw-r--r--drivers/usb/musb/musb_gadget.c178
-rw-r--r--drivers/usb/musb/musb_gadget_ep0.c22
-rw-r--r--drivers/usb/musb/musb_host.c157
-rw-r--r--drivers/usb/musb/musb_virthub.c25
-rw-r--r--drivers/usb/musb/musbhsdma.c11
-rw-r--r--drivers/usb/musb/omap2430.c25
-rw-r--r--drivers/usb/musb/tusb6010.c62
-rw-r--r--drivers/usb/musb/tusb6010_omap.c32
-rw-r--r--drivers/usb/musb/ux500_dma.c422
18 files changed, 846 insertions, 396 deletions
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 74073b363c30..13093481f918 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -14,7 +14,7 @@ config USB_MUSB_HDRC
14 select TWL4030_USB if MACH_OMAP_3430SDP 14 select TWL4030_USB if MACH_OMAP_3430SDP
15 select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA 15 select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA
16 select USB_OTG_UTILS 16 select USB_OTG_UTILS
17 bool 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)' 17 tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
18 help 18 help
19 Say Y here if your system has a dual role high speed USB 19 Say Y here if your system has a dual role high speed USB
20 controller based on the Mentor Graphics silicon IP. Then 20 controller based on the Mentor Graphics silicon IP. Then
@@ -30,39 +30,39 @@ config USB_MUSB_HDRC
30 30
31 If you do not know what this is, please say N. 31 If you do not know what this is, please say N.
32 32
33# To compile this driver as a module, choose M here; the 33 To compile this driver as a module, choose M here; the
34# module will be called "musb-hdrc". 34 module will be called "musb-hdrc".
35 35
36choice 36choice
37 prompt "Platform Glue Layer" 37 prompt "Platform Glue Layer"
38 depends on USB_MUSB_HDRC 38 depends on USB_MUSB_HDRC
39 39
40config USB_MUSB_DAVINCI 40config USB_MUSB_DAVINCI
41 bool "DaVinci" 41 tristate "DaVinci"
42 depends on ARCH_DAVINCI_DMx 42 depends on ARCH_DAVINCI_DMx
43 43
44config USB_MUSB_DA8XX 44config USB_MUSB_DA8XX
45 bool "DA8xx/OMAP-L1x" 45 tristate "DA8xx/OMAP-L1x"
46 depends on ARCH_DAVINCI_DA8XX 46 depends on ARCH_DAVINCI_DA8XX
47 47
48config USB_MUSB_TUSB6010 48config USB_MUSB_TUSB6010
49 bool "TUSB6010" 49 tristate "TUSB6010"
50 depends on ARCH_OMAP 50 depends on ARCH_OMAP
51 51
52config USB_MUSB_OMAP2PLUS 52config USB_MUSB_OMAP2PLUS
53 bool "OMAP2430 and onwards" 53 tristate "OMAP2430 and onwards"
54 depends on ARCH_OMAP2PLUS 54 depends on ARCH_OMAP2PLUS
55 55
56config USB_MUSB_AM35X 56config USB_MUSB_AM35X
57 bool "AM35x" 57 tristate "AM35x"
58 depends on ARCH_OMAP 58 depends on ARCH_OMAP
59 59
60config USB_MUSB_BLACKFIN 60config USB_MUSB_BLACKFIN
61 bool "Blackfin" 61 tristate "Blackfin"
62 depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523) 62 depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
63 63
64config USB_MUSB_UX500 64config USB_MUSB_UX500
65 bool "U8500 and U5500" 65 tristate "U8500 and U5500"
66 depends on (ARCH_U8500 && AB8500_USB) || (ARCH_U5500) 66 depends on (ARCH_U8500 && AB8500_USB) || (ARCH_U5500)
67 67
68endchoice 68endchoice
@@ -153,6 +153,13 @@ config MUSB_PIO_ONLY
153 you can still disable it at run time using the "use_dma=n" module 153 you can still disable it at run time using the "use_dma=n" module
154 parameter. 154 parameter.
155 155
156config USB_UX500_DMA
157 bool
158 depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
159 default USB_MUSB_UX500
160 help
161 Enable DMA transfers on UX500 platforms.
162
156config USB_INVENTRA_DMA 163config USB_INVENTRA_DMA
157 bool 164 bool
158 depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY 165 depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
@@ -176,11 +183,3 @@ config USB_TUSB_OMAP_DMA
176 help 183 help
177 Enable DMA transfers on TUSB 6010 when OMAP DMA is available. 184 Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
178 185
179config USB_MUSB_DEBUG
180 depends on USB_MUSB_HDRC
181 bool "Enable debugging messages"
182 default n
183 help
184 This enables musb debugging. To set the logging level use the debug
185 module parameter. Starting at level 3, per-transfer (urb, usb_request,
186 packet, or dma transfer) tracing may kick in.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 74df5284894f..c4d228b6ef8a 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -2,8 +2,6 @@
2# for USB OTG silicon based on Mentor Graphics INVENTRA designs 2# for USB OTG silicon based on Mentor Graphics INVENTRA designs
3# 3#
4 4
5ccflags-$(CONFIG_USB_MUSB_DEBUG) := -DDEBUG
6
7obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o 5obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
8 6
9musb_hdrc-y := musb_core.o 7musb_hdrc-y := musb_core.o
@@ -39,6 +37,11 @@ ifneq ($(CONFIG_MUSB_PIO_ONLY),y)
39 ifeq ($(CONFIG_USB_TUSB_OMAP_DMA),y) 37 ifeq ($(CONFIG_USB_TUSB_OMAP_DMA),y)
40 musb_hdrc-y += tusb6010_omap.o 38 musb_hdrc-y += tusb6010_omap.o
41 39
40 else
41 ifeq ($(CONFIG_USB_UX500_DMA),y)
42 musb_hdrc-y += ux500_dma.o
43
44 endif
42 endif 45 endif
43 endif 46 endif
44 endif 47 endif
diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
index d5a3da37c90c..23ac28f98d91 100644
--- a/drivers/usb/musb/am35x.c
+++ b/drivers/usb/musb/am35x.c
@@ -151,7 +151,8 @@ static void otg_timer(unsigned long _musb)
151 * status change events (from the transceiver) otherwise. 151 * status change events (from the transceiver) otherwise.
152 */ 152 */
153 devctl = musb_readb(mregs, MUSB_DEVCTL); 153 devctl = musb_readb(mregs, MUSB_DEVCTL);
154 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); 154 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
155 otg_state_string(musb->xceiv->state));
155 156
156 spin_lock_irqsave(&musb->lock, flags); 157 spin_lock_irqsave(&musb->lock, flags);
157 switch (musb->xceiv->state) { 158 switch (musb->xceiv->state) {
@@ -202,20 +203,22 @@ static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
202 /* Never idle if active, or when VBUS timeout is not set as host */ 203 /* Never idle if active, or when VBUS timeout is not set as host */
203 if (musb->is_active || (musb->a_wait_bcon == 0 && 204 if (musb->is_active || (musb->a_wait_bcon == 0 &&
204 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { 205 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
205 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 206 dev_dbg(musb->controller, "%s active, deleting timer\n",
207 otg_state_string(musb->xceiv->state));
206 del_timer(&otg_workaround); 208 del_timer(&otg_workaround);
207 last_timer = jiffies; 209 last_timer = jiffies;
208 return; 210 return;
209 } 211 }
210 212
211 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 213 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
212 DBG(4, "Longer idle timer already pending, ignoring...\n"); 214 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
213 return; 215 return;
214 } 216 }
215 last_timer = timeout; 217 last_timer = timeout;
216 218
217 DBG(4, "%s inactive, starting idle timer for %u ms\n", 219 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
218 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies)); 220 otg_state_string(musb->xceiv->state),
221 jiffies_to_msecs(timeout - jiffies));
219 mod_timer(&otg_workaround, timeout); 222 mod_timer(&otg_workaround, timeout);
220} 223}
221 224
@@ -302,9 +305,9 @@ static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
302 } 305 }
303 306
304 /* NOTE: this must complete power-on within 100 ms. */ 307 /* NOTE: this must complete power-on within 100 ms. */
305 DBG(2, "VBUS %s (%s)%s, devctl %02x\n", 308 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
306 drvvbus ? "on" : "off", 309 drvvbus ? "on" : "off",
307 otg_state_string(musb), 310 otg_state_string(musb->xceiv->state),
308 err ? " ERROR" : "", 311 err ? " ERROR" : "",
309 devctl); 312 devctl);
310 ret = IRQ_HANDLED; 313 ret = IRQ_HANDLED;
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
index 8e2a1ff8a35a..ae8c39617743 100644
--- a/drivers/usb/musb/blackfin.c
+++ b/drivers/usb/musb/blackfin.c
@@ -35,6 +35,7 @@ struct bfin_glue {
35 */ 35 */
36void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 36void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
37{ 37{
38 struct musb *musb = hw_ep->musb;
38 void __iomem *fifo = hw_ep->fifo; 39 void __iomem *fifo = hw_ep->fifo;
39 void __iomem *epio = hw_ep->regs; 40 void __iomem *epio = hw_ep->regs;
40 u8 epnum = hw_ep->epnum; 41 u8 epnum = hw_ep->epnum;
@@ -43,7 +44,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
43 44
44 musb_writew(epio, MUSB_TXCOUNT, len); 45 musb_writew(epio, MUSB_TXCOUNT, len);
45 46
46 DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n", 47 dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
47 hw_ep->epnum, fifo, len, src, epio); 48 hw_ep->epnum, fifo, len, src, epio);
48 49
49 dump_fifo_data(src, len); 50 dump_fifo_data(src, len);
@@ -98,6 +99,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
98 */ 99 */
99void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 100void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
100{ 101{
102 struct musb *musb = hw_ep->musb;
101 void __iomem *fifo = hw_ep->fifo; 103 void __iomem *fifo = hw_ep->fifo;
102 u8 epnum = hw_ep->epnum; 104 u8 epnum = hw_ep->epnum;
103 105
@@ -154,7 +156,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
154 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4); 156 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
155 } 157 }
156 } 158 }
157 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 159 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
158 'R', hw_ep->epnum, fifo, len, dst); 160 'R', hw_ep->epnum, fifo, len, dst);
159 161
160 dump_fifo_data(dst, len); 162 dump_fifo_data(dst, len);
@@ -279,12 +281,14 @@ static void musb_conn_timer_handler(unsigned long _musb)
279 } 281 }
280 break; 282 break;
281 default: 283 default:
282 DBG(1, "%s state not handled\n", otg_state_string(musb)); 284 dev_dbg(musb->controller, "%s state not handled\n",
285 otg_state_string(musb->xceiv->state));
283 break; 286 break;
284 } 287 }
285 spin_unlock_irqrestore(&musb->lock, flags); 288 spin_unlock_irqrestore(&musb->lock, flags);
286 289
287 DBG(4, "state is %s\n", otg_state_string(musb)); 290 dev_dbg(musb->controller, "state is %s\n",
291 otg_state_string(musb->xceiv->state));
288} 292}
289 293
290static void bfin_musb_enable(struct musb *musb) 294static void bfin_musb_enable(struct musb *musb)
@@ -306,9 +310,9 @@ static void bfin_musb_set_vbus(struct musb *musb, int is_on)
306 value = !value; 310 value = !value;
307 gpio_set_value(musb->config->gpio_vrsel, value); 311 gpio_set_value(musb->config->gpio_vrsel, value);
308 312
309 DBG(1, "VBUS %s, devctl %02x " 313 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
310 /* otg %3x conf %08x prcm %08x */ "\n", 314 /* otg %3x conf %08x prcm %08x */ "\n",
311 otg_state_string(musb), 315 otg_state_string(musb->xceiv->state),
312 musb_readb(musb->mregs, MUSB_DEVCTL)); 316 musb_readb(musb->mregs, MUSB_DEVCTL));
313} 317}
314 318
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index ab434fbd8c35..149f3f310a0a 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -236,7 +236,7 @@ static int cppi_controller_stop(struct dma_controller *c)
236 musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG, 236 musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
237 DAVINCI_DMA_ALL_CHANNELS_ENABLE); 237 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
238 238
239 DBG(1, "Tearing down RX and TX Channels\n"); 239 dev_dbg(musb->controller, "Tearing down RX and TX Channels\n");
240 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { 240 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
241 /* FIXME restructure of txdma to use bds like rxdma */ 241 /* FIXME restructure of txdma to use bds like rxdma */
242 controller->tx[i].last_processed = NULL; 242 controller->tx[i].last_processed = NULL;
@@ -301,13 +301,13 @@ cppi_channel_allocate(struct dma_controller *c,
301 */ 301 */
302 if (transmit) { 302 if (transmit) {
303 if (index >= ARRAY_SIZE(controller->tx)) { 303 if (index >= ARRAY_SIZE(controller->tx)) {
304 DBG(1, "no %cX%d CPPI channel\n", 'T', index); 304 dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'T', index);
305 return NULL; 305 return NULL;
306 } 306 }
307 cppi_ch = controller->tx + index; 307 cppi_ch = controller->tx + index;
308 } else { 308 } else {
309 if (index >= ARRAY_SIZE(controller->rx)) { 309 if (index >= ARRAY_SIZE(controller->rx)) {
310 DBG(1, "no %cX%d CPPI channel\n", 'R', index); 310 dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'R', index);
311 return NULL; 311 return NULL;
312 } 312 }
313 cppi_ch = controller->rx + index; 313 cppi_ch = controller->rx + index;
@@ -318,13 +318,13 @@ cppi_channel_allocate(struct dma_controller *c,
318 * with the other DMA engine too 318 * with the other DMA engine too
319 */ 319 */
320 if (cppi_ch->hw_ep) 320 if (cppi_ch->hw_ep)
321 DBG(1, "re-allocating DMA%d %cX channel %p\n", 321 dev_dbg(musb->controller, "re-allocating DMA%d %cX channel %p\n",
322 index, transmit ? 'T' : 'R', cppi_ch); 322 index, transmit ? 'T' : 'R', cppi_ch);
323 cppi_ch->hw_ep = ep; 323 cppi_ch->hw_ep = ep;
324 cppi_ch->channel.status = MUSB_DMA_STATUS_FREE; 324 cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
325 cppi_ch->channel.max_len = 0x7fffffff; 325 cppi_ch->channel.max_len = 0x7fffffff;
326 326
327 DBG(4, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R'); 327 dev_dbg(musb->controller, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
328 return &cppi_ch->channel; 328 return &cppi_ch->channel;
329} 329}
330 330
@@ -339,7 +339,7 @@ static void cppi_channel_release(struct dma_channel *channel)
339 c = container_of(channel, struct cppi_channel, channel); 339 c = container_of(channel, struct cppi_channel, channel);
340 tibase = c->controller->tibase; 340 tibase = c->controller->tibase;
341 if (!c->hw_ep) 341 if (!c->hw_ep)
342 DBG(1, "releasing idle DMA channel %p\n", c); 342 dev_dbg(musb->controller, "releasing idle DMA channel %p\n", c);
343 else if (!c->transmit) 343 else if (!c->transmit)
344 core_rxirq_enable(tibase, c->index + 1); 344 core_rxirq_enable(tibase, c->index + 1);
345 345
@@ -597,7 +597,7 @@ cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
597 length = min(n_bds * maxpacket, length); 597 length = min(n_bds * maxpacket, length);
598 } 598 }
599 599
600 DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n", 600 dev_dbg(musb->controller, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
601 tx->index, 601 tx->index,
602 maxpacket, 602 maxpacket,
603 rndis ? "rndis" : "transparent", 603 rndis ? "rndis" : "transparent",
@@ -654,7 +654,7 @@ cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
654 bd->hw_options |= CPPI_ZERO_SET; 654 bd->hw_options |= CPPI_ZERO_SET;
655 } 655 }
656 656
657 DBG(5, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n", 657 dev_dbg(musb->controller, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
658 bd, bd->hw_next, bd->hw_bufp, 658 bd, bd->hw_next, bd->hw_bufp,
659 bd->hw_off_len, bd->hw_options); 659 bd->hw_off_len, bd->hw_options);
660 660
@@ -819,7 +819,7 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
819 819
820 length = min(n_bds * maxpacket, length); 820 length = min(n_bds * maxpacket, length);
821 821
822 DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) " 822 dev_dbg(musb->controller, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
823 "dma 0x%llx len %u %u/%u\n", 823 "dma 0x%llx len %u %u/%u\n",
824 rx->index, maxpacket, 824 rx->index, maxpacket,
825 onepacket 825 onepacket
@@ -936,7 +936,7 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
936 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) 936 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
937 & 0xffff; 937 & 0xffff;
938 if (i < (2 + n_bds)) { 938 if (i < (2 + n_bds)) {
939 DBG(2, "bufcnt%d underrun - %d (for %d)\n", 939 dev_dbg(musb->controller, "bufcnt%d underrun - %d (for %d)\n",
940 rx->index, i, n_bds); 940 rx->index, i, n_bds);
941 musb_writel(tibase, 941 musb_writel(tibase,
942 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), 942 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
@@ -985,7 +985,7 @@ static int cppi_channel_program(struct dma_channel *ch,
985 /* WARN_ON(1); */ 985 /* WARN_ON(1); */
986 break; 986 break;
987 case MUSB_DMA_STATUS_UNKNOWN: 987 case MUSB_DMA_STATUS_UNKNOWN:
988 DBG(1, "%cX DMA%d not allocated!\n", 988 dev_dbg(musb->controller, "%cX DMA%d not allocated!\n",
989 cppi_ch->transmit ? 'T' : 'R', 989 cppi_ch->transmit ? 'T' : 'R',
990 cppi_ch->index); 990 cppi_ch->index);
991 /* FALLTHROUGH */ 991 /* FALLTHROUGH */
@@ -1040,7 +1040,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1040 if (!completed && (bd->hw_options & CPPI_OWN_SET)) 1040 if (!completed && (bd->hw_options & CPPI_OWN_SET))
1041 break; 1041 break;
1042 1042
1043 DBG(5, "C/RXBD %llx: nxt %08x buf %08x " 1043 dev_dbg(musb->controller, "C/RXBD %llx: nxt %08x buf %08x "
1044 "off.len %08x opt.len %08x (%d)\n", 1044 "off.len %08x opt.len %08x (%d)\n",
1045 (unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp, 1045 (unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
1046 bd->hw_off_len, bd->hw_options, 1046 bd->hw_off_len, bd->hw_options,
@@ -1062,7 +1062,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1062 * CPPI ignores those BDs even though OWN is still set. 1062 * CPPI ignores those BDs even though OWN is still set.
1063 */ 1063 */
1064 completed = true; 1064 completed = true;
1065 DBG(3, "rx short %d/%d (%d)\n", 1065 dev_dbg(musb->controller, "rx short %d/%d (%d)\n",
1066 len, bd->buflen, 1066 len, bd->buflen,
1067 rx->channel.actual_len); 1067 rx->channel.actual_len);
1068 } 1068 }
@@ -1112,7 +1112,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1112 musb_ep_select(cppi->mregs, rx->index + 1); 1112 musb_ep_select(cppi->mregs, rx->index + 1);
1113 csr = musb_readw(regs, MUSB_RXCSR); 1113 csr = musb_readw(regs, MUSB_RXCSR);
1114 if (csr & MUSB_RXCSR_DMAENAB) { 1114 if (csr & MUSB_RXCSR_DMAENAB) {
1115 DBG(4, "list%d %p/%p, last %llx%s, csr %04x\n", 1115 dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
1116 rx->index, 1116 rx->index,
1117 rx->head, rx->tail, 1117 rx->head, rx->tail,
1118 rx->last_processed 1118 rx->last_processed
@@ -1175,7 +1175,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1175 return IRQ_NONE; 1175 return IRQ_NONE;
1176 } 1176 }
1177 1177
1178 DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx); 1178 dev_dbg(musb->controller, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
1179 1179
1180 /* process TX channels */ 1180 /* process TX channels */
1181 for (index = 0; tx; tx = tx >> 1, index++) { 1181 for (index = 0; tx; tx = tx >> 1, index++) {
@@ -1203,7 +1203,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1203 * that needs to be acknowledged. 1203 * that needs to be acknowledged.
1204 */ 1204 */
1205 if (NULL == bd) { 1205 if (NULL == bd) {
1206 DBG(1, "null BD\n"); 1206 dev_dbg(musb->controller, "null BD\n");
1207 musb_writel(&tx_ram->tx_complete, 0, 0); 1207 musb_writel(&tx_ram->tx_complete, 0, 0);
1208 continue; 1208 continue;
1209 } 1209 }
@@ -1218,7 +1218,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1218 if (bd->hw_options & CPPI_OWN_SET) 1218 if (bd->hw_options & CPPI_OWN_SET)
1219 break; 1219 break;
1220 1220
1221 DBG(5, "C/TXBD %p n %x b %x off %x opt %x\n", 1221 dev_dbg(musb->controller, "C/TXBD %p n %x b %x off %x opt %x\n",
1222 bd, bd->hw_next, bd->hw_bufp, 1222 bd, bd->hw_next, bd->hw_bufp,
1223 bd->hw_off_len, bd->hw_options); 1223 bd->hw_off_len, bd->hw_options);
1224 1224
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index 69a0da3c8f09..662ed34980bd 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -199,7 +199,8 @@ static void otg_timer(unsigned long _musb)
199 * status change events (from the transceiver) otherwise. 199 * status change events (from the transceiver) otherwise.
200 */ 200 */
201 devctl = musb_readb(mregs, MUSB_DEVCTL); 201 devctl = musb_readb(mregs, MUSB_DEVCTL);
202 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); 202 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
203 otg_state_string(musb->xceiv->state));
203 204
204 spin_lock_irqsave(&musb->lock, flags); 205 spin_lock_irqsave(&musb->lock, flags);
205 switch (musb->xceiv->state) { 206 switch (musb->xceiv->state) {
@@ -273,20 +274,22 @@ static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
273 /* Never idle if active, or when VBUS timeout is not set as host */ 274 /* Never idle if active, or when VBUS timeout is not set as host */
274 if (musb->is_active || (musb->a_wait_bcon == 0 && 275 if (musb->is_active || (musb->a_wait_bcon == 0 &&
275 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { 276 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
276 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 277 dev_dbg(musb->controller, "%s active, deleting timer\n",
278 otg_state_string(musb->xceiv->state));
277 del_timer(&otg_workaround); 279 del_timer(&otg_workaround);
278 last_timer = jiffies; 280 last_timer = jiffies;
279 return; 281 return;
280 } 282 }
281 283
282 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 284 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
283 DBG(4, "Longer idle timer already pending, ignoring...\n"); 285 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
284 return; 286 return;
285 } 287 }
286 last_timer = timeout; 288 last_timer = timeout;
287 289
288 DBG(4, "%s inactive, starting idle timer for %u ms\n", 290 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
289 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies)); 291 otg_state_string(musb->xceiv->state),
292 jiffies_to_msecs(timeout - jiffies));
290 mod_timer(&otg_workaround, timeout); 293 mod_timer(&otg_workaround, timeout);
291} 294}
292 295
@@ -311,7 +314,7 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
311 goto eoi; 314 goto eoi;
312 315
313 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); 316 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
314 DBG(4, "USB IRQ %08x\n", status); 317 dev_dbg(musb->controller, "USB IRQ %08x\n", status);
315 318
316 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT; 319 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
317 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT; 320 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
@@ -363,9 +366,9 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
363 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 366 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
364 } 367 }
365 368
366 DBG(2, "VBUS %s (%s)%s, devctl %02x\n", 369 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
367 drvvbus ? "on" : "off", 370 drvvbus ? "on" : "off",
368 otg_state_string(musb), 371 otg_state_string(musb->xceiv->state),
369 err ? " ERROR" : "", 372 err ? " ERROR" : "",
370 devctl); 373 devctl);
371 ret = IRQ_HANDLED; 374 ret = IRQ_HANDLED;
@@ -410,7 +413,7 @@ static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
410 break; 413 break;
411#endif 414#endif
412 default: 415 default:
413 DBG(2, "Trying to set unsupported mode %u\n", musb_mode); 416 dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
414 } 417 }
415 418
416 __raw_writel(cfgchip2, CFGCHIP2); 419 __raw_writel(cfgchip2, CFGCHIP2);
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index e6de097fb7e8..2a2adf6492cd 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -220,7 +220,8 @@ static void otg_timer(unsigned long _musb)
220 * status change events (from the transceiver) otherwise. 220 * status change events (from the transceiver) otherwise.
221 */ 221 */
222 devctl = musb_readb(mregs, MUSB_DEVCTL); 222 devctl = musb_readb(mregs, MUSB_DEVCTL);
223 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); 223 dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
224 otg_state_string(musb->xceiv->state));
224 225
225 spin_lock_irqsave(&musb->lock, flags); 226 spin_lock_irqsave(&musb->lock, flags);
226 switch (musb->xceiv->state) { 227 switch (musb->xceiv->state) {
@@ -297,7 +298,7 @@ static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
297 /* ack and handle non-CPPI interrupts */ 298 /* ack and handle non-CPPI interrupts */
298 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); 299 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
299 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); 300 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
300 DBG(4, "IRQ %08x\n", tmp); 301 dev_dbg(musb->controller, "IRQ %08x\n", tmp);
301 302
302 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) 303 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
303 >> DAVINCI_USB_RXINT_SHIFT; 304 >> DAVINCI_USB_RXINT_SHIFT;
@@ -354,9 +355,9 @@ static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
354 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that. 355 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
355 */ 356 */
356 davinci_musb_source_power(musb, drvvbus, 0); 357 davinci_musb_source_power(musb, drvvbus, 0);
357 DBG(2, "VBUS %s (%s)%s, devctl %02x\n", 358 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
358 drvvbus ? "on" : "off", 359 drvvbus ? "on" : "off",
359 otg_state_string(musb), 360 otg_state_string(musb->xceiv->state),
360 err ? " ERROR" : "", 361 err ? " ERROR" : "",
361 devctl); 362 devctl);
362 retval = IRQ_HANDLED; 363 retval = IRQ_HANDLED;
@@ -484,7 +485,7 @@ static int davinci_musb_exit(struct musb *musb)
484 break; 485 break;
485 if ((devctl & MUSB_DEVCTL_VBUS) != warn) { 486 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
486 warn = devctl & MUSB_DEVCTL_VBUS; 487 warn = devctl & MUSB_DEVCTL_VBUS;
487 DBG(1, "VBUS %d\n", 488 dev_dbg(musb->controller, "VBUS %d\n",
488 warn >> MUSB_DEVCTL_VBUS_SHIFT); 489 warn >> MUSB_DEVCTL_VBUS_SHIFT);
489 } 490 }
490 msleep(1000); 491 msleep(1000);
@@ -493,7 +494,7 @@ static int davinci_musb_exit(struct musb *musb)
493 494
494 /* in OTG mode, another host might be connected */ 495 /* in OTG mode, another host might be connected */
495 if (devctl & MUSB_DEVCTL_VBUS) 496 if (devctl & MUSB_DEVCTL_VBUS)
496 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl); 497 dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
497 } 498 }
498 499
499 phy_off(); 500 phy_off();
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index f10ff00ca09e..ab8e1001e5e2 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -104,10 +104,6 @@
104#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 104#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
105 105
106 106
107unsigned musb_debug;
108module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
109MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
110
111#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 107#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
112#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 108#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113 109
@@ -157,10 +153,8 @@ static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 153 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) { 154 & MUSB_ULPI_REG_CMPLT)) {
159 i++; 155 i++;
160 if (i == 10000) { 156 if (i == 10000)
161 DBG(3, "ULPI read timed out\n");
162 return -ETIMEDOUT; 157 return -ETIMEDOUT;
163 }
164 158
165 } 159 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 160 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
@@ -190,10 +184,8 @@ static int musb_ulpi_write(struct otg_transceiver *otg,
190 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 184 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
191 & MUSB_ULPI_REG_CMPLT)) { 185 & MUSB_ULPI_REG_CMPLT)) {
192 i++; 186 i++;
193 if (i == 10000) { 187 if (i == 10000)
194 DBG(3, "ULPI write timed out\n");
195 return -ETIMEDOUT; 188 return -ETIMEDOUT;
196 }
197 } 189 }
198 190
199 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 191 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
@@ -221,11 +213,12 @@ static struct otg_io_access_ops musb_ulpi_access = {
221 */ 213 */
222void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 214void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
223{ 215{
216 struct musb *musb = hw_ep->musb;
224 void __iomem *fifo = hw_ep->fifo; 217 void __iomem *fifo = hw_ep->fifo;
225 218
226 prefetch((u8 *)src); 219 prefetch((u8 *)src);
227 220
228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 221 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'T', hw_ep->epnum, fifo, len, src); 222 'T', hw_ep->epnum, fifo, len, src);
230 223
231 /* we can't assume unaligned reads work */ 224 /* we can't assume unaligned reads work */
@@ -262,9 +255,10 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
262 */ 255 */
263void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 256void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
264{ 257{
258 struct musb *musb = hw_ep->musb;
265 void __iomem *fifo = hw_ep->fifo; 259 void __iomem *fifo = hw_ep->fifo;
266 260
267 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 261 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
268 'R', hw_ep->epnum, fifo, len, dst); 262 'R', hw_ep->epnum, fifo, len, dst);
269 263
270 /* we can't assume unaligned writes work */ 264 /* we can't assume unaligned writes work */
@@ -333,26 +327,6 @@ void musb_load_testpacket(struct musb *musb)
333 327
334/*-------------------------------------------------------------------------*/ 328/*-------------------------------------------------------------------------*/
335 329
336const char *otg_state_string(struct musb *musb)
337{
338 switch (musb->xceiv->state) {
339 case OTG_STATE_A_IDLE: return "a_idle";
340 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
341 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
342 case OTG_STATE_A_HOST: return "a_host";
343 case OTG_STATE_A_SUSPEND: return "a_suspend";
344 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
345 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
346 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
347 case OTG_STATE_B_IDLE: return "b_idle";
348 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
349 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
350 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
351 case OTG_STATE_B_HOST: return "b_host";
352 default: return "UNDEFINED";
353 }
354}
355
356#ifdef CONFIG_USB_MUSB_OTG 330#ifdef CONFIG_USB_MUSB_OTG
357 331
358/* 332/*
@@ -366,19 +340,21 @@ void musb_otg_timer_func(unsigned long data)
366 spin_lock_irqsave(&musb->lock, flags); 340 spin_lock_irqsave(&musb->lock, flags);
367 switch (musb->xceiv->state) { 341 switch (musb->xceiv->state) {
368 case OTG_STATE_B_WAIT_ACON: 342 case OTG_STATE_B_WAIT_ACON:
369 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 343 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
370 musb_g_disconnect(musb); 344 musb_g_disconnect(musb);
371 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 345 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
372 musb->is_active = 0; 346 musb->is_active = 0;
373 break; 347 break;
374 case OTG_STATE_A_SUSPEND: 348 case OTG_STATE_A_SUSPEND:
375 case OTG_STATE_A_WAIT_BCON: 349 case OTG_STATE_A_WAIT_BCON:
376 DBG(1, "HNP: %s timeout\n", otg_state_string(musb)); 350 dev_dbg(musb->controller, "HNP: %s timeout\n",
351 otg_state_string(musb->xceiv->state));
377 musb_platform_set_vbus(musb, 0); 352 musb_platform_set_vbus(musb, 0);
378 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 353 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
379 break; 354 break;
380 default: 355 default:
381 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 356 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
357 otg_state_string(musb->xceiv->state));
382 } 358 }
383 musb->ignore_disconnect = 0; 359 musb->ignore_disconnect = 0;
384 spin_unlock_irqrestore(&musb->lock, flags); 360 spin_unlock_irqrestore(&musb->lock, flags);
@@ -393,15 +369,16 @@ void musb_hnp_stop(struct musb *musb)
393 void __iomem *mbase = musb->mregs; 369 void __iomem *mbase = musb->mregs;
394 u8 reg; 370 u8 reg;
395 371
396 DBG(1, "HNP: stop from %s\n", otg_state_string(musb)); 372 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
397 373
398 switch (musb->xceiv->state) { 374 switch (musb->xceiv->state) {
399 case OTG_STATE_A_PERIPHERAL: 375 case OTG_STATE_A_PERIPHERAL:
400 musb_g_disconnect(musb); 376 musb_g_disconnect(musb);
401 DBG(1, "HNP: back to %s\n", otg_state_string(musb)); 377 dev_dbg(musb->controller, "HNP: back to %s\n",
378 otg_state_string(musb->xceiv->state));
402 break; 379 break;
403 case OTG_STATE_B_HOST: 380 case OTG_STATE_B_HOST:
404 DBG(1, "HNP: Disabling HR\n"); 381 dev_dbg(musb->controller, "HNP: Disabling HR\n");
405 hcd->self.is_b_host = 0; 382 hcd->self.is_b_host = 0;
406 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 383 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
407 MUSB_DEV_MODE(musb); 384 MUSB_DEV_MODE(musb);
@@ -411,8 +388,8 @@ void musb_hnp_stop(struct musb *musb)
411 /* REVISIT: Start SESSION_REQUEST here? */ 388 /* REVISIT: Start SESSION_REQUEST here? */
412 break; 389 break;
413 default: 390 default:
414 DBG(1, "HNP: Stopping in unknown state %s\n", 391 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
415 otg_state_string(musb)); 392 otg_state_string(musb->xceiv->state));
416 } 393 }
417 394
418 /* 395 /*
@@ -442,7 +419,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
442{ 419{
443 irqreturn_t handled = IRQ_NONE; 420 irqreturn_t handled = IRQ_NONE;
444 421
445 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 422 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
446 int_usb); 423 int_usb);
447 424
448 /* in host mode, the peripheral may issue remote wakeup. 425 /* in host mode, the peripheral may issue remote wakeup.
@@ -451,7 +428,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
451 */ 428 */
452 if (int_usb & MUSB_INTR_RESUME) { 429 if (int_usb & MUSB_INTR_RESUME) {
453 handled = IRQ_HANDLED; 430 handled = IRQ_HANDLED;
454 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 431 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
455 432
456 if (devctl & MUSB_DEVCTL_HM) { 433 if (devctl & MUSB_DEVCTL_HM) {
457#ifdef CONFIG_USB_MUSB_HDRC_HCD 434#ifdef CONFIG_USB_MUSB_HDRC_HCD
@@ -466,7 +443,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
466 if (power & MUSB_POWER_SUSPENDM) { 443 if (power & MUSB_POWER_SUSPENDM) {
467 /* spurious */ 444 /* spurious */
468 musb->int_usb &= ~MUSB_INTR_SUSPEND; 445 musb->int_usb &= ~MUSB_INTR_SUSPEND;
469 DBG(2, "Spurious SUSPENDM\n"); 446 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
470 break; 447 break;
471 } 448 }
472 449
@@ -492,7 +469,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
492 default: 469 default:
493 WARNING("bogus %s RESUME (%s)\n", 470 WARNING("bogus %s RESUME (%s)\n",
494 "host", 471 "host",
495 otg_state_string(musb)); 472 otg_state_string(musb->xceiv->state));
496 } 473 }
497#endif 474#endif
498 } else { 475 } else {
@@ -526,7 +503,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
526 default: 503 default:
527 WARNING("bogus %s RESUME (%s)\n", 504 WARNING("bogus %s RESUME (%s)\n",
528 "peripheral", 505 "peripheral",
529 otg_state_string(musb)); 506 otg_state_string(musb->xceiv->state));
530 } 507 }
531 } 508 }
532 } 509 }
@@ -538,11 +515,12 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
538 515
539 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 516 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
540 && (devctl & MUSB_DEVCTL_BDEVICE)) { 517 && (devctl & MUSB_DEVCTL_BDEVICE)) {
541 DBG(3, "SessReq while on B state\n"); 518 dev_dbg(musb->controller, "SessReq while on B state\n");
542 return IRQ_HANDLED; 519 return IRQ_HANDLED;
543 } 520 }
544 521
545 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 522 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
523 otg_state_string(musb->xceiv->state));
546 524
547 /* IRQ arrives from ID pin sense or (later, if VBUS power 525 /* IRQ arrives from ID pin sense or (later, if VBUS power
548 * is removed) SRP. responses are time critical: 526 * is removed) SRP. responses are time critical:
@@ -606,8 +584,8 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
606 break; 584 break;
607 } 585 }
608 586
609 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 587 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
610 otg_state_string(musb), 588 otg_state_string(musb->xceiv->state),
611 devctl, 589 devctl,
612 ({ char *s; 590 ({ char *s;
613 switch (devctl & MUSB_DEVCTL_VBUS) { 591 switch (devctl & MUSB_DEVCTL_VBUS) {
@@ -632,8 +610,8 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
632 610
633#endif 611#endif
634 if (int_usb & MUSB_INTR_SUSPEND) { 612 if (int_usb & MUSB_INTR_SUSPEND) {
635 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 613 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
636 otg_state_string(musb), devctl, power); 614 otg_state_string(musb->xceiv->state), devctl, power);
637 handled = IRQ_HANDLED; 615 handled = IRQ_HANDLED;
638 616
639 switch (musb->xceiv->state) { 617 switch (musb->xceiv->state) {
@@ -665,7 +643,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
665 if (musb->is_active) { 643 if (musb->is_active) {
666#ifdef CONFIG_USB_MUSB_OTG 644#ifdef CONFIG_USB_MUSB_OTG
667 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 645 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
668 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 646 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
669 mod_timer(&musb->otg_timer, jiffies 647 mod_timer(&musb->otg_timer, jiffies
670 + msecs_to_jiffies( 648 + msecs_to_jiffies(
671 OTG_TIME_B_ASE0_BRST)); 649 OTG_TIME_B_ASE0_BRST));
@@ -684,7 +662,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
684 break; 662 break;
685 case OTG_STATE_B_HOST: 663 case OTG_STATE_B_HOST:
686 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 664 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
687 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 665 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
688 break; 666 break;
689 default: 667 default:
690 /* "should not happen" */ 668 /* "should not happen" */
@@ -727,14 +705,14 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
727 switch (musb->xceiv->state) { 705 switch (musb->xceiv->state) {
728 case OTG_STATE_B_PERIPHERAL: 706 case OTG_STATE_B_PERIPHERAL:
729 if (int_usb & MUSB_INTR_SUSPEND) { 707 if (int_usb & MUSB_INTR_SUSPEND) {
730 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 708 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
731 int_usb &= ~MUSB_INTR_SUSPEND; 709 int_usb &= ~MUSB_INTR_SUSPEND;
732 goto b_host; 710 goto b_host;
733 } else 711 } else
734 DBG(1, "CONNECT as b_peripheral???\n"); 712 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
735 break; 713 break;
736 case OTG_STATE_B_WAIT_ACON: 714 case OTG_STATE_B_WAIT_ACON:
737 DBG(1, "HNP: CONNECT, now b_host\n"); 715 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
738b_host: 716b_host:
739 musb->xceiv->state = OTG_STATE_B_HOST; 717 musb->xceiv->state = OTG_STATE_B_HOST;
740 hcd->self.is_b_host = 1; 718 hcd->self.is_b_host = 1;
@@ -757,14 +735,14 @@ b_host:
757 else 735 else
758 usb_hcd_resume_root_hub(hcd); 736 usb_hcd_resume_root_hub(hcd);
759 737
760 DBG(1, "CONNECT (%s) devctl %02x\n", 738 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
761 otg_state_string(musb), devctl); 739 otg_state_string(musb->xceiv->state), devctl);
762 } 740 }
763#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 741#endif /* CONFIG_USB_MUSB_HDRC_HCD */
764 742
765 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 743 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
766 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 744 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
767 otg_state_string(musb), 745 otg_state_string(musb->xceiv->state),
768 MUSB_MODE(musb), devctl); 746 MUSB_MODE(musb), devctl);
769 handled = IRQ_HANDLED; 747 handled = IRQ_HANDLED;
770 748
@@ -807,7 +785,7 @@ b_host:
807#endif /* GADGET */ 785#endif /* GADGET */
808 default: 786 default:
809 WARNING("unhandled DISCONNECT transition (%s)\n", 787 WARNING("unhandled DISCONNECT transition (%s)\n",
810 otg_state_string(musb)); 788 otg_state_string(musb->xceiv->state));
811 break; 789 break;
812 } 790 }
813 } 791 }
@@ -826,13 +804,14 @@ b_host:
826 * stop the session. 804 * stop the session.
827 */ 805 */
828 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 806 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
829 DBG(1, "BABBLE devctl: %02x\n", devctl); 807 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
830 else { 808 else {
831 ERR("Stopping host session -- babble\n"); 809 ERR("Stopping host session -- babble\n");
832 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 810 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
833 } 811 }
834 } else if (is_peripheral_capable()) { 812 } else if (is_peripheral_capable()) {
835 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 813 dev_dbg(musb->controller, "BUS RESET as %s\n",
814 otg_state_string(musb->xceiv->state));
836 switch (musb->xceiv->state) { 815 switch (musb->xceiv->state) {
837#ifdef CONFIG_USB_OTG 816#ifdef CONFIG_USB_OTG
838 case OTG_STATE_A_SUSPEND: 817 case OTG_STATE_A_SUSPEND:
@@ -845,9 +824,9 @@ b_host:
845 /* FALLTHROUGH */ 824 /* FALLTHROUGH */
846 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 825 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
847 /* never use invalid T(a_wait_bcon) */ 826 /* never use invalid T(a_wait_bcon) */
848 DBG(1, "HNP: in %s, %d msec timeout\n", 827 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
849 otg_state_string(musb), 828 otg_state_string(musb->xceiv->state),
850 TA_WAIT_BCON(musb)); 829 TA_WAIT_BCON(musb));
851 mod_timer(&musb->otg_timer, jiffies 830 mod_timer(&musb->otg_timer, jiffies
852 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 831 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
853 break; 832 break;
@@ -857,8 +836,8 @@ b_host:
857 musb_g_reset(musb); 836 musb_g_reset(musb);
858 break; 837 break;
859 case OTG_STATE_B_WAIT_ACON: 838 case OTG_STATE_B_WAIT_ACON:
860 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 839 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
861 otg_state_string(musb)); 840 otg_state_string(musb->xceiv->state));
862 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 841 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
863 musb_g_reset(musb); 842 musb_g_reset(musb);
864 break; 843 break;
@@ -870,8 +849,8 @@ b_host:
870 musb_g_reset(musb); 849 musb_g_reset(musb);
871 break; 850 break;
872 default: 851 default:
873 DBG(1, "Unhandled BUS RESET as %s\n", 852 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
874 otg_state_string(musb)); 853 otg_state_string(musb->xceiv->state));
875 } 854 }
876 } 855 }
877 } 856 }
@@ -894,7 +873,7 @@ b_host:
894 u8 epnum; 873 u8 epnum;
895 u16 frame; 874 u16 frame;
896 875
897 DBG(6, "START_OF_FRAME\n"); 876 dev_dbg(musb->controller, "START_OF_FRAME\n");
898 handled = IRQ_HANDLED; 877 handled = IRQ_HANDLED;
899 878
900 /* start any periodic Tx transfers waiting for current frame */ 879 /* start any periodic Tx transfers waiting for current frame */
@@ -936,7 +915,7 @@ void musb_start(struct musb *musb)
936 void __iomem *regs = musb->mregs; 915 void __iomem *regs = musb->mregs;
937 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 916 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
938 917
939 DBG(2, "<== devctl %02x\n", devctl); 918 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
940 919
941 /* Set INT enable registers, enable interrupts */ 920 /* Set INT enable registers, enable interrupts */
942 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 921 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
@@ -1013,7 +992,7 @@ void musb_stop(struct musb *musb)
1013 /* stop IRQs, timers, ... */ 992 /* stop IRQs, timers, ... */
1014 musb_platform_disable(musb); 993 musb_platform_disable(musb);
1015 musb_generic_disable(musb); 994 musb_generic_disable(musb);
1016 DBG(3, "HDRC disabled\n"); 995 dev_dbg(musb->controller, "HDRC disabled\n");
1017 996
1018 /* FIXME 997 /* FIXME
1019 * - mark host and/or peripheral drivers unusable/inactive 998 * - mark host and/or peripheral drivers unusable/inactive
@@ -1359,7 +1338,7 @@ static int __init ep_config_from_hw(struct musb *musb)
1359 void *mbase = musb->mregs; 1338 void *mbase = musb->mregs;
1360 int ret = 0; 1339 int ret = 0;
1361 1340
1362 DBG(2, "<== static silicon ep config\n"); 1341 dev_dbg(musb->controller, "<== static silicon ep config\n");
1363 1342
1364 /* FIXME pick up ep0 maxpacket size */ 1343 /* FIXME pick up ep0 maxpacket size */
1365 1344
@@ -1506,7 +1485,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1506#endif 1485#endif
1507 1486
1508 if (hw_ep->max_packet_sz_tx) { 1487 if (hw_ep->max_packet_sz_tx) {
1509 DBG(1, 1488 dev_dbg(musb->controller,
1510 "%s: hw_ep %d%s, %smax %d\n", 1489 "%s: hw_ep %d%s, %smax %d\n",
1511 musb_driver_name, i, 1490 musb_driver_name, i,
1512 hw_ep->is_shared_fifo ? "shared" : "tx", 1491 hw_ep->is_shared_fifo ? "shared" : "tx",
@@ -1515,7 +1494,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1515 hw_ep->max_packet_sz_tx); 1494 hw_ep->max_packet_sz_tx);
1516 } 1495 }
1517 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1496 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1518 DBG(1, 1497 dev_dbg(musb->controller,
1519 "%s: hw_ep %d%s, %smax %d\n", 1498 "%s: hw_ep %d%s, %smax %d\n",
1520 musb_driver_name, i, 1499 musb_driver_name, i,
1521 "rx", 1500 "rx",
@@ -1524,7 +1503,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1524 hw_ep->max_packet_sz_rx); 1503 hw_ep->max_packet_sz_rx);
1525 } 1504 }
1526 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1505 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1527 DBG(1, "hw_ep %d not configured\n", i); 1506 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1528 } 1507 }
1529 1508
1530 return 0; 1509 return 0;
@@ -1577,14 +1556,14 @@ irqreturn_t musb_interrupt(struct musb *musb)
1577 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1556 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1578 power = musb_readb(musb->mregs, MUSB_POWER); 1557 power = musb_readb(musb->mregs, MUSB_POWER);
1579 1558
1580 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1559 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1581 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1560 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1582 musb->int_usb, musb->int_tx, musb->int_rx); 1561 musb->int_usb, musb->int_tx, musb->int_rx);
1583 1562
1584#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1563#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1585 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 1564 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1586 if (!musb->gadget_driver) { 1565 if (!musb->gadget_driver) {
1587 DBG(5, "No gadget driver loaded\n"); 1566 dev_dbg(musb->controller, "No gadget driver loaded\n");
1588 return IRQ_HANDLED; 1567 return IRQ_HANDLED;
1589 } 1568 }
1590#endif 1569#endif
@@ -1649,7 +1628,7 @@ irqreturn_t musb_interrupt(struct musb *musb)
1649 1628
1650 return retval; 1629 return retval;
1651} 1630}
1652 1631EXPORT_SYMBOL_GPL(musb_interrupt);
1653 1632
1654#ifndef CONFIG_MUSB_PIO_ONLY 1633#ifndef CONFIG_MUSB_PIO_ONLY
1655static int __initdata use_dma = 1; 1634static int __initdata use_dma = 1;
@@ -1713,7 +1692,7 @@ musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1713 int ret = -EINVAL; 1692 int ret = -EINVAL;
1714 1693
1715 spin_lock_irqsave(&musb->lock, flags); 1694 spin_lock_irqsave(&musb->lock, flags);
1716 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1695 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1717 spin_unlock_irqrestore(&musb->lock, flags); 1696 spin_unlock_irqrestore(&musb->lock, flags);
1718 1697
1719 return ret; 1698 return ret;
@@ -2075,7 +2054,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2075 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2054 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2076 2055
2077 hcd->self.uses_pio_for_control = 1; 2056 hcd->self.uses_pio_for_control = 1;
2078 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2057 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2079 "HOST", status, 2058 "HOST", status,
2080 musb_readb(musb->mregs, MUSB_DEVCTL), 2059 musb_readb(musb->mregs, MUSB_DEVCTL),
2081 (musb_readb(musb->mregs, MUSB_DEVCTL) 2060 (musb_readb(musb->mregs, MUSB_DEVCTL)
@@ -2089,7 +2068,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2089 2068
2090 status = musb_gadget_setup(musb); 2069 status = musb_gadget_setup(musb);
2091 2070
2092 DBG(1, "%s mode, status %d, dev%02x\n", 2071 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2093 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2072 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2094 status, 2073 status,
2095 musb_readb(musb->mregs, MUSB_DEVCTL)); 2074 musb_readb(musb->mregs, MUSB_DEVCTL));
@@ -2460,6 +2439,8 @@ static int __init musb_init(void)
2460 "musb-dma" 2439 "musb-dma"
2461#elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2440#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2462 "tusb-omap-dma" 2441 "tusb-omap-dma"
2442#elif defined(CONFIG_USB_UX500_DMA)
2443 "ux500-dma"
2463#else 2444#else
2464 "?dma?" 2445 "?dma?"
2465#endif 2446#endif
@@ -2471,8 +2452,8 @@ static int __init musb_init(void)
2471#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2452#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2472 "host" 2453 "host"
2473#endif 2454#endif
2474 ", debug=%d\n", 2455 ,
2475 musb_driver_name, musb_debug); 2456 musb_driver_name);
2476 return platform_driver_probe(&musb_driver, musb_probe); 2457 return platform_driver_probe(&musb_driver, musb_probe);
2477} 2458}
2478 2459
diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h
index 94f6973cf8f7..742eada5002e 100644
--- a/drivers/usb/musb/musb_debug.h
+++ b/drivers/usb/musb/musb_debug.h
@@ -42,20 +42,6 @@
42#define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args) 42#define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args)
43#define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args) 43#define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
44 44
45#define DBG(level, format, args...) do { \
46 if (_dbg_level(level)) \
47 pr_debug("%s %d: " format, __func__, __LINE__, ## args); \
48 } while (0)
49
50extern unsigned musb_debug;
51
52static inline int _dbg_level(unsigned l)
53{
54 return musb_debug >= l;
55}
56
57extern const char *otg_state_string(struct musb *);
58
59#ifdef CONFIG_DEBUG_FS 45#ifdef CONFIG_DEBUG_FS
60extern int musb_init_debugfs(struct musb *musb); 46extern int musb_init_debugfs(struct musb *musb);
61extern void musb_exit_debugfs(struct musb *musb); 47extern void musb_exit_debugfs(struct musb *musb);
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index f47c20197c61..0a50a35e1853 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -147,7 +147,8 @@ static inline void unmap_dma_buffer(struct musb_request *request,
147 return; 147 return;
148 148
149 if (request->request.dma == DMA_ADDR_INVALID) { 149 if (request->request.dma == DMA_ADDR_INVALID) {
150 DBG(20, "not unmapping a never mapped buffer\n"); 150 dev_vdbg(musb->controller,
151 "not unmapping a never mapped buffer\n");
151 return; 152 return;
152 } 153 }
153 if (request->map_state == MUSB_MAPPED) { 154 if (request->map_state == MUSB_MAPPED) {
@@ -198,11 +199,11 @@ __acquires(ep->musb->lock)
198 spin_unlock(&musb->lock); 199 spin_unlock(&musb->lock);
199 unmap_dma_buffer(req, musb); 200 unmap_dma_buffer(req, musb);
200 if (request->status == 0) 201 if (request->status == 0)
201 DBG(5, "%s done request %p, %d/%d\n", 202 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
202 ep->end_point.name, request, 203 ep->end_point.name, request,
203 req->request.actual, req->request.length); 204 req->request.actual, req->request.length);
204 else 205 else
205 DBG(2, "%s request %p, %d/%d fault %d\n", 206 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
206 ep->end_point.name, request, 207 ep->end_point.name, request,
207 req->request.actual, req->request.length, 208 req->request.actual, req->request.length,
208 request->status); 209 request->status);
@@ -219,6 +220,7 @@ __acquires(ep->musb->lock)
219 */ 220 */
220static void nuke(struct musb_ep *ep, const int status) 221static void nuke(struct musb_ep *ep, const int status)
221{ 222{
223 struct musb *musb = ep->musb;
222 struct musb_request *req = NULL; 224 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; 225 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
224 226
@@ -246,7 +248,8 @@ static void nuke(struct musb_ep *ep, const int status)
246 } 248 }
247 249
248 value = c->channel_abort(ep->dma); 250 value = c->channel_abort(ep->dma);
249 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value); 251 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
252 ep->name, value);
250 c->channel_release(ep->dma); 253 c->channel_release(ep->dma);
251 ep->dma = NULL; 254 ep->dma = NULL;
252 } 255 }
@@ -329,7 +332,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
329 332
330 /* we shouldn't get here while DMA is active ... but we do ... */ 333 /* we shouldn't get here while DMA is active ... but we do ... */
331 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 334 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
332 DBG(4, "dma pending...\n"); 335 dev_dbg(musb->controller, "dma pending...\n");
333 return; 336 return;
334 } 337 }
335 338
@@ -341,18 +344,18 @@ static void txstate(struct musb *musb, struct musb_request *req)
341 (int)(request->length - request->actual)); 344 (int)(request->length - request->actual));
342 345
343 if (csr & MUSB_TXCSR_TXPKTRDY) { 346 if (csr & MUSB_TXCSR_TXPKTRDY) {
344 DBG(5, "%s old packet still ready , txcsr %03x\n", 347 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
345 musb_ep->end_point.name, csr); 348 musb_ep->end_point.name, csr);
346 return; 349 return;
347 } 350 }
348 351
349 if (csr & MUSB_TXCSR_P_SENDSTALL) { 352 if (csr & MUSB_TXCSR_P_SENDSTALL) {
350 DBG(5, "%s stalling, txcsr %03x\n", 353 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
351 musb_ep->end_point.name, csr); 354 musb_ep->end_point.name, csr);
352 return; 355 return;
353 } 356 }
354 357
355 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", 358 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
356 epnum, musb_ep->packet_sz, fifo_count, 359 epnum, musb_ep->packet_sz, fifo_count,
357 csr); 360 csr);
358 361
@@ -369,7 +372,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
369 372
370 /* MUSB_TXCSR_P_ISO is still set correctly */ 373 /* MUSB_TXCSR_P_ISO is still set correctly */
371 374
372#ifdef CONFIG_USB_INVENTRA_DMA 375#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
373 { 376 {
374 if (request_size < musb_ep->packet_sz) 377 if (request_size < musb_ep->packet_sz)
375 musb_ep->dma->desired_mode = 0; 378 musb_ep->dma->desired_mode = 0;
@@ -469,7 +472,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
469 } 472 }
470 473
471 /* host may already have the data when this message shows... */ 474 /* host may already have the data when this message shows... */
472 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", 475 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
473 musb_ep->end_point.name, use_dma ? "dma" : "pio", 476 musb_ep->end_point.name, use_dma ? "dma" : "pio",
474 request->actual, request->length, 477 request->actual, request->length,
475 musb_readw(epio, MUSB_TXCSR), 478 musb_readw(epio, MUSB_TXCSR),
@@ -496,7 +499,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
496 request = &req->request; 499 request = &req->request;
497 500
498 csr = musb_readw(epio, MUSB_TXCSR); 501 csr = musb_readw(epio, MUSB_TXCSR);
499 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); 502 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
500 503
501 dma = is_dma_capable() ? musb_ep->dma : NULL; 504 dma = is_dma_capable() ? musb_ep->dma : NULL;
502 505
@@ -516,7 +519,8 @@ void musb_g_tx(struct musb *musb, u8 epnum)
516 csr |= MUSB_TXCSR_P_WZC_BITS; 519 csr |= MUSB_TXCSR_P_WZC_BITS;
517 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 520 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
518 musb_writew(epio, MUSB_TXCSR, csr); 521 musb_writew(epio, MUSB_TXCSR, csr);
519 DBG(20, "underrun on ep%d, req %p\n", epnum, request); 522 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
523 epnum, request);
520 } 524 }
521 525
522 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 526 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
@@ -524,7 +528,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
524 * SHOULD NOT HAPPEN... has with CPPI though, after 528 * SHOULD NOT HAPPEN... has with CPPI though, after
525 * changing SENDSTALL (and other cases); harmless? 529 * changing SENDSTALL (and other cases); harmless?
526 */ 530 */
527 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); 531 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
528 return; 532 return;
529 } 533 }
530 534
@@ -540,7 +544,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
540 /* Ensure writebuffer is empty. */ 544 /* Ensure writebuffer is empty. */
541 csr = musb_readw(epio, MUSB_TXCSR); 545 csr = musb_readw(epio, MUSB_TXCSR);
542 request->actual += musb_ep->dma->actual_len; 546 request->actual += musb_ep->dma->actual_len;
543 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n", 547 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
544 epnum, csr, musb_ep->dma->actual_len, request); 548 epnum, csr, musb_ep->dma->actual_len, request);
545 } 549 }
546 550
@@ -551,7 +555,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
551 if ((request->zero && request->length 555 if ((request->zero && request->length
552 && (request->length % musb_ep->packet_sz == 0) 556 && (request->length % musb_ep->packet_sz == 0)
553 && (request->actual == request->length)) 557 && (request->actual == request->length))
554#ifdef CONFIG_USB_INVENTRA_DMA 558#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
555 || (is_dma && (!dma->desired_mode || 559 || (is_dma && (!dma->desired_mode ||
556 (request->actual & 560 (request->actual &
557 (musb_ep->packet_sz - 1)))) 561 (musb_ep->packet_sz - 1))))
@@ -564,7 +568,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
564 if (csr & MUSB_TXCSR_TXPKTRDY) 568 if (csr & MUSB_TXCSR_TXPKTRDY)
565 return; 569 return;
566 570
567 DBG(4, "sending zero pkt\n"); 571 dev_dbg(musb->controller, "sending zero pkt\n");
568 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE 572 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
569 | MUSB_TXCSR_TXPKTRDY); 573 | MUSB_TXCSR_TXPKTRDY);
570 request->zero = 0; 574 request->zero = 0;
@@ -574,7 +578,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
574 musb_g_giveback(musb_ep, request, 0); 578 musb_g_giveback(musb_ep, request, 0);
575 req = musb_ep->desc ? next_request(musb_ep) : NULL; 579 req = musb_ep->desc ? next_request(musb_ep) : NULL;
576 if (!req) { 580 if (!req) {
577 DBG(4, "%s idle now\n", 581 dev_dbg(musb->controller, "%s idle now\n",
578 musb_ep->end_point.name); 582 musb_ep->end_point.name);
579 return; 583 return;
580 } 584 }
@@ -640,12 +644,12 @@ static void rxstate(struct musb *musb, struct musb_request *req)
640 644
641 /* We shouldn't get here while DMA is active, but we do... */ 645 /* We shouldn't get here while DMA is active, but we do... */
642 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 646 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
643 DBG(4, "DMA pending...\n"); 647 dev_dbg(musb->controller, "DMA pending...\n");
644 return; 648 return;
645 } 649 }
646 650
647 if (csr & MUSB_RXCSR_P_SENDSTALL) { 651 if (csr & MUSB_RXCSR_P_SENDSTALL) {
648 DBG(5, "%s stalling, RXCSR %04x\n", 652 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
649 musb_ep->end_point.name, csr); 653 musb_ep->end_point.name, csr);
650 return; 654 return;
651 } 655 }
@@ -754,10 +758,57 @@ static void rxstate(struct musb *musb, struct musb_request *req)
754 if (use_dma) 758 if (use_dma)
755 return; 759 return;
756 } 760 }
761#elif defined(CONFIG_USB_UX500_DMA)
762 if ((is_buffer_mapped(req)) &&
763 (request->actual < request->length)) {
764
765 struct dma_controller *c;
766 struct dma_channel *channel;
767 int transfer_size = 0;
768
769 c = musb->dma_controller;
770 channel = musb_ep->dma;
771
772 /* In case first packet is short */
773 if (len < musb_ep->packet_sz)
774 transfer_size = len;
775 else if (request->short_not_ok)
776 transfer_size = min(request->length -
777 request->actual,
778 channel->max_len);
779 else
780 transfer_size = min(request->length -
781 request->actual,
782 (unsigned)len);
783
784 csr &= ~MUSB_RXCSR_DMAMODE;
785 csr |= (MUSB_RXCSR_DMAENAB |
786 MUSB_RXCSR_AUTOCLEAR);
787
788 musb_writew(epio, MUSB_RXCSR, csr);
789
790 if (transfer_size <= musb_ep->packet_sz) {
791 musb_ep->dma->desired_mode = 0;
792 } else {
793 musb_ep->dma->desired_mode = 1;
794 /* Mode must be set after DMAENAB */
795 csr |= MUSB_RXCSR_DMAMODE;
796 musb_writew(epio, MUSB_RXCSR, csr);
797 }
798
799 if (c->channel_program(channel,
800 musb_ep->packet_sz,
801 channel->desired_mode,
802 request->dma
803 + request->actual,
804 transfer_size))
805
806 return;
807 }
757#endif /* Mentor's DMA */ 808#endif /* Mentor's DMA */
758 809
759 fifo_count = request->length - request->actual; 810 fifo_count = request->length - request->actual;
760 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", 811 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
761 musb_ep->end_point.name, 812 musb_ep->end_point.name,
762 len, fifo_count, 813 len, fifo_count,
763 musb_ep->packet_sz); 814 musb_ep->packet_sz);
@@ -846,7 +897,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
846 csr = musb_readw(epio, MUSB_RXCSR); 897 csr = musb_readw(epio, MUSB_RXCSR);
847 dma = is_dma_capable() ? musb_ep->dma : NULL; 898 dma = is_dma_capable() ? musb_ep->dma : NULL;
848 899
849 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, 900 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
850 csr, dma ? " (dma)" : "", request); 901 csr, dma ? " (dma)" : "", request);
851 902
852 if (csr & MUSB_RXCSR_P_SENTSTALL) { 903 if (csr & MUSB_RXCSR_P_SENTSTALL) {
@@ -861,19 +912,18 @@ void musb_g_rx(struct musb *musb, u8 epnum)
861 csr &= ~MUSB_RXCSR_P_OVERRUN; 912 csr &= ~MUSB_RXCSR_P_OVERRUN;
862 musb_writew(epio, MUSB_RXCSR, csr); 913 musb_writew(epio, MUSB_RXCSR, csr);
863 914
864 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request); 915 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
865 if (request->status == -EINPROGRESS) 916 if (request->status == -EINPROGRESS)
866 request->status = -EOVERFLOW; 917 request->status = -EOVERFLOW;
867 } 918 }
868 if (csr & MUSB_RXCSR_INCOMPRX) { 919 if (csr & MUSB_RXCSR_INCOMPRX) {
869 /* REVISIT not necessarily an error */ 920 /* REVISIT not necessarily an error */
870 DBG(4, "%s, incomprx\n", musb_ep->end_point.name); 921 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
871 } 922 }
872 923
873 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 924 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
874 /* "should not happen"; likely RXPKTRDY pending for DMA */ 925 /* "should not happen"; likely RXPKTRDY pending for DMA */
875 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1, 926 dev_dbg(musb->controller, "%s busy, csr %04x\n",
876 "%s busy, csr %04x\n",
877 musb_ep->end_point.name, csr); 927 musb_ep->end_point.name, csr);
878 return; 928 return;
879 } 929 }
@@ -887,12 +937,13 @@ void musb_g_rx(struct musb *musb, u8 epnum)
887 937
888 request->actual += musb_ep->dma->actual_len; 938 request->actual += musb_ep->dma->actual_len;
889 939
890 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", 940 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
891 epnum, csr, 941 epnum, csr,
892 musb_readw(epio, MUSB_RXCSR), 942 musb_readw(epio, MUSB_RXCSR),
893 musb_ep->dma->actual_len, request); 943 musb_ep->dma->actual_len, request);
894 944
895#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) 945#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
946 defined(CONFIG_USB_UX500_DMA)
896 /* Autoclear doesn't clear RxPktRdy for short packets */ 947 /* Autoclear doesn't clear RxPktRdy for short packets */
897 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered) 948 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
898 || (dma->actual_len 949 || (dma->actual_len
@@ -922,7 +973,8 @@ void musb_g_rx(struct musb *musb, u8 epnum)
922 if (!req) 973 if (!req)
923 return; 974 return;
924 } 975 }
925#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) 976#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
977 defined(CONFIG_USB_UX500_DMA)
926exit: 978exit:
927#endif 979#endif
928 /* Analyze request */ 980 /* Analyze request */
@@ -978,7 +1030,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
978 ok = musb->hb_iso_rx; 1030 ok = musb->hb_iso_rx;
979 1031
980 if (!ok) { 1032 if (!ok) {
981 DBG(4, "no support for high bandwidth ISO\n"); 1033 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
982 goto fail; 1034 goto fail;
983 } 1035 }
984 musb_ep->hb_mult = (tmp >> 11) & 3; 1036 musb_ep->hb_mult = (tmp >> 11) & 3;
@@ -1002,7 +1054,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
1002 goto fail; 1054 goto fail;
1003 1055
1004 if (tmp > hw_ep->max_packet_sz_tx) { 1056 if (tmp > hw_ep->max_packet_sz_tx) {
1005 DBG(4, "packet size beyond hardware FIFO size\n"); 1057 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1006 goto fail; 1058 goto fail;
1007 } 1059 }
1008 1060
@@ -1042,7 +1094,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
1042 goto fail; 1094 goto fail;
1043 1095
1044 if (tmp > hw_ep->max_packet_sz_rx) { 1096 if (tmp > hw_ep->max_packet_sz_rx) {
1045 DBG(4, "packet size beyond hardware FIFO size\n"); 1097 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1046 goto fail; 1098 goto fail;
1047 } 1099 }
1048 1100
@@ -1155,7 +1207,7 @@ static int musb_gadget_disable(struct usb_ep *ep)
1155 1207
1156 spin_unlock_irqrestore(&(musb->lock), flags); 1208 spin_unlock_irqrestore(&(musb->lock), flags);
1157 1209
1158 DBG(2, "%s\n", musb_ep->end_point.name); 1210 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1159 1211
1160 return status; 1212 return status;
1161} 1213}
@@ -1167,11 +1219,12 @@ static int musb_gadget_disable(struct usb_ep *ep)
1167struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 1219struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1168{ 1220{
1169 struct musb_ep *musb_ep = to_musb_ep(ep); 1221 struct musb_ep *musb_ep = to_musb_ep(ep);
1222 struct musb *musb = musb_ep->musb;
1170 struct musb_request *request = NULL; 1223 struct musb_request *request = NULL;
1171 1224
1172 request = kzalloc(sizeof *request, gfp_flags); 1225 request = kzalloc(sizeof *request, gfp_flags);
1173 if (!request) { 1226 if (!request) {
1174 DBG(4, "not enough memory\n"); 1227 dev_dbg(musb->controller, "not enough memory\n");
1175 return NULL; 1228 return NULL;
1176 } 1229 }
1177 1230
@@ -1205,7 +1258,7 @@ struct free_record {
1205 */ 1258 */
1206void musb_ep_restart(struct musb *musb, struct musb_request *req) 1259void musb_ep_restart(struct musb *musb, struct musb_request *req)
1207{ 1260{
1208 DBG(3, "<== %s request %p len %u on hw_ep%d\n", 1261 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1209 req->tx ? "TX/IN" : "RX/OUT", 1262 req->tx ? "TX/IN" : "RX/OUT",
1210 &req->request, req->request.length, req->epnum); 1263 &req->request, req->request.length, req->epnum);
1211 1264
@@ -1239,7 +1292,7 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1239 if (request->ep != musb_ep) 1292 if (request->ep != musb_ep)
1240 return -EINVAL; 1293 return -EINVAL;
1241 1294
1242 DBG(4, "<== to %s request=%p\n", ep->name, req); 1295 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1243 1296
1244 /* request is mine now... */ 1297 /* request is mine now... */
1245 request->request.actual = 0; 1298 request->request.actual = 0;
@@ -1253,7 +1306,7 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1253 1306
1254 /* don't queue if the ep is down */ 1307 /* don't queue if the ep is down */
1255 if (!musb_ep->desc) { 1308 if (!musb_ep->desc) {
1256 DBG(4, "req %p queued to %s while ep %s\n", 1309 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1257 req, ep->name, "disabled"); 1310 req, ep->name, "disabled");
1258 status = -ESHUTDOWN; 1311 status = -ESHUTDOWN;
1259 goto cleanup; 1312 goto cleanup;
@@ -1290,7 +1343,7 @@ static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1290 break; 1343 break;
1291 } 1344 }
1292 if (r != req) { 1345 if (r != req) {
1293 DBG(3, "request %p not queued to %s\n", request, ep->name); 1346 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1294 status = -EINVAL; 1347 status = -EINVAL;
1295 goto done; 1348 goto done;
1296 } 1349 }
@@ -1356,7 +1409,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1356 request = next_request(musb_ep); 1409 request = next_request(musb_ep);
1357 if (value) { 1410 if (value) {
1358 if (request) { 1411 if (request) {
1359 DBG(3, "request in progress, cannot halt %s\n", 1412 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1360 ep->name); 1413 ep->name);
1361 status = -EAGAIN; 1414 status = -EAGAIN;
1362 goto done; 1415 goto done;
@@ -1365,7 +1418,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1365 if (musb_ep->is_in) { 1418 if (musb_ep->is_in) {
1366 csr = musb_readw(epio, MUSB_TXCSR); 1419 csr = musb_readw(epio, MUSB_TXCSR);
1367 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1420 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1368 DBG(3, "FIFO busy, cannot halt %s\n", ep->name); 1421 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1369 status = -EAGAIN; 1422 status = -EAGAIN;
1370 goto done; 1423 goto done;
1371 } 1424 }
@@ -1374,7 +1427,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1374 musb_ep->wedged = 0; 1427 musb_ep->wedged = 0;
1375 1428
1376 /* set/clear the stall and toggle bits */ 1429 /* set/clear the stall and toggle bits */
1377 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); 1430 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1378 if (musb_ep->is_in) { 1431 if (musb_ep->is_in) {
1379 csr = musb_readw(epio, MUSB_TXCSR); 1432 csr = musb_readw(epio, MUSB_TXCSR);
1380 csr |= MUSB_TXCSR_P_WZC_BITS 1433 csr |= MUSB_TXCSR_P_WZC_BITS
@@ -1401,7 +1454,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1401 1454
1402 /* maybe start the first request in the queue */ 1455 /* maybe start the first request in the queue */
1403 if (!musb_ep->busy && !value && request) { 1456 if (!musb_ep->busy && !value && request) {
1404 DBG(3, "restarting the request\n"); 1457 dev_dbg(musb->controller, "restarting the request\n");
1405 musb_ep_restart(musb, request); 1458 musb_ep_restart(musb, request);
1406 } 1459 }
1407 1460
@@ -1532,7 +1585,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
1532 case OTG_STATE_B_IDLE: 1585 case OTG_STATE_B_IDLE:
1533 /* Start SRP ... OTG not required. */ 1586 /* Start SRP ... OTG not required. */
1534 devctl = musb_readb(mregs, MUSB_DEVCTL); 1587 devctl = musb_readb(mregs, MUSB_DEVCTL);
1535 DBG(2, "Sending SRP: devctl: %02x\n", devctl); 1588 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1536 devctl |= MUSB_DEVCTL_SESSION; 1589 devctl |= MUSB_DEVCTL_SESSION;
1537 musb_writeb(mregs, MUSB_DEVCTL, devctl); 1590 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1538 devctl = musb_readb(mregs, MUSB_DEVCTL); 1591 devctl = musb_readb(mregs, MUSB_DEVCTL);
@@ -1549,6 +1602,10 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
1549 break; 1602 break;
1550 } 1603 }
1551 1604
1605 spin_unlock_irqrestore(&musb->lock, flags);
1606 otg_start_srp(musb->xceiv);
1607 spin_lock_irqsave(&musb->lock, flags);
1608
1552 /* Block idling for at least 1s */ 1609 /* Block idling for at least 1s */
1553 musb_platform_try_idle(musb, 1610 musb_platform_try_idle(musb,
1554 jiffies + msecs_to_jiffies(1 * HZ)); 1611 jiffies + msecs_to_jiffies(1 * HZ));
@@ -1556,7 +1613,8 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
1556 status = 0; 1613 status = 0;
1557 goto done; 1614 goto done;
1558 default: 1615 default:
1559 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb)); 1616 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1617 otg_state_string(musb->xceiv->state));
1560 goto done; 1618 goto done;
1561 } 1619 }
1562 1620
@@ -1565,7 +1623,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
1565 power = musb_readb(mregs, MUSB_POWER); 1623 power = musb_readb(mregs, MUSB_POWER);
1566 power |= MUSB_POWER_RESUME; 1624 power |= MUSB_POWER_RESUME;
1567 musb_writeb(mregs, MUSB_POWER, power); 1625 musb_writeb(mregs, MUSB_POWER, power);
1568 DBG(2, "issue wakeup\n"); 1626 dev_dbg(musb->controller, "issue wakeup\n");
1569 1627
1570 /* FIXME do this next chunk in a timer callback, no udelay */ 1628 /* FIXME do this next chunk in a timer callback, no udelay */
1571 mdelay(2); 1629 mdelay(2);
@@ -1599,7 +1657,7 @@ static void musb_pullup(struct musb *musb, int is_on)
1599 1657
1600 /* FIXME if on, HdrcStart; if off, HdrcStop */ 1658 /* FIXME if on, HdrcStart; if off, HdrcStop */
1601 1659
1602 DBG(3, "gadget %s D+ pullup %s\n", 1660 dev_dbg(musb->controller, "gadget %s D+ pullup %s\n",
1603 musb->gadget_driver->function, is_on ? "on" : "off"); 1661 musb->gadget_driver->function, is_on ? "on" : "off");
1604 musb_writeb(musb->mregs, MUSB_POWER, power); 1662 musb_writeb(musb->mregs, MUSB_POWER, power);
1605} 1663}
@@ -1607,7 +1665,7 @@ static void musb_pullup(struct musb *musb, int is_on)
1607#if 0 1665#if 0
1608static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) 1666static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1609{ 1667{
1610 DBG(2, "<= %s =>\n", __func__); 1668 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1611 1669
1612 /* 1670 /*
1613 * FIXME iff driver's softconnect flag is set (as it is during probe, 1671 * FIXME iff driver's softconnect flag is set (as it is during probe,
@@ -1816,17 +1874,17 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1816 1874
1817 /* driver must be initialized to support peripheral mode */ 1875 /* driver must be initialized to support peripheral mode */
1818 if (!musb) { 1876 if (!musb) {
1819 DBG(1, "no dev??\n"); 1877 dev_dbg(musb->controller, "no dev??\n");
1820 retval = -ENODEV; 1878 retval = -ENODEV;
1821 goto err0; 1879 goto err0;
1822 } 1880 }
1823 1881
1824 pm_runtime_get_sync(musb->controller); 1882 pm_runtime_get_sync(musb->controller);
1825 1883
1826 DBG(3, "registering driver %s\n", driver->function); 1884 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1827 1885
1828 if (musb->gadget_driver) { 1886 if (musb->gadget_driver) {
1829 DBG(1, "%s is already bound to %s\n", 1887 dev_dbg(musb->controller, "%s is already bound to %s\n",
1830 musb_driver_name, 1888 musb_driver_name,
1831 musb->gadget_driver->driver.name); 1889 musb->gadget_driver->driver.name);
1832 retval = -EBUSY; 1890 retval = -EBUSY;
@@ -1842,7 +1900,7 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1842 1900
1843 retval = bind(&musb->g); 1901 retval = bind(&musb->g);
1844 if (retval) { 1902 if (retval) {
1845 DBG(3, "bind to driver %s failed --> %d\n", 1903 dev_dbg(musb->controller, "bind to driver %s failed --> %d\n",
1846 driver->driver.name, retval); 1904 driver->driver.name, retval);
1847 goto err1; 1905 goto err1;
1848 } 1906 }
@@ -1870,7 +1928,7 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1870 if (is_otg_enabled(musb)) { 1928 if (is_otg_enabled(musb)) {
1871 struct usb_hcd *hcd = musb_to_hcd(musb); 1929 struct usb_hcd *hcd = musb_to_hcd(musb);
1872 1930
1873 DBG(3, "OTG startup...\n"); 1931 dev_dbg(musb->controller, "OTG startup...\n");
1874 1932
1875 /* REVISIT: funcall to other code, which also 1933 /* REVISIT: funcall to other code, which also
1876 * handles power budgeting ... this way also 1934 * handles power budgeting ... this way also
@@ -1878,7 +1936,7 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1878 */ 1936 */
1879 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); 1937 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1880 if (retval < 0) { 1938 if (retval < 0) {
1881 DBG(1, "add_hcd failed, %d\n", retval); 1939 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1882 goto err2; 1940 goto err2;
1883 } 1941 }
1884 1942
@@ -1985,7 +2043,7 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1985 stop_activity(musb, driver); 2043 stop_activity(musb, driver);
1986 otg_set_peripheral(musb->xceiv, NULL); 2044 otg_set_peripheral(musb->xceiv, NULL);
1987 2045
1988 DBG(3, "unregistering driver %s\n", driver->function); 2046 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
1989 2047
1990 spin_unlock_irqrestore(&musb->lock, flags); 2048 spin_unlock_irqrestore(&musb->lock, flags);
1991 driver->unbind(&musb->g); 2049 driver->unbind(&musb->g);
@@ -2037,7 +2095,7 @@ void musb_g_resume(struct musb *musb)
2037 break; 2095 break;
2038 default: 2096 default:
2039 WARNING("unhandled RESUME transition (%s)\n", 2097 WARNING("unhandled RESUME transition (%s)\n",
2040 otg_state_string(musb)); 2098 otg_state_string(musb->xceiv->state));
2041 } 2099 }
2042} 2100}
2043 2101
@@ -2047,7 +2105,7 @@ void musb_g_suspend(struct musb *musb)
2047 u8 devctl; 2105 u8 devctl;
2048 2106
2049 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2107 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2050 DBG(3, "devctl %02x\n", devctl); 2108 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2051 2109
2052 switch (musb->xceiv->state) { 2110 switch (musb->xceiv->state) {
2053 case OTG_STATE_B_IDLE: 2111 case OTG_STATE_B_IDLE:
@@ -2067,7 +2125,7 @@ void musb_g_suspend(struct musb *musb)
2067 * A_PERIPHERAL may need care too 2125 * A_PERIPHERAL may need care too
2068 */ 2126 */
2069 WARNING("unhandled SUSPEND transition (%s)\n", 2127 WARNING("unhandled SUSPEND transition (%s)\n",
2070 otg_state_string(musb)); 2128 otg_state_string(musb->xceiv->state));
2071 } 2129 }
2072} 2130}
2073 2131
@@ -2083,7 +2141,7 @@ void musb_g_disconnect(struct musb *musb)
2083 void __iomem *mregs = musb->mregs; 2141 void __iomem *mregs = musb->mregs;
2084 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 2142 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2085 2143
2086 DBG(3, "devctl %02x\n", devctl); 2144 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2087 2145
2088 /* clear HR */ 2146 /* clear HR */
2089 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); 2147 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
@@ -2101,8 +2159,8 @@ void musb_g_disconnect(struct musb *musb)
2101 switch (musb->xceiv->state) { 2159 switch (musb->xceiv->state) {
2102 default: 2160 default:
2103#ifdef CONFIG_USB_MUSB_OTG 2161#ifdef CONFIG_USB_MUSB_OTG
2104 DBG(2, "Unhandled disconnect %s, setting a_idle\n", 2162 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2105 otg_state_string(musb)); 2163 otg_state_string(musb->xceiv->state));
2106 musb->xceiv->state = OTG_STATE_A_IDLE; 2164 musb->xceiv->state = OTG_STATE_A_IDLE;
2107 MUSB_HST_MODE(musb); 2165 MUSB_HST_MODE(musb);
2108 break; 2166 break;
@@ -2132,7 +2190,7 @@ __acquires(musb->lock)
2132 u8 devctl = musb_readb(mbase, MUSB_DEVCTL); 2190 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2133 u8 power; 2191 u8 power;
2134 2192
2135 DBG(3, "<== %s addr=%x driver '%s'\n", 2193 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
2136 (devctl & MUSB_DEVCTL_BDEVICE) 2194 (devctl & MUSB_DEVCTL_BDEVICE)
2137 ? "B-Device" : "A-Device", 2195 ? "B-Device" : "A-Device",
2138 musb_readb(mbase, MUSB_FADDR), 2196 musb_readb(mbase, MUSB_FADDR),
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index 75a542e42fdf..b2faff235507 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -209,7 +209,7 @@ static inline void musb_try_b_hnp_enable(struct musb *musb)
209 void __iomem *mbase = musb->mregs; 209 void __iomem *mbase = musb->mregs;
210 u8 devctl; 210 u8 devctl;
211 211
212 DBG(1, "HNP: Setting HR\n"); 212 dev_dbg(musb->controller, "HNP: Setting HR\n");
213 devctl = musb_readb(mbase, MUSB_DEVCTL); 213 devctl = musb_readb(mbase, MUSB_DEVCTL);
214 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR); 214 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
215} 215}
@@ -306,7 +306,7 @@ __acquires(musb->lock)
306 /* Maybe start the first request in the queue */ 306 /* Maybe start the first request in the queue */
307 request = next_request(musb_ep); 307 request = next_request(musb_ep);
308 if (!musb_ep->busy && request) { 308 if (!musb_ep->busy && request) {
309 DBG(3, "restarting the request\n"); 309 dev_dbg(musb->controller, "restarting the request\n");
310 musb_ep_restart(musb, request); 310 musb_ep_restart(musb, request);
311 } 311 }
312 312
@@ -553,7 +553,7 @@ static void ep0_txstate(struct musb *musb)
553 553
554 if (!req) { 554 if (!req) {
555 /* WARN_ON(1); */ 555 /* WARN_ON(1); */
556 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0)); 556 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
557 return; 557 return;
558 } 558 }
559 559
@@ -610,7 +610,7 @@ musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
610 /* NOTE: earlier 2.6 versions changed setup packets to host 610 /* NOTE: earlier 2.6 versions changed setup packets to host
611 * order, but now USB packets always stay in USB byte order. 611 * order, but now USB packets always stay in USB byte order.
612 */ 612 */
613 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n", 613 dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
614 req->bRequestType, 614 req->bRequestType,
615 req->bRequest, 615 req->bRequest,
616 le16_to_cpu(req->wValue), 616 le16_to_cpu(req->wValue),
@@ -678,7 +678,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
678 csr = musb_readw(regs, MUSB_CSR0); 678 csr = musb_readw(regs, MUSB_CSR0);
679 len = musb_readb(regs, MUSB_COUNT0); 679 len = musb_readb(regs, MUSB_COUNT0);
680 680
681 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n", 681 dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
682 csr, len, 682 csr, len,
683 musb_readb(mbase, MUSB_FADDR), 683 musb_readb(mbase, MUSB_FADDR),
684 decode_ep0stage(musb->ep0_state)); 684 decode_ep0stage(musb->ep0_state));
@@ -749,7 +749,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
749 749
750 /* enter test mode if needed (exit by reset) */ 750 /* enter test mode if needed (exit by reset) */
751 else if (musb->test_mode) { 751 else if (musb->test_mode) {
752 DBG(1, "entering TESTMODE\n"); 752 dev_dbg(musb->controller, "entering TESTMODE\n");
753 753
754 if (MUSB_TEST_PACKET == musb->test_mode_nr) 754 if (MUSB_TEST_PACKET == musb->test_mode_nr)
755 musb_load_testpacket(musb); 755 musb_load_testpacket(musb);
@@ -861,7 +861,7 @@ setup:
861 break; 861 break;
862 } 862 }
863 863
864 DBG(3, "handled %d, csr %04x, ep0stage %s\n", 864 dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
865 handled, csr, 865 handled, csr,
866 decode_ep0stage(musb->ep0_state)); 866 decode_ep0stage(musb->ep0_state));
867 867
@@ -878,7 +878,7 @@ setup:
878 if (handled < 0) { 878 if (handled < 0) {
879 musb_ep_select(mbase, 0); 879 musb_ep_select(mbase, 0);
880stall: 880stall:
881 DBG(3, "stall (%d)\n", handled); 881 dev_dbg(musb->controller, "stall (%d)\n", handled);
882 musb->ackpend |= MUSB_CSR0_P_SENDSTALL; 882 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
883 musb->ep0_state = MUSB_EP0_STAGE_IDLE; 883 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
884finish: 884finish:
@@ -958,7 +958,7 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
958 status = 0; 958 status = 0;
959 break; 959 break;
960 default: 960 default:
961 DBG(1, "ep0 request queued in state %d\n", 961 dev_dbg(musb->controller, "ep0 request queued in state %d\n",
962 musb->ep0_state); 962 musb->ep0_state);
963 status = -EINVAL; 963 status = -EINVAL;
964 goto cleanup; 964 goto cleanup;
@@ -967,7 +967,7 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
967 /* add request to the list */ 967 /* add request to the list */
968 list_add_tail(&req->list, &ep->req_list); 968 list_add_tail(&req->list, &ep->req_list);
969 969
970 DBG(3, "queue to %s (%s), length=%d\n", 970 dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
971 ep->name, ep->is_in ? "IN/TX" : "OUT/RX", 971 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
972 req->request.length); 972 req->request.length);
973 973
@@ -1060,7 +1060,7 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
1060 musb->ackpend = 0; 1060 musb->ackpend = 0;
1061 break; 1061 break;
1062 default: 1062 default:
1063 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state); 1063 dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
1064 status = -EINVAL; 1064 status = -EINVAL;
1065 } 1065 }
1066 1066
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 5eef4a8847db..7295e316bdfc 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -106,6 +106,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
106 */ 106 */
107static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 107static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
108{ 108{
109 struct musb *musb = ep->musb;
109 void __iomem *epio = ep->regs; 110 void __iomem *epio = ep->regs;
110 u16 csr; 111 u16 csr;
111 u16 lastcsr = 0; 112 u16 lastcsr = 0;
@@ -114,7 +115,7 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
114 csr = musb_readw(epio, MUSB_TXCSR); 115 csr = musb_readw(epio, MUSB_TXCSR);
115 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 116 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
116 if (csr != lastcsr) 117 if (csr != lastcsr)
117 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 118 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
118 lastcsr = csr; 119 lastcsr = csr;
119 csr |= MUSB_TXCSR_FLUSHFIFO; 120 csr |= MUSB_TXCSR_FLUSHFIFO;
120 musb_writew(epio, MUSB_TXCSR, csr); 121 musb_writew(epio, MUSB_TXCSR, csr);
@@ -240,7 +241,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
240 len = urb->transfer_buffer_length - urb->actual_length; 241 len = urb->transfer_buffer_length - urb->actual_length;
241 } 242 }
242 243
243 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 244 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
244 qh, urb, address, qh->epnum, 245 qh, urb, address, qh->epnum,
245 is_in ? "in" : "out", 246 is_in ? "in" : "out",
246 ({char *s; switch (qh->type) { 247 ({char *s; switch (qh->type) {
@@ -263,7 +264,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
263 switch (qh->type) { 264 switch (qh->type) {
264 case USB_ENDPOINT_XFER_ISOC: 265 case USB_ENDPOINT_XFER_ISOC:
265 case USB_ENDPOINT_XFER_INT: 266 case USB_ENDPOINT_XFER_INT:
266 DBG(3, "check whether there's still time for periodic Tx\n"); 267 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
267 frame = musb_readw(mbase, MUSB_FRAME); 268 frame = musb_readw(mbase, MUSB_FRAME);
268 /* FIXME this doesn't implement that scheduling policy ... 269 /* FIXME this doesn't implement that scheduling policy ...
269 * or handle framecounter wrapping 270 * or handle framecounter wrapping
@@ -278,7 +279,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
278 } else { 279 } else {
279 qh->frame = urb->start_frame; 280 qh->frame = urb->start_frame;
280 /* enable SOF interrupt so we can count down */ 281 /* enable SOF interrupt so we can count down */
281 DBG(1, "SOF for %d\n", epnum); 282 dev_dbg(musb->controller, "SOF for %d\n", epnum);
282#if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 283#if 1 /* ifndef CONFIG_ARCH_DAVINCI */
283 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 284 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
284#endif 285#endif
@@ -286,7 +287,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
286 break; 287 break;
287 default: 288 default:
288start: 289start:
289 DBG(4, "Start TX%d %s\n", epnum, 290 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
290 hw_ep->tx_channel ? "dma" : "pio"); 291 hw_ep->tx_channel ? "dma" : "pio");
291 292
292 if (!hw_ep->tx_channel) 293 if (!hw_ep->tx_channel)
@@ -301,21 +302,7 @@ static void musb_giveback(struct musb *musb, struct urb *urb, int status)
301__releases(musb->lock) 302__releases(musb->lock)
302__acquires(musb->lock) 303__acquires(musb->lock)
303{ 304{
304 DBG(({ int level; switch (status) { 305 dev_dbg(musb->controller,
305 case 0:
306 level = 4;
307 break;
308 /* common/boring faults */
309 case -EREMOTEIO:
310 case -ESHUTDOWN:
311 case -ECONNRESET:
312 case -EPIPE:
313 level = 3;
314 break;
315 default:
316 level = 2;
317 break;
318 }; level; }),
319 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 306 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
320 urb, urb->complete, status, 307 urb, urb->complete, status,
321 usb_pipedevice(urb->pipe), 308 usb_pipedevice(urb->pipe),
@@ -426,7 +413,7 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
426 } 413 }
427 414
428 if (qh != NULL && qh->is_ready) { 415 if (qh != NULL && qh->is_ready) {
429 DBG(4, "... next ep%d %cX urb %p\n", 416 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
430 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 417 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
431 musb_start_urb(musb, is_in, qh); 418 musb_start_urb(musb, is_in, qh);
432 } 419 }
@@ -471,7 +458,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
471 458
472 /* musb_ep_select(mbase, epnum); */ 459 /* musb_ep_select(mbase, epnum); */
473 rx_count = musb_readw(epio, MUSB_RXCOUNT); 460 rx_count = musb_readw(epio, MUSB_RXCOUNT);
474 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 461 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
475 urb->transfer_buffer, qh->offset, 462 urb->transfer_buffer, qh->offset,
476 urb->transfer_buffer_length); 463 urb->transfer_buffer_length);
477 464
@@ -493,7 +480,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
493 status = -EOVERFLOW; 480 status = -EOVERFLOW;
494 urb->error_count++; 481 urb->error_count++;
495 } 482 }
496 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 483 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
497 do_flush = 1; 484 do_flush = 1;
498 } else 485 } else
499 length = rx_count; 486 length = rx_count;
@@ -511,7 +498,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
511 if (rx_count > length) { 498 if (rx_count > length) {
512 if (urb->status == -EINPROGRESS) 499 if (urb->status == -EINPROGRESS)
513 urb->status = -EOVERFLOW; 500 urb->status = -EOVERFLOW;
514 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 501 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
515 do_flush = 1; 502 do_flush = 1;
516 } else 503 } else
517 length = rx_count; 504 length = rx_count;
@@ -697,7 +684,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
697 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 684 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
698 u16 packet_sz = qh->maxpacket; 685 u16 packet_sz = qh->maxpacket;
699 686
700 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s " 687 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
701 "h_addr%02x h_port%02x bytes %d\n", 688 "h_addr%02x h_port%02x bytes %d\n",
702 is_out ? "-->" : "<--", 689 is_out ? "-->" : "<--",
703 epnum, urb, urb->dev->speed, 690 epnum, urb, urb->dev->speed,
@@ -850,37 +837,32 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
850 /* kick things off */ 837 /* kick things off */
851 838
852 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { 839 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
853 /* candidate for DMA */ 840 /* Candidate for DMA */
854 if (dma_channel) { 841 dma_channel->actual_len = 0L;
855 dma_channel->actual_len = 0L; 842 qh->segsize = len;
856 qh->segsize = len; 843
857 844 /* AUTOREQ is in a DMA register */
858 /* AUTOREQ is in a DMA register */ 845 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
859 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 846 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
860 csr = musb_readw(hw_ep->regs, 847
861 MUSB_RXCSR); 848 /*
862 849 * Unless caller treats short RX transfers as
863 /* unless caller treats short rx transfers as 850 * errors, we dare not queue multiple transfers.
864 * errors, we dare not queue multiple transfers. 851 */
865 */ 852 dma_ok = dma_controller->channel_program(dma_channel,
866 dma_ok = dma_controller->channel_program( 853 packet_sz, !(urb->transfer_flags &
867 dma_channel, packet_sz, 854 URB_SHORT_NOT_OK),
868 !(urb->transfer_flags 855 urb->transfer_dma + offset,
869 & URB_SHORT_NOT_OK), 856 qh->segsize);
870 urb->transfer_dma + offset, 857 if (!dma_ok) {
871 qh->segsize); 858 dma_controller->channel_release(dma_channel);
872 if (!dma_ok) { 859 hw_ep->rx_channel = dma_channel = NULL;
873 dma_controller->channel_release( 860 } else
874 dma_channel); 861 csr |= MUSB_RXCSR_DMAENAB;
875 hw_ep->rx_channel = NULL;
876 dma_channel = NULL;
877 } else
878 csr |= MUSB_RXCSR_DMAENAB;
879 }
880 } 862 }
881 863
882 csr |= MUSB_RXCSR_H_REQPKT; 864 csr |= MUSB_RXCSR_H_REQPKT;
883 DBG(7, "RXCSR%d := %04x\n", epnum, csr); 865 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
884 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 866 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
885 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 867 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
886 } 868 }
@@ -923,15 +905,15 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
923 request = (struct usb_ctrlrequest *) urb->setup_packet; 905 request = (struct usb_ctrlrequest *) urb->setup_packet;
924 906
925 if (!request->wLength) { 907 if (!request->wLength) {
926 DBG(4, "start no-DATA\n"); 908 dev_dbg(musb->controller, "start no-DATA\n");
927 break; 909 break;
928 } else if (request->bRequestType & USB_DIR_IN) { 910 } else if (request->bRequestType & USB_DIR_IN) {
929 DBG(4, "start IN-DATA\n"); 911 dev_dbg(musb->controller, "start IN-DATA\n");
930 musb->ep0_stage = MUSB_EP0_IN; 912 musb->ep0_stage = MUSB_EP0_IN;
931 more = true; 913 more = true;
932 break; 914 break;
933 } else { 915 } else {
934 DBG(4, "start OUT-DATA\n"); 916 dev_dbg(musb->controller, "start OUT-DATA\n");
935 musb->ep0_stage = MUSB_EP0_OUT; 917 musb->ep0_stage = MUSB_EP0_OUT;
936 more = true; 918 more = true;
937 } 919 }
@@ -943,7 +925,7 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
943 if (fifo_count) { 925 if (fifo_count) {
944 fifo_dest = (u8 *) (urb->transfer_buffer 926 fifo_dest = (u8 *) (urb->transfer_buffer
945 + urb->actual_length); 927 + urb->actual_length);
946 DBG(3, "Sending %d byte%s to ep0 fifo %p\n", 928 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
947 fifo_count, 929 fifo_count,
948 (fifo_count == 1) ? "" : "s", 930 (fifo_count == 1) ? "" : "s",
949 fifo_dest); 931 fifo_dest);
@@ -988,7 +970,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
988 ? musb_readb(epio, MUSB_COUNT0) 970 ? musb_readb(epio, MUSB_COUNT0)
989 : 0; 971 : 0;
990 972
991 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 973 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
992 csr, qh, len, urb, musb->ep0_stage); 974 csr, qh, len, urb, musb->ep0_stage);
993 975
994 /* if we just did status stage, we are done */ 976 /* if we just did status stage, we are done */
@@ -999,15 +981,15 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
999 981
1000 /* prepare status */ 982 /* prepare status */
1001 if (csr & MUSB_CSR0_H_RXSTALL) { 983 if (csr & MUSB_CSR0_H_RXSTALL) {
1002 DBG(6, "STALLING ENDPOINT\n"); 984 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1003 status = -EPIPE; 985 status = -EPIPE;
1004 986
1005 } else if (csr & MUSB_CSR0_H_ERROR) { 987 } else if (csr & MUSB_CSR0_H_ERROR) {
1006 DBG(2, "no response, csr0 %04x\n", csr); 988 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1007 status = -EPROTO; 989 status = -EPROTO;
1008 990
1009 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 991 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1010 DBG(2, "control NAK timeout\n"); 992 dev_dbg(musb->controller, "control NAK timeout\n");
1011 993
1012 /* NOTE: this code path would be a good place to PAUSE a 994 /* NOTE: this code path would be a good place to PAUSE a
1013 * control transfer, if another one is queued, so that 995 * control transfer, if another one is queued, so that
@@ -1022,7 +1004,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
1022 } 1004 }
1023 1005
1024 if (status) { 1006 if (status) {
1025 DBG(6, "aborting\n"); 1007 dev_dbg(musb->controller, "aborting\n");
1026 retval = IRQ_HANDLED; 1008 retval = IRQ_HANDLED;
1027 if (urb) 1009 if (urb)
1028 urb->status = status; 1010 urb->status = status;
@@ -1072,7 +1054,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
1072 /* flag status stage */ 1054 /* flag status stage */
1073 musb->ep0_stage = MUSB_EP0_STATUS; 1055 musb->ep0_stage = MUSB_EP0_STATUS;
1074 1056
1075 DBG(5, "ep0 STATUS, csr %04x\n", csr); 1057 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1076 1058
1077 } 1059 }
1078 musb_writew(epio, MUSB_CSR0, csr); 1060 musb_writew(epio, MUSB_CSR0, csr);
@@ -1126,31 +1108,31 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1126 1108
1127 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1109 /* with CPPI, DMA sometimes triggers "extra" irqs */
1128 if (!urb) { 1110 if (!urb) {
1129 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1111 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1130 return; 1112 return;
1131 } 1113 }
1132 1114
1133 pipe = urb->pipe; 1115 pipe = urb->pipe;
1134 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1116 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1135 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1117 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1136 dma ? ", dma" : ""); 1118 dma ? ", dma" : "");
1137 1119
1138 /* check for errors */ 1120 /* check for errors */
1139 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1121 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1140 /* dma was disabled, fifo flushed */ 1122 /* dma was disabled, fifo flushed */
1141 DBG(3, "TX end %d stall\n", epnum); 1123 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1142 1124
1143 /* stall; record URB status */ 1125 /* stall; record URB status */
1144 status = -EPIPE; 1126 status = -EPIPE;
1145 1127
1146 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1128 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1147 /* (NON-ISO) dma was disabled, fifo flushed */ 1129 /* (NON-ISO) dma was disabled, fifo flushed */
1148 DBG(3, "TX 3strikes on ep=%d\n", epnum); 1130 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1149 1131
1150 status = -ETIMEDOUT; 1132 status = -ETIMEDOUT;
1151 1133
1152 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1134 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1153 DBG(6, "TX end=%d device not responding\n", epnum); 1135 dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
1154 1136
1155 /* NOTE: this code path would be a good place to PAUSE a 1137 /* NOTE: this code path would be a good place to PAUSE a
1156 * transfer, if there's some other (nonperiodic) tx urb 1138 * transfer, if there's some other (nonperiodic) tx urb
@@ -1195,7 +1177,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1195 1177
1196 /* second cppi case */ 1178 /* second cppi case */
1197 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1179 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1198 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1180 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1199 return; 1181 return;
1200 } 1182 }
1201 1183
@@ -1254,7 +1236,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1254 * FIFO mode too... 1236 * FIFO mode too...
1255 */ 1237 */
1256 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1238 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1257 DBG(2, "DMA complete but packet still in FIFO, " 1239 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1258 "CSR %04x\n", tx_csr); 1240 "CSR %04x\n", tx_csr);
1259 return; 1241 return;
1260 } 1242 }
@@ -1321,7 +1303,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1321 return; 1303 return;
1322 } 1304 }
1323 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1305 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1324 DBG(1, "not complete, but DMA enabled?\n"); 1306 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1325 return; 1307 return;
1326 } 1308 }
1327 1309
@@ -1462,7 +1444,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1462 * usbtest #11 (unlinks) triggers it regularly, sometimes 1444 * usbtest #11 (unlinks) triggers it regularly, sometimes
1463 * with fifo full. (Only with DMA??) 1445 * with fifo full. (Only with DMA??)
1464 */ 1446 */
1465 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1447 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1466 musb_readw(epio, MUSB_RXCOUNT)); 1448 musb_readw(epio, MUSB_RXCOUNT));
1467 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1449 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1468 return; 1450 return;
@@ -1470,20 +1452,20 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1470 1452
1471 pipe = urb->pipe; 1453 pipe = urb->pipe;
1472 1454
1473 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1455 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1474 epnum, rx_csr, urb->actual_length, 1456 epnum, rx_csr, urb->actual_length,
1475 dma ? dma->actual_len : 0); 1457 dma ? dma->actual_len : 0);
1476 1458
1477 /* check for errors, concurrent stall & unlink is not really 1459 /* check for errors, concurrent stall & unlink is not really
1478 * handled yet! */ 1460 * handled yet! */
1479 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1461 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1480 DBG(3, "RX end %d STALL\n", epnum); 1462 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1481 1463
1482 /* stall; record URB status */ 1464 /* stall; record URB status */
1483 status = -EPIPE; 1465 status = -EPIPE;
1484 1466
1485 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1467 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1486 DBG(3, "end %d RX proto error\n", epnum); 1468 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1487 1469
1488 status = -EPROTO; 1470 status = -EPROTO;
1489 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1471 musb_writeb(epio, MUSB_RXINTERVAL, 0);
@@ -1491,7 +1473,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1491 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1473 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1492 1474
1493 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1475 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1494 DBG(6, "RX end %d NAK timeout\n", epnum); 1476 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1495 1477
1496 /* NOTE: NAKing is *NOT* an error, so we want to 1478 /* NOTE: NAKing is *NOT* an error, so we want to
1497 * continue. Except ... if there's a request for 1479 * continue. Except ... if there's a request for
@@ -1514,12 +1496,12 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1514 1496
1515 goto finish; 1497 goto finish;
1516 } else { 1498 } else {
1517 DBG(4, "RX end %d ISO data error\n", epnum); 1499 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1518 /* packet error reported later */ 1500 /* packet error reported later */
1519 iso_err = true; 1501 iso_err = true;
1520 } 1502 }
1521 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1503 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1522 DBG(3, "end %d high bandwidth incomplete ISO packet RX\n", 1504 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1523 epnum); 1505 epnum);
1524 status = -EPROTO; 1506 status = -EPROTO;
1525 } 1507 }
@@ -1565,7 +1547,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1565 done = true; 1547 done = true;
1566 } 1548 }
1567 1549
1568 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1550 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1569 xfer_len, dma ? ", dma" : ""); 1551 xfer_len, dma ? ", dma" : "");
1570 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1552 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1571 1553
@@ -1615,7 +1597,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1615 MUSB_RXCSR_H_WZC_BITS | val); 1597 MUSB_RXCSR_H_WZC_BITS | val);
1616 } 1598 }
1617 1599
1618 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, 1600 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1619 done ? "off" : "reset", 1601 done ? "off" : "reset",
1620 musb_readw(epio, MUSB_RXCSR), 1602 musb_readw(epio, MUSB_RXCSR),
1621 musb_readw(epio, MUSB_RXCOUNT)); 1603 musb_readw(epio, MUSB_RXCOUNT));
@@ -1648,7 +1630,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1648 1630
1649 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1631 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1650 1632
1651 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n", 1633 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
1652 epnum, rx_count, 1634 epnum, rx_count,
1653 urb->transfer_dma 1635 urb->transfer_dma
1654 + urb->actual_length, 1636 + urb->actual_length,
@@ -1672,7 +1654,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1672 d_status = -EOVERFLOW; 1654 d_status = -EOVERFLOW;
1673 urb->error_count++; 1655 urb->error_count++;
1674 } 1656 }
1675 DBG(2, "** OVERFLOW %d into %d\n",\ 1657 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1676 rx_count, d->length); 1658 rx_count, d->length);
1677 1659
1678 length = d->length; 1660 length = d->length;
@@ -1760,7 +1742,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1760 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); 1742 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1761 done = musb_host_packet_rx(musb, urb, 1743 done = musb_host_packet_rx(musb, urb,
1762 epnum, iso_err); 1744 epnum, iso_err);
1763 DBG(6, "read %spacket\n", done ? "last " : ""); 1745 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
1764 } 1746 }
1765 } 1747 }
1766 1748
@@ -1881,7 +1863,7 @@ static int musb_schedule(
1881 idle = 1; 1863 idle = 1;
1882 qh->mux = 0; 1864 qh->mux = 0;
1883 hw_ep = musb->endpoints + best_end; 1865 hw_ep = musb->endpoints + best_end;
1884 DBG(4, "qh %p periodic slot %d\n", qh, best_end); 1866 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
1885success: 1867success:
1886 if (head) { 1868 if (head) {
1887 idle = list_empty(head); 1869 idle = list_empty(head);
@@ -2087,6 +2069,7 @@ done:
2087static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2069static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2088{ 2070{
2089 struct musb_hw_ep *ep = qh->hw_ep; 2071 struct musb_hw_ep *ep = qh->hw_ep;
2072 struct musb *musb = ep->musb;
2090 void __iomem *epio = ep->regs; 2073 void __iomem *epio = ep->regs;
2091 unsigned hw_end = ep->epnum; 2074 unsigned hw_end = ep->epnum;
2092 void __iomem *regs = ep->musb->mregs; 2075 void __iomem *regs = ep->musb->mregs;
@@ -2102,7 +2085,7 @@ static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2102 dma = is_in ? ep->rx_channel : ep->tx_channel; 2085 dma = is_in ? ep->rx_channel : ep->tx_channel;
2103 if (dma) { 2086 if (dma) {
2104 status = ep->musb->dma_controller->channel_abort(dma); 2087 status = ep->musb->dma_controller->channel_abort(dma);
2105 DBG(status ? 1 : 3, 2088 dev_dbg(musb->controller,
2106 "abort %cX%d DMA for urb %p --> %d\n", 2089 "abort %cX%d DMA for urb %p --> %d\n",
2107 is_in ? 'R' : 'T', ep->epnum, 2090 is_in ? 'R' : 'T', ep->epnum,
2108 urb, status); 2091 urb, status);
@@ -2149,7 +2132,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2149 int is_in = usb_pipein(urb->pipe); 2132 int is_in = usb_pipein(urb->pipe);
2150 int ret; 2133 int ret;
2151 2134
2152 DBG(4, "urb=%p, dev%d ep%d%s\n", urb, 2135 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2153 usb_pipedevice(urb->pipe), 2136 usb_pipedevice(urb->pipe),
2154 usb_pipeendpoint(urb->pipe), 2137 usb_pipeendpoint(urb->pipe),
2155 is_in ? "in" : "out"); 2138 is_in ? "in" : "out");
@@ -2304,7 +2287,7 @@ static int musb_bus_suspend(struct usb_hcd *hcd)
2304 2287
2305 if (musb->is_active) { 2288 if (musb->is_active) {
2306 WARNING("trying to suspend as %s while active\n", 2289 WARNING("trying to suspend as %s while active\n",
2307 otg_state_string(musb)); 2290 otg_state_string(musb->xceiv->state));
2308 return -EBUSY; 2291 return -EBUSY;
2309 } else 2292 } else
2310 return 0; 2293 return 0;
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index 489104a5ae14..2d80a5758838 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -74,7 +74,7 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
74 break; 74 break;
75 } 75 }
76 76
77 DBG(3, "Root port suspended, power %02x\n", power); 77 dev_dbg(musb->controller, "Root port suspended, power %02x\n", power);
78 78
79 musb->port1_status |= USB_PORT_STAT_SUSPEND; 79 musb->port1_status |= USB_PORT_STAT_SUSPEND;
80 switch (musb->xceiv->state) { 80 switch (musb->xceiv->state) {
@@ -97,15 +97,15 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
97 break; 97 break;
98#endif 98#endif
99 default: 99 default:
100 DBG(1, "bogus rh suspend? %s\n", 100 dev_dbg(musb->controller, "bogus rh suspend? %s\n",
101 otg_state_string(musb)); 101 otg_state_string(musb->xceiv->state));
102 } 102 }
103 } else if (power & MUSB_POWER_SUSPENDM) { 103 } else if (power & MUSB_POWER_SUSPENDM) {
104 power &= ~MUSB_POWER_SUSPENDM; 104 power &= ~MUSB_POWER_SUSPENDM;
105 power |= MUSB_POWER_RESUME; 105 power |= MUSB_POWER_RESUME;
106 musb_writeb(mbase, MUSB_POWER, power); 106 musb_writeb(mbase, MUSB_POWER, power);
107 107
108 DBG(3, "Root port resuming, power %02x\n", power); 108 dev_dbg(musb->controller, "Root port resuming, power %02x\n", power);
109 109
110 /* later, GetPortStatus will stop RESUME signaling */ 110 /* later, GetPortStatus will stop RESUME signaling */
111 musb->port1_status |= MUSB_PORT_STAT_RESUME; 111 musb->port1_status |= MUSB_PORT_STAT_RESUME;
@@ -120,7 +120,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
120 120
121#ifdef CONFIG_USB_MUSB_OTG 121#ifdef CONFIG_USB_MUSB_OTG
122 if (musb->xceiv->state == OTG_STATE_B_IDLE) { 122 if (musb->xceiv->state == OTG_STATE_B_IDLE) {
123 DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n"); 123 dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
124 musb->port1_status &= ~USB_PORT_STAT_RESET; 124 musb->port1_status &= ~USB_PORT_STAT_RESET;
125 return; 125 return;
126 } 126 }
@@ -159,7 +159,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
159 musb->port1_status &= ~USB_PORT_STAT_ENABLE; 159 musb->port1_status &= ~USB_PORT_STAT_ENABLE;
160 musb->rh_timer = jiffies + msecs_to_jiffies(50); 160 musb->rh_timer = jiffies + msecs_to_jiffies(50);
161 } else { 161 } else {
162 DBG(4, "root port reset stopped\n"); 162 dev_dbg(musb->controller, "root port reset stopped\n");
163 musb_writeb(mbase, MUSB_POWER, 163 musb_writeb(mbase, MUSB_POWER,
164 power & ~MUSB_POWER_RESET); 164 power & ~MUSB_POWER_RESET);
165 165
@@ -167,7 +167,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
167 167
168 power = musb_readb(mbase, MUSB_POWER); 168 power = musb_readb(mbase, MUSB_POWER);
169 if (power & MUSB_POWER_HSMODE) { 169 if (power & MUSB_POWER_HSMODE) {
170 DBG(4, "high-speed device connected\n"); 170 dev_dbg(musb->controller, "high-speed device connected\n");
171 musb->port1_status |= USB_PORT_STAT_HIGH_SPEED; 171 musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;
172 } 172 }
173 173
@@ -208,7 +208,8 @@ void musb_root_disconnect(struct musb *musb)
208 musb->xceiv->state = OTG_STATE_B_IDLE; 208 musb->xceiv->state = OTG_STATE_B_IDLE;
209 break; 209 break;
210 default: 210 default:
211 DBG(1, "host disconnect (%s)\n", otg_state_string(musb)); 211 dev_dbg(musb->controller, "host disconnect (%s)\n",
212 otg_state_string(musb->xceiv->state));
212 } 213 }
213} 214}
214 215
@@ -287,7 +288,7 @@ int musb_hub_control(
287 default: 288 default:
288 goto error; 289 goto error;
289 } 290 }
290 DBG(5, "clear feature %d\n", wValue); 291 dev_dbg(musb->controller, "clear feature %d\n", wValue);
291 musb->port1_status &= ~(1 << wValue); 292 musb->port1_status &= ~(1 << wValue);
292 break; 293 break;
293 case GetHubDescriptor: 294 case GetHubDescriptor:
@@ -329,7 +330,7 @@ int musb_hub_control(
329 330
330 power = musb_readb(musb->mregs, MUSB_POWER); 331 power = musb_readb(musb->mregs, MUSB_POWER);
331 power &= ~MUSB_POWER_RESUME; 332 power &= ~MUSB_POWER_RESUME;
332 DBG(4, "root port resume stopped, power %02x\n", 333 dev_dbg(musb->controller, "root port resume stopped, power %02x\n",
333 power); 334 power);
334 musb_writeb(musb->mregs, MUSB_POWER, power); 335 musb_writeb(musb->mregs, MUSB_POWER, power);
335 336
@@ -352,7 +353,7 @@ int musb_hub_control(
352 (__le32 *) buf); 353 (__le32 *) buf);
353 354
354 /* port change status is more interesting */ 355 /* port change status is more interesting */
355 DBG(get_unaligned((u16 *)(buf+2)) ? 2 : 5, "port status %08x\n", 356 dev_dbg(musb->controller, "port status %08x\n",
356 musb->port1_status); 357 musb->port1_status);
357 break; 358 break;
358 case SetPortFeature: 359 case SetPortFeature:
@@ -423,7 +424,7 @@ int musb_hub_control(
423 default: 424 default:
424 goto error; 425 goto error;
425 } 426 }
426 DBG(5, "set feature %d\n", wValue); 427 dev_dbg(musb->controller, "set feature %d\n", wValue);
427 musb->port1_status |= 1 << wValue; 428 musb->port1_status |= 1 << wValue;
428 break; 429 break;
429 430
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index d281792db05c..f70c5a577736 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -122,11 +122,12 @@ static void configure_channel(struct dma_channel *channel,
122{ 122{
123 struct musb_dma_channel *musb_channel = channel->private_data; 123 struct musb_dma_channel *musb_channel = channel->private_data;
124 struct musb_dma_controller *controller = musb_channel->controller; 124 struct musb_dma_controller *controller = musb_channel->controller;
125 struct musb *musb = controller->private_data;
125 void __iomem *mbase = controller->base; 126 void __iomem *mbase = controller->base;
126 u8 bchannel = musb_channel->idx; 127 u8 bchannel = musb_channel->idx;
127 u16 csr = 0; 128 u16 csr = 0;
128 129
129 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", 130 dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
130 channel, packet_sz, dma_addr, len, mode); 131 channel, packet_sz, dma_addr, len, mode);
131 132
132 if (mode) { 133 if (mode) {
@@ -161,7 +162,7 @@ static int dma_channel_program(struct dma_channel *channel,
161 struct musb_dma_controller *controller = musb_channel->controller; 162 struct musb_dma_controller *controller = musb_channel->controller;
162 struct musb *musb = controller->private_data; 163 struct musb *musb = controller->private_data;
163 164
164 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", 165 dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
165 musb_channel->epnum, 166 musb_channel->epnum,
166 musb_channel->transmit ? "Tx" : "Rx", 167 musb_channel->transmit ? "Tx" : "Rx",
167 packet_sz, dma_addr, len, mode); 168 packet_sz, dma_addr, len, mode);
@@ -274,7 +275,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
274#endif 275#endif
275 276
276 if (!int_hsdma) { 277 if (!int_hsdma) {
277 DBG(2, "spurious DMA irq\n"); 278 dev_dbg(musb->controller, "spurious DMA irq\n");
278 279
279 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 280 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
280 musb_channel = (struct musb_dma_channel *) 281 musb_channel = (struct musb_dma_channel *)
@@ -288,7 +289,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
288 } 289 }
289 } 290 }
290 291
291 DBG(2, "int_hsdma = 0x%x\n", int_hsdma); 292 dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
292 293
293 if (!int_hsdma) 294 if (!int_hsdma)
294 goto done; 295 goto done;
@@ -315,7 +316,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
315 channel->actual_len = addr 316 channel->actual_len = addr
316 - musb_channel->start_addr; 317 - musb_channel->start_addr;
317 318
318 DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", 319 dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
319 channel, musb_channel->start_addr, 320 channel, musb_channel->start_addr,
320 addr, channel->actual_len, 321 addr, channel->actual_len,
321 musb_channel->len, 322 musb_channel->len,
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index e9e60b6e0583..c5d4c44d0ffa 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -76,7 +76,7 @@ static void musb_do_idle(unsigned long _musb)
76 if (musb->port1_status & MUSB_PORT_STAT_RESUME) { 76 if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
77 power = musb_readb(musb->mregs, MUSB_POWER); 77 power = musb_readb(musb->mregs, MUSB_POWER);
78 power &= ~MUSB_POWER_RESUME; 78 power &= ~MUSB_POWER_RESUME;
79 DBG(1, "root port resume stopped, power %02x\n", power); 79 dev_dbg(musb->controller, "root port resume stopped, power %02x\n", power);
80 musb_writeb(musb->mregs, MUSB_POWER, power); 80 musb_writeb(musb->mregs, MUSB_POWER, power);
81 musb->is_active = 1; 81 musb->is_active = 1;
82 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND 82 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
@@ -114,7 +114,8 @@ static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
114 /* Never idle if active, or when VBUS timeout is not set as host */ 114 /* Never idle if active, or when VBUS timeout is not set as host */
115 if (musb->is_active || ((musb->a_wait_bcon == 0) 115 if (musb->is_active || ((musb->a_wait_bcon == 0)
116 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 116 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
117 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 117 dev_dbg(musb->controller, "%s active, deleting timer\n",
118 otg_state_string(musb->xceiv->state));
118 del_timer(&musb_idle_timer); 119 del_timer(&musb_idle_timer);
119 last_timer = jiffies; 120 last_timer = jiffies;
120 return; 121 return;
@@ -124,14 +125,14 @@ static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
124 if (!timer_pending(&musb_idle_timer)) 125 if (!timer_pending(&musb_idle_timer))
125 last_timer = timeout; 126 last_timer = timeout;
126 else { 127 else {
127 DBG(4, "Longer idle timer already pending, ignoring\n"); 128 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
128 return; 129 return;
129 } 130 }
130 } 131 }
131 last_timer = timeout; 132 last_timer = timeout;
132 133
133 DBG(4, "%s inactive, for idle timer for %lu ms\n", 134 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
134 otg_state_string(musb), 135 otg_state_string(musb->xceiv->state),
135 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 136 (unsigned long)jiffies_to_msecs(timeout - jiffies));
136 mod_timer(&musb_idle_timer, timeout); 137 mod_timer(&musb_idle_timer, timeout);
137} 138}
@@ -193,9 +194,9 @@ static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
193 } 194 }
194 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 195 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
195 196
196 DBG(1, "VBUS %s, devctl %02x " 197 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
197 /* otg %3x conf %08x prcm %08x */ "\n", 198 /* otg %3x conf %08x prcm %08x */ "\n",
198 otg_state_string(musb), 199 otg_state_string(musb->xceiv->state),
199 musb_readb(musb->mregs, MUSB_DEVCTL)); 200 musb_readb(musb->mregs, MUSB_DEVCTL));
200} 201}
201 202
@@ -239,7 +240,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
239 240
240 switch (event) { 241 switch (event) {
241 case USB_EVENT_ID: 242 case USB_EVENT_ID:
242 DBG(4, "ID GND\n"); 243 dev_dbg(musb->controller, "ID GND\n");
243 244
244 if (is_otg_enabled(musb)) { 245 if (is_otg_enabled(musb)) {
245#ifdef CONFIG_USB_GADGET_MUSB_HDRC 246#ifdef CONFIG_USB_GADGET_MUSB_HDRC
@@ -257,7 +258,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
257 break; 258 break;
258 259
259 case USB_EVENT_VBUS: 260 case USB_EVENT_VBUS:
260 DBG(4, "VBUS Connect\n"); 261 dev_dbg(musb->controller, "VBUS Connect\n");
261 262
262#ifdef CONFIG_USB_GADGET_MUSB_HDRC 263#ifdef CONFIG_USB_GADGET_MUSB_HDRC
263 if (musb->gadget_driver) 264 if (musb->gadget_driver)
@@ -267,7 +268,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
267 break; 268 break;
268 269
269 case USB_EVENT_NONE: 270 case USB_EVENT_NONE:
270 DBG(4, "VBUS Disconnect\n"); 271 dev_dbg(musb->controller, "VBUS Disconnect\n");
271 272
272#ifdef CONFIG_USB_GADGET_MUSB_HDRC 273#ifdef CONFIG_USB_GADGET_MUSB_HDRC
273 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 274 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
@@ -285,7 +286,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
285 otg_shutdown(musb->xceiv); 286 otg_shutdown(musb->xceiv);
286 break; 287 break;
287 default: 288 default:
288 DBG(4, "ID float\n"); 289 dev_dbg(musb->controller, "ID float\n");
289 return NOTIFY_DONE; 290 return NOTIFY_DONE;
290 } 291 }
291 292
@@ -339,7 +340,7 @@ static int omap2430_musb_init(struct musb *musb)
339 status = otg_register_notifier(musb->xceiv, &musb->nb); 340 status = otg_register_notifier(musb->xceiv, &musb->nb);
340 341
341 if (status) 342 if (status)
342 DBG(1, "notification register failed\n"); 343 dev_dbg(musb->controller, "notification register failed\n");
343 344
344 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 345 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
345 346
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index c47aac4a1f98..b410357cf016 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -106,7 +106,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
@@ -115,7 +115,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
118 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
121 phy_otg_ctrl = 0; 121 phy_otg_ctrl = 0;
@@ -172,13 +172,14 @@ static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
172 172
173void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 173void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
174{ 174{
175 struct musb *musb = hw_ep->musb;
175 void __iomem *ep_conf = hw_ep->conf; 176 void __iomem *ep_conf = hw_ep->conf;
176 void __iomem *fifo = hw_ep->fifo; 177 void __iomem *fifo = hw_ep->fifo;
177 u8 epnum = hw_ep->epnum; 178 u8 epnum = hw_ep->epnum;
178 179
179 prefetch(buf); 180 prefetch(buf);
180 181
181 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 182 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
182 'T', epnum, fifo, len, buf); 183 'T', epnum, fifo, len, buf);
183 184
184 if (epnum) 185 if (epnum)
@@ -221,11 +222,12 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
221 222
222void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 223void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
223{ 224{
225 struct musb *musb = hw_ep->musb;
224 void __iomem *ep_conf = hw_ep->conf; 226 void __iomem *ep_conf = hw_ep->conf;
225 void __iomem *fifo = hw_ep->fifo; 227 void __iomem *fifo = hw_ep->fifo;
226 u8 epnum = hw_ep->epnum; 228 u8 epnum = hw_ep->epnum;
227 229
228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 230 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'R', epnum, fifo, len, buf); 231 'R', epnum, fifo, len, buf);
230 232
231 if (epnum) 233 if (epnum)
@@ -304,7 +306,7 @@ static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
304 } 306 }
305 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 307 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
306 308
307 DBG(2, "draw max %d mA VBUS\n", mA); 309 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
308 return 0; 310 return 0;
309} 311}
310 312
@@ -374,7 +376,7 @@ static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 376 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 377 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
376 378
377 DBG(6, "idle, wake on %02x\n", wakeup_enables); 379 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
378} 380}
379 381
380/* 382/*
@@ -421,8 +423,8 @@ static void musb_do_idle(unsigned long _musb)
421 if ((musb->a_wait_bcon != 0) 423 if ((musb->a_wait_bcon != 0)
422 && (musb->idle_timeout == 0 424 && (musb->idle_timeout == 0
423 || time_after(jiffies, musb->idle_timeout))) { 425 || time_after(jiffies, musb->idle_timeout))) {
424 DBG(4, "Nothing connected %s, turning off VBUS\n", 426 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
425 otg_state_string(musb)); 427 otg_state_string(musb->xceiv->state));
426 } 428 }
427 /* FALLTHROUGH */ 429 /* FALLTHROUGH */
428 case OTG_STATE_A_IDLE: 430 case OTG_STATE_A_IDLE:
@@ -481,7 +483,8 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
481 /* Never idle if active, or when VBUS timeout is not set as host */ 483 /* Never idle if active, or when VBUS timeout is not set as host */
482 if (musb->is_active || ((musb->a_wait_bcon == 0) 484 if (musb->is_active || ((musb->a_wait_bcon == 0)
483 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 485 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
484 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 486 dev_dbg(musb->controller, "%s active, deleting timer\n",
487 otg_state_string(musb->xceiv->state));
485 del_timer(&musb_idle_timer); 488 del_timer(&musb_idle_timer);
486 last_timer = jiffies; 489 last_timer = jiffies;
487 return; 490 return;
@@ -491,14 +494,14 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
491 if (!timer_pending(&musb_idle_timer)) 494 if (!timer_pending(&musb_idle_timer))
492 last_timer = timeout; 495 last_timer = timeout;
493 else { 496 else {
494 DBG(4, "Longer idle timer already pending, ignoring\n"); 497 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
495 return; 498 return;
496 } 499 }
497 } 500 }
498 last_timer = timeout; 501 last_timer = timeout;
499 502
500 DBG(4, "%s inactive, for idle timer for %lu ms\n", 503 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
501 otg_state_string(musb), 504 otg_state_string(musb->xceiv->state),
502 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 505 (unsigned long)jiffies_to_msecs(timeout - jiffies));
503 mod_timer(&musb_idle_timer, timeout); 506 mod_timer(&musb_idle_timer, timeout);
504} 507}
@@ -572,8 +575,8 @@ static void tusb_musb_set_vbus(struct musb *musb, int is_on)
572 musb_writel(tbase, TUSB_DEV_CONF, conf); 575 musb_writel(tbase, TUSB_DEV_CONF, conf);
573 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 576 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
574 577
575 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 578 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
576 otg_state_string(musb), 579 otg_state_string(musb->xceiv->state),
577 musb_readb(musb->mregs, MUSB_DEVCTL), 580 musb_readb(musb->mregs, MUSB_DEVCTL),
578 musb_readl(tbase, TUSB_DEV_OTG_STAT), 581 musb_readl(tbase, TUSB_DEV_OTG_STAT),
579 conf, prcm); 582 conf, prcm);
@@ -633,7 +636,7 @@ static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
633#endif 636#endif
634 637
635 default: 638 default:
636 DBG(2, "Trying to set mode %i\n", musb_mode); 639 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
637 return -EINVAL; 640 return -EINVAL;
638 } 641 }
639 642
@@ -666,7 +669,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
666 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 669 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
667 else 670 else
668 default_a = is_host_enabled(musb); 671 default_a = is_host_enabled(musb);
669 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 672 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
670 musb->xceiv->default_a = default_a; 673 musb->xceiv->default_a = default_a;
671 tusb_musb_set_vbus(musb, default_a); 674 tusb_musb_set_vbus(musb, default_a);
672 675
@@ -693,7 +696,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
693#endif 696#endif
694 697
695 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 698 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
696 DBG(1, "Forcing disconnect (no interrupt)\n"); 699 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
697 if (musb->xceiv->state != OTG_STATE_B_IDLE) { 700 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
698 /* INTR_DISCONNECT can hide... */ 701 /* INTR_DISCONNECT can hide... */
699 musb->xceiv->state = OTG_STATE_B_IDLE; 702 musb->xceiv->state = OTG_STATE_B_IDLE;
@@ -701,18 +704,18 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
701 } 704 }
702 musb->is_active = 0; 705 musb->is_active = 0;
703 } 706 }
704 DBG(2, "vbus change, %s, otg %03x\n", 707 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
705 otg_state_string(musb), otg_stat); 708 otg_state_string(musb->xceiv->state), otg_stat);
706 idle_timeout = jiffies + (1 * HZ); 709 idle_timeout = jiffies + (1 * HZ);
707 schedule_work(&musb->irq_work); 710 schedule_work(&musb->irq_work);
708 711
709 } else /* A-dev state machine */ { 712 } else /* A-dev state machine */ {
710 DBG(2, "vbus change, %s, otg %03x\n", 713 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
711 otg_state_string(musb), otg_stat); 714 otg_state_string(musb->xceiv->state), otg_stat);
712 715
713 switch (musb->xceiv->state) { 716 switch (musb->xceiv->state) {
714 case OTG_STATE_A_IDLE: 717 case OTG_STATE_A_IDLE:
715 DBG(2, "Got SRP, turning on VBUS\n"); 718 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
716 musb_platform_set_vbus(musb, 1); 719 musb_platform_set_vbus(musb, 1);
717 720
718 /* CONNECT can wake if a_wait_bcon is set */ 721 /* CONNECT can wake if a_wait_bcon is set */
@@ -756,7 +759,8 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
756 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 759 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
757 u8 devctl; 760 u8 devctl;
758 761
759 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat); 762 dev_dbg(musb->controller, "%s timer, %03x\n",
763 otg_state_string(musb->xceiv->state), otg_stat);
760 764
761 switch (musb->xceiv->state) { 765 switch (musb->xceiv->state) {
762 case OTG_STATE_A_WAIT_VRISE: 766 case OTG_STATE_A_WAIT_VRISE:
@@ -767,7 +771,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
767 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 771 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
768 if ((devctl & MUSB_DEVCTL_VBUS) 772 if ((devctl & MUSB_DEVCTL_VBUS)
769 != MUSB_DEVCTL_VBUS) { 773 != MUSB_DEVCTL_VBUS) {
770 DBG(2, "devctl %02x\n", devctl); 774 dev_dbg(musb->controller, "devctl %02x\n", devctl);
771 break; 775 break;
772 } 776 }
773 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 777 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
@@ -812,7 +816,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
812 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 816 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
813 817
814 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 818 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
815 DBG(3, "TUSB IRQ %08x\n", int_src); 819 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
816 820
817 musb->int_usb = (u8) int_src; 821 musb->int_usb = (u8) int_src;
818 822
@@ -833,7 +837,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
833 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 837 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
834 if (reg == i) 838 if (reg == i)
835 break; 839 break;
836 DBG(6, "TUSB NOR not ready\n"); 840 dev_dbg(musb->controller, "TUSB NOR not ready\n");
837 } 841 }
838 842
839 /* work around issue 13 (2nd half) */ 843 /* work around issue 13 (2nd half) */
@@ -845,7 +849,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
845 musb->is_active = 1; 849 musb->is_active = 1;
846 schedule_work(&musb->irq_work); 850 schedule_work(&musb->irq_work);
847 } 851 }
848 DBG(3, "wake %sactive %02x\n", 852 dev_dbg(musb->controller, "wake %sactive %02x\n",
849 musb->is_active ? "" : "in", reg); 853 musb->is_active ? "" : "in", reg);
850 854
851 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 855 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
@@ -867,7 +871,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
867 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 871 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
868 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 872 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
869 873
870 DBG(3, "DMA IRQ %08x\n", dma_src); 874 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
871 real_dma_src = ~real_dma_src & dma_src; 875 real_dma_src = ~real_dma_src & dma_src;
872 if (tusb_dma_omap() && real_dma_src) { 876 if (tusb_dma_omap() && real_dma_src) {
873 int tx_source = (real_dma_src & 0xffff); 877 int tx_source = (real_dma_src & 0xffff);
@@ -875,7 +879,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
875 879
876 for (i = 1; i <= 15; i++) { 880 for (i = 1; i <= 15; i++) {
877 if (tx_source & (1 << i)) { 881 if (tx_source & (1 << i)) {
878 DBG(3, "completing ep%i %s\n", i, "tx"); 882 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
879 musb_dma_completion(musb, i, 1); 883 musb_dma_completion(musb, i, 1);
880 } 884 }
881 } 885 }
diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
index 99cb541e4ef0..c784e6c03aac 100644
--- a/drivers/usb/musb/tusb6010_omap.c
+++ b/drivers/usb/musb/tusb6010_omap.c
@@ -65,7 +65,7 @@ static int tusb_omap_dma_start(struct dma_controller *c)
65 65
66 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 66 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
67 67
68 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */ 68 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
69 69
70 return 0; 70 return 0;
71} 71}
@@ -76,7 +76,7 @@ static int tusb_omap_dma_stop(struct dma_controller *c)
76 76
77 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 77 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
78 78
79 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */ 79 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
80 80
81 return 0; 81 return 0;
82} 82}
@@ -89,7 +89,7 @@ static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
89 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 89 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
90 90
91 if (reg != 0) { 91 if (reg != 0) {
92 DBG(3, "ep%i dmareq0 is busy for ep%i\n", 92 dev_dbg(musb->controller, "ep%i dmareq0 is busy for ep%i\n",
93 chdat->epnum, reg & 0xf); 93 chdat->epnum, reg & 0xf);
94 return -EAGAIN; 94 return -EAGAIN;
95 } 95 }
@@ -143,7 +143,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
143 if (ch_status != OMAP_DMA_BLOCK_IRQ) 143 if (ch_status != OMAP_DMA_BLOCK_IRQ)
144 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); 144 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
145 145
146 DBG(3, "ep%i %s dma callback ch: %i status: %x\n", 146 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
147 chdat->epnum, chdat->tx ? "tx" : "rx", 147 chdat->epnum, chdat->tx ? "tx" : "rx",
148 ch, ch_status); 148 ch, ch_status);
149 149
@@ -156,7 +156,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
156 156
157 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ 157 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
158 if (unlikely(remaining > chdat->transfer_len)) { 158 if (unlikely(remaining > chdat->transfer_len)) {
159 DBG(2, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", 159 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
160 chdat->tx ? "tx" : "rx", chdat->ch, 160 chdat->tx ? "tx" : "rx", chdat->ch,
161 remaining); 161 remaining);
162 remaining = 0; 162 remaining = 0;
@@ -165,13 +165,13 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
165 channel->actual_len = chdat->transfer_len - remaining; 165 channel->actual_len = chdat->transfer_len - remaining;
166 pio = chdat->len - channel->actual_len; 166 pio = chdat->len - channel->actual_len;
167 167
168 DBG(3, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); 168 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
169 169
170 /* Transfer remaining 1 - 31 bytes */ 170 /* Transfer remaining 1 - 31 bytes */
171 if (pio > 0 && pio < 32) { 171 if (pio > 0 && pio < 32) {
172 u8 *buf; 172 u8 *buf;
173 173
174 DBG(3, "Using PIO for remaining %lu bytes\n", pio); 174 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
175 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 175 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
176 if (chdat->tx) { 176 if (chdat->tx) {
177 dma_unmap_single(dev, chdat->dma_addr, 177 dma_unmap_single(dev, chdat->dma_addr,
@@ -209,7 +209,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
209 u16 csr; 209 u16 csr;
210 210
211 if (chdat->tx) { 211 if (chdat->tx) {
212 DBG(3, "terminating short tx packet\n"); 212 dev_dbg(musb->controller, "terminating short tx packet\n");
213 musb_ep_select(mbase, chdat->epnum); 213 musb_ep_select(mbase, chdat->epnum);
214 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 214 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
215 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY 215 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
@@ -264,7 +264,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
264 264
265 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); 265 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
266 if (dma_remaining) { 266 if (dma_remaining) {
267 DBG(2, "Busy %s dma ch%i, not using: %08x\n", 267 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
268 chdat->tx ? "tx" : "rx", chdat->ch, 268 chdat->tx ? "tx" : "rx", chdat->ch,
269 dma_remaining); 269 dma_remaining);
270 return false; 270 return false;
@@ -283,7 +283,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
283 sync_dev = chdat->sync_dev; 283 sync_dev = chdat->sync_dev;
284 } else { 284 } else {
285 if (tusb_omap_use_shared_dmareq(chdat) != 0) { 285 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
286 DBG(3, "could not get dma for ep%i\n", chdat->epnum); 286 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
287 return false; 287 return false;
288 } 288 }
289 if (tusb_dma->ch < 0) { 289 if (tusb_dma->ch < 0) {
@@ -326,7 +326,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
326 326
327 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ 327 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
328 328
329 DBG(3, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n", 329 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
330 chdat->epnum, chdat->tx ? "tx" : "rx", 330 chdat->epnum, chdat->tx ? "tx" : "rx",
331 ch, dma_addr, chdat->transfer_len, len, 331 ch, dma_addr, chdat->transfer_len, len,
332 chdat->transfer_packet_sz, packet_sz); 332 chdat->transfer_packet_sz, packet_sz);
@@ -370,7 +370,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
370 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ 370 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
371 } 371 }
372 372
373 DBG(3, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", 373 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
374 chdat->epnum, chdat->tx ? "tx" : "rx", 374 chdat->epnum, chdat->tx ? "tx" : "rx",
375 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, 375 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
376 ((dma_addr & 0x3) == 0) ? "sync" : "async", 376 ((dma_addr & 0x3) == 0) ? "sync" : "async",
@@ -525,7 +525,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
525 525
526 /* REVISIT: Why does dmareq5 not work? */ 526 /* REVISIT: Why does dmareq5 not work? */
527 if (hw_ep->epnum == 0) { 527 if (hw_ep->epnum == 0) {
528 DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); 528 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
529 return NULL; 529 return NULL;
530 } 530 }
531 531
@@ -585,7 +585,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
585 chdat->ch = -1; 585 chdat->ch = -1;
586 } 586 }
587 587
588 DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", 588 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
589 chdat->epnum, 589 chdat->epnum,
590 chdat->tx ? "tx" : "rx", 590 chdat->tx ? "tx" : "rx",
591 chdat->ch >= 0 ? "dedicated" : "shared", 591 chdat->ch >= 0 ? "dedicated" : "shared",
@@ -598,7 +598,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
598free_dmareq: 598free_dmareq:
599 tusb_omap_dma_free_dmareq(chdat); 599 tusb_omap_dma_free_dmareq(chdat);
600 600
601 DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum); 601 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
602 channel->status = MUSB_DMA_STATUS_UNKNOWN; 602 channel->status = MUSB_DMA_STATUS_UNKNOWN;
603 603
604 return NULL; 604 return NULL;
@@ -611,7 +611,7 @@ static void tusb_omap_dma_release(struct dma_channel *channel)
611 void __iomem *tbase = musb->ctrl_base; 611 void __iomem *tbase = musb->ctrl_base;
612 u32 reg; 612 u32 reg;
613 613
614 DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch); 614 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
615 615
616 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 616 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
617 if (chdat->tx) 617 if (chdat->tx)
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
new file mode 100644
index 000000000000..cecace411832
--- /dev/null
+++ b/drivers/usb/musb/ux500_dma.c
@@ -0,0 +1,422 @@
1/*
2 * drivers/usb/musb/ux500_dma.c
3 *
4 * U8500 and U5500 DMA support code
5 *
6 * Copyright (C) 2009 STMicroelectronics
7 * Copyright (C) 2011 ST-Ericsson SA
8 * Authors:
9 * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
10 * Praveena Nadahally <praveen.nadahally@stericsson.com>
11 * Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
12 *
13 * This program is free software: you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation, either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 */
26
27#include <linux/device.h>
28#include <linux/interrupt.h>
29#include <linux/platform_device.h>
30#include <linux/dma-mapping.h>
31#include <linux/dmaengine.h>
32#include <linux/pfn.h>
33#include <mach/usb.h>
34#include "musb_core.h"
35
36struct ux500_dma_channel {
37 struct dma_channel channel;
38 struct ux500_dma_controller *controller;
39 struct musb_hw_ep *hw_ep;
40 struct work_struct channel_work;
41 struct dma_chan *dma_chan;
42 unsigned int cur_len;
43 dma_cookie_t cookie;
44 u8 ch_num;
45 u8 is_tx;
46 u8 is_allocated;
47};
48
49struct ux500_dma_controller {
50 struct dma_controller controller;
51 struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
52 struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
53 u32 num_rx_channels;
54 u32 num_tx_channels;
55 void *private_data;
56 dma_addr_t phy_base;
57};
58
59/* Work function invoked from DMA callback to handle tx transfers. */
60static void ux500_tx_work(struct work_struct *data)
61{
62 struct ux500_dma_channel *ux500_channel = container_of(data,
63 struct ux500_dma_channel, channel_work);
64 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
65 struct musb *musb = hw_ep->musb;
66 unsigned long flags;
67
68 DBG(4, "DMA tx transfer done on hw_ep=%d\n", hw_ep->epnum);
69
70 spin_lock_irqsave(&musb->lock, flags);
71 ux500_channel->channel.actual_len = ux500_channel->cur_len;
72 ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
73 musb_dma_completion(musb, hw_ep->epnum,
74 ux500_channel->is_tx);
75 spin_unlock_irqrestore(&musb->lock, flags);
76}
77
78/* Work function invoked from DMA callback to handle rx transfers. */
79static void ux500_rx_work(struct work_struct *data)
80{
81 struct ux500_dma_channel *ux500_channel = container_of(data,
82 struct ux500_dma_channel, channel_work);
83 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
84 struct musb *musb = hw_ep->musb;
85 unsigned long flags;
86
87 DBG(4, "DMA rx transfer done on hw_ep=%d\n", hw_ep->epnum);
88
89 spin_lock_irqsave(&musb->lock, flags);
90 ux500_channel->channel.actual_len = ux500_channel->cur_len;
91 ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
92 musb_dma_completion(musb, hw_ep->epnum,
93 ux500_channel->is_tx);
94 spin_unlock_irqrestore(&musb->lock, flags);
95}
96
97void ux500_dma_callback(void *private_data)
98{
99 struct dma_channel *channel = (struct dma_channel *)private_data;
100 struct ux500_dma_channel *ux500_channel = channel->private_data;
101
102 schedule_work(&ux500_channel->channel_work);
103}
104
105static bool ux500_configure_channel(struct dma_channel *channel,
106 u16 packet_sz, u8 mode,
107 dma_addr_t dma_addr, u32 len)
108{
109 struct ux500_dma_channel *ux500_channel = channel->private_data;
110 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
111 struct dma_chan *dma_chan = ux500_channel->dma_chan;
112 struct dma_async_tx_descriptor *dma_desc;
113 enum dma_data_direction direction;
114 struct scatterlist sg;
115 struct dma_slave_config slave_conf;
116 enum dma_slave_buswidth addr_width;
117 dma_addr_t usb_fifo_addr = (MUSB_FIFO_OFFSET(hw_ep->epnum) +
118 ux500_channel->controller->phy_base);
119
120 DBG(4, "packet_sz=%d, mode=%d, dma_addr=0x%x, len=%d is_tx=%d\n",
121 packet_sz, mode, dma_addr, len, ux500_channel->is_tx);
122
123 ux500_channel->cur_len = len;
124
125 sg_init_table(&sg, 1);
126 sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
127 offset_in_page(dma_addr));
128 sg_dma_address(&sg) = dma_addr;
129 sg_dma_len(&sg) = len;
130
131 direction = ux500_channel->is_tx ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
132 addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
133 DMA_SLAVE_BUSWIDTH_4_BYTES;
134
135 slave_conf.direction = direction;
136 if (direction == DMA_FROM_DEVICE) {
137 slave_conf.src_addr = usb_fifo_addr;
138 slave_conf.src_addr_width = addr_width;
139 slave_conf.src_maxburst = 16;
140 } else {
141 slave_conf.dst_addr = usb_fifo_addr;
142 slave_conf.dst_addr_width = addr_width;
143 slave_conf.dst_maxburst = 16;
144 }
145 dma_chan->device->device_control(dma_chan, DMA_SLAVE_CONFIG,
146 (unsigned long) &slave_conf);
147
148 dma_desc = dma_chan->device->
149 device_prep_slave_sg(dma_chan, &sg, 1, direction,
150 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
151 if (!dma_desc)
152 return false;
153
154 dma_desc->callback = ux500_dma_callback;
155 dma_desc->callback_param = channel;
156 ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
157
158 dma_async_issue_pending(dma_chan);
159
160 return true;
161}
162
163static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
164 struct musb_hw_ep *hw_ep, u8 is_tx)
165{
166 struct ux500_dma_controller *controller = container_of(c,
167 struct ux500_dma_controller, controller);
168 struct ux500_dma_channel *ux500_channel = NULL;
169 u8 ch_num = hw_ep->epnum - 1;
170 u32 max_ch;
171
172 /* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
173 * to specified hw_ep. For example DMA channel 0 can only be allocated
174 * to hw_ep 1 and 9.
175 */
176 if (ch_num > 7)
177 ch_num -= 8;
178
179 max_ch = is_tx ? controller->num_tx_channels :
180 controller->num_rx_channels;
181
182 if (ch_num >= max_ch)
183 return NULL;
184
185 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
186 &(controller->rx_channel[ch_num]) ;
187
188 /* Check if channel is already used. */
189 if (ux500_channel->is_allocated)
190 return NULL;
191
192 ux500_channel->hw_ep = hw_ep;
193 ux500_channel->is_allocated = 1;
194
195 DBG(7, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
196 hw_ep->epnum, is_tx, ch_num);
197
198 return &(ux500_channel->channel);
199}
200
201static void ux500_dma_channel_release(struct dma_channel *channel)
202{
203 struct ux500_dma_channel *ux500_channel = channel->private_data;
204
205 DBG(7, "channel=%d\n", ux500_channel->ch_num);
206
207 if (ux500_channel->is_allocated) {
208 ux500_channel->is_allocated = 0;
209 channel->status = MUSB_DMA_STATUS_FREE;
210 channel->actual_len = 0;
211 }
212}
213
214static int ux500_dma_is_compatible(struct dma_channel *channel,
215 u16 maxpacket, void *buf, u32 length)
216{
217 if ((maxpacket & 0x3) ||
218 ((int)buf & 0x3) ||
219 (length < 512) ||
220 (length & 0x3))
221 return false;
222 else
223 return true;
224}
225
226static int ux500_dma_channel_program(struct dma_channel *channel,
227 u16 packet_sz, u8 mode,
228 dma_addr_t dma_addr, u32 len)
229{
230 int ret;
231
232 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
233 channel->status == MUSB_DMA_STATUS_BUSY);
234
235 if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len))
236 return false;
237
238 channel->status = MUSB_DMA_STATUS_BUSY;
239 channel->actual_len = 0;
240 ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
241 if (!ret)
242 channel->status = MUSB_DMA_STATUS_FREE;
243
244 return ret;
245}
246
247static int ux500_dma_channel_abort(struct dma_channel *channel)
248{
249 struct ux500_dma_channel *ux500_channel = channel->private_data;
250 struct ux500_dma_controller *controller = ux500_channel->controller;
251 struct musb *musb = controller->private_data;
252 void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
253 u16 csr;
254
255 DBG(4, "channel=%d, is_tx=%d\n", ux500_channel->ch_num,
256 ux500_channel->is_tx);
257
258 if (channel->status == MUSB_DMA_STATUS_BUSY) {
259 if (ux500_channel->is_tx) {
260 csr = musb_readw(epio, MUSB_TXCSR);
261 csr &= ~(MUSB_TXCSR_AUTOSET |
262 MUSB_TXCSR_DMAENAB |
263 MUSB_TXCSR_DMAMODE);
264 musb_writew(epio, MUSB_TXCSR, csr);
265 } else {
266 csr = musb_readw(epio, MUSB_RXCSR);
267 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
268 MUSB_RXCSR_DMAENAB |
269 MUSB_RXCSR_DMAMODE);
270 musb_writew(epio, MUSB_RXCSR, csr);
271 }
272
273 ux500_channel->dma_chan->device->
274 device_control(ux500_channel->dma_chan,
275 DMA_TERMINATE_ALL, 0);
276 channel->status = MUSB_DMA_STATUS_FREE;
277 }
278 return 0;
279}
280
281static int ux500_dma_controller_stop(struct dma_controller *c)
282{
283 struct ux500_dma_controller *controller = container_of(c,
284 struct ux500_dma_controller, controller);
285 struct ux500_dma_channel *ux500_channel;
286 struct dma_channel *channel;
287 u8 ch_num;
288
289 for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
290 channel = &controller->rx_channel[ch_num].channel;
291 ux500_channel = channel->private_data;
292
293 ux500_dma_channel_release(channel);
294
295 if (ux500_channel->dma_chan)
296 dma_release_channel(ux500_channel->dma_chan);
297 }
298
299 for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
300 channel = &controller->tx_channel[ch_num].channel;
301 ux500_channel = channel->private_data;
302
303 ux500_dma_channel_release(channel);
304
305 if (ux500_channel->dma_chan)
306 dma_release_channel(ux500_channel->dma_chan);
307 }
308
309 return 0;
310}
311
312static int ux500_dma_controller_start(struct dma_controller *c)
313{
314 struct ux500_dma_controller *controller = container_of(c,
315 struct ux500_dma_controller, controller);
316 struct ux500_dma_channel *ux500_channel = NULL;
317 struct musb *musb = controller->private_data;
318 struct device *dev = musb->controller;
319 struct musb_hdrc_platform_data *plat = dev->platform_data;
320 struct ux500_musb_board_data *data = plat->board_data;
321 struct dma_channel *dma_channel = NULL;
322 u32 ch_num;
323 u8 dir;
324 u8 is_tx = 0;
325
326 void **param_array;
327 struct ux500_dma_channel *channel_array;
328 u32 ch_count;
329 void (*musb_channel_work)(struct work_struct *);
330 dma_cap_mask_t mask;
331
332 if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
333 (data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
334 return -EINVAL;
335
336 controller->num_rx_channels = data->num_rx_channels;
337 controller->num_tx_channels = data->num_tx_channels;
338
339 dma_cap_zero(mask);
340 dma_cap_set(DMA_SLAVE, mask);
341
342 /* Prepare the loop for RX channels */
343 channel_array = controller->rx_channel;
344 ch_count = data->num_rx_channels;
345 param_array = data->dma_rx_param_array;
346 musb_channel_work = ux500_rx_work;
347
348 for (dir = 0; dir < 2; dir++) {
349 for (ch_num = 0; ch_num < ch_count; ch_num++) {
350 ux500_channel = &channel_array[ch_num];
351 ux500_channel->controller = controller;
352 ux500_channel->ch_num = ch_num;
353 ux500_channel->is_tx = is_tx;
354
355 dma_channel = &(ux500_channel->channel);
356 dma_channel->private_data = ux500_channel;
357 dma_channel->status = MUSB_DMA_STATUS_FREE;
358 dma_channel->max_len = SZ_16M;
359
360 ux500_channel->dma_chan = dma_request_channel(mask,
361 data->dma_filter,
362 param_array[ch_num]);
363 if (!ux500_channel->dma_chan) {
364 ERR("Dma pipe allocation error dir=%d ch=%d\n",
365 dir, ch_num);
366
367 /* Release already allocated channels */
368 ux500_dma_controller_stop(c);
369
370 return -EBUSY;
371 }
372
373 INIT_WORK(&ux500_channel->channel_work,
374 musb_channel_work);
375 }
376
377 /* Prepare the loop for TX channels */
378 channel_array = controller->tx_channel;
379 ch_count = data->num_tx_channels;
380 param_array = data->dma_tx_param_array;
381 musb_channel_work = ux500_tx_work;
382 is_tx = 1;
383 }
384
385 return 0;
386}
387
388void dma_controller_destroy(struct dma_controller *c)
389{
390 struct ux500_dma_controller *controller = container_of(c,
391 struct ux500_dma_controller, controller);
392
393 kfree(controller);
394}
395
396struct dma_controller *__init
397dma_controller_create(struct musb *musb, void __iomem *base)
398{
399 struct ux500_dma_controller *controller;
400 struct platform_device *pdev = to_platform_device(musb->controller);
401 struct resource *iomem;
402
403 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
404 if (!controller)
405 return NULL;
406
407 controller->private_data = musb;
408
409 /* Save physical address for DMA controller. */
410 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
411 controller->phy_base = (dma_addr_t) iomem->start;
412
413 controller->controller.start = ux500_dma_controller_start;
414 controller->controller.stop = ux500_dma_controller_stop;
415 controller->controller.channel_alloc = ux500_dma_channel_allocate;
416 controller->controller.channel_release = ux500_dma_channel_release;
417 controller->controller.channel_program = ux500_dma_channel_program;
418 controller->controller.channel_abort = ux500_dma_channel_abort;
419 controller->controller.is_compatible = ux500_dma_is_compatible;
420
421 return &controller->controller;
422}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 18:32:58 -0400