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-rw-r--r--drivers/usb/musb/Kconfig2
-rw-r--r--drivers/usb/musb/blackfin.c11
-rw-r--r--drivers/usb/musb/cppi_dma.c34
-rw-r--r--drivers/usb/musb/cppi_dma.h6
-rw-r--r--drivers/usb/musb/davinci.c54
-rw-r--r--drivers/usb/musb/musb_core.c228
-rw-r--r--drivers/usb/musb/musb_core.h22
-rw-r--r--drivers/usb/musb/musb_gadget.c45
-rw-r--r--drivers/usb/musb/musb_gadget_ep0.c45
-rw-r--r--drivers/usb/musb/musb_host.c273
-rw-r--r--drivers/usb/musb/musb_host.h1
-rw-r--r--drivers/usb/musb/musb_virthub.c35
-rw-r--r--drivers/usb/musb/omap2430.c71
-rw-r--r--drivers/usb/musb/tusb6010.c70
14 files changed, 484 insertions, 413 deletions
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index b66e8544d8b9..70073b157f0a 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -10,6 +10,7 @@ comment "Enable Host or Gadget support to see Inventra options"
10config USB_MUSB_HDRC 10config USB_MUSB_HDRC
11 depends on (USB || USB_GADGET) && HAVE_CLK 11 depends on (USB || USB_GADGET) && HAVE_CLK
12 depends on !SUPERH 12 depends on !SUPERH
13 select NOP_USB_XCEIV if ARCH_DAVINCI
13 select TWL4030_USB if MACH_OMAP_3430SDP 14 select TWL4030_USB if MACH_OMAP_3430SDP
14 select USB_OTG_UTILS 15 select USB_OTG_UTILS
15 tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)' 16 tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
@@ -55,6 +56,7 @@ comment "Blackfin high speed USB Support"
55config USB_TUSB6010 56config USB_TUSB6010
56 boolean "TUSB 6010 support" 57 boolean "TUSB 6010 support"
57 depends on USB_MUSB_HDRC && !USB_MUSB_SOC 58 depends on USB_MUSB_HDRC && !USB_MUSB_SOC
59 select NOP_USB_XCEIV
58 default y 60 default y
59 help 61 help
60 The TUSB 6010 chip, from Texas Instruments, connects a discrete 62 The TUSB 6010 chip, from Texas Instruments, connects a discrete
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
index 786134852092..f2f66ebc7362 100644
--- a/drivers/usb/musb/blackfin.c
+++ b/drivers/usb/musb/blackfin.c
@@ -143,7 +143,7 @@ static void musb_conn_timer_handler(unsigned long _musb)
143 u16 val; 143 u16 val;
144 144
145 spin_lock_irqsave(&musb->lock, flags); 145 spin_lock_irqsave(&musb->lock, flags);
146 switch (musb->xceiv.state) { 146 switch (musb->xceiv->state) {
147 case OTG_STATE_A_IDLE: 147 case OTG_STATE_A_IDLE:
148 case OTG_STATE_A_WAIT_BCON: 148 case OTG_STATE_A_WAIT_BCON:
149 /* Start a new session */ 149 /* Start a new session */
@@ -154,7 +154,7 @@ static void musb_conn_timer_handler(unsigned long _musb)
154 val = musb_readw(musb->mregs, MUSB_DEVCTL); 154 val = musb_readw(musb->mregs, MUSB_DEVCTL);
155 if (!(val & MUSB_DEVCTL_BDEVICE)) { 155 if (!(val & MUSB_DEVCTL_BDEVICE)) {
156 gpio_set_value(musb->config->gpio_vrsel, 1); 156 gpio_set_value(musb->config->gpio_vrsel, 1);
157 musb->xceiv.state = OTG_STATE_A_WAIT_BCON; 157 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
158 } else { 158 } else {
159 gpio_set_value(musb->config->gpio_vrsel, 0); 159 gpio_set_value(musb->config->gpio_vrsel, 0);
160 160
@@ -247,6 +247,11 @@ int __init musb_platform_init(struct musb *musb)
247 } 247 }
248 gpio_direction_output(musb->config->gpio_vrsel, 0); 248 gpio_direction_output(musb->config->gpio_vrsel, 0);
249 249
250 usb_nop_xceiv_register();
251 musb->xceiv = otg_get_transceiver();
252 if (!musb->xceiv)
253 return -ENODEV;
254
250 if (ANOMALY_05000346) { 255 if (ANOMALY_05000346) {
251 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value); 256 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
252 SSYNC(); 257 SSYNC();
@@ -291,7 +296,7 @@ int __init musb_platform_init(struct musb *musb)
291 musb_conn_timer_handler, (unsigned long) musb); 296 musb_conn_timer_handler, (unsigned long) musb);
292 } 297 }
293 if (is_peripheral_enabled(musb)) 298 if (is_peripheral_enabled(musb))
294 musb->xceiv.set_power = bfin_set_power; 299 musb->xceiv->set_power = bfin_set_power;
295 300
296 musb->isr = blackfin_interrupt; 301 musb->isr = blackfin_interrupt;
297 302
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index 1976e9b41800..c3577bbbae6c 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -6,6 +6,7 @@
6 * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci. 6 * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci.
7 */ 7 */
8 8
9#include <linux/platform_device.h>
9#include <linux/usb.h> 10#include <linux/usb.h>
10 11
11#include "musb_core.h" 12#include "musb_core.h"
@@ -1145,17 +1146,27 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1145 return completed; 1146 return completed;
1146} 1147}
1147 1148
1148void cppi_completion(struct musb *musb, u32 rx, u32 tx) 1149irqreturn_t cppi_interrupt(int irq, void *dev_id)
1149{ 1150{
1150 void __iomem *tibase; 1151 struct musb *musb = dev_id;
1151 int i, index;
1152 struct cppi *cppi; 1152 struct cppi *cppi;
1153 void __iomem *tibase;
1153 struct musb_hw_ep *hw_ep = NULL; 1154 struct musb_hw_ep *hw_ep = NULL;
1155 u32 rx, tx;
1156 int i, index;
1154 1157
1155 cppi = container_of(musb->dma_controller, struct cppi, controller); 1158 cppi = container_of(musb->dma_controller, struct cppi, controller);
1156 1159
1157 tibase = musb->ctrl_base; 1160 tibase = musb->ctrl_base;
1158 1161
1162 tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
1163 rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
1164
1165 if (!tx && !rx)
1166 return IRQ_NONE;
1167
1168 DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
1169
1159 /* process TX channels */ 1170 /* process TX channels */
1160 for (index = 0; tx; tx = tx >> 1, index++) { 1171 for (index = 0; tx; tx = tx >> 1, index++) {
1161 struct cppi_channel *tx_ch; 1172 struct cppi_channel *tx_ch;
@@ -1273,6 +1284,8 @@ void cppi_completion(struct musb *musb, u32 rx, u32 tx)
1273 1284
1274 /* write to CPPI EOI register to re-enable interrupts */ 1285 /* write to CPPI EOI register to re-enable interrupts */
1275 musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0); 1286 musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
1287
1288 return IRQ_HANDLED;
1276} 1289}
1277 1290
1278/* Instantiate a software object representing a DMA controller. */ 1291/* Instantiate a software object representing a DMA controller. */
@@ -1280,6 +1293,9 @@ struct dma_controller *__init
1280dma_controller_create(struct musb *musb, void __iomem *mregs) 1293dma_controller_create(struct musb *musb, void __iomem *mregs)
1281{ 1294{
1282 struct cppi *controller; 1295 struct cppi *controller;
1296 struct device *dev = musb->controller;
1297 struct platform_device *pdev = to_platform_device(dev);
1298 int irq = platform_get_irq(pdev, 1);
1283 1299
1284 controller = kzalloc(sizeof *controller, GFP_KERNEL); 1300 controller = kzalloc(sizeof *controller, GFP_KERNEL);
1285 if (!controller) 1301 if (!controller)
@@ -1310,6 +1326,15 @@ dma_controller_create(struct musb *musb, void __iomem *mregs)
1310 return NULL; 1326 return NULL;
1311 } 1327 }
1312 1328
1329 if (irq > 0) {
1330 if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
1331 dev_err(dev, "request_irq %d failed!\n", irq);
1332 dma_controller_destroy(&controller->controller);
1333 return NULL;
1334 }
1335 controller->irq = irq;
1336 }
1337
1313 return &controller->controller; 1338 return &controller->controller;
1314} 1339}
1315 1340
@@ -1322,6 +1347,9 @@ void dma_controller_destroy(struct dma_controller *c)
1322 1347
1323 cppi = container_of(c, struct cppi, controller); 1348 cppi = container_of(c, struct cppi, controller);
1324 1349
1350 if (cppi->irq)
1351 free_irq(cppi->irq, cppi->musb);
1352
1325 /* assert: caller stopped the controller first */ 1353 /* assert: caller stopped the controller first */
1326 dma_pool_destroy(cppi->pool); 1354 dma_pool_destroy(cppi->pool);
1327 1355
diff --git a/drivers/usb/musb/cppi_dma.h b/drivers/usb/musb/cppi_dma.h
index 729b4071787b..8a39de3e6e47 100644
--- a/drivers/usb/musb/cppi_dma.h
+++ b/drivers/usb/musb/cppi_dma.h
@@ -119,6 +119,8 @@ struct cppi {
119 void __iomem *mregs; /* Mentor regs */ 119 void __iomem *mregs; /* Mentor regs */
120 void __iomem *tibase; /* TI/CPPI regs */ 120 void __iomem *tibase; /* TI/CPPI regs */
121 121
122 int irq;
123
122 struct cppi_channel tx[4]; 124 struct cppi_channel tx[4];
123 struct cppi_channel rx[4]; 125 struct cppi_channel rx[4];
124 126
@@ -127,7 +129,7 @@ struct cppi {
127 struct list_head tx_complete; 129 struct list_head tx_complete;
128}; 130};
129 131
130/* irq handling hook */ 132/* CPPI IRQ handler */
131extern void cppi_completion(struct musb *, u32 rx, u32 tx); 133extern irqreturn_t cppi_interrupt(int, void *);
132 134
133#endif /* end of ifndef _CPPI_DMA_H_ */ 135#endif /* end of ifndef _CPPI_DMA_H_ */
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 10d11ab113ab..180d7daa4099 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -215,7 +215,7 @@ static void otg_timer(unsigned long _musb)
215 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); 215 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
216 216
217 spin_lock_irqsave(&musb->lock, flags); 217 spin_lock_irqsave(&musb->lock, flags);
218 switch (musb->xceiv.state) { 218 switch (musb->xceiv->state) {
219 case OTG_STATE_A_WAIT_VFALL: 219 case OTG_STATE_A_WAIT_VFALL:
220 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL 220 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
221 * seems to mis-handle session "start" otherwise (or in our 221 * seems to mis-handle session "start" otherwise (or in our
@@ -226,7 +226,7 @@ static void otg_timer(unsigned long _musb)
226 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 226 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
227 break; 227 break;
228 } 228 }
229 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE; 229 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
230 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, 230 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
231 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT); 231 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
232 break; 232 break;
@@ -251,7 +251,7 @@ static void otg_timer(unsigned long _musb)
251 if (devctl & MUSB_DEVCTL_BDEVICE) 251 if (devctl & MUSB_DEVCTL_BDEVICE)
252 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 252 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
253 else 253 else
254 musb->xceiv.state = OTG_STATE_A_IDLE; 254 musb->xceiv->state = OTG_STATE_A_IDLE;
255 break; 255 break;
256 default: 256 default:
257 break; 257 break;
@@ -265,6 +265,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
265 irqreturn_t retval = IRQ_NONE; 265 irqreturn_t retval = IRQ_NONE;
266 struct musb *musb = __hci; 266 struct musb *musb = __hci;
267 void __iomem *tibase = musb->ctrl_base; 267 void __iomem *tibase = musb->ctrl_base;
268 struct cppi *cppi;
268 u32 tmp; 269 u32 tmp;
269 270
270 spin_lock_irqsave(&musb->lock, flags); 271 spin_lock_irqsave(&musb->lock, flags);
@@ -281,16 +282,9 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
281 /* CPPI interrupts share the same IRQ line, but have their own 282 /* CPPI interrupts share the same IRQ line, but have their own
282 * mask, state, "vector", and EOI registers. 283 * mask, state, "vector", and EOI registers.
283 */ 284 */
284 if (is_cppi_enabled()) { 285 cppi = container_of(musb->dma_controller, struct cppi, controller);
285 u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG); 286 if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
286 u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG); 287 retval = cppi_interrupt(irq, __hci);
287
288 if (cppi_tx || cppi_rx) {
289 DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
290 cppi_completion(musb, cppi_rx, cppi_tx);
291 retval = IRQ_HANDLED;
292 }
293 }
294 288
295 /* ack and handle non-CPPI interrupts */ 289 /* ack and handle non-CPPI interrupts */
296 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); 290 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
@@ -331,21 +325,21 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
331 * to stop registering in devctl. 325 * to stop registering in devctl.
332 */ 326 */
333 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 327 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
334 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL; 328 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
335 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 329 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
336 WARNING("VBUS error workaround (delay coming)\n"); 330 WARNING("VBUS error workaround (delay coming)\n");
337 } else if (is_host_enabled(musb) && drvvbus) { 331 } else if (is_host_enabled(musb) && drvvbus) {
338 musb->is_active = 1; 332 musb->is_active = 1;
339 MUSB_HST_MODE(musb); 333 MUSB_HST_MODE(musb);
340 musb->xceiv.default_a = 1; 334 musb->xceiv->default_a = 1;
341 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE; 335 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
342 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 336 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
343 del_timer(&otg_workaround); 337 del_timer(&otg_workaround);
344 } else { 338 } else {
345 musb->is_active = 0; 339 musb->is_active = 0;
346 MUSB_DEV_MODE(musb); 340 MUSB_DEV_MODE(musb);
347 musb->xceiv.default_a = 0; 341 musb->xceiv->default_a = 0;
348 musb->xceiv.state = OTG_STATE_B_IDLE; 342 musb->xceiv->state = OTG_STATE_B_IDLE;
349 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 343 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
350 } 344 }
351 345
@@ -367,17 +361,12 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
367 361
368 /* poll for ID change */ 362 /* poll for ID change */
369 if (is_otg_enabled(musb) 363 if (is_otg_enabled(musb)
370 && musb->xceiv.state == OTG_STATE_B_IDLE) 364 && musb->xceiv->state == OTG_STATE_B_IDLE)
371 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 365 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
372 366
373 spin_unlock_irqrestore(&musb->lock, flags); 367 spin_unlock_irqrestore(&musb->lock, flags);
374 368
375 /* REVISIT we sometimes get unhandled IRQs 369 return retval;
376 * (e.g. ep0). not clear why...
377 */
378 if (retval != IRQ_HANDLED)
379 DBG(5, "unhandled? %08x\n", tmp);
380 return IRQ_HANDLED;
381} 370}
382 371
383int musb_platform_set_mode(struct musb *musb, u8 mode) 372int musb_platform_set_mode(struct musb *musb, u8 mode)
@@ -391,6 +380,11 @@ int __init musb_platform_init(struct musb *musb)
391 void __iomem *tibase = musb->ctrl_base; 380 void __iomem *tibase = musb->ctrl_base;
392 u32 revision; 381 u32 revision;
393 382
383 usb_nop_xceiv_register();
384 musb->xceiv = otg_get_transceiver();
385 if (!musb->xceiv)
386 return -ENODEV;
387
394 musb->mregs += DAVINCI_BASE_OFFSET; 388 musb->mregs += DAVINCI_BASE_OFFSET;
395 389
396 clk_enable(musb->clock); 390 clk_enable(musb->clock);
@@ -398,7 +392,7 @@ int __init musb_platform_init(struct musb *musb)
398 /* returns zero if e.g. not clocked */ 392 /* returns zero if e.g. not clocked */
399 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); 393 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
400 if (revision == 0) 394 if (revision == 0)
401 return -ENODEV; 395 goto fail;
402 396
403 if (is_host_enabled(musb)) 397 if (is_host_enabled(musb))
404 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); 398 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
@@ -432,6 +426,10 @@ int __init musb_platform_init(struct musb *musb)
432 426
433 musb->isr = davinci_interrupt; 427 musb->isr = davinci_interrupt;
434 return 0; 428 return 0;
429
430fail:
431 usb_nop_xceiv_unregister();
432 return -ENODEV;
435} 433}
436 434
437int musb_platform_exit(struct musb *musb) 435int musb_platform_exit(struct musb *musb)
@@ -442,7 +440,7 @@ int musb_platform_exit(struct musb *musb)
442 davinci_source_power(musb, 0 /*off*/, 1); 440 davinci_source_power(musb, 0 /*off*/, 1);
443 441
444 /* delay, to avoid problems with module reload */ 442 /* delay, to avoid problems with module reload */
445 if (is_host_enabled(musb) && musb->xceiv.default_a) { 443 if (is_host_enabled(musb) && musb->xceiv->default_a) {
446 int maxdelay = 30; 444 int maxdelay = 30;
447 u8 devctl, warn = 0; 445 u8 devctl, warn = 0;
448 446
@@ -471,5 +469,7 @@ int musb_platform_exit(struct musb *musb)
471 469
472 clk_disable(musb->clock); 470 clk_disable(musb->clock);
473 471
472 usb_nop_xceiv_unregister();
473
474 return 0; 474 return 0;
475} 475}
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 4000cf6d1e81..554a414f65d1 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -112,6 +112,7 @@
112#include "davinci.h" 112#include "davinci.h"
113#endif 113#endif
114 114
115#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
115 116
116 117
117unsigned musb_debug; 118unsigned musb_debug;
@@ -267,7 +268,7 @@ void musb_load_testpacket(struct musb *musb)
267 268
268const char *otg_state_string(struct musb *musb) 269const char *otg_state_string(struct musb *musb)
269{ 270{
270 switch (musb->xceiv.state) { 271 switch (musb->xceiv->state) {
271 case OTG_STATE_A_IDLE: return "a_idle"; 272 case OTG_STATE_A_IDLE: return "a_idle";
272 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
273 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
@@ -288,12 +289,6 @@ const char *otg_state_string(struct musb *musb)
288#ifdef CONFIG_USB_MUSB_OTG 289#ifdef CONFIG_USB_MUSB_OTG
289 290
290/* 291/*
291 * See also USB_OTG_1-3.pdf 6.6.5 Timers
292 * REVISIT: Are the other timers done in the hardware?
293 */
294#define TB_ASE0_BRST 100 /* Min 3.125 ms */
295
296/*
297 * Handles OTG hnp timeouts, such as b_ase0_brst 292 * Handles OTG hnp timeouts, such as b_ase0_brst
298 */ 293 */
299void musb_otg_timer_func(unsigned long data) 294void musb_otg_timer_func(unsigned long data)
@@ -302,16 +297,18 @@ void musb_otg_timer_func(unsigned long data)
302 unsigned long flags; 297 unsigned long flags;
303 298
304 spin_lock_irqsave(&musb->lock, flags); 299 spin_lock_irqsave(&musb->lock, flags);
305 switch (musb->xceiv.state) { 300 switch (musb->xceiv->state) {
306 case OTG_STATE_B_WAIT_ACON: 301 case OTG_STATE_B_WAIT_ACON:
307 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
308 musb_g_disconnect(musb); 303 musb_g_disconnect(musb);
309 musb->xceiv.state = OTG_STATE_B_PERIPHERAL; 304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
310 musb->is_active = 0; 305 musb->is_active = 0;
311 break; 306 break;
307 case OTG_STATE_A_SUSPEND:
312 case OTG_STATE_A_WAIT_BCON: 308 case OTG_STATE_A_WAIT_BCON:
313 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n"); 309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
314 musb_hnp_stop(musb); 310 musb_set_vbus(musb, 0);
311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
315 break; 312 break;
316 default: 313 default:
317 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
@@ -320,10 +317,8 @@ void musb_otg_timer_func(unsigned long data)
320 spin_unlock_irqrestore(&musb->lock, flags); 317 spin_unlock_irqrestore(&musb->lock, flags);
321} 318}
322 319
323static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
324
325/* 320/*
326 * Stops the B-device HNP state. Caller must take care of locking. 321 * Stops the HNP transition. Caller must take care of locking.
327 */ 322 */
328void musb_hnp_stop(struct musb *musb) 323void musb_hnp_stop(struct musb *musb)
329{ 324{
@@ -331,20 +326,17 @@ void musb_hnp_stop(struct musb *musb)
331 void __iomem *mbase = musb->mregs; 326 void __iomem *mbase = musb->mregs;
332 u8 reg; 327 u8 reg;
333 328
334 switch (musb->xceiv.state) { 329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
330
331 switch (musb->xceiv->state) {
335 case OTG_STATE_A_PERIPHERAL: 332 case OTG_STATE_A_PERIPHERAL:
336 case OTG_STATE_A_WAIT_VFALL:
337 case OTG_STATE_A_WAIT_BCON:
338 DBG(1, "HNP: Switching back to A-host\n");
339 musb_g_disconnect(musb); 333 musb_g_disconnect(musb);
340 musb->xceiv.state = OTG_STATE_A_IDLE; 334 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
341 MUSB_HST_MODE(musb);
342 musb->is_active = 0;
343 break; 335 break;
344 case OTG_STATE_B_HOST: 336 case OTG_STATE_B_HOST:
345 DBG(1, "HNP: Disabling HR\n"); 337 DBG(1, "HNP: Disabling HR\n");
346 hcd->self.is_b_host = 0; 338 hcd->self.is_b_host = 0;
347 musb->xceiv.state = OTG_STATE_B_PERIPHERAL; 339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
348 MUSB_DEV_MODE(musb); 340 MUSB_DEV_MODE(musb);
349 reg = musb_readb(mbase, MUSB_POWER); 341 reg = musb_readb(mbase, MUSB_POWER);
350 reg |= MUSB_POWER_SUSPENDM; 342 reg |= MUSB_POWER_SUSPENDM;
@@ -402,7 +394,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
402 394
403 if (devctl & MUSB_DEVCTL_HM) { 395 if (devctl & MUSB_DEVCTL_HM) {
404#ifdef CONFIG_USB_MUSB_HDRC_HCD 396#ifdef CONFIG_USB_MUSB_HDRC_HCD
405 switch (musb->xceiv.state) { 397 switch (musb->xceiv->state) {
406 case OTG_STATE_A_SUSPEND: 398 case OTG_STATE_A_SUSPEND:
407 /* remote wakeup? later, GetPortStatus 399 /* remote wakeup? later, GetPortStatus
408 * will stop RESUME signaling 400 * will stop RESUME signaling
@@ -425,12 +417,12 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
425 musb->rh_timer = jiffies 417 musb->rh_timer = jiffies
426 + msecs_to_jiffies(20); 418 + msecs_to_jiffies(20);
427 419
428 musb->xceiv.state = OTG_STATE_A_HOST; 420 musb->xceiv->state = OTG_STATE_A_HOST;
429 musb->is_active = 1; 421 musb->is_active = 1;
430 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 422 usb_hcd_resume_root_hub(musb_to_hcd(musb));
431 break; 423 break;
432 case OTG_STATE_B_WAIT_ACON: 424 case OTG_STATE_B_WAIT_ACON:
433 musb->xceiv.state = OTG_STATE_B_PERIPHERAL; 425 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
434 musb->is_active = 1; 426 musb->is_active = 1;
435 MUSB_DEV_MODE(musb); 427 MUSB_DEV_MODE(musb);
436 break; 428 break;
@@ -441,11 +433,11 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
441 } 433 }
442#endif 434#endif
443 } else { 435 } else {
444 switch (musb->xceiv.state) { 436 switch (musb->xceiv->state) {
445#ifdef CONFIG_USB_MUSB_HDRC_HCD 437#ifdef CONFIG_USB_MUSB_HDRC_HCD
446 case OTG_STATE_A_SUSPEND: 438 case OTG_STATE_A_SUSPEND:
447 /* possibly DISCONNECT is upcoming */ 439 /* possibly DISCONNECT is upcoming */
448 musb->xceiv.state = OTG_STATE_A_HOST; 440 musb->xceiv->state = OTG_STATE_A_HOST;
449 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 441 usb_hcd_resume_root_hub(musb_to_hcd(musb));
450 break; 442 break;
451#endif 443#endif
@@ -490,7 +482,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
490 */ 482 */
491 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 483 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
492 musb->ep0_stage = MUSB_EP0_START; 484 musb->ep0_stage = MUSB_EP0_START;
493 musb->xceiv.state = OTG_STATE_A_IDLE; 485 musb->xceiv->state = OTG_STATE_A_IDLE;
494 MUSB_HST_MODE(musb); 486 MUSB_HST_MODE(musb);
495 musb_set_vbus(musb, 1); 487 musb_set_vbus(musb, 1);
496 488
@@ -516,7 +508,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
516 * REVISIT: do delays from lots of DEBUG_KERNEL checks 508 * REVISIT: do delays from lots of DEBUG_KERNEL checks
517 * make trouble here, keeping VBUS < 4.4V ? 509 * make trouble here, keeping VBUS < 4.4V ?
518 */ 510 */
519 switch (musb->xceiv.state) { 511 switch (musb->xceiv->state) {
520 case OTG_STATE_A_HOST: 512 case OTG_STATE_A_HOST:
521 /* recovery is dicey once we've gotten past the 513 /* recovery is dicey once we've gotten past the
522 * initial stages of enumeration, but if VBUS 514 * initial stages of enumeration, but if VBUS
@@ -594,37 +586,40 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
594 if (devctl & MUSB_DEVCTL_LSDEV) 586 if (devctl & MUSB_DEVCTL_LSDEV)
595 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 587 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
596 588
597 if (hcd->status_urb)
598 usb_hcd_poll_rh_status(hcd);
599 else
600 usb_hcd_resume_root_hub(hcd);
601
602 MUSB_HST_MODE(musb);
603
604 /* indicate new connection to OTG machine */ 589 /* indicate new connection to OTG machine */
605 switch (musb->xceiv.state) { 590 switch (musb->xceiv->state) {
606 case OTG_STATE_B_PERIPHERAL: 591 case OTG_STATE_B_PERIPHERAL:
607 if (int_usb & MUSB_INTR_SUSPEND) { 592 if (int_usb & MUSB_INTR_SUSPEND) {
608 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 593 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
609 musb->xceiv.state = OTG_STATE_B_HOST;
610 hcd->self.is_b_host = 1;
611 int_usb &= ~MUSB_INTR_SUSPEND; 594 int_usb &= ~MUSB_INTR_SUSPEND;
595 goto b_host;
612 } else 596 } else
613 DBG(1, "CONNECT as b_peripheral???\n"); 597 DBG(1, "CONNECT as b_peripheral???\n");
614 break; 598 break;
615 case OTG_STATE_B_WAIT_ACON: 599 case OTG_STATE_B_WAIT_ACON:
616 DBG(1, "HNP: Waiting to switch to b_host state\n"); 600 DBG(1, "HNP: CONNECT, now b_host\n");
617 musb->xceiv.state = OTG_STATE_B_HOST; 601b_host:
602 musb->xceiv->state = OTG_STATE_B_HOST;
618 hcd->self.is_b_host = 1; 603 hcd->self.is_b_host = 1;
604 musb->ignore_disconnect = 0;
605 del_timer(&musb->otg_timer);
619 break; 606 break;
620 default: 607 default:
621 if ((devctl & MUSB_DEVCTL_VBUS) 608 if ((devctl & MUSB_DEVCTL_VBUS)
622 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 609 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
623 musb->xceiv.state = OTG_STATE_A_HOST; 610 musb->xceiv->state = OTG_STATE_A_HOST;
624 hcd->self.is_b_host = 0; 611 hcd->self.is_b_host = 0;
625 } 612 }
626 break; 613 break;
627 } 614 }
615
616 /* poke the root hub */
617 MUSB_HST_MODE(musb);
618 if (hcd->status_urb)
619 usb_hcd_poll_rh_status(hcd);
620 else
621 usb_hcd_resume_root_hub(hcd);
622
628 DBG(1, "CONNECT (%s) devctl %02x\n", 623 DBG(1, "CONNECT (%s) devctl %02x\n",
629 otg_state_string(musb), devctl); 624 otg_state_string(musb), devctl);
630 } 625 }
@@ -650,7 +645,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
650 } 645 }
651 } else if (is_peripheral_capable()) { 646 } else if (is_peripheral_capable()) {
652 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 647 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
653 switch (musb->xceiv.state) { 648 switch (musb->xceiv->state) {
654#ifdef CONFIG_USB_OTG 649#ifdef CONFIG_USB_OTG
655 case OTG_STATE_A_SUSPEND: 650 case OTG_STATE_A_SUSPEND:
656 /* We need to ignore disconnect on suspend 651 /* We need to ignore disconnect on suspend
@@ -661,24 +656,27 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
661 musb_g_reset(musb); 656 musb_g_reset(musb);
662 /* FALLTHROUGH */ 657 /* FALLTHROUGH */
663 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 658 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
664 DBG(1, "HNP: Setting timer as %s\n", 659 /* never use invalid T(a_wait_bcon) */
665 otg_state_string(musb)); 660 DBG(1, "HNP: in %s, %d msec timeout\n",
666 musb_otg_timer.data = (unsigned long)musb; 661 otg_state_string(musb),
667 mod_timer(&musb_otg_timer, jiffies 662 TA_WAIT_BCON(musb));
668 + msecs_to_jiffies(100)); 663 mod_timer(&musb->otg_timer, jiffies
664 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
669 break; 665 break;
670 case OTG_STATE_A_PERIPHERAL: 666 case OTG_STATE_A_PERIPHERAL:
671 musb_hnp_stop(musb); 667 musb->ignore_disconnect = 0;
668 del_timer(&musb->otg_timer);
669 musb_g_reset(musb);
672 break; 670 break;
673 case OTG_STATE_B_WAIT_ACON: 671 case OTG_STATE_B_WAIT_ACON:
674 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 672 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
675 otg_state_string(musb)); 673 otg_state_string(musb));
676 musb->xceiv.state = OTG_STATE_B_PERIPHERAL; 674 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
677 musb_g_reset(musb); 675 musb_g_reset(musb);
678 break; 676 break;
679#endif 677#endif
680 case OTG_STATE_B_IDLE: 678 case OTG_STATE_B_IDLE:
681 musb->xceiv.state = OTG_STATE_B_PERIPHERAL; 679 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
682 /* FALLTHROUGH */ 680 /* FALLTHROUGH */
683 case OTG_STATE_B_PERIPHERAL: 681 case OTG_STATE_B_PERIPHERAL:
684 musb_g_reset(musb); 682 musb_g_reset(musb);
@@ -763,7 +761,7 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
763 MUSB_MODE(musb), devctl); 761 MUSB_MODE(musb), devctl);
764 handled = IRQ_HANDLED; 762 handled = IRQ_HANDLED;
765 763
766 switch (musb->xceiv.state) { 764 switch (musb->xceiv->state) {
767#ifdef CONFIG_USB_MUSB_HDRC_HCD 765#ifdef CONFIG_USB_MUSB_HDRC_HCD
768 case OTG_STATE_A_HOST: 766 case OTG_STATE_A_HOST:
769 case OTG_STATE_A_SUSPEND: 767 case OTG_STATE_A_SUSPEND:
@@ -776,7 +774,16 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
776#endif /* HOST */ 774#endif /* HOST */
777#ifdef CONFIG_USB_MUSB_OTG 775#ifdef CONFIG_USB_MUSB_OTG
778 case OTG_STATE_B_HOST: 776 case OTG_STATE_B_HOST:
779 musb_hnp_stop(musb); 777 /* REVISIT this behaves for "real disconnect"
778 * cases; make sure the other transitions from
779 * from B_HOST act right too. The B_HOST code
780 * in hnp_stop() is currently not used...
781 */
782 musb_root_disconnect(musb);
783 musb_to_hcd(musb)->self.is_b_host = 0;
784 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
785 MUSB_DEV_MODE(musb);
786 musb_g_disconnect(musb);
780 break; 787 break;
781 case OTG_STATE_A_PERIPHERAL: 788 case OTG_STATE_A_PERIPHERAL:
782 musb_hnp_stop(musb); 789 musb_hnp_stop(musb);
@@ -805,26 +812,35 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
805 otg_state_string(musb), devctl, power); 812 otg_state_string(musb), devctl, power);
806 handled = IRQ_HANDLED; 813 handled = IRQ_HANDLED;
807 814
808 switch (musb->xceiv.state) { 815 switch (musb->xceiv->state) {
809#ifdef CONFIG_USB_MUSB_OTG 816#ifdef CONFIG_USB_MUSB_OTG
810 case OTG_STATE_A_PERIPHERAL: 817 case OTG_STATE_A_PERIPHERAL:
811 /* 818 /* We also come here if the cable is removed, since
812 * We cannot stop HNP here, devctl BDEVICE might be 819 * this silicon doesn't report ID-no-longer-grounded.
813 * still set. 820 *
821 * We depend on T(a_wait_bcon) to shut us down, and
822 * hope users don't do anything dicey during this
823 * undesired detour through A_WAIT_BCON.
814 */ 824 */
825 musb_hnp_stop(musb);
826 usb_hcd_resume_root_hub(musb_to_hcd(musb));
827 musb_root_disconnect(musb);
828 musb_platform_try_idle(musb, jiffies
829 + msecs_to_jiffies(musb->a_wait_bcon
830 ? : OTG_TIME_A_WAIT_BCON));
815 break; 831 break;
816#endif 832#endif
817 case OTG_STATE_B_PERIPHERAL: 833 case OTG_STATE_B_PERIPHERAL:
818 musb_g_suspend(musb); 834 musb_g_suspend(musb);
819 musb->is_active = is_otg_enabled(musb) 835 musb->is_active = is_otg_enabled(musb)
820 && musb->xceiv.gadget->b_hnp_enable; 836 && musb->xceiv->gadget->b_hnp_enable;
821 if (musb->is_active) { 837 if (musb->is_active) {
822#ifdef CONFIG_USB_MUSB_OTG 838#ifdef CONFIG_USB_MUSB_OTG
823 musb->xceiv.state = OTG_STATE_B_WAIT_ACON; 839 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
824 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 840 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
825 musb_otg_timer.data = (unsigned long)musb; 841 mod_timer(&musb->otg_timer, jiffies
826 mod_timer(&musb_otg_timer, jiffies 842 + msecs_to_jiffies(
827 + msecs_to_jiffies(TB_ASE0_BRST)); 843 OTG_TIME_B_ASE0_BRST));
828#endif 844#endif
829 } 845 }
830 break; 846 break;
@@ -834,9 +850,9 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
834 + msecs_to_jiffies(musb->a_wait_bcon)); 850 + msecs_to_jiffies(musb->a_wait_bcon));
835 break; 851 break;
836 case OTG_STATE_A_HOST: 852 case OTG_STATE_A_HOST:
837 musb->xceiv.state = OTG_STATE_A_SUSPEND; 853 musb->xceiv->state = OTG_STATE_A_SUSPEND;
838 musb->is_active = is_otg_enabled(musb) 854 musb->is_active = is_otg_enabled(musb)
839 && musb->xceiv.host->b_hnp_enable; 855 && musb->xceiv->host->b_hnp_enable;
840 break; 856 break;
841 case OTG_STATE_B_HOST: 857 case OTG_STATE_B_HOST:
842 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 858 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
@@ -1068,14 +1084,13 @@ static struct fifo_cfg __initdata mode_4_cfg[] = {
1068{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1084{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1069{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1085{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1070{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1086{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1071{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, }, 1087{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1072{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, }, 1088{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1073{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, }, 1089{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1074{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, }, 1090{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1075{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, }, 1091{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1076{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, }, 1092{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1077{ .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, }, 1093{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1078{ .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1079{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1094{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1080{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1095{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1081}; 1096};
@@ -1335,11 +1350,11 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1335 } 1350 }
1336 if (reg & MUSB_CONFIGDATA_HBRXE) { 1351 if (reg & MUSB_CONFIGDATA_HBRXE) {
1337 strcat(aInfo, ", HB-ISO Rx"); 1352 strcat(aInfo, ", HB-ISO Rx");
1338 strcat(aInfo, " (X)"); /* no driver support */ 1353 musb->hb_iso_rx = true;
1339 } 1354 }
1340 if (reg & MUSB_CONFIGDATA_HBTXE) { 1355 if (reg & MUSB_CONFIGDATA_HBTXE) {
1341 strcat(aInfo, ", HB-ISO Tx"); 1356 strcat(aInfo, ", HB-ISO Tx");
1342 strcat(aInfo, " (X)"); /* no driver support */ 1357 musb->hb_iso_tx = true;
1343 } 1358 }
1344 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1359 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1345 strcat(aInfo, ", SoftConn"); 1360 strcat(aInfo, ", SoftConn");
@@ -1481,13 +1496,7 @@ static irqreturn_t generic_interrupt(int irq, void *__hci)
1481 1496
1482 spin_unlock_irqrestore(&musb->lock, flags); 1497 spin_unlock_irqrestore(&musb->lock, flags);
1483 1498
1484 /* REVISIT we sometimes get spurious IRQs on g_ep0 1499 return retval;
1485 * not clear why...
1486 */
1487 if (retval != IRQ_HANDLED)
1488 DBG(5, "spurious?\n");
1489
1490 return IRQ_HANDLED;
1491} 1500}
1492 1501
1493#else 1502#else
@@ -1687,8 +1696,9 @@ musb_vbus_store(struct device *dev, struct device_attribute *attr,
1687 } 1696 }
1688 1697
1689 spin_lock_irqsave(&musb->lock, flags); 1698 spin_lock_irqsave(&musb->lock, flags);
1690 musb->a_wait_bcon = val; 1699 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1691 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON) 1700 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1701 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1692 musb->is_active = 0; 1702 musb->is_active = 0;
1693 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1703 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1694 spin_unlock_irqrestore(&musb->lock, flags); 1704 spin_unlock_irqrestore(&musb->lock, flags);
@@ -1706,10 +1716,13 @@ musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1706 1716
1707 spin_lock_irqsave(&musb->lock, flags); 1717 spin_lock_irqsave(&musb->lock, flags);
1708 val = musb->a_wait_bcon; 1718 val = musb->a_wait_bcon;
1719 /* FIXME get_vbus_status() is normally #defined as false...
1720 * and is effectively TUSB-specific.
1721 */
1709 vbus = musb_platform_get_vbus_status(musb); 1722 vbus = musb_platform_get_vbus_status(musb);
1710 spin_unlock_irqrestore(&musb->lock, flags); 1723 spin_unlock_irqrestore(&musb->lock, flags);
1711 1724
1712 return sprintf(buf, "Vbus %s, timeout %lu\n", 1725 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1713 vbus ? "on" : "off", val); 1726 vbus ? "on" : "off", val);
1714} 1727}
1715static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1728static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
@@ -1749,8 +1762,8 @@ static void musb_irq_work(struct work_struct *data)
1749 struct musb *musb = container_of(data, struct musb, irq_work); 1762 struct musb *musb = container_of(data, struct musb, irq_work);
1750 static int old_state; 1763 static int old_state;
1751 1764
1752 if (musb->xceiv.state != old_state) { 1765 if (musb->xceiv->state != old_state) {
1753 old_state = musb->xceiv.state; 1766 old_state = musb->xceiv->state;
1754 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1767 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1755 } 1768 }
1756} 1769}
@@ -1782,6 +1795,7 @@ allocate_instance(struct device *dev,
1782 hcd->uses_new_polling = 1; 1795 hcd->uses_new_polling = 1;
1783 1796
1784 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1797 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1798 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1785#else 1799#else
1786 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1800 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1787 if (!musb) 1801 if (!musb)
@@ -1847,7 +1861,7 @@ static void musb_free(struct musb *musb)
1847 } 1861 }
1848 1862
1849#ifdef CONFIG_USB_MUSB_OTG 1863#ifdef CONFIG_USB_MUSB_OTG
1850 put_device(musb->xceiv.dev); 1864 put_device(musb->xceiv->dev);
1851#endif 1865#endif
1852 1866
1853#ifdef CONFIG_USB_MUSB_HDRC_HCD 1867#ifdef CONFIG_USB_MUSB_HDRC_HCD
@@ -1928,10 +1942,18 @@ bad_config:
1928 } 1942 }
1929 } 1943 }
1930 1944
1931 /* assume vbus is off */ 1945 /* The musb_platform_init() call:
1932 1946 * - adjusts musb->mregs and musb->isr if needed,
1933 /* platform adjusts musb->mregs and musb->isr if needed, 1947 * - may initialize an integrated tranceiver
1934 * and activates clocks 1948 * - initializes musb->xceiv, usually by otg_get_transceiver()
1949 * - activates clocks.
1950 * - stops powering VBUS
1951 * - assigns musb->board_set_vbus if host mode is enabled
1952 *
1953 * There are various transciever configurations. Blackfin,
1954 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1955 * external/discrete ones in various flavors (twl4030 family,
1956 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1935 */ 1957 */
1936 musb->isr = generic_interrupt; 1958 musb->isr = generic_interrupt;
1937 status = musb_platform_init(musb); 1959 status = musb_platform_init(musb);
@@ -1968,6 +1990,10 @@ bad_config:
1968 if (status < 0) 1990 if (status < 0)
1969 goto fail2; 1991 goto fail2;
1970 1992
1993#ifdef CONFIG_USB_OTG
1994 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1995#endif
1996
1971 /* Init IRQ workqueue before request_irq */ 1997 /* Init IRQ workqueue before request_irq */
1972 INIT_WORK(&musb->irq_work, musb_irq_work); 1998 INIT_WORK(&musb->irq_work, musb_irq_work);
1973 1999
@@ -1999,17 +2025,17 @@ bad_config:
1999 ? "DMA" : "PIO", 2025 ? "DMA" : "PIO",
2000 musb->nIrq); 2026 musb->nIrq);
2001 2027
2002#ifdef CONFIG_USB_MUSB_HDRC_HCD 2028 /* host side needs more setup */
2003 /* host side needs more setup, except for no-host modes */ 2029 if (is_host_enabled(musb)) {
2004 if (musb->board_mode != MUSB_PERIPHERAL) {
2005 struct usb_hcd *hcd = musb_to_hcd(musb); 2030 struct usb_hcd *hcd = musb_to_hcd(musb);
2006 2031
2007 if (musb->board_mode == MUSB_OTG) 2032 otg_set_host(musb->xceiv, &hcd->self);
2033
2034 if (is_otg_enabled(musb))
2008 hcd->self.otg_port = 1; 2035 hcd->self.otg_port = 1;
2009 musb->xceiv.host = &hcd->self; 2036 musb->xceiv->host = &hcd->self;
2010 hcd->power_budget = 2 * (plat->power ? : 250); 2037 hcd->power_budget = 2 * (plat->power ? : 250);
2011 } 2038 }
2012#endif /* CONFIG_USB_MUSB_HDRC_HCD */
2013 2039
2014 /* For the host-only role, we can activate right away. 2040 /* For the host-only role, we can activate right away.
2015 * (We expect the ID pin to be forcibly grounded!!) 2041 * (We expect the ID pin to be forcibly grounded!!)
@@ -2017,8 +2043,8 @@ bad_config:
2017 */ 2043 */
2018 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2044 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2019 MUSB_HST_MODE(musb); 2045 MUSB_HST_MODE(musb);
2020 musb->xceiv.default_a = 1; 2046 musb->xceiv->default_a = 1;
2021 musb->xceiv.state = OTG_STATE_A_IDLE; 2047 musb->xceiv->state = OTG_STATE_A_IDLE;
2022 2048
2023 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2049 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2024 if (status) 2050 if (status)
@@ -2033,8 +2059,8 @@ bad_config:
2033 2059
2034 } else /* peripheral is enabled */ { 2060 } else /* peripheral is enabled */ {
2035 MUSB_DEV_MODE(musb); 2061 MUSB_DEV_MODE(musb);
2036 musb->xceiv.default_a = 0; 2062 musb->xceiv->default_a = 0;
2037 musb->xceiv.state = OTG_STATE_B_IDLE; 2063 musb->xceiv->state = OTG_STATE_B_IDLE;
2038 2064
2039 status = musb_gadget_setup(musb); 2065 status = musb_gadget_setup(musb);
2040 if (status) 2066 if (status)
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index efb39b5e55b5..f3772ca3b2cf 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -40,6 +40,7 @@
40#include <linux/interrupt.h> 40#include <linux/interrupt.h>
41#include <linux/smp_lock.h> 41#include <linux/smp_lock.h>
42#include <linux/errno.h> 42#include <linux/errno.h>
43#include <linux/timer.h>
43#include <linux/clk.h> 44#include <linux/clk.h>
44#include <linux/device.h> 45#include <linux/device.h>
45#include <linux/usb/ch9.h> 46#include <linux/usb/ch9.h>
@@ -171,7 +172,8 @@ enum musb_h_ep0_state {
171 172
172/* peripheral side ep0 states */ 173/* peripheral side ep0 states */
173enum musb_g_ep0_state { 174enum musb_g_ep0_state {
174 MUSB_EP0_STAGE_SETUP, /* idle, waiting for setup */ 175 MUSB_EP0_STAGE_IDLE, /* idle, waiting for SETUP */
176 MUSB_EP0_STAGE_SETUP, /* received SETUP */
175 MUSB_EP0_STAGE_TX, /* IN data */ 177 MUSB_EP0_STAGE_TX, /* IN data */
176 MUSB_EP0_STAGE_RX, /* OUT data */ 178 MUSB_EP0_STAGE_RX, /* OUT data */
177 MUSB_EP0_STAGE_STATUSIN, /* (after OUT data) */ 179 MUSB_EP0_STAGE_STATUSIN, /* (after OUT data) */
@@ -179,10 +181,15 @@ enum musb_g_ep0_state {
179 MUSB_EP0_STAGE_ACKWAIT, /* after zlp, before statusin */ 181 MUSB_EP0_STAGE_ACKWAIT, /* after zlp, before statusin */
180} __attribute__ ((packed)); 182} __attribute__ ((packed));
181 183
182/* OTG protocol constants */ 184/*
185 * OTG protocol constants. See USB OTG 1.3 spec,
186 * sections 5.5 "Device Timings" and 6.6.5 "Timers".
187 */
183#define OTG_TIME_A_WAIT_VRISE 100 /* msec (max) */ 188#define OTG_TIME_A_WAIT_VRISE 100 /* msec (max) */
184#define OTG_TIME_A_WAIT_BCON 0 /* 0=infinite; min 1000 msec */ 189#define OTG_TIME_A_WAIT_BCON 1100 /* min 1 second */
185#define OTG_TIME_A_IDLE_BDIS 200 /* msec (min) */ 190#define OTG_TIME_A_AIDL_BDIS 200 /* min 200 msec */
191#define OTG_TIME_B_ASE0_BRST 100 /* min 3.125 ms */
192
186 193
187/*************************** REGISTER ACCESS ********************************/ 194/*************************** REGISTER ACCESS ********************************/
188 195
@@ -331,6 +338,8 @@ struct musb {
331 struct list_head control; /* of musb_qh */ 338 struct list_head control; /* of musb_qh */
332 struct list_head in_bulk; /* of musb_qh */ 339 struct list_head in_bulk; /* of musb_qh */
333 struct list_head out_bulk; /* of musb_qh */ 340 struct list_head out_bulk; /* of musb_qh */
341
342 struct timer_list otg_timer;
334#endif 343#endif
335 344
336 /* called with IRQs blocked; ON/nonzero implies starting a session, 345 /* called with IRQs blocked; ON/nonzero implies starting a session,
@@ -355,7 +364,7 @@ struct musb {
355 u16 int_rx; 364 u16 int_rx;
356 u16 int_tx; 365 u16 int_tx;
357 366
358 struct otg_transceiver xceiv; 367 struct otg_transceiver *xceiv;
359 368
360 int nIrq; 369 int nIrq;
361 unsigned irq_wake:1; 370 unsigned irq_wake:1;
@@ -386,6 +395,9 @@ struct musb {
386 unsigned is_multipoint:1; 395 unsigned is_multipoint:1;
387 unsigned ignore_disconnect:1; /* during bus resets */ 396 unsigned ignore_disconnect:1; /* during bus resets */
388 397
398 unsigned hb_iso_rx:1; /* high bandwidth iso rx? */
399 unsigned hb_iso_tx:1; /* high bandwidth iso tx? */
400
389#ifdef C_MP_TX 401#ifdef C_MP_TX
390 unsigned bulk_split:1; 402 unsigned bulk_split:1;
391#define can_bulk_split(musb,type) \ 403#define can_bulk_split(musb,type) \
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index f79440cdfe7e..8b3c4e2ed7b8 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -310,7 +310,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
310 /* setup DMA, then program endpoint CSR */ 310 /* setup DMA, then program endpoint CSR */
311 request_size = min(request->length, 311 request_size = min(request->length,
312 musb_ep->dma->max_len); 312 musb_ep->dma->max_len);
313 if (request_size <= musb_ep->packet_sz) 313 if (request_size < musb_ep->packet_sz)
314 musb_ep->dma->desired_mode = 0; 314 musb_ep->dma->desired_mode = 0;
315 else 315 else
316 musb_ep->dma->desired_mode = 1; 316 musb_ep->dma->desired_mode = 1;
@@ -349,7 +349,8 @@ static void txstate(struct musb *musb, struct musb_request *req)
349#elif defined(CONFIG_USB_TI_CPPI_DMA) 349#elif defined(CONFIG_USB_TI_CPPI_DMA)
350 /* program endpoint CSR first, then setup DMA */ 350 /* program endpoint CSR first, then setup DMA */
351 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 351 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
352 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_DMAENAB; 352 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
353 MUSB_TXCSR_MODE;
353 musb_writew(epio, MUSB_TXCSR, 354 musb_writew(epio, MUSB_TXCSR,
354 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) 355 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
355 | csr); 356 | csr);
@@ -1405,7 +1406,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
1405 1406
1406 spin_lock_irqsave(&musb->lock, flags); 1407 spin_lock_irqsave(&musb->lock, flags);
1407 1408
1408 switch (musb->xceiv.state) { 1409 switch (musb->xceiv->state) {
1409 case OTG_STATE_B_PERIPHERAL: 1410 case OTG_STATE_B_PERIPHERAL:
1410 /* NOTE: OTG state machine doesn't include B_SUSPENDED; 1411 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1411 * that's part of the standard usb 1.1 state machine, and 1412 * that's part of the standard usb 1.1 state machine, and
@@ -1507,9 +1508,9 @@ static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1507{ 1508{
1508 struct musb *musb = gadget_to_musb(gadget); 1509 struct musb *musb = gadget_to_musb(gadget);
1509 1510
1510 if (!musb->xceiv.set_power) 1511 if (!musb->xceiv->set_power)
1511 return -EOPNOTSUPP; 1512 return -EOPNOTSUPP;
1512 return otg_set_power(&musb->xceiv, mA); 1513 return otg_set_power(musb->xceiv, mA);
1513} 1514}
1514 1515
1515static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) 1516static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
@@ -1732,11 +1733,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1732 1733
1733 spin_lock_irqsave(&musb->lock, flags); 1734 spin_lock_irqsave(&musb->lock, flags);
1734 1735
1735 /* REVISIT always use otg_set_peripheral(), handling 1736 otg_set_peripheral(musb->xceiv, &musb->g);
1736 * issues including the root hub one below ...
1737 */
1738 musb->xceiv.gadget = &musb->g;
1739 musb->xceiv.state = OTG_STATE_B_IDLE;
1740 musb->is_active = 1; 1737 musb->is_active = 1;
1741 1738
1742 /* FIXME this ignores the softconnect flag. Drivers are 1739 /* FIXME this ignores the softconnect flag. Drivers are
@@ -1748,6 +1745,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1748 if (!is_otg_enabled(musb)) 1745 if (!is_otg_enabled(musb))
1749 musb_start(musb); 1746 musb_start(musb);
1750 1747
1748 otg_set_peripheral(musb->xceiv, &musb->g);
1749
1751 spin_unlock_irqrestore(&musb->lock, flags); 1750 spin_unlock_irqrestore(&musb->lock, flags);
1752 1751
1753 if (is_otg_enabled(musb)) { 1752 if (is_otg_enabled(musb)) {
@@ -1761,8 +1760,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1761 if (retval < 0) { 1760 if (retval < 0) {
1762 DBG(1, "add_hcd failed, %d\n", retval); 1761 DBG(1, "add_hcd failed, %d\n", retval);
1763 spin_lock_irqsave(&musb->lock, flags); 1762 spin_lock_irqsave(&musb->lock, flags);
1764 musb->xceiv.gadget = NULL; 1763 otg_set_peripheral(musb->xceiv, NULL);
1765 musb->xceiv.state = OTG_STATE_UNDEFINED;
1766 musb->gadget_driver = NULL; 1764 musb->gadget_driver = NULL;
1767 musb->g.dev.driver = NULL; 1765 musb->g.dev.driver = NULL;
1768 spin_unlock_irqrestore(&musb->lock, flags); 1766 spin_unlock_irqrestore(&musb->lock, flags);
@@ -1845,8 +1843,9 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1845 1843
1846 (void) musb_gadget_vbus_draw(&musb->g, 0); 1844 (void) musb_gadget_vbus_draw(&musb->g, 0);
1847 1845
1848 musb->xceiv.state = OTG_STATE_UNDEFINED; 1846 musb->xceiv->state = OTG_STATE_UNDEFINED;
1849 stop_activity(musb, driver); 1847 stop_activity(musb, driver);
1848 otg_set_peripheral(musb->xceiv, NULL);
1850 1849
1851 DBG(3, "unregistering driver %s\n", driver->function); 1850 DBG(3, "unregistering driver %s\n", driver->function);
1852 spin_unlock_irqrestore(&musb->lock, flags); 1851 spin_unlock_irqrestore(&musb->lock, flags);
@@ -1882,7 +1881,7 @@ EXPORT_SYMBOL(usb_gadget_unregister_driver);
1882void musb_g_resume(struct musb *musb) 1881void musb_g_resume(struct musb *musb)
1883{ 1882{
1884 musb->is_suspended = 0; 1883 musb->is_suspended = 0;
1885 switch (musb->xceiv.state) { 1884 switch (musb->xceiv->state) {
1886 case OTG_STATE_B_IDLE: 1885 case OTG_STATE_B_IDLE:
1887 break; 1886 break;
1888 case OTG_STATE_B_WAIT_ACON: 1887 case OTG_STATE_B_WAIT_ACON:
@@ -1908,10 +1907,10 @@ void musb_g_suspend(struct musb *musb)
1908 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1907 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1909 DBG(3, "devctl %02x\n", devctl); 1908 DBG(3, "devctl %02x\n", devctl);
1910 1909
1911 switch (musb->xceiv.state) { 1910 switch (musb->xceiv->state) {
1912 case OTG_STATE_B_IDLE: 1911 case OTG_STATE_B_IDLE:
1913 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 1912 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1914 musb->xceiv.state = OTG_STATE_B_PERIPHERAL; 1913 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1915 break; 1914 break;
1916 case OTG_STATE_B_PERIPHERAL: 1915 case OTG_STATE_B_PERIPHERAL:
1917 musb->is_suspended = 1; 1916 musb->is_suspended = 1;
@@ -1957,22 +1956,24 @@ void musb_g_disconnect(struct musb *musb)
1957 spin_lock(&musb->lock); 1956 spin_lock(&musb->lock);
1958 } 1957 }
1959 1958
1960 switch (musb->xceiv.state) { 1959 switch (musb->xceiv->state) {
1961 default: 1960 default:
1962#ifdef CONFIG_USB_MUSB_OTG 1961#ifdef CONFIG_USB_MUSB_OTG
1963 DBG(2, "Unhandled disconnect %s, setting a_idle\n", 1962 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1964 otg_state_string(musb)); 1963 otg_state_string(musb));
1965 musb->xceiv.state = OTG_STATE_A_IDLE; 1964 musb->xceiv->state = OTG_STATE_A_IDLE;
1965 MUSB_HST_MODE(musb);
1966 break; 1966 break;
1967 case OTG_STATE_A_PERIPHERAL: 1967 case OTG_STATE_A_PERIPHERAL:
1968 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL; 1968 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
1969 MUSB_HST_MODE(musb);
1969 break; 1970 break;
1970 case OTG_STATE_B_WAIT_ACON: 1971 case OTG_STATE_B_WAIT_ACON:
1971 case OTG_STATE_B_HOST: 1972 case OTG_STATE_B_HOST:
1972#endif 1973#endif
1973 case OTG_STATE_B_PERIPHERAL: 1974 case OTG_STATE_B_PERIPHERAL:
1974 case OTG_STATE_B_IDLE: 1975 case OTG_STATE_B_IDLE:
1975 musb->xceiv.state = OTG_STATE_B_IDLE; 1976 musb->xceiv->state = OTG_STATE_B_IDLE;
1976 break; 1977 break;
1977 case OTG_STATE_B_SRP_INIT: 1978 case OTG_STATE_B_SRP_INIT:
1978 break; 1979 break;
@@ -2028,10 +2029,10 @@ __acquires(musb->lock)
2028 * or else after HNP, as A-Device 2029 * or else after HNP, as A-Device
2029 */ 2030 */
2030 if (devctl & MUSB_DEVCTL_BDEVICE) { 2031 if (devctl & MUSB_DEVCTL_BDEVICE) {
2031 musb->xceiv.state = OTG_STATE_B_PERIPHERAL; 2032 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2032 musb->g.is_a_peripheral = 0; 2033 musb->g.is_a_peripheral = 0;
2033 } else if (is_otg_enabled(musb)) { 2034 } else if (is_otg_enabled(musb)) {
2034 musb->xceiv.state = OTG_STATE_A_PERIPHERAL; 2035 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2035 musb->g.is_a_peripheral = 1; 2036 musb->g.is_a_peripheral = 1;
2036 } else 2037 } else
2037 WARN_ON(1); 2038 WARN_ON(1);
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index 3f5e30ddfa27..40ed50ecedff 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -4,6 +4,7 @@
4 * Copyright 2005 Mentor Graphics Corporation 4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments 5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation 6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
7 * 8 *
8 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
@@ -58,7 +59,8 @@
58static char *decode_ep0stage(u8 stage) 59static char *decode_ep0stage(u8 stage)
59{ 60{
60 switch (stage) { 61 switch (stage) {
61 case MUSB_EP0_STAGE_SETUP: return "idle"; 62 case MUSB_EP0_STAGE_IDLE: return "idle";
63 case MUSB_EP0_STAGE_SETUP: return "setup";
62 case MUSB_EP0_STAGE_TX: return "in"; 64 case MUSB_EP0_STAGE_TX: return "in";
63 case MUSB_EP0_STAGE_RX: return "out"; 65 case MUSB_EP0_STAGE_RX: return "out";
64 case MUSB_EP0_STAGE_ACKWAIT: return "wait"; 66 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
@@ -628,7 +630,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
628 musb_writew(regs, MUSB_CSR0, 630 musb_writew(regs, MUSB_CSR0,
629 csr & ~MUSB_CSR0_P_SENTSTALL); 631 csr & ~MUSB_CSR0_P_SENTSTALL);
630 retval = IRQ_HANDLED; 632 retval = IRQ_HANDLED;
631 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 633 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
632 csr = musb_readw(regs, MUSB_CSR0); 634 csr = musb_readw(regs, MUSB_CSR0);
633 } 635 }
634 636
@@ -636,7 +638,18 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
636 if (csr & MUSB_CSR0_P_SETUPEND) { 638 if (csr & MUSB_CSR0_P_SETUPEND) {
637 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND); 639 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
638 retval = IRQ_HANDLED; 640 retval = IRQ_HANDLED;
639 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 641 /* Transition into the early status phase */
642 switch (musb->ep0_state) {
643 case MUSB_EP0_STAGE_TX:
644 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
645 break;
646 case MUSB_EP0_STAGE_RX:
647 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
648 break;
649 default:
650 ERR("SetupEnd came in a wrong ep0stage %s",
651 decode_ep0stage(musb->ep0_state));
652 }
640 csr = musb_readw(regs, MUSB_CSR0); 653 csr = musb_readw(regs, MUSB_CSR0);
641 /* NOTE: request may need completion */ 654 /* NOTE: request may need completion */
642 } 655 }
@@ -697,11 +710,31 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
697 if (req) 710 if (req)
698 musb_g_ep0_giveback(musb, req); 711 musb_g_ep0_giveback(musb, req);
699 } 712 }
713
714 /*
715 * In case when several interrupts can get coalesced,
716 * check to see if we've already received a SETUP packet...
717 */
718 if (csr & MUSB_CSR0_RXPKTRDY)
719 goto setup;
720
721 retval = IRQ_HANDLED;
722 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
723 break;
724
725 case MUSB_EP0_STAGE_IDLE:
726 /*
727 * This state is typically (but not always) indiscernible
728 * from the status states since the corresponding interrupts
729 * tend to happen within too little period of time (with only
730 * a zero-length packet in between) and so get coalesced...
731 */
700 retval = IRQ_HANDLED; 732 retval = IRQ_HANDLED;
701 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 733 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
702 /* FALLTHROUGH */ 734 /* FALLTHROUGH */
703 735
704 case MUSB_EP0_STAGE_SETUP: 736 case MUSB_EP0_STAGE_SETUP:
737setup:
705 if (csr & MUSB_CSR0_RXPKTRDY) { 738 if (csr & MUSB_CSR0_RXPKTRDY) {
706 struct usb_ctrlrequest setup; 739 struct usb_ctrlrequest setup;
707 int handled = 0; 740 int handled = 0;
@@ -783,7 +816,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
783stall: 816stall:
784 DBG(3, "stall (%d)\n", handled); 817 DBG(3, "stall (%d)\n", handled);
785 musb->ackpend |= MUSB_CSR0_P_SENDSTALL; 818 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
786 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 819 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
787finish: 820finish:
788 musb_writew(regs, MUSB_CSR0, 821 musb_writew(regs, MUSB_CSR0,
789 musb->ackpend); 822 musb->ackpend);
@@ -803,7 +836,7 @@ finish:
803 /* "can't happen" */ 836 /* "can't happen" */
804 WARN_ON(1); 837 WARN_ON(1);
805 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL); 838 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
806 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 839 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
807 break; 840 break;
808 } 841 }
809 842
@@ -959,7 +992,7 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
959 992
960 csr |= MUSB_CSR0_P_SENDSTALL; 993 csr |= MUSB_CSR0_P_SENDSTALL;
961 musb_writew(regs, MUSB_CSR0, csr); 994 musb_writew(regs, MUSB_CSR0, csr);
962 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 995 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
963 musb->ackpend = 0; 996 musb->ackpend = 0;
964 break; 997 break;
965 default: 998 default:
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index db1b57415ec7..94a2a350a414 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -181,6 +181,19 @@ static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
181 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 181 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
182} 182}
183 183
184static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
185{
186 if (is_in != 0 || ep->is_shared_fifo)
187 ep->in_qh = qh;
188 if (is_in == 0 || ep->is_shared_fifo)
189 ep->out_qh = qh;
190}
191
192static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
193{
194 return is_in ? ep->in_qh : ep->out_qh;
195}
196
184/* 197/*
185 * Start the URB at the front of an endpoint's queue 198 * Start the URB at the front of an endpoint's queue
186 * end must be claimed from the caller. 199 * end must be claimed from the caller.
@@ -210,7 +223,6 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
210 case USB_ENDPOINT_XFER_CONTROL: 223 case USB_ENDPOINT_XFER_CONTROL:
211 /* control transfers always start with SETUP */ 224 /* control transfers always start with SETUP */
212 is_in = 0; 225 is_in = 0;
213 hw_ep->out_qh = qh;
214 musb->ep0_stage = MUSB_EP0_START; 226 musb->ep0_stage = MUSB_EP0_START;
215 buf = urb->setup_packet; 227 buf = urb->setup_packet;
216 len = 8; 228 len = 8;
@@ -239,10 +251,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
239 epnum, buf + offset, len); 251 epnum, buf + offset, len);
240 252
241 /* Configure endpoint */ 253 /* Configure endpoint */
242 if (is_in || hw_ep->is_shared_fifo) 254 musb_ep_set_qh(hw_ep, is_in, qh);
243 hw_ep->in_qh = qh;
244 else
245 hw_ep->out_qh = qh;
246 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); 255 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
247 256
248 /* transmit may have more work: start it when it is time */ 257 /* transmit may have more work: start it when it is time */
@@ -286,9 +295,8 @@ start:
286 } 295 }
287} 296}
288 297
289/* caller owns controller lock, irqs are blocked */ 298/* Context: caller owns controller lock, IRQs are blocked */
290static void 299static void musb_giveback(struct musb *musb, struct urb *urb, int status)
291__musb_giveback(struct musb *musb, struct urb *urb, int status)
292__releases(musb->lock) 300__releases(musb->lock)
293__acquires(musb->lock) 301__acquires(musb->lock)
294{ 302{
@@ -321,60 +329,57 @@ __acquires(musb->lock)
321 spin_lock(&musb->lock); 329 spin_lock(&musb->lock);
322} 330}
323 331
324/* for bulk/interrupt endpoints only */ 332/* For bulk/interrupt endpoints only */
325static inline void 333static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
326musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb) 334 struct urb *urb)
327{ 335{
328 struct usb_device *udev = urb->dev; 336 void __iomem *epio = qh->hw_ep->regs;
329 u16 csr; 337 u16 csr;
330 void __iomem *epio = ep->regs;
331 struct musb_qh *qh;
332 338
333 /* FIXME: the current Mentor DMA code seems to have 339 /*
340 * FIXME: the current Mentor DMA code seems to have
334 * problems getting toggle correct. 341 * problems getting toggle correct.
335 */ 342 */
336 343
337 if (is_in || ep->is_shared_fifo) 344 if (is_in)
338 qh = ep->in_qh; 345 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
339 else 346 else
340 qh = ep->out_qh; 347 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
341 348
342 if (!is_in) { 349 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
343 csr = musb_readw(epio, MUSB_TXCSR);
344 usb_settoggle(udev, qh->epnum, 1,
345 (csr & MUSB_TXCSR_H_DATATOGGLE)
346 ? 1 : 0);
347 } else {
348 csr = musb_readw(epio, MUSB_RXCSR);
349 usb_settoggle(udev, qh->epnum, 0,
350 (csr & MUSB_RXCSR_H_DATATOGGLE)
351 ? 1 : 0);
352 }
353} 350}
354 351
355/* caller owns controller lock, irqs are blocked */ 352/*
356static struct musb_qh * 353 * Advance this hardware endpoint's queue, completing the specified URB and
357musb_giveback(struct musb_qh *qh, struct urb *urb, int status) 354 * advancing to either the next URB queued to that qh, or else invalidating
355 * that qh and advancing to the next qh scheduled after the current one.
356 *
357 * Context: caller owns controller lock, IRQs are blocked
358 */
359static void musb_advance_schedule(struct musb *musb, struct urb *urb,
360 struct musb_hw_ep *hw_ep, int is_in)
358{ 361{
362 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
359 struct musb_hw_ep *ep = qh->hw_ep; 363 struct musb_hw_ep *ep = qh->hw_ep;
360 struct musb *musb = ep->musb;
361 int is_in = usb_pipein(urb->pipe);
362 int ready = qh->is_ready; 364 int ready = qh->is_ready;
365 int status;
366
367 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
363 368
364 /* save toggle eagerly, for paranoia */ 369 /* save toggle eagerly, for paranoia */
365 switch (qh->type) { 370 switch (qh->type) {
366 case USB_ENDPOINT_XFER_BULK: 371 case USB_ENDPOINT_XFER_BULK:
367 case USB_ENDPOINT_XFER_INT: 372 case USB_ENDPOINT_XFER_INT:
368 musb_save_toggle(ep, is_in, urb); 373 musb_save_toggle(qh, is_in, urb);
369 break; 374 break;
370 case USB_ENDPOINT_XFER_ISOC: 375 case USB_ENDPOINT_XFER_ISOC:
371 if (status == 0 && urb->error_count) 376 if (urb->error_count)
372 status = -EXDEV; 377 status = -EXDEV;
373 break; 378 break;
374 } 379 }
375 380
376 qh->is_ready = 0; 381 qh->is_ready = 0;
377 __musb_giveback(musb, urb, status); 382 musb_giveback(musb, urb, status);
378 qh->is_ready = ready; 383 qh->is_ready = ready;
379 384
380 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 385 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
@@ -388,11 +393,8 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
388 else 393 else
389 ep->tx_reinit = 1; 394 ep->tx_reinit = 1;
390 395
391 /* clobber old pointers to this qh */ 396 /* Clobber old pointers to this qh */
392 if (is_in || ep->is_shared_fifo) 397 musb_ep_set_qh(ep, is_in, NULL);
393 ep->in_qh = NULL;
394 else
395 ep->out_qh = NULL;
396 qh->hep->hcpriv = NULL; 398 qh->hep->hcpriv = NULL;
397 399
398 switch (qh->type) { 400 switch (qh->type) {
@@ -421,36 +423,10 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
421 break; 423 break;
422 } 424 }
423 } 425 }
424 return qh;
425}
426
427/*
428 * Advance this hardware endpoint's queue, completing the specified urb and
429 * advancing to either the next urb queued to that qh, or else invalidating
430 * that qh and advancing to the next qh scheduled after the current one.
431 *
432 * Context: caller owns controller lock, irqs are blocked
433 */
434static void
435musb_advance_schedule(struct musb *musb, struct urb *urb,
436 struct musb_hw_ep *hw_ep, int is_in)
437{
438 struct musb_qh *qh;
439
440 if (is_in || hw_ep->is_shared_fifo)
441 qh = hw_ep->in_qh;
442 else
443 qh = hw_ep->out_qh;
444
445 if (urb->status == -EINPROGRESS)
446 qh = musb_giveback(qh, urb, 0);
447 else
448 qh = musb_giveback(qh, urb, urb->status);
449 426
450 if (qh != NULL && qh->is_ready) { 427 if (qh != NULL && qh->is_ready) {
451 DBG(4, "... next ep%d %cX urb %p\n", 428 DBG(4, "... next ep%d %cX urb %p\n",
452 hw_ep->epnum, is_in ? 'R' : 'T', 429 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
453 next_urb(qh));
454 musb_start_urb(musb, is_in, qh); 430 musb_start_urb(musb, is_in, qh);
455 } 431 }
456} 432}
@@ -629,7 +605,8 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
629 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
630 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
631 /* NOTE: bulk combining rewrites high bits of maxpacket */ 607 /* NOTE: bulk combining rewrites high bits of maxpacket */
632 musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket); 608 musb_writew(ep->regs, MUSB_RXMAXP,
609 qh->maxpacket | ((qh->hb_mult - 1) << 11));
633 610
634 ep->rx_reinit = 0; 611 ep->rx_reinit = 0;
635} 612}
@@ -651,9 +628,10 @@ static bool musb_tx_dma_program(struct dma_controller *dma,
651 csr = musb_readw(epio, MUSB_TXCSR); 628 csr = musb_readw(epio, MUSB_TXCSR);
652 if (length > pkt_size) { 629 if (length > pkt_size) {
653 mode = 1; 630 mode = 1;
654 csr |= MUSB_TXCSR_AUTOSET 631 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
655 | MUSB_TXCSR_DMAMODE 632 /* autoset shouldn't be set in high bandwidth */
656 | MUSB_TXCSR_DMAENAB; 633 if (qh->hb_mult == 1)
634 csr |= MUSB_TXCSR_AUTOSET;
657 } else { 635 } else {
658 mode = 0; 636 mode = 0;
659 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); 637 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
@@ -703,15 +681,8 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
703 void __iomem *mbase = musb->mregs; 681 void __iomem *mbase = musb->mregs;
704 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 682 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
705 void __iomem *epio = hw_ep->regs; 683 void __iomem *epio = hw_ep->regs;
706 struct musb_qh *qh; 684 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
707 u16 packet_sz; 685 u16 packet_sz = qh->maxpacket;
708
709 if (!is_out || hw_ep->is_shared_fifo)
710 qh = hw_ep->in_qh;
711 else
712 qh = hw_ep->out_qh;
713
714 packet_sz = qh->maxpacket;
715 686
716 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s " 687 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
717 "h_addr%02x h_port%02x bytes %d\n", 688 "h_addr%02x h_port%02x bytes %d\n",
@@ -1129,17 +1100,14 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1129 u16 tx_csr; 1100 u16 tx_csr;
1130 size_t length = 0; 1101 size_t length = 0;
1131 size_t offset = 0; 1102 size_t offset = 0;
1132 struct urb *urb;
1133 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1103 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1134 void __iomem *epio = hw_ep->regs; 1104 void __iomem *epio = hw_ep->regs;
1135 struct musb_qh *qh = hw_ep->is_shared_fifo ? hw_ep->in_qh 1105 struct musb_qh *qh = hw_ep->out_qh;
1136 : hw_ep->out_qh; 1106 struct urb *urb = next_urb(qh);
1137 u32 status = 0; 1107 u32 status = 0;
1138 void __iomem *mbase = musb->mregs; 1108 void __iomem *mbase = musb->mregs;
1139 struct dma_channel *dma; 1109 struct dma_channel *dma;
1140 1110
1141 urb = next_urb(qh);
1142
1143 musb_ep_select(mbase, epnum); 1111 musb_ep_select(mbase, epnum);
1144 tx_csr = musb_readw(epio, MUSB_TXCSR); 1112 tx_csr = musb_readw(epio, MUSB_TXCSR);
1145 1113
@@ -1427,7 +1395,7 @@ static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
1427 urb->actual_length += dma->actual_len; 1395 urb->actual_length += dma->actual_len;
1428 dma->actual_len = 0L; 1396 dma->actual_len = 0L;
1429 } 1397 }
1430 musb_save_toggle(ep, 1, urb); 1398 musb_save_toggle(cur_qh, 1, urb);
1431 1399
1432 /* move cur_qh to end of queue */ 1400 /* move cur_qh to end of queue */
1433 list_move_tail(&cur_qh->ring, &musb->in_bulk); 1401 list_move_tail(&cur_qh->ring, &musb->in_bulk);
@@ -1531,6 +1499,10 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1531 /* packet error reported later */ 1499 /* packet error reported later */
1532 iso_err = true; 1500 iso_err = true;
1533 } 1501 }
1502 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1503 DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
1504 epnum);
1505 status = -EPROTO;
1534 } 1506 }
1535 1507
1536 /* faults abort the transfer */ 1508 /* faults abort the transfer */
@@ -1738,7 +1710,11 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1738 val &= ~MUSB_RXCSR_H_AUTOREQ; 1710 val &= ~MUSB_RXCSR_H_AUTOREQ;
1739 else 1711 else
1740 val |= MUSB_RXCSR_H_AUTOREQ; 1712 val |= MUSB_RXCSR_H_AUTOREQ;
1741 val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB; 1713 val |= MUSB_RXCSR_DMAENAB;
1714
1715 /* autoclear shouldn't be set in high bandwidth */
1716 if (qh->hb_mult == 1)
1717 val |= MUSB_RXCSR_AUTOCLEAR;
1742 1718
1743 musb_writew(epio, MUSB_RXCSR, 1719 musb_writew(epio, MUSB_RXCSR,
1744 MUSB_RXCSR_H_WZC_BITS | val); 1720 MUSB_RXCSR_H_WZC_BITS | val);
@@ -1817,19 +1793,17 @@ static int musb_schedule(
1817 epnum++, hw_ep++) { 1793 epnum++, hw_ep++) {
1818 int diff; 1794 int diff;
1819 1795
1820 if (is_in || hw_ep->is_shared_fifo) { 1796 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1821 if (hw_ep->in_qh != NULL)
1822 continue;
1823 } else if (hw_ep->out_qh != NULL)
1824 continue; 1797 continue;
1825 1798
1826 if (hw_ep == musb->bulk_ep) 1799 if (hw_ep == musb->bulk_ep)
1827 continue; 1800 continue;
1828 1801
1829 if (is_in) 1802 if (is_in)
1830 diff = hw_ep->max_packet_sz_rx - qh->maxpacket; 1803 diff = hw_ep->max_packet_sz_rx;
1831 else 1804 else
1832 diff = hw_ep->max_packet_sz_tx - qh->maxpacket; 1805 diff = hw_ep->max_packet_sz_tx;
1806 diff -= (qh->maxpacket * qh->hb_mult);
1833 1807
1834 if (diff >= 0 && best_diff > diff) { 1808 if (diff >= 0 && best_diff > diff) {
1835 best_diff = diff; 1809 best_diff = diff;
@@ -1932,15 +1906,27 @@ static int musb_urb_enqueue(
1932 qh->is_ready = 1; 1906 qh->is_ready = 1;
1933 1907
1934 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize); 1908 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1909 qh->type = usb_endpoint_type(epd);
1935 1910
1936 /* no high bandwidth support yet */ 1911 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
1937 if (qh->maxpacket & ~0x7ff) { 1912 * Some musb cores don't support high bandwidth ISO transfers; and
1938 ret = -EMSGSIZE; 1913 * we don't (yet!) support high bandwidth interrupt transfers.
1939 goto done; 1914 */
1915 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
1916 if (qh->hb_mult > 1) {
1917 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
1918
1919 if (ok)
1920 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
1921 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
1922 if (!ok) {
1923 ret = -EMSGSIZE;
1924 goto done;
1925 }
1926 qh->maxpacket &= 0x7ff;
1940 } 1927 }
1941 1928
1942 qh->epnum = usb_endpoint_num(epd); 1929 qh->epnum = usb_endpoint_num(epd);
1943 qh->type = usb_endpoint_type(epd);
1944 1930
1945 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 1931 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1946 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 1932 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
@@ -2052,14 +2038,15 @@ done:
2052 * called with controller locked, irqs blocked 2038 * called with controller locked, irqs blocked
2053 * that hardware queue advances to the next transfer, unless prevented 2039 * that hardware queue advances to the next transfer, unless prevented
2054 */ 2040 */
2055static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in) 2041static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2056{ 2042{
2057 struct musb_hw_ep *ep = qh->hw_ep; 2043 struct musb_hw_ep *ep = qh->hw_ep;
2058 void __iomem *epio = ep->regs; 2044 void __iomem *epio = ep->regs;
2059 unsigned hw_end = ep->epnum; 2045 unsigned hw_end = ep->epnum;
2060 void __iomem *regs = ep->musb->mregs; 2046 void __iomem *regs = ep->musb->mregs;
2061 u16 csr; 2047 int is_in = usb_pipein(urb->pipe);
2062 int status = 0; 2048 int status = 0;
2049 u16 csr;
2063 2050
2064 musb_ep_select(regs, hw_end); 2051 musb_ep_select(regs, hw_end);
2065 2052
@@ -2112,14 +2099,14 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2112{ 2099{
2113 struct musb *musb = hcd_to_musb(hcd); 2100 struct musb *musb = hcd_to_musb(hcd);
2114 struct musb_qh *qh; 2101 struct musb_qh *qh;
2115 struct list_head *sched;
2116 unsigned long flags; 2102 unsigned long flags;
2103 int is_in = usb_pipein(urb->pipe);
2117 int ret; 2104 int ret;
2118 2105
2119 DBG(4, "urb=%p, dev%d ep%d%s\n", urb, 2106 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
2120 usb_pipedevice(urb->pipe), 2107 usb_pipedevice(urb->pipe),
2121 usb_pipeendpoint(urb->pipe), 2108 usb_pipeendpoint(urb->pipe),
2122 usb_pipein(urb->pipe) ? "in" : "out"); 2109 is_in ? "in" : "out");
2123 2110
2124 spin_lock_irqsave(&musb->lock, flags); 2111 spin_lock_irqsave(&musb->lock, flags);
2125 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2112 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
@@ -2130,47 +2117,25 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2130 if (!qh) 2117 if (!qh)
2131 goto done; 2118 goto done;
2132 2119
2133 /* Any URB not actively programmed into endpoint hardware can be 2120 /*
2121 * Any URB not actively programmed into endpoint hardware can be
2134 * immediately given back; that's any URB not at the head of an 2122 * immediately given back; that's any URB not at the head of an
2135 * endpoint queue, unless someday we get real DMA queues. And even 2123 * endpoint queue, unless someday we get real DMA queues. And even
2136 * if it's at the head, it might not be known to the hardware... 2124 * if it's at the head, it might not be known to the hardware...
2137 * 2125 *
2138 * Otherwise abort current transfer, pending dma, etc.; urb->status 2126 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2139 * has already been updated. This is a synchronous abort; it'd be 2127 * has already been updated. This is a synchronous abort; it'd be
2140 * OK to hold off until after some IRQ, though. 2128 * OK to hold off until after some IRQ, though.
2129 *
2130 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2141 */ 2131 */
2142 if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list) 2132 if (!qh->is_ready
2143 ret = -EINPROGRESS; 2133 || urb->urb_list.prev != &qh->hep->urb_list
2144 else { 2134 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2145 switch (qh->type) {
2146 case USB_ENDPOINT_XFER_CONTROL:
2147 sched = &musb->control;
2148 break;
2149 case USB_ENDPOINT_XFER_BULK:
2150 if (qh->mux == 1) {
2151 if (usb_pipein(urb->pipe))
2152 sched = &musb->in_bulk;
2153 else
2154 sched = &musb->out_bulk;
2155 break;
2156 }
2157 default:
2158 /* REVISIT when we get a schedule tree, periodic
2159 * transfers won't always be at the head of a
2160 * singleton queue...
2161 */
2162 sched = NULL;
2163 break;
2164 }
2165 }
2166
2167 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2168 if (ret < 0 || (sched && qh != first_qh(sched))) {
2169 int ready = qh->is_ready; 2135 int ready = qh->is_ready;
2170 2136
2171 ret = 0;
2172 qh->is_ready = 0; 2137 qh->is_ready = 0;
2173 __musb_giveback(musb, urb, 0); 2138 musb_giveback(musb, urb, 0);
2174 qh->is_ready = ready; 2139 qh->is_ready = ready;
2175 2140
2176 /* If nothing else (usually musb_giveback) is using it 2141 /* If nothing else (usually musb_giveback) is using it
@@ -2182,7 +2147,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2182 kfree(qh); 2147 kfree(qh);
2183 } 2148 }
2184 } else 2149 } else
2185 ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN); 2150 ret = musb_cleanup_urb(urb, qh);
2186done: 2151done:
2187 spin_unlock_irqrestore(&musb->lock, flags); 2152 spin_unlock_irqrestore(&musb->lock, flags);
2188 return ret; 2153 return ret;
@@ -2192,13 +2157,11 @@ done:
2192static void 2157static void
2193musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2158musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2194{ 2159{
2195 u8 epnum = hep->desc.bEndpointAddress; 2160 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2196 unsigned long flags; 2161 unsigned long flags;
2197 struct musb *musb = hcd_to_musb(hcd); 2162 struct musb *musb = hcd_to_musb(hcd);
2198 u8 is_in = epnum & USB_DIR_IN;
2199 struct musb_qh *qh; 2163 struct musb_qh *qh;
2200 struct urb *urb; 2164 struct urb *urb;
2201 struct list_head *sched;
2202 2165
2203 spin_lock_irqsave(&musb->lock, flags); 2166 spin_lock_irqsave(&musb->lock, flags);
2204 2167
@@ -2206,31 +2169,11 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2206 if (qh == NULL) 2169 if (qh == NULL)
2207 goto exit; 2170 goto exit;
2208 2171
2209 switch (qh->type) { 2172 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2210 case USB_ENDPOINT_XFER_CONTROL:
2211 sched = &musb->control;
2212 break;
2213 case USB_ENDPOINT_XFER_BULK:
2214 if (qh->mux == 1) {
2215 if (is_in)
2216 sched = &musb->in_bulk;
2217 else
2218 sched = &musb->out_bulk;
2219 break;
2220 }
2221 default:
2222 /* REVISIT when we get a schedule tree, periodic transfers
2223 * won't always be at the head of a singleton queue...
2224 */
2225 sched = NULL;
2226 break;
2227 }
2228
2229 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2230 2173
2231 /* kick first urb off the hardware, if needed */ 2174 /* Kick the first URB off the hardware, if needed */
2232 qh->is_ready = 0; 2175 qh->is_ready = 0;
2233 if (!sched || qh == first_qh(sched)) { 2176 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2234 urb = next_urb(qh); 2177 urb = next_urb(qh);
2235 2178
2236 /* make software (then hardware) stop ASAP */ 2179 /* make software (then hardware) stop ASAP */
@@ -2238,7 +2181,7 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2238 urb->status = -ESHUTDOWN; 2181 urb->status = -ESHUTDOWN;
2239 2182
2240 /* cleanup */ 2183 /* cleanup */
2241 musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN); 2184 musb_cleanup_urb(urb, qh);
2242 2185
2243 /* Then nuke all the others ... and advance the 2186 /* Then nuke all the others ... and advance the
2244 * queue on hw_ep (e.g. bulk ring) when we're done. 2187 * queue on hw_ep (e.g. bulk ring) when we're done.
@@ -2254,7 +2197,7 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2254 * will activate any of these as it advances. 2197 * will activate any of these as it advances.
2255 */ 2198 */
2256 while (!list_empty(&hep->urb_list)) 2199 while (!list_empty(&hep->urb_list))
2257 __musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2200 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2258 2201
2259 hep->hcpriv = NULL; 2202 hep->hcpriv = NULL;
2260 list_del(&qh->ring); 2203 list_del(&qh->ring);
@@ -2293,7 +2236,7 @@ static int musb_bus_suspend(struct usb_hcd *hcd)
2293{ 2236{
2294 struct musb *musb = hcd_to_musb(hcd); 2237 struct musb *musb = hcd_to_musb(hcd);
2295 2238
2296 if (musb->xceiv.state == OTG_STATE_A_SUSPEND) 2239 if (musb->xceiv->state == OTG_STATE_A_SUSPEND)
2297 return 0; 2240 return 0;
2298 2241
2299 if (is_host_active(musb) && musb->is_active) { 2242 if (is_host_active(musb) && musb->is_active) {
diff --git a/drivers/usb/musb/musb_host.h b/drivers/usb/musb/musb_host.h
index 0b7fbcd21963..14b00776638d 100644
--- a/drivers/usb/musb/musb_host.h
+++ b/drivers/usb/musb/musb_host.h
@@ -67,6 +67,7 @@ struct musb_qh {
67 u8 is_ready; /* safe to modify hw_ep */ 67 u8 is_ready; /* safe to modify hw_ep */
68 u8 type; /* XFERTYPE_* */ 68 u8 type; /* XFERTYPE_* */
69 u8 epnum; 69 u8 epnum;
70 u8 hb_mult; /* high bandwidth pkts per uf */
70 u16 maxpacket; 71 u16 maxpacket;
71 u16 frame; /* for periodic schedule */ 72 u16 frame; /* for periodic schedule */
72 unsigned iso_idx; /* in urb->iso_frame_desc[] */ 73 unsigned iso_idx; /* in urb->iso_frame_desc[] */
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index bf677acc83db..bfe5fe4ebfee 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -78,18 +78,22 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
78 DBG(3, "Root port suspended, power %02x\n", power); 78 DBG(3, "Root port suspended, power %02x\n", power);
79 79
80 musb->port1_status |= USB_PORT_STAT_SUSPEND; 80 musb->port1_status |= USB_PORT_STAT_SUSPEND;
81 switch (musb->xceiv.state) { 81 switch (musb->xceiv->state) {
82 case OTG_STATE_A_HOST: 82 case OTG_STATE_A_HOST:
83 musb->xceiv.state = OTG_STATE_A_SUSPEND; 83 musb->xceiv->state = OTG_STATE_A_SUSPEND;
84 musb->is_active = is_otg_enabled(musb) 84 musb->is_active = is_otg_enabled(musb)
85 && musb->xceiv.host->b_hnp_enable; 85 && musb->xceiv->host->b_hnp_enable;
86 if (musb->is_active)
87 mod_timer(&musb->otg_timer, jiffies
88 + msecs_to_jiffies(
89 OTG_TIME_A_AIDL_BDIS));
86 musb_platform_try_idle(musb, 0); 90 musb_platform_try_idle(musb, 0);
87 break; 91 break;
88#ifdef CONFIG_USB_MUSB_OTG 92#ifdef CONFIG_USB_MUSB_OTG
89 case OTG_STATE_B_HOST: 93 case OTG_STATE_B_HOST:
90 musb->xceiv.state = OTG_STATE_B_WAIT_ACON; 94 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
91 musb->is_active = is_otg_enabled(musb) 95 musb->is_active = is_otg_enabled(musb)
92 && musb->xceiv.host->b_hnp_enable; 96 && musb->xceiv->host->b_hnp_enable;
93 musb_platform_try_idle(musb, 0); 97 musb_platform_try_idle(musb, 0);
94 break; 98 break;
95#endif 99#endif
@@ -116,7 +120,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
116 void __iomem *mbase = musb->mregs; 120 void __iomem *mbase = musb->mregs;
117 121
118#ifdef CONFIG_USB_MUSB_OTG 122#ifdef CONFIG_USB_MUSB_OTG
119 if (musb->xceiv.state == OTG_STATE_B_IDLE) { 123 if (musb->xceiv->state == OTG_STATE_B_IDLE) {
120 DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n"); 124 DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n");
121 musb->port1_status &= ~USB_PORT_STAT_RESET; 125 musb->port1_status &= ~USB_PORT_STAT_RESET;
122 return; 126 return;
@@ -186,14 +190,23 @@ void musb_root_disconnect(struct musb *musb)
186 usb_hcd_poll_rh_status(musb_to_hcd(musb)); 190 usb_hcd_poll_rh_status(musb_to_hcd(musb));
187 musb->is_active = 0; 191 musb->is_active = 0;
188 192
189 switch (musb->xceiv.state) { 193 switch (musb->xceiv->state) {
190 case OTG_STATE_A_HOST:
191 case OTG_STATE_A_SUSPEND: 194 case OTG_STATE_A_SUSPEND:
192 musb->xceiv.state = OTG_STATE_A_WAIT_BCON; 195#ifdef CONFIG_USB_MUSB_OTG
196 if (is_otg_enabled(musb)
197 && musb->xceiv->host->b_hnp_enable) {
198 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
199 musb->g.is_a_peripheral = 1;
200 break;
201 }
202#endif
203 /* FALLTHROUGH */
204 case OTG_STATE_A_HOST:
205 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
193 musb->is_active = 0; 206 musb->is_active = 0;
194 break; 207 break;
195 case OTG_STATE_A_WAIT_VFALL: 208 case OTG_STATE_A_WAIT_VFALL:
196 musb->xceiv.state = OTG_STATE_B_IDLE; 209 musb->xceiv->state = OTG_STATE_B_IDLE;
197 break; 210 break;
198 default: 211 default:
199 DBG(1, "host disconnect (%s)\n", otg_state_string(musb)); 212 DBG(1, "host disconnect (%s)\n", otg_state_string(musb));
@@ -332,7 +345,7 @@ int musb_hub_control(
332 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16; 345 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
333 usb_hcd_poll_rh_status(musb_to_hcd(musb)); 346 usb_hcd_poll_rh_status(musb_to_hcd(musb));
334 /* NOTE: it might really be A_WAIT_BCON ... */ 347 /* NOTE: it might really be A_WAIT_BCON ... */
335 musb->xceiv.state = OTG_STATE_A_HOST; 348 musb->xceiv->state = OTG_STATE_A_HOST;
336 } 349 }
337 350
338 put_unaligned(cpu_to_le32(musb->port1_status 351 put_unaligned(cpu_to_le32(musb->port1_status
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 60924ce08493..34875201ee04 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -44,7 +44,6 @@
44#define get_cpu_rev() 2 44#define get_cpu_rev() 2
45#endif 45#endif
46 46
47#define MUSB_TIMEOUT_A_WAIT_BCON 1100
48 47
49static struct timer_list musb_idle_timer; 48static struct timer_list musb_idle_timer;
50 49
@@ -61,17 +60,17 @@ static void musb_do_idle(unsigned long _musb)
61 60
62 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 61 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
63 62
64 switch (musb->xceiv.state) { 63 switch (musb->xceiv->state) {
65 case OTG_STATE_A_WAIT_BCON: 64 case OTG_STATE_A_WAIT_BCON:
66 devctl &= ~MUSB_DEVCTL_SESSION; 65 devctl &= ~MUSB_DEVCTL_SESSION;
67 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 66 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
68 67
69 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 68 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
70 if (devctl & MUSB_DEVCTL_BDEVICE) { 69 if (devctl & MUSB_DEVCTL_BDEVICE) {
71 musb->xceiv.state = OTG_STATE_B_IDLE; 70 musb->xceiv->state = OTG_STATE_B_IDLE;
72 MUSB_DEV_MODE(musb); 71 MUSB_DEV_MODE(musb);
73 } else { 72 } else {
74 musb->xceiv.state = OTG_STATE_A_IDLE; 73 musb->xceiv->state = OTG_STATE_A_IDLE;
75 MUSB_HST_MODE(musb); 74 MUSB_HST_MODE(musb);
76 } 75 }
77 break; 76 break;
@@ -89,7 +88,7 @@ static void musb_do_idle(unsigned long _musb)
89 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16; 88 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
90 usb_hcd_poll_rh_status(musb_to_hcd(musb)); 89 usb_hcd_poll_rh_status(musb_to_hcd(musb));
91 /* NOTE: it might really be A_WAIT_BCON ... */ 90 /* NOTE: it might really be A_WAIT_BCON ... */
92 musb->xceiv.state = OTG_STATE_A_HOST; 91 musb->xceiv->state = OTG_STATE_A_HOST;
93 } 92 }
94 break; 93 break;
95#endif 94#endif
@@ -97,9 +96,9 @@ static void musb_do_idle(unsigned long _musb)
97 case OTG_STATE_A_HOST: 96 case OTG_STATE_A_HOST:
98 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 97 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
99 if (devctl & MUSB_DEVCTL_BDEVICE) 98 if (devctl & MUSB_DEVCTL_BDEVICE)
100 musb->xceiv.state = OTG_STATE_B_IDLE; 99 musb->xceiv->state = OTG_STATE_B_IDLE;
101 else 100 else
102 musb->xceiv.state = OTG_STATE_A_WAIT_BCON; 101 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
103#endif 102#endif
104 default: 103 default:
105 break; 104 break;
@@ -118,7 +117,7 @@ void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
118 117
119 /* Never idle if active, or when VBUS timeout is not set as host */ 118 /* Never idle if active, or when VBUS timeout is not set as host */
120 if (musb->is_active || ((musb->a_wait_bcon == 0) 119 if (musb->is_active || ((musb->a_wait_bcon == 0)
121 && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) { 120 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
122 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 121 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
123 del_timer(&musb_idle_timer); 122 del_timer(&musb_idle_timer);
124 last_timer = jiffies; 123 last_timer = jiffies;
@@ -163,8 +162,8 @@ static void omap_set_vbus(struct musb *musb, int is_on)
163 162
164 if (is_on) { 163 if (is_on) {
165 musb->is_active = 1; 164 musb->is_active = 1;
166 musb->xceiv.default_a = 1; 165 musb->xceiv->default_a = 1;
167 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE; 166 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
168 devctl |= MUSB_DEVCTL_SESSION; 167 devctl |= MUSB_DEVCTL_SESSION;
169 168
170 MUSB_HST_MODE(musb); 169 MUSB_HST_MODE(musb);
@@ -175,8 +174,8 @@ static void omap_set_vbus(struct musb *musb, int is_on)
175 * jumping right to B_IDLE... 174 * jumping right to B_IDLE...
176 */ 175 */
177 176
178 musb->xceiv.default_a = 0; 177 musb->xceiv->default_a = 0;
179 musb->xceiv.state = OTG_STATE_B_IDLE; 178 musb->xceiv->state = OTG_STATE_B_IDLE;
180 devctl &= ~MUSB_DEVCTL_SESSION; 179 devctl &= ~MUSB_DEVCTL_SESSION;
181 180
182 MUSB_DEV_MODE(musb); 181 MUSB_DEV_MODE(musb);
@@ -188,10 +187,6 @@ static void omap_set_vbus(struct musb *musb, int is_on)
188 otg_state_string(musb), 187 otg_state_string(musb),
189 musb_readb(musb->mregs, MUSB_DEVCTL)); 188 musb_readb(musb->mregs, MUSB_DEVCTL));
190} 189}
191static int omap_set_power(struct otg_transceiver *x, unsigned mA)
192{
193 return 0;
194}
195 190
196static int musb_platform_resume(struct musb *musb); 191static int musb_platform_resume(struct musb *musb);
197 192
@@ -202,24 +197,6 @@ int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
202 devctl |= MUSB_DEVCTL_SESSION; 197 devctl |= MUSB_DEVCTL_SESSION;
203 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 198 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
204 199
205 switch (musb_mode) {
206#ifdef CONFIG_USB_MUSB_HDRC_HCD
207 case MUSB_HOST:
208 otg_set_host(&musb->xceiv, musb->xceiv.host);
209 break;
210#endif
211#ifdef CONFIG_USB_GADGET_MUSB_HDRC
212 case MUSB_PERIPHERAL:
213 otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
214 break;
215#endif
216#ifdef CONFIG_USB_MUSB_OTG
217 case MUSB_OTG:
218 break;
219#endif
220 default:
221 return -EINVAL;
222 }
223 return 0; 200 return 0;
224} 201}
225 202
@@ -231,6 +208,16 @@ int __init musb_platform_init(struct musb *musb)
231 omap_cfg_reg(AE5_2430_USB0HS_STP); 208 omap_cfg_reg(AE5_2430_USB0HS_STP);
232#endif 209#endif
233 210
211 /* We require some kind of external transceiver, hooked
212 * up through ULPI. TWL4030-family PMICs include one,
213 * which needs a driver, drivers aren't always needed.
214 */
215 musb->xceiv = otg_get_transceiver();
216 if (!musb->xceiv) {
217 pr_err("HS USB OTG: no transceiver configured\n");
218 return -ENODEV;
219 }
220
234 musb_platform_resume(musb); 221 musb_platform_resume(musb);
235 222
236 l = omap_readl(OTG_SYSCONFIG); 223 l = omap_readl(OTG_SYSCONFIG);
@@ -240,7 +227,12 @@ int __init musb_platform_init(struct musb *musb)
240 l &= ~AUTOIDLE; /* disable auto idle */ 227 l &= ~AUTOIDLE; /* disable auto idle */
241 l &= ~NOIDLE; /* remove possible noidle */ 228 l &= ~NOIDLE; /* remove possible noidle */
242 l |= SMARTIDLE; /* enable smart idle */ 229 l |= SMARTIDLE; /* enable smart idle */
243 l |= AUTOIDLE; /* enable auto idle */ 230 /*
231 * MUSB AUTOIDLE don't work in 3430.
232 * Workaround by Richard Woodruff/TI
233 */
234 if (!cpu_is_omap3430())
235 l |= AUTOIDLE; /* enable auto idle */
244 omap_writel(l, OTG_SYSCONFIG); 236 omap_writel(l, OTG_SYSCONFIG);
245 237
246 l = omap_readl(OTG_INTERFSEL); 238 l = omap_readl(OTG_INTERFSEL);
@@ -257,9 +249,6 @@ int __init musb_platform_init(struct musb *musb)
257 249
258 if (is_host_enabled(musb)) 250 if (is_host_enabled(musb))
259 musb->board_set_vbus = omap_set_vbus; 251 musb->board_set_vbus = omap_set_vbus;
260 if (is_peripheral_enabled(musb))
261 musb->xceiv.set_power = omap_set_power;
262 musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
263 252
264 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 253 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
265 254
@@ -282,8 +271,7 @@ int musb_platform_suspend(struct musb *musb)
282 l |= ENABLEWAKEUP; /* enable wakeup */ 271 l |= ENABLEWAKEUP; /* enable wakeup */
283 omap_writel(l, OTG_SYSCONFIG); 272 omap_writel(l, OTG_SYSCONFIG);
284 273
285 if (musb->xceiv.set_suspend) 274 otg_set_suspend(musb->xceiv, 1);
286 musb->xceiv.set_suspend(&musb->xceiv, 1);
287 275
288 if (musb->set_clock) 276 if (musb->set_clock)
289 musb->set_clock(musb->clock, 0); 277 musb->set_clock(musb->clock, 0);
@@ -300,8 +288,7 @@ static int musb_platform_resume(struct musb *musb)
300 if (!musb->clock) 288 if (!musb->clock)
301 return 0; 289 return 0;
302 290
303 if (musb->xceiv.set_suspend) 291 otg_set_suspend(musb->xceiv, 0);
304 musb->xceiv.set_suspend(&musb->xceiv, 0);
305 292
306 if (musb->set_clock) 293 if (musb->set_clock)
307 musb->set_clock(musb->clock, 1); 294 musb->set_clock(musb->clock, 1);
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index 4ac1477d3569..88b587c703e9 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -259,6 +259,8 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
259 tusb_fifo_read_unaligned(fifo, buf, len); 259 tusb_fifo_read_unaligned(fifo, buf, len);
260} 260}
261 261
262static struct musb *the_musb;
263
262#ifdef CONFIG_USB_GADGET_MUSB_HDRC 264#ifdef CONFIG_USB_GADGET_MUSB_HDRC
263 265
264/* This is used by gadget drivers, and OTG transceiver logic, allowing 266/* This is used by gadget drivers, and OTG transceiver logic, allowing
@@ -269,7 +271,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
269 */ 271 */
270static int tusb_draw_power(struct otg_transceiver *x, unsigned mA) 272static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
271{ 273{
272 struct musb *musb = container_of(x, struct musb, xceiv); 274 struct musb *musb = the_musb;
273 void __iomem *tbase = musb->ctrl_base; 275 void __iomem *tbase = musb->ctrl_base;
274 u32 reg; 276 u32 reg;
275 277
@@ -419,7 +421,7 @@ static void musb_do_idle(unsigned long _musb)
419 421
420 spin_lock_irqsave(&musb->lock, flags); 422 spin_lock_irqsave(&musb->lock, flags);
421 423
422 switch (musb->xceiv.state) { 424 switch (musb->xceiv->state) {
423 case OTG_STATE_A_WAIT_BCON: 425 case OTG_STATE_A_WAIT_BCON:
424 if ((musb->a_wait_bcon != 0) 426 if ((musb->a_wait_bcon != 0)
425 && (musb->idle_timeout == 0 427 && (musb->idle_timeout == 0
@@ -483,7 +485,7 @@ void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
483 485
484 /* Never idle if active, or when VBUS timeout is not set as host */ 486 /* Never idle if active, or when VBUS timeout is not set as host */
485 if (musb->is_active || ((musb->a_wait_bcon == 0) 487 if (musb->is_active || ((musb->a_wait_bcon == 0)
486 && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) { 488 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
487 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 489 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
488 del_timer(&musb_idle_timer); 490 del_timer(&musb_idle_timer);
489 last_timer = jiffies; 491 last_timer = jiffies;
@@ -532,8 +534,8 @@ static void tusb_source_power(struct musb *musb, int is_on)
532 if (musb->set_clock) 534 if (musb->set_clock)
533 musb->set_clock(musb->clock, 1); 535 musb->set_clock(musb->clock, 1);
534 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 536 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
535 musb->xceiv.default_a = 1; 537 musb->xceiv->default_a = 1;
536 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE; 538 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
537 devctl |= MUSB_DEVCTL_SESSION; 539 devctl |= MUSB_DEVCTL_SESSION;
538 540
539 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 541 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
@@ -546,24 +548,24 @@ static void tusb_source_power(struct musb *musb, int is_on)
546 /* If ID pin is grounded, we want to be a_idle */ 548 /* If ID pin is grounded, we want to be a_idle */
547 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 549 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
548 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 550 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
549 switch (musb->xceiv.state) { 551 switch (musb->xceiv->state) {
550 case OTG_STATE_A_WAIT_VRISE: 552 case OTG_STATE_A_WAIT_VRISE:
551 case OTG_STATE_A_WAIT_BCON: 553 case OTG_STATE_A_WAIT_BCON:
552 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL; 554 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
553 break; 555 break;
554 case OTG_STATE_A_WAIT_VFALL: 556 case OTG_STATE_A_WAIT_VFALL:
555 musb->xceiv.state = OTG_STATE_A_IDLE; 557 musb->xceiv->state = OTG_STATE_A_IDLE;
556 break; 558 break;
557 default: 559 default:
558 musb->xceiv.state = OTG_STATE_A_IDLE; 560 musb->xceiv->state = OTG_STATE_A_IDLE;
559 } 561 }
560 musb->is_active = 0; 562 musb->is_active = 0;
561 musb->xceiv.default_a = 1; 563 musb->xceiv->default_a = 1;
562 MUSB_HST_MODE(musb); 564 MUSB_HST_MODE(musb);
563 } else { 565 } else {
564 musb->is_active = 0; 566 musb->is_active = 0;
565 musb->xceiv.default_a = 0; 567 musb->xceiv->default_a = 0;
566 musb->xceiv.state = OTG_STATE_B_IDLE; 568 musb->xceiv->state = OTG_STATE_B_IDLE;
567 MUSB_DEV_MODE(musb); 569 MUSB_DEV_MODE(musb);
568 } 570 }
569 571
@@ -674,7 +676,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
674 else 676 else
675 default_a = is_host_enabled(musb); 677 default_a = is_host_enabled(musb);
676 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 678 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
677 musb->xceiv.default_a = default_a; 679 musb->xceiv->default_a = default_a;
678 tusb_source_power(musb, default_a); 680 tusb_source_power(musb, default_a);
679 681
680 /* Don't allow idling immediately */ 682 /* Don't allow idling immediately */
@@ -686,7 +688,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
686 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 688 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
687 689
688 /* B-dev state machine: no vbus ~= disconnect */ 690 /* B-dev state machine: no vbus ~= disconnect */
689 if ((is_otg_enabled(musb) && !musb->xceiv.default_a) 691 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
690 || !is_host_enabled(musb)) { 692 || !is_host_enabled(musb)) {
691#ifdef CONFIG_USB_MUSB_HDRC_HCD 693#ifdef CONFIG_USB_MUSB_HDRC_HCD
692 /* ? musb_root_disconnect(musb); */ 694 /* ? musb_root_disconnect(musb); */
@@ -701,9 +703,9 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
701 703
702 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 704 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
703 DBG(1, "Forcing disconnect (no interrupt)\n"); 705 DBG(1, "Forcing disconnect (no interrupt)\n");
704 if (musb->xceiv.state != OTG_STATE_B_IDLE) { 706 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
705 /* INTR_DISCONNECT can hide... */ 707 /* INTR_DISCONNECT can hide... */
706 musb->xceiv.state = OTG_STATE_B_IDLE; 708 musb->xceiv->state = OTG_STATE_B_IDLE;
707 musb->int_usb |= MUSB_INTR_DISCONNECT; 709 musb->int_usb |= MUSB_INTR_DISCONNECT;
708 } 710 }
709 musb->is_active = 0; 711 musb->is_active = 0;
@@ -717,7 +719,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
717 DBG(2, "vbus change, %s, otg %03x\n", 719 DBG(2, "vbus change, %s, otg %03x\n",
718 otg_state_string(musb), otg_stat); 720 otg_state_string(musb), otg_stat);
719 721
720 switch (musb->xceiv.state) { 722 switch (musb->xceiv->state) {
721 case OTG_STATE_A_IDLE: 723 case OTG_STATE_A_IDLE:
722 DBG(2, "Got SRP, turning on VBUS\n"); 724 DBG(2, "Got SRP, turning on VBUS\n");
723 musb_set_vbus(musb, 1); 725 musb_set_vbus(musb, 1);
@@ -765,7 +767,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
765 767
766 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat); 768 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
767 769
768 switch (musb->xceiv.state) { 770 switch (musb->xceiv->state) {
769 case OTG_STATE_A_WAIT_VRISE: 771 case OTG_STATE_A_WAIT_VRISE:
770 /* VBUS has probably been valid for a while now, 772 /* VBUS has probably been valid for a while now,
771 * but may well have bounced out of range a bit 773 * but may well have bounced out of range a bit
@@ -777,7 +779,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
777 DBG(2, "devctl %02x\n", devctl); 779 DBG(2, "devctl %02x\n", devctl);
778 break; 780 break;
779 } 781 }
780 musb->xceiv.state = OTG_STATE_A_WAIT_BCON; 782 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
781 musb->is_active = 0; 783 musb->is_active = 0;
782 idle_timeout = jiffies 784 idle_timeout = jiffies
783 + msecs_to_jiffies(musb->a_wait_bcon); 785 + msecs_to_jiffies(musb->a_wait_bcon);
@@ -1093,9 +1095,14 @@ int __init musb_platform_init(struct musb *musb)
1093{ 1095{
1094 struct platform_device *pdev; 1096 struct platform_device *pdev;
1095 struct resource *mem; 1097 struct resource *mem;
1096 void __iomem *sync; 1098 void __iomem *sync = NULL;
1097 int ret; 1099 int ret;
1098 1100
1101 usb_nop_xceiv_register();
1102 musb->xceiv = otg_get_transceiver();
1103 if (!musb->xceiv)
1104 return -ENODEV;
1105
1099 pdev = to_platform_device(musb->controller); 1106 pdev = to_platform_device(musb->controller);
1100 1107
1101 /* dma address for async dma */ 1108 /* dma address for async dma */
@@ -1106,14 +1113,16 @@ int __init musb_platform_init(struct musb *musb)
1106 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1113 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1107 if (!mem) { 1114 if (!mem) {
1108 pr_debug("no sync dma resource?\n"); 1115 pr_debug("no sync dma resource?\n");
1109 return -ENODEV; 1116 ret = -ENODEV;
1117 goto done;
1110 } 1118 }
1111 musb->sync = mem->start; 1119 musb->sync = mem->start;
1112 1120
1113 sync = ioremap(mem->start, mem->end - mem->start + 1); 1121 sync = ioremap(mem->start, mem->end - mem->start + 1);
1114 if (!sync) { 1122 if (!sync) {
1115 pr_debug("ioremap for sync failed\n"); 1123 pr_debug("ioremap for sync failed\n");
1116 return -ENOMEM; 1124 ret = -ENOMEM;
1125 goto done;
1117 } 1126 }
1118 musb->sync_va = sync; 1127 musb->sync_va = sync;
1119 1128
@@ -1126,28 +1135,37 @@ int __init musb_platform_init(struct musb *musb)
1126 if (ret) { 1135 if (ret) {
1127 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1136 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1128 ret); 1137 ret);
1129 return -ENODEV; 1138 goto done;
1130 } 1139 }
1131 musb->isr = tusb_interrupt; 1140 musb->isr = tusb_interrupt;
1132 1141
1133 if (is_host_enabled(musb)) 1142 if (is_host_enabled(musb))
1134 musb->board_set_vbus = tusb_source_power; 1143 musb->board_set_vbus = tusb_source_power;
1135 if (is_peripheral_enabled(musb)) 1144 if (is_peripheral_enabled(musb)) {
1136 musb->xceiv.set_power = tusb_draw_power; 1145 musb->xceiv->set_power = tusb_draw_power;
1146 the_musb = musb;
1147 }
1137 1148
1138 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 1149 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1139 1150
1151done:
1152 if (ret < 0) {
1153 if (sync)
1154 iounmap(sync);
1155 usb_nop_xceiv_unregister();
1156 }
1140 return ret; 1157 return ret;
1141} 1158}
1142 1159
1143int musb_platform_exit(struct musb *musb) 1160int musb_platform_exit(struct musb *musb)
1144{ 1161{
1145 del_timer_sync(&musb_idle_timer); 1162 del_timer_sync(&musb_idle_timer);
1163 the_musb = NULL;
1146 1164
1147 if (musb->board_set_power) 1165 if (musb->board_set_power)
1148 musb->board_set_power(0); 1166 musb->board_set_power(0);
1149 1167
1150 iounmap(musb->sync_va); 1168 iounmap(musb->sync_va);
1151 1169 usb_nop_xceiv_unregister();
1152 return 0; 1170 return 0;
1153} 1171}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 08:27:00 -0500