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-rw-r--r--drivers/usb/musb/tusb6010.h169
1 files changed, 0 insertions, 169 deletions
diff --git a/drivers/usb/musb/tusb6010.h b/drivers/usb/musb/tusb6010.h
index db6dad0750ae..ab8c96286ce6 100644
--- a/drivers/usb/musb/tusb6010.h
+++ b/drivers/usb/musb/tusb6010.h
@@ -230,173 +230,4 @@ extern u8 tusb_get_revision(struct musb *musb);
230#define TUSB_REV_30 0x30 230#define TUSB_REV_30 0x30
231#define TUSB_REV_31 0x31 231#define TUSB_REV_31 0x31
232 232
233/*----------------------------------------------------------------------------*/
234
235#ifdef CONFIG_USB_TUSB6010
236
237/* configuration parameters specific to this silicon */
238
239/* Number of Tx endpoints. Legal values are 1 - 16 (this value includes EP0) */
240#define MUSB_C_NUM_EPT 16
241
242/* Number of Rx endpoints. Legal values are 1 - 16 (this value includes EP0) */
243#define MUSB_C_NUM_EPR 16
244
245/* Endpoint 1 to 15 direction types. C_EP1_DEF is defined if either Tx endpoint
246 * 1 or Rx endpoint 1 are used.
247 */
248#define MUSB_C_EP1_DEF
249
250/* C_EP1_TX_DEF is defined if Tx endpoint 1 is used */
251#define MUSB_C_EP1_TX_DEF
252
253/* C_EP1_RX_DEF is defined if Rx endpoint 1 is used */
254#define MUSB_C_EP1_RX_DEF
255
256/* C_EP1_TOR_DEF is defined if Tx endpoint 1 and Rx endpoint 1 share a FIFO */
257/* #define C_EP1_TOR_DEF */
258
259/* C_EP1_TAR_DEF is defined if both Tx endpoint 1 and Rx endpoint 1 are used
260 * and do not share a FIFO.
261 */
262#define MUSB_C_EP1_TAR_DEF
263
264/* Similarly for all other used endpoints */
265#define MUSB_C_EP2_DEF
266#define MUSB_C_EP2_TX_DEF
267#define MUSB_C_EP2_RX_DEF
268#define MUSB_C_EP2_TAR_DEF
269#define MUSB_C_EP3_DEF
270#define MUSB_C_EP3_TX_DEF
271#define MUSB_C_EP3_RX_DEF
272#define MUSB_C_EP3_TAR_DEF
273#define MUSB_C_EP4_DEF
274#define MUSB_C_EP4_TX_DEF
275#define MUSB_C_EP4_RX_DEF
276#define MUSB_C_EP4_TAR_DEF
277
278/* Endpoint 1 to 15 FIFO address bits. Legal values are 3 to 13 - corresponding
279 * to FIFO sizes of 8 to 8192 bytes. If an Tx endpoint shares a FIFO with an Rx
280 * endpoint then the Rx FIFO size must be the same as the Tx FIFO size. All
281 * endpoints 1 to 15 must be defined, unused endpoints should be set to 2.
282 */
283#define MUSB_C_EP1T_BITS 5
284#define MUSB_C_EP1R_BITS 5
285#define MUSB_C_EP2T_BITS 5
286#define MUSB_C_EP2R_BITS 5
287#define MUSB_C_EP3T_BITS 3
288#define MUSB_C_EP3R_BITS 3
289#define MUSB_C_EP4T_BITS 3
290#define MUSB_C_EP4R_BITS 3
291
292#define MUSB_C_EP5T_BITS 2
293#define MUSB_C_EP5R_BITS 2
294#define MUSB_C_EP6T_BITS 2
295#define MUSB_C_EP6R_BITS 2
296#define MUSB_C_EP7T_BITS 2
297#define MUSB_C_EP7R_BITS 2
298#define MUSB_C_EP8T_BITS 2
299#define MUSB_C_EP8R_BITS 2
300#define MUSB_C_EP9T_BITS 2
301#define MUSB_C_EP9R_BITS 2
302#define MUSB_C_EP10T_BITS 2
303#define MUSB_C_EP10R_BITS 2
304#define MUSB_C_EP11T_BITS 2
305#define MUSB_C_EP11R_BITS 2
306#define MUSB_C_EP12T_BITS 2
307#define MUSB_C_EP12R_BITS 2
308#define MUSB_C_EP13T_BITS 2
309#define MUSB_C_EP13R_BITS 2
310#define MUSB_C_EP14T_BITS 2
311#define MUSB_C_EP14R_BITS 2
312#define MUSB_C_EP15T_BITS 2
313#define MUSB_C_EP15R_BITS 2
314
315/* Define the following constant if the USB2.0 Transceiver Macrocell data width
316 * is 16-bits.
317 */
318/* #define C_UTM_16 */
319
320/* Define this constant if the CPU uses big-endian byte ordering. */
321/* #define C_BIGEND */
322
323/* Define the following constant if any Tx endpoint is required to support
324 * multiple bulk packets.
325 */
326/* #define C_MP_TX */
327
328/* Define the following constant if any Rx endpoint is required to support
329 * multiple bulk packets.
330 */
331/* #define C_MP_RX */
332
333/* Define the following constant if any Tx endpoint is required to support high
334 * bandwidth ISO.
335 */
336/* #define C_HB_TX */
337
338/* Define the following constant if any Rx endpoint is required to support high
339 * bandwidth ISO.
340 */
341/* #define C_HB_RX */
342
343/* Define the following constant if software connect/disconnect control is
344 * required.
345 */
346#define MUSB_C_SOFT_CON
347
348/* Define the following constant if Vendor Control Registers are required. */
349/* #define C_VEND_REG */
350
351/* Vendor control register widths. */
352#define MUSB_C_VCTL_BITS 4
353#define MUSB_C_VSTAT_BITS 8
354
355/* Define the following constant to include a DMA controller. */
356/* #define C_DMA */
357
358/* Define the following constant if 2 or more DMA channels are required. */
359/* #define C_DMA2 */
360
361/* Define the following constant if 3 or more DMA channels are required. */
362/* #define C_DMA3 */
363
364/* Define the following constant if 4 or more DMA channels are required. */
365/* #define C_DMA4 */
366
367/* Define the following constant if 5 or more DMA channels are required. */
368/* #define C_DMA5 */
369
370/* Define the following constant if 6 or more DMA channels are required. */
371/* #define C_DMA6 */
372
373/* Define the following constant if 7 or more DMA channels are required. */
374/* #define C_DMA7 */
375
376/* Define the following constant if 8 or more DMA channels are required. */
377/* #define C_DMA8 */
378
379/* Enable Dynamic FIFO Sizing */
380#define MUSB_C_DYNFIFO_DEF
381
382/* Derived constants. The following constants are derived from the previous
383 * configuration constants
384 */
385
386/* Total number of endpoints. Legal values are 2 - 16. This must be equal to
387 * the larger of C_NUM_EPT, C_NUM_EPR
388 */
389/* #define MUSB_C_NUM_EPS 5 */
390
391/* C_EPMAX_BITS is equal to the largest endpoint FIFO word address bits */
392#define MUSB_C_EPMAX_BITS 11
393
394/* C_RAM_BITS is the number of address bits required to address the RAM (32-bit
395 * addresses). It is defined as log2 of the sum of 2** of all the endpoint FIFO
396 * dword address bits (rounded up).
397 */
398#define MUSB_C_RAM_BITS 12
399
400#endif /* CONFIG_USB_TUSB6010 */
401
402#endif /* __TUSB6010_H__ */ 233#endif /* __TUSB6010_H__ */