diff options
Diffstat (limited to 'drivers/usb/musb/musbhsdma.c')
| -rw-r--r-- | drivers/usb/musb/musbhsdma.c | 84 |
1 files changed, 14 insertions, 70 deletions
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c index 8c734ef2c1ed..8662e9e159c3 100644 --- a/drivers/usb/musb/musbhsdma.c +++ b/drivers/usb/musb/musbhsdma.c | |||
| @@ -34,58 +34,7 @@ | |||
| 34 | #include <linux/interrupt.h> | 34 | #include <linux/interrupt.h> |
| 35 | #include <linux/platform_device.h> | 35 | #include <linux/platform_device.h> |
| 36 | #include "musb_core.h" | 36 | #include "musb_core.h" |
| 37 | 37 | #include "musbhsdma.h" | |
| 38 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) | ||
| 39 | #include "omap2430.h" | ||
| 40 | #endif | ||
| 41 | |||
| 42 | #define MUSB_HSDMA_BASE 0x200 | ||
| 43 | #define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0) | ||
| 44 | #define MUSB_HSDMA_CONTROL 0x4 | ||
| 45 | #define MUSB_HSDMA_ADDRESS 0x8 | ||
| 46 | #define MUSB_HSDMA_COUNT 0xc | ||
| 47 | |||
| 48 | #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \ | ||
| 49 | (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset) | ||
| 50 | |||
| 51 | /* control register (16-bit): */ | ||
| 52 | #define MUSB_HSDMA_ENABLE_SHIFT 0 | ||
| 53 | #define MUSB_HSDMA_TRANSMIT_SHIFT 1 | ||
| 54 | #define MUSB_HSDMA_MODE1_SHIFT 2 | ||
| 55 | #define MUSB_HSDMA_IRQENABLE_SHIFT 3 | ||
| 56 | #define MUSB_HSDMA_ENDPOINT_SHIFT 4 | ||
| 57 | #define MUSB_HSDMA_BUSERROR_SHIFT 8 | ||
| 58 | #define MUSB_HSDMA_BURSTMODE_SHIFT 9 | ||
| 59 | #define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT) | ||
| 60 | #define MUSB_HSDMA_BURSTMODE_UNSPEC 0 | ||
| 61 | #define MUSB_HSDMA_BURSTMODE_INCR4 1 | ||
| 62 | #define MUSB_HSDMA_BURSTMODE_INCR8 2 | ||
| 63 | #define MUSB_HSDMA_BURSTMODE_INCR16 3 | ||
| 64 | |||
| 65 | #define MUSB_HSDMA_CHANNELS 8 | ||
| 66 | |||
| 67 | struct musb_dma_controller; | ||
| 68 | |||
| 69 | struct musb_dma_channel { | ||
| 70 | struct dma_channel channel; | ||
| 71 | struct musb_dma_controller *controller; | ||
| 72 | u32 start_addr; | ||
| 73 | u32 len; | ||
| 74 | u16 max_packet_sz; | ||
| 75 | u8 idx; | ||
| 76 | u8 epnum; | ||
| 77 | u8 transmit; | ||
| 78 | }; | ||
| 79 | |||
| 80 | struct musb_dma_controller { | ||
| 81 | struct dma_controller controller; | ||
| 82 | struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS]; | ||
| 83 | void *private_data; | ||
| 84 | void __iomem *base; | ||
| 85 | u8 channel_count; | ||
| 86 | u8 used_channels; | ||
| 87 | u8 irq; | ||
| 88 | }; | ||
| 89 | 38 | ||
| 90 | static int dma_controller_start(struct dma_controller *c) | 39 | static int dma_controller_start(struct dma_controller *c) |
| 91 | { | 40 | { |
| @@ -203,12 +152,8 @@ static void configure_channel(struct dma_channel *channel, | |||
| 203 | : 0); | 152 | : 0); |
| 204 | 153 | ||
| 205 | /* address/count */ | 154 | /* address/count */ |
| 206 | musb_writel(mbase, | 155 | musb_write_hsdma_addr(mbase, bchannel, dma_addr); |
| 207 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), | 156 | musb_write_hsdma_count(mbase, bchannel, len); |
| 208 | dma_addr); | ||
| 209 | musb_writel(mbase, | ||
| 210 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), | ||
| 211 | len); | ||
| 212 | 157 | ||
| 213 | /* control (this should start things) */ | 158 | /* control (this should start things) */ |
| 214 | musb_writew(mbase, | 159 | musb_writew(mbase, |
| @@ -279,13 +224,8 @@ static int dma_channel_abort(struct dma_channel *channel) | |||
| 279 | musb_writew(mbase, | 224 | musb_writew(mbase, |
| 280 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), | 225 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), |
| 281 | 0); | 226 | 0); |
| 282 | musb_writel(mbase, | 227 | musb_write_hsdma_addr(mbase, bchannel, 0); |
| 283 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), | 228 | musb_write_hsdma_count(mbase, bchannel, 0); |
| 284 | 0); | ||
| 285 | musb_writel(mbase, | ||
| 286 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), | ||
| 287 | 0); | ||
| 288 | |||
| 289 | channel->status = MUSB_DMA_STATUS_FREE; | 229 | channel->status = MUSB_DMA_STATUS_FREE; |
| 290 | } | 230 | } |
| 291 | 231 | ||
| @@ -333,10 +273,8 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data) | |||
| 333 | } else { | 273 | } else { |
| 334 | u8 devctl; | 274 | u8 devctl; |
| 335 | 275 | ||
| 336 | addr = musb_readl(mbase, | 276 | addr = musb_read_hsdma_addr(mbase, |
| 337 | MUSB_HSDMA_CHANNEL_OFFSET( | 277 | bchannel); |
| 338 | bchannel, | ||
| 339 | MUSB_HSDMA_ADDRESS)); | ||
| 340 | channel->actual_len = addr | 278 | channel->actual_len = addr |
| 341 | - musb_channel->start_addr; | 279 | - musb_channel->start_addr; |
| 342 | 280 | ||
| @@ -375,6 +313,12 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data) | |||
| 375 | } | 313 | } |
| 376 | } | 314 | } |
| 377 | } | 315 | } |
| 316 | |||
| 317 | #ifdef CONFIG_BLACKFIN | ||
| 318 | /* Clear DMA interrup flags */ | ||
| 319 | musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); | ||
| 320 | #endif | ||
| 321 | |||
| 378 | retval = IRQ_HANDLED; | 322 | retval = IRQ_HANDLED; |
| 379 | done: | 323 | done: |
| 380 | spin_unlock_irqrestore(&musb->lock, flags); | 324 | spin_unlock_irqrestore(&musb->lock, flags); |
| @@ -424,7 +368,7 @@ dma_controller_create(struct musb *musb, void __iomem *base) | |||
| 424 | controller->controller.channel_abort = dma_channel_abort; | 368 | controller->controller.channel_abort = dma_channel_abort; |
| 425 | 369 | ||
| 426 | if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, | 370 | if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, |
| 427 | musb->controller->bus_id, &controller->controller)) { | 371 | dev_name(musb->controller), &controller->controller)) { |
| 428 | dev_err(dev, "request_irq %d failed!\n", irq); | 372 | dev_err(dev, "request_irq %d failed!\n", irq); |
| 429 | dma_controller_destroy(&controller->controller); | 373 | dma_controller_destroy(&controller->controller); |
| 430 | 374 | ||
