diff options
Diffstat (limited to 'drivers/usb/musb/musb_host.c')
| -rw-r--r-- | drivers/usb/musb/musb_host.c | 45 |
1 files changed, 21 insertions, 24 deletions
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index cc64462d4c4e..99fa61234876 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c | |||
| @@ -112,18 +112,21 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) | |||
| 112 | { | 112 | { |
| 113 | void __iomem *epio = ep->regs; | 113 | void __iomem *epio = ep->regs; |
| 114 | u16 csr; | 114 | u16 csr; |
| 115 | u16 lastcsr = 0; | ||
| 115 | int retries = 1000; | 116 | int retries = 1000; |
| 116 | 117 | ||
| 117 | csr = musb_readw(epio, MUSB_TXCSR); | 118 | csr = musb_readw(epio, MUSB_TXCSR); |
| 118 | while (csr & MUSB_TXCSR_FIFONOTEMPTY) { | 119 | while (csr & MUSB_TXCSR_FIFONOTEMPTY) { |
| 119 | DBG(5, "Host TX FIFONOTEMPTY csr: %02x\n", csr); | 120 | if (csr != lastcsr) |
| 121 | DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); | ||
| 122 | lastcsr = csr; | ||
| 120 | csr |= MUSB_TXCSR_FLUSHFIFO; | 123 | csr |= MUSB_TXCSR_FLUSHFIFO; |
| 121 | musb_writew(epio, MUSB_TXCSR, csr); | 124 | musb_writew(epio, MUSB_TXCSR, csr); |
| 122 | csr = musb_readw(epio, MUSB_TXCSR); | 125 | csr = musb_readw(epio, MUSB_TXCSR); |
| 123 | if (retries-- < 1) { | 126 | if (WARN(retries-- < 1, |
| 124 | ERR("Could not flush host TX fifo: csr: %04x\n", csr); | 127 | "Could not flush host TX%d fifo: csr: %04x\n", |
| 128 | ep->epnum, csr)) | ||
| 125 | return; | 129 | return; |
| 126 | } | ||
| 127 | mdelay(1); | 130 | mdelay(1); |
| 128 | } | 131 | } |
| 129 | } | 132 | } |
| @@ -268,7 +271,7 @@ __musb_giveback(struct musb *musb, struct urb *urb, int status) | |||
| 268 | __releases(musb->lock) | 271 | __releases(musb->lock) |
| 269 | __acquires(musb->lock) | 272 | __acquires(musb->lock) |
| 270 | { | 273 | { |
| 271 | DBG(({ int level; switch (urb->status) { | 274 | DBG(({ int level; switch (status) { |
| 272 | case 0: | 275 | case 0: |
| 273 | level = 4; | 276 | level = 4; |
| 274 | break; | 277 | break; |
| @@ -283,8 +286,8 @@ __acquires(musb->lock) | |||
| 283 | level = 2; | 286 | level = 2; |
| 284 | break; | 287 | break; |
| 285 | }; level; }), | 288 | }; level; }), |
| 286 | "complete %p (%d), dev%d ep%d%s, %d/%d\n", | 289 | "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", |
| 287 | urb, urb->status, | 290 | urb, urb->complete, status, |
| 288 | usb_pipedevice(urb->pipe), | 291 | usb_pipedevice(urb->pipe), |
| 289 | usb_pipeendpoint(urb->pipe), | 292 | usb_pipeendpoint(urb->pipe), |
| 290 | usb_pipein(urb->pipe) ? "in" : "out", | 293 | usb_pipein(urb->pipe) ? "in" : "out", |
| @@ -593,12 +596,10 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) | |||
| 593 | 596 | ||
| 594 | /* target addr and (for multipoint) hub addr/port */ | 597 | /* target addr and (for multipoint) hub addr/port */ |
| 595 | if (musb->is_multipoint) { | 598 | if (musb->is_multipoint) { |
| 596 | musb_writeb(ep->target_regs, MUSB_RXFUNCADDR, | 599 | musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); |
| 597 | qh->addr_reg); | 600 | musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); |
| 598 | musb_writeb(ep->target_regs, MUSB_RXHUBADDR, | 601 | musb_write_rxhubport(ep->target_regs, qh->h_port_reg); |
| 599 | qh->h_addr_reg); | 602 | |
| 600 | musb_writeb(ep->target_regs, MUSB_RXHUBPORT, | ||
| 601 | qh->h_port_reg); | ||
| 602 | } else | 603 | } else |
| 603 | musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); | 604 | musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); |
| 604 | 605 | ||
| @@ -712,15 +713,9 @@ static void musb_ep_program(struct musb *musb, u8 epnum, | |||
| 712 | 713 | ||
| 713 | /* target addr and (for multipoint) hub addr/port */ | 714 | /* target addr and (for multipoint) hub addr/port */ |
| 714 | if (musb->is_multipoint) { | 715 | if (musb->is_multipoint) { |
| 715 | musb_writeb(mbase, | 716 | musb_write_txfunaddr(mbase, epnum, qh->addr_reg); |
| 716 | MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR), | 717 | musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); |
| 717 | qh->addr_reg); | 718 | musb_write_txhubport(mbase, epnum, qh->h_port_reg); |
| 718 | musb_writeb(mbase, | ||
| 719 | MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR), | ||
| 720 | qh->h_addr_reg); | ||
| 721 | musb_writeb(mbase, | ||
| 722 | MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT), | ||
| 723 | qh->h_port_reg); | ||
| 724 | /* FIXME if !epnum, do the same for RX ... */ | 719 | /* FIXME if !epnum, do the same for RX ... */ |
| 725 | } else | 720 | } else |
| 726 | musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); | 721 | musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); |
| @@ -988,8 +983,10 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) | |||
| 988 | if (fifo_count) { | 983 | if (fifo_count) { |
| 989 | fifo_dest = (u8 *) (urb->transfer_buffer | 984 | fifo_dest = (u8 *) (urb->transfer_buffer |
| 990 | + urb->actual_length); | 985 | + urb->actual_length); |
| 991 | DBG(3, "Sending %d bytes to %p\n", | 986 | DBG(3, "Sending %d byte%s to ep0 fifo %p\n", |
| 992 | fifo_count, fifo_dest); | 987 | fifo_count, |
| 988 | (fifo_count == 1) ? "" : "s", | ||
| 989 | fifo_dest); | ||
| 993 | musb_write_fifo(hw_ep, fifo_count, fifo_dest); | 990 | musb_write_fifo(hw_ep, fifo_count, fifo_dest); |
| 994 | 991 | ||
| 995 | urb->actual_length += fifo_count; | 992 | urb->actual_length += fifo_count; |
