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-rw-r--r--drivers/usb/musb/musb_gadget.c2033
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diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
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index 000000000000..b3773f13ee0a
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1/*
2 * MUSB OTG driver peripheral support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/list.h>
37#include <linux/timer.h>
38#include <linux/module.h>
39#include <linux/smp.h>
40#include <linux/spinlock.h>
41#include <linux/delay.h>
42#include <linux/moduleparam.h>
43#include <linux/stat.h>
44#include <linux/dma-mapping.h>
45
46#include "musb_core.h"
47
48
49/* MUSB PERIPHERAL status 3-mar-2006:
50 *
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
52 * Minor glitches:
53 *
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
58 * clearing SENDSTALL?
59 *
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
63 * required.
64 *
65 * - TX/IN
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
71 *
72 * - RX/OUT
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
78 *
79 * - ISO not tested ... might work, but only weakly isochronous
80 *
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
84 *
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
89 */
90
91/* ----------------------------------------------------------------------- */
92
93/*
94 * Immediately complete a request.
95 *
96 * @param request the request to complete
97 * @param status the status to complete the request with
98 * Context: controller locked, IRQs blocked.
99 */
100void musb_g_giveback(
101 struct musb_ep *ep,
102 struct usb_request *request,
103 int status)
104__releases(ep->musb->lock)
105__acquires(ep->musb->lock)
106{
107 struct musb_request *req;
108 struct musb *musb;
109 int busy = ep->busy;
110
111 req = to_musb_request(request);
112
113 list_del(&request->list);
114 if (req->request.status == -EINPROGRESS)
115 req->request.status = status;
116 musb = req->musb;
117
118 ep->busy = 1;
119 spin_unlock(&musb->lock);
120 if (is_dma_capable()) {
121 if (req->mapped) {
122 dma_unmap_single(musb->controller,
123 req->request.dma,
124 req->request.length,
125 req->tx
126 ? DMA_TO_DEVICE
127 : DMA_FROM_DEVICE);
128 req->request.dma = DMA_ADDR_INVALID;
129 req->mapped = 0;
130 } else if (req->request.dma != DMA_ADDR_INVALID)
131 dma_sync_single_for_cpu(musb->controller,
132 req->request.dma,
133 req->request.length,
134 req->tx
135 ? DMA_TO_DEVICE
136 : DMA_FROM_DEVICE);
137 }
138 if (request->status == 0)
139 DBG(5, "%s done request %p, %d/%d\n",
140 ep->end_point.name, request,
141 req->request.actual, req->request.length);
142 else
143 DBG(2, "%s request %p, %d/%d fault %d\n",
144 ep->end_point.name, request,
145 req->request.actual, req->request.length,
146 request->status);
147 req->request.complete(&req->ep->end_point, &req->request);
148 spin_lock(&musb->lock);
149 ep->busy = busy;
150}
151
152/* ----------------------------------------------------------------------- */
153
154/*
155 * Abort requests queued to an endpoint using the status. Synchronous.
156 * caller locked controller and blocked irqs, and selected this ep.
157 */
158static void nuke(struct musb_ep *ep, const int status)
159{
160 struct musb_request *req = NULL;
161 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
162
163 ep->busy = 1;
164
165 if (is_dma_capable() && ep->dma) {
166 struct dma_controller *c = ep->musb->dma_controller;
167 int value;
168 if (ep->is_in) {
169 musb_writew(epio, MUSB_TXCSR,
170 0 | MUSB_TXCSR_FLUSHFIFO);
171 musb_writew(epio, MUSB_TXCSR,
172 0 | MUSB_TXCSR_FLUSHFIFO);
173 } else {
174 musb_writew(epio, MUSB_RXCSR,
175 0 | MUSB_RXCSR_FLUSHFIFO);
176 musb_writew(epio, MUSB_RXCSR,
177 0 | MUSB_RXCSR_FLUSHFIFO);
178 }
179
180 value = c->channel_abort(ep->dma);
181 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
182 c->channel_release(ep->dma);
183 ep->dma = NULL;
184 }
185
186 while (!list_empty(&(ep->req_list))) {
187 req = container_of(ep->req_list.next, struct musb_request,
188 request.list);
189 musb_g_giveback(ep, &req->request, status);
190 }
191}
192
193/* ----------------------------------------------------------------------- */
194
195/* Data transfers - pure PIO, pure DMA, or mixed mode */
196
197/*
198 * This assumes the separate CPPI engine is responding to DMA requests
199 * from the usb core ... sequenced a bit differently from mentor dma.
200 */
201
202static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
203{
204 if (can_bulk_split(musb, ep->type))
205 return ep->hw_ep->max_packet_sz_tx;
206 else
207 return ep->packet_sz;
208}
209
210
211#ifdef CONFIG_USB_INVENTRA_DMA
212
213/* Peripheral tx (IN) using Mentor DMA works as follows:
214 Only mode 0 is used for transfers <= wPktSize,
215 mode 1 is used for larger transfers,
216
217 One of the following happens:
218 - Host sends IN token which causes an endpoint interrupt
219 -> TxAvail
220 -> if DMA is currently busy, exit.
221 -> if queue is non-empty, txstate().
222
223 - Request is queued by the gadget driver.
224 -> if queue was previously empty, txstate()
225
226 txstate()
227 -> start
228 /\ -> setup DMA
229 | (data is transferred to the FIFO, then sent out when
230 | IN token(s) are recd from Host.
231 | -> DMA interrupt on completion
232 | calls TxAvail.
233 | -> stop DMA, ~DmaEenab,
234 | -> set TxPktRdy for last short pkt or zlp
235 | -> Complete Request
236 | -> Continue next request (call txstate)
237 |___________________________________|
238
239 * Non-Mentor DMA engines can of course work differently, such as by
240 * upleveling from irq-per-packet to irq-per-buffer.
241 */
242
243#endif
244
245/*
246 * An endpoint is transmitting data. This can be called either from
247 * the IRQ routine or from ep.queue() to kickstart a request on an
248 * endpoint.
249 *
250 * Context: controller locked, IRQs blocked, endpoint selected
251 */
252static void txstate(struct musb *musb, struct musb_request *req)
253{
254 u8 epnum = req->epnum;
255 struct musb_ep *musb_ep;
256 void __iomem *epio = musb->endpoints[epnum].regs;
257 struct usb_request *request;
258 u16 fifo_count = 0, csr;
259 int use_dma = 0;
260
261 musb_ep = req->ep;
262
263 /* we shouldn't get here while DMA is active ... but we do ... */
264 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
265 DBG(4, "dma pending...\n");
266 return;
267 }
268
269 /* read TXCSR before */
270 csr = musb_readw(epio, MUSB_TXCSR);
271
272 request = &req->request;
273 fifo_count = min(max_ep_writesize(musb, musb_ep),
274 (int)(request->length - request->actual));
275
276 if (csr & MUSB_TXCSR_TXPKTRDY) {
277 DBG(5, "%s old packet still ready , txcsr %03x\n",
278 musb_ep->end_point.name, csr);
279 return;
280 }
281
282 if (csr & MUSB_TXCSR_P_SENDSTALL) {
283 DBG(5, "%s stalling, txcsr %03x\n",
284 musb_ep->end_point.name, csr);
285 return;
286 }
287
288 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
289 epnum, musb_ep->packet_sz, fifo_count,
290 csr);
291
292#ifndef CONFIG_MUSB_PIO_ONLY
293 if (is_dma_capable() && musb_ep->dma) {
294 struct dma_controller *c = musb->dma_controller;
295
296 use_dma = (request->dma != DMA_ADDR_INVALID);
297
298 /* MUSB_TXCSR_P_ISO is still set correctly */
299
300#ifdef CONFIG_USB_INVENTRA_DMA
301 {
302 size_t request_size;
303
304 /* setup DMA, then program endpoint CSR */
305 request_size = min(request->length,
306 musb_ep->dma->max_len);
307 if (request_size <= musb_ep->packet_sz)
308 musb_ep->dma->desired_mode = 0;
309 else
310 musb_ep->dma->desired_mode = 1;
311
312 use_dma = use_dma && c->channel_program(
313 musb_ep->dma, musb_ep->packet_sz,
314 musb_ep->dma->desired_mode,
315 request->dma, request_size);
316 if (use_dma) {
317 if (musb_ep->dma->desired_mode == 0) {
318 /* ASSERT: DMAENAB is clear */
319 csr &= ~(MUSB_TXCSR_AUTOSET |
320 MUSB_TXCSR_DMAMODE);
321 csr |= (MUSB_TXCSR_DMAENAB |
322 MUSB_TXCSR_MODE);
323 /* against programming guide */
324 } else
325 csr |= (MUSB_TXCSR_AUTOSET
326 | MUSB_TXCSR_DMAENAB
327 | MUSB_TXCSR_DMAMODE
328 | MUSB_TXCSR_MODE);
329
330 csr &= ~MUSB_TXCSR_P_UNDERRUN;
331 musb_writew(epio, MUSB_TXCSR, csr);
332 }
333 }
334
335#elif defined(CONFIG_USB_TI_CPPI_DMA)
336 /* program endpoint CSR first, then setup DMA */
337 csr &= ~(MUSB_TXCSR_AUTOSET
338 | MUSB_TXCSR_DMAMODE
339 | MUSB_TXCSR_P_UNDERRUN
340 | MUSB_TXCSR_TXPKTRDY);
341 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_DMAENAB;
342 musb_writew(epio, MUSB_TXCSR,
343 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
344 | csr);
345
346 /* ensure writebuffer is empty */
347 csr = musb_readw(epio, MUSB_TXCSR);
348
349 /* NOTE host side sets DMAENAB later than this; both are
350 * OK since the transfer dma glue (between CPPI and Mentor
351 * fifos) just tells CPPI it could start. Data only moves
352 * to the USB TX fifo when both fifos are ready.
353 */
354
355 /* "mode" is irrelevant here; handle terminating ZLPs like
356 * PIO does, since the hardware RNDIS mode seems unreliable
357 * except for the last-packet-is-already-short case.
358 */
359 use_dma = use_dma && c->channel_program(
360 musb_ep->dma, musb_ep->packet_sz,
361 0,
362 request->dma,
363 request->length);
364 if (!use_dma) {
365 c->channel_release(musb_ep->dma);
366 musb_ep->dma = NULL;
367 /* ASSERT: DMAENAB clear */
368 csr &= ~(MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
369 /* invariant: prequest->buf is non-null */
370 }
371#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
372 use_dma = use_dma && c->channel_program(
373 musb_ep->dma, musb_ep->packet_sz,
374 request->zero,
375 request->dma,
376 request->length);
377#endif
378 }
379#endif
380
381 if (!use_dma) {
382 musb_write_fifo(musb_ep->hw_ep, fifo_count,
383 (u8 *) (request->buf + request->actual));
384 request->actual += fifo_count;
385 csr |= MUSB_TXCSR_TXPKTRDY;
386 csr &= ~MUSB_TXCSR_P_UNDERRUN;
387 musb_writew(epio, MUSB_TXCSR, csr);
388 }
389
390 /* host may already have the data when this message shows... */
391 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
392 musb_ep->end_point.name, use_dma ? "dma" : "pio",
393 request->actual, request->length,
394 musb_readw(epio, MUSB_TXCSR),
395 fifo_count,
396 musb_readw(epio, MUSB_TXMAXP));
397}
398
399/*
400 * FIFO state update (e.g. data ready).
401 * Called from IRQ, with controller locked.
402 */
403void musb_g_tx(struct musb *musb, u8 epnum)
404{
405 u16 csr;
406 struct usb_request *request;
407 u8 __iomem *mbase = musb->mregs;
408 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
409 void __iomem *epio = musb->endpoints[epnum].regs;
410 struct dma_channel *dma;
411
412 musb_ep_select(mbase, epnum);
413 request = next_request(musb_ep);
414
415 csr = musb_readw(epio, MUSB_TXCSR);
416 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
417
418 dma = is_dma_capable() ? musb_ep->dma : NULL;
419 do {
420 /* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX
421 * probably rates reporting as a host error
422 */
423 if (csr & MUSB_TXCSR_P_SENTSTALL) {
424 csr |= MUSB_TXCSR_P_WZC_BITS;
425 csr &= ~MUSB_TXCSR_P_SENTSTALL;
426 musb_writew(epio, MUSB_TXCSR, csr);
427 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
428 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
429 musb->dma_controller->channel_abort(dma);
430 }
431
432 if (request)
433 musb_g_giveback(musb_ep, request, -EPIPE);
434
435 break;
436 }
437
438 if (csr & MUSB_TXCSR_P_UNDERRUN) {
439 /* we NAKed, no big deal ... little reason to care */
440 csr |= MUSB_TXCSR_P_WZC_BITS;
441 csr &= ~(MUSB_TXCSR_P_UNDERRUN
442 | MUSB_TXCSR_TXPKTRDY);
443 musb_writew(epio, MUSB_TXCSR, csr);
444 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
445 }
446
447 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
448 /* SHOULD NOT HAPPEN ... has with cppi though, after
449 * changing SENDSTALL (and other cases); harmless?
450 */
451 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
452 break;
453 }
454
455 if (request) {
456 u8 is_dma = 0;
457
458 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
459 is_dma = 1;
460 csr |= MUSB_TXCSR_P_WZC_BITS;
461 csr &= ~(MUSB_TXCSR_DMAENAB
462 | MUSB_TXCSR_P_UNDERRUN
463 | MUSB_TXCSR_TXPKTRDY);
464 musb_writew(epio, MUSB_TXCSR, csr);
465 /* ensure writebuffer is empty */
466 csr = musb_readw(epio, MUSB_TXCSR);
467 request->actual += musb_ep->dma->actual_len;
468 DBG(4, "TXCSR%d %04x, dma off, "
469 "len %zu, req %p\n",
470 epnum, csr,
471 musb_ep->dma->actual_len,
472 request);
473 }
474
475 if (is_dma || request->actual == request->length) {
476
477 /* First, maybe a terminating short packet.
478 * Some DMA engines might handle this by
479 * themselves.
480 */
481 if ((request->zero
482 && request->length
483 && (request->length
484 % musb_ep->packet_sz)
485 == 0)
486#ifdef CONFIG_USB_INVENTRA_DMA
487 || (is_dma &&
488 ((!dma->desired_mode) ||
489 (request->actual &
490 (musb_ep->packet_sz - 1))))
491#endif
492 ) {
493 /* on dma completion, fifo may not
494 * be available yet ...
495 */
496 if (csr & MUSB_TXCSR_TXPKTRDY)
497 break;
498
499 DBG(4, "sending zero pkt\n");
500 musb_writew(epio, MUSB_TXCSR,
501 MUSB_TXCSR_MODE
502 | MUSB_TXCSR_TXPKTRDY);
503 request->zero = 0;
504 }
505
506 /* ... or if not, then complete it */
507 musb_g_giveback(musb_ep, request, 0);
508
509 /* kickstart next transfer if appropriate;
510 * the packet that just completed might not
511 * be transmitted for hours or days.
512 * REVISIT for double buffering...
513 * FIXME revisit for stalls too...
514 */
515 musb_ep_select(mbase, epnum);
516 csr = musb_readw(epio, MUSB_TXCSR);
517 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
518 break;
519 request = musb_ep->desc
520 ? next_request(musb_ep)
521 : NULL;
522 if (!request) {
523 DBG(4, "%s idle now\n",
524 musb_ep->end_point.name);
525 break;
526 }
527 }
528
529 txstate(musb, to_musb_request(request));
530 }
531
532 } while (0);
533}
534
535/* ------------------------------------------------------------ */
536
537#ifdef CONFIG_USB_INVENTRA_DMA
538
539/* Peripheral rx (OUT) using Mentor DMA works as follows:
540 - Only mode 0 is used.
541
542 - Request is queued by the gadget class driver.
543 -> if queue was previously empty, rxstate()
544
545 - Host sends OUT token which causes an endpoint interrupt
546 /\ -> RxReady
547 | -> if request queued, call rxstate
548 | /\ -> setup DMA
549 | | -> DMA interrupt on completion
550 | | -> RxReady
551 | | -> stop DMA
552 | | -> ack the read
553 | | -> if data recd = max expected
554 | | by the request, or host
555 | | sent a short packet,
556 | | complete the request,
557 | | and start the next one.
558 | |_____________________________________|
559 | else just wait for the host
560 | to send the next OUT token.
561 |__________________________________________________|
562
563 * Non-Mentor DMA engines can of course work differently.
564 */
565
566#endif
567
568/*
569 * Context: controller locked, IRQs blocked, endpoint selected
570 */
571static void rxstate(struct musb *musb, struct musb_request *req)
572{
573 u16 csr = 0;
574 const u8 epnum = req->epnum;
575 struct usb_request *request = &req->request;
576 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
577 void __iomem *epio = musb->endpoints[epnum].regs;
578 u16 fifo_count = 0;
579 u16 len = musb_ep->packet_sz;
580
581 csr = musb_readw(epio, MUSB_RXCSR);
582
583 if (is_cppi_enabled() && musb_ep->dma) {
584 struct dma_controller *c = musb->dma_controller;
585 struct dma_channel *channel = musb_ep->dma;
586
587 /* NOTE: CPPI won't actually stop advancing the DMA
588 * queue after short packet transfers, so this is almost
589 * always going to run as IRQ-per-packet DMA so that
590 * faults will be handled correctly.
591 */
592 if (c->channel_program(channel,
593 musb_ep->packet_sz,
594 !request->short_not_ok,
595 request->dma + request->actual,
596 request->length - request->actual)) {
597
598 /* make sure that if an rxpkt arrived after the irq,
599 * the cppi engine will be ready to take it as soon
600 * as DMA is enabled
601 */
602 csr &= ~(MUSB_RXCSR_AUTOCLEAR
603 | MUSB_RXCSR_DMAMODE);
604 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
605 musb_writew(epio, MUSB_RXCSR, csr);
606 return;
607 }
608 }
609
610 if (csr & MUSB_RXCSR_RXPKTRDY) {
611 len = musb_readw(epio, MUSB_RXCOUNT);
612 if (request->actual < request->length) {
613#ifdef CONFIG_USB_INVENTRA_DMA
614 if (is_dma_capable() && musb_ep->dma) {
615 struct dma_controller *c;
616 struct dma_channel *channel;
617 int use_dma = 0;
618
619 c = musb->dma_controller;
620 channel = musb_ep->dma;
621
622 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
623 * mode 0 only. So we do not get endpoint interrupts due to DMA
624 * completion. We only get interrupts from DMA controller.
625 *
626 * We could operate in DMA mode 1 if we knew the size of the tranfer
627 * in advance. For mass storage class, request->length = what the host
628 * sends, so that'd work. But for pretty much everything else,
629 * request->length is routinely more than what the host sends. For
630 * most these gadgets, end of is signified either by a short packet,
631 * or filling the last byte of the buffer. (Sending extra data in
632 * that last pckate should trigger an overflow fault.) But in mode 1,
633 * we don't get DMA completion interrrupt for short packets.
634 *
635 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
636 * to get endpoint interrupt on every DMA req, but that didn't seem
637 * to work reliably.
638 *
639 * REVISIT an updated g_file_storage can set req->short_not_ok, which
640 * then becomes usable as a runtime "use mode 1" hint...
641 */
642
643 csr |= MUSB_RXCSR_DMAENAB;
644#ifdef USE_MODE1
645 csr |= MUSB_RXCSR_AUTOCLEAR;
646 /* csr |= MUSB_RXCSR_DMAMODE; */
647
648 /* this special sequence (enabling and then
649 * disabling MUSB_RXCSR_DMAMODE) is required
650 * to get DMAReq to activate
651 */
652 musb_writew(epio, MUSB_RXCSR,
653 csr | MUSB_RXCSR_DMAMODE);
654#endif
655 musb_writew(epio, MUSB_RXCSR, csr);
656
657 if (request->actual < request->length) {
658 int transfer_size = 0;
659#ifdef USE_MODE1
660 transfer_size = min(request->length,
661 channel->max_len);
662#else
663 transfer_size = len;
664#endif
665 if (transfer_size <= musb_ep->packet_sz)
666 musb_ep->dma->desired_mode = 0;
667 else
668 musb_ep->dma->desired_mode = 1;
669
670 use_dma = c->channel_program(
671 channel,
672 musb_ep->packet_sz,
673 channel->desired_mode,
674 request->dma
675 + request->actual,
676 transfer_size);
677 }
678
679 if (use_dma)
680 return;
681 }
682#endif /* Mentor's DMA */
683
684 fifo_count = request->length - request->actual;
685 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
686 musb_ep->end_point.name,
687 len, fifo_count,
688 musb_ep->packet_sz);
689
690 fifo_count = min(len, fifo_count);
691
692#ifdef CONFIG_USB_TUSB_OMAP_DMA
693 if (tusb_dma_omap() && musb_ep->dma) {
694 struct dma_controller *c = musb->dma_controller;
695 struct dma_channel *channel = musb_ep->dma;
696 u32 dma_addr = request->dma + request->actual;
697 int ret;
698
699 ret = c->channel_program(channel,
700 musb_ep->packet_sz,
701 channel->desired_mode,
702 dma_addr,
703 fifo_count);
704 if (ret)
705 return;
706 }
707#endif
708
709 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
710 (request->buf + request->actual));
711 request->actual += fifo_count;
712
713 /* REVISIT if we left anything in the fifo, flush
714 * it and report -EOVERFLOW
715 */
716
717 /* ack the read! */
718 csr |= MUSB_RXCSR_P_WZC_BITS;
719 csr &= ~MUSB_RXCSR_RXPKTRDY;
720 musb_writew(epio, MUSB_RXCSR, csr);
721 }
722 }
723
724 /* reach the end or short packet detected */
725 if (request->actual == request->length || len < musb_ep->packet_sz)
726 musb_g_giveback(musb_ep, request, 0);
727}
728
729/*
730 * Data ready for a request; called from IRQ
731 */
732void musb_g_rx(struct musb *musb, u8 epnum)
733{
734 u16 csr;
735 struct usb_request *request;
736 void __iomem *mbase = musb->mregs;
737 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
738 void __iomem *epio = musb->endpoints[epnum].regs;
739 struct dma_channel *dma;
740
741 musb_ep_select(mbase, epnum);
742
743 request = next_request(musb_ep);
744
745 csr = musb_readw(epio, MUSB_RXCSR);
746 dma = is_dma_capable() ? musb_ep->dma : NULL;
747
748 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
749 csr, dma ? " (dma)" : "", request);
750
751 if (csr & MUSB_RXCSR_P_SENTSTALL) {
752 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
753 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
754 (void) musb->dma_controller->channel_abort(dma);
755 request->actual += musb_ep->dma->actual_len;
756 }
757
758 csr |= MUSB_RXCSR_P_WZC_BITS;
759 csr &= ~MUSB_RXCSR_P_SENTSTALL;
760 musb_writew(epio, MUSB_RXCSR, csr);
761
762 if (request)
763 musb_g_giveback(musb_ep, request, -EPIPE);
764 goto done;
765 }
766
767 if (csr & MUSB_RXCSR_P_OVERRUN) {
768 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
769 csr &= ~MUSB_RXCSR_P_OVERRUN;
770 musb_writew(epio, MUSB_RXCSR, csr);
771
772 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
773 if (request && request->status == -EINPROGRESS)
774 request->status = -EOVERFLOW;
775 }
776 if (csr & MUSB_RXCSR_INCOMPRX) {
777 /* REVISIT not necessarily an error */
778 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
779 }
780
781 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
782 /* "should not happen"; likely RXPKTRDY pending for DMA */
783 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
784 "%s busy, csr %04x\n",
785 musb_ep->end_point.name, csr);
786 goto done;
787 }
788
789 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
790 csr &= ~(MUSB_RXCSR_AUTOCLEAR
791 | MUSB_RXCSR_DMAENAB
792 | MUSB_RXCSR_DMAMODE);
793 musb_writew(epio, MUSB_RXCSR,
794 MUSB_RXCSR_P_WZC_BITS | csr);
795
796 request->actual += musb_ep->dma->actual_len;
797
798 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
799 epnum, csr,
800 musb_readw(epio, MUSB_RXCSR),
801 musb_ep->dma->actual_len, request);
802
803#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
804 /* Autoclear doesn't clear RxPktRdy for short packets */
805 if ((dma->desired_mode == 0)
806 || (dma->actual_len
807 & (musb_ep->packet_sz - 1))) {
808 /* ack the read! */
809 csr &= ~MUSB_RXCSR_RXPKTRDY;
810 musb_writew(epio, MUSB_RXCSR, csr);
811 }
812
813 /* incomplete, and not short? wait for next IN packet */
814 if ((request->actual < request->length)
815 && (musb_ep->dma->actual_len
816 == musb_ep->packet_sz))
817 goto done;
818#endif
819 musb_g_giveback(musb_ep, request, 0);
820
821 request = next_request(musb_ep);
822 if (!request)
823 goto done;
824
825 /* don't start more i/o till the stall clears */
826 musb_ep_select(mbase, epnum);
827 csr = musb_readw(epio, MUSB_RXCSR);
828 if (csr & MUSB_RXCSR_P_SENDSTALL)
829 goto done;
830 }
831
832
833 /* analyze request if the ep is hot */
834 if (request)
835 rxstate(musb, to_musb_request(request));
836 else
837 DBG(3, "packet waiting for %s%s request\n",
838 musb_ep->desc ? "" : "inactive ",
839 musb_ep->end_point.name);
840
841done:
842 return;
843}
844
845/* ------------------------------------------------------------ */
846
847static int musb_gadget_enable(struct usb_ep *ep,
848 const struct usb_endpoint_descriptor *desc)
849{
850 unsigned long flags;
851 struct musb_ep *musb_ep;
852 struct musb_hw_ep *hw_ep;
853 void __iomem *regs;
854 struct musb *musb;
855 void __iomem *mbase;
856 u8 epnum;
857 u16 csr;
858 unsigned tmp;
859 int status = -EINVAL;
860
861 if (!ep || !desc)
862 return -EINVAL;
863
864 musb_ep = to_musb_ep(ep);
865 hw_ep = musb_ep->hw_ep;
866 regs = hw_ep->regs;
867 musb = musb_ep->musb;
868 mbase = musb->mregs;
869 epnum = musb_ep->current_epnum;
870
871 spin_lock_irqsave(&musb->lock, flags);
872
873 if (musb_ep->desc) {
874 status = -EBUSY;
875 goto fail;
876 }
877 musb_ep->type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
878
879 /* check direction and (later) maxpacket size against endpoint */
880 if ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != epnum)
881 goto fail;
882
883 /* REVISIT this rules out high bandwidth periodic transfers */
884 tmp = le16_to_cpu(desc->wMaxPacketSize);
885 if (tmp & ~0x07ff)
886 goto fail;
887 musb_ep->packet_sz = tmp;
888
889 /* enable the interrupts for the endpoint, set the endpoint
890 * packet size (or fail), set the mode, clear the fifo
891 */
892 musb_ep_select(mbase, epnum);
893 if (desc->bEndpointAddress & USB_DIR_IN) {
894 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
895
896 if (hw_ep->is_shared_fifo)
897 musb_ep->is_in = 1;
898 if (!musb_ep->is_in)
899 goto fail;
900 if (tmp > hw_ep->max_packet_sz_tx)
901 goto fail;
902
903 int_txe |= (1 << epnum);
904 musb_writew(mbase, MUSB_INTRTXE, int_txe);
905
906 /* REVISIT if can_bulk_split(), use by updating "tmp";
907 * likewise high bandwidth periodic tx
908 */
909 musb_writew(regs, MUSB_TXMAXP, tmp);
910
911 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
912 if (musb_readw(regs, MUSB_TXCSR)
913 & MUSB_TXCSR_FIFONOTEMPTY)
914 csr |= MUSB_TXCSR_FLUSHFIFO;
915 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
916 csr |= MUSB_TXCSR_P_ISO;
917
918 /* set twice in case of double buffering */
919 musb_writew(regs, MUSB_TXCSR, csr);
920 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
921 musb_writew(regs, MUSB_TXCSR, csr);
922
923 } else {
924 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
925
926 if (hw_ep->is_shared_fifo)
927 musb_ep->is_in = 0;
928 if (musb_ep->is_in)
929 goto fail;
930 if (tmp > hw_ep->max_packet_sz_rx)
931 goto fail;
932
933 int_rxe |= (1 << epnum);
934 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
935
936 /* REVISIT if can_bulk_combine() use by updating "tmp"
937 * likewise high bandwidth periodic rx
938 */
939 musb_writew(regs, MUSB_RXMAXP, tmp);
940
941 /* force shared fifo to OUT-only mode */
942 if (hw_ep->is_shared_fifo) {
943 csr = musb_readw(regs, MUSB_TXCSR);
944 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
945 musb_writew(regs, MUSB_TXCSR, csr);
946 }
947
948 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
949 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
950 csr |= MUSB_RXCSR_P_ISO;
951 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
952 csr |= MUSB_RXCSR_DISNYET;
953
954 /* set twice in case of double buffering */
955 musb_writew(regs, MUSB_RXCSR, csr);
956 musb_writew(regs, MUSB_RXCSR, csr);
957 }
958
959 /* NOTE: all the I/O code _should_ work fine without DMA, in case
960 * for some reason you run out of channels here.
961 */
962 if (is_dma_capable() && musb->dma_controller) {
963 struct dma_controller *c = musb->dma_controller;
964
965 musb_ep->dma = c->channel_alloc(c, hw_ep,
966 (desc->bEndpointAddress & USB_DIR_IN));
967 } else
968 musb_ep->dma = NULL;
969
970 musb_ep->desc = desc;
971 musb_ep->busy = 0;
972 status = 0;
973
974 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
975 musb_driver_name, musb_ep->end_point.name,
976 ({ char *s; switch (musb_ep->type) {
977 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
978 case USB_ENDPOINT_XFER_INT: s = "int"; break;
979 default: s = "iso"; break;
980 }; s; }),
981 musb_ep->is_in ? "IN" : "OUT",
982 musb_ep->dma ? "dma, " : "",
983 musb_ep->packet_sz);
984
985 schedule_work(&musb->irq_work);
986
987fail:
988 spin_unlock_irqrestore(&musb->lock, flags);
989 return status;
990}
991
992/*
993 * Disable an endpoint flushing all requests queued.
994 */
995static int musb_gadget_disable(struct usb_ep *ep)
996{
997 unsigned long flags;
998 struct musb *musb;
999 u8 epnum;
1000 struct musb_ep *musb_ep;
1001 void __iomem *epio;
1002 int status = 0;
1003
1004 musb_ep = to_musb_ep(ep);
1005 musb = musb_ep->musb;
1006 epnum = musb_ep->current_epnum;
1007 epio = musb->endpoints[epnum].regs;
1008
1009 spin_lock_irqsave(&musb->lock, flags);
1010 musb_ep_select(musb->mregs, epnum);
1011
1012 /* zero the endpoint sizes */
1013 if (musb_ep->is_in) {
1014 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1015 int_txe &= ~(1 << epnum);
1016 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1017 musb_writew(epio, MUSB_TXMAXP, 0);
1018 } else {
1019 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1020 int_rxe &= ~(1 << epnum);
1021 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1022 musb_writew(epio, MUSB_RXMAXP, 0);
1023 }
1024
1025 musb_ep->desc = NULL;
1026
1027 /* abort all pending DMA and requests */
1028 nuke(musb_ep, -ESHUTDOWN);
1029
1030 schedule_work(&musb->irq_work);
1031
1032 spin_unlock_irqrestore(&(musb->lock), flags);
1033
1034 DBG(2, "%s\n", musb_ep->end_point.name);
1035
1036 return status;
1037}
1038
1039/*
1040 * Allocate a request for an endpoint.
1041 * Reused by ep0 code.
1042 */
1043struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1044{
1045 struct musb_ep *musb_ep = to_musb_ep(ep);
1046 struct musb_request *request = NULL;
1047
1048 request = kzalloc(sizeof *request, gfp_flags);
1049 if (request) {
1050 INIT_LIST_HEAD(&request->request.list);
1051 request->request.dma = DMA_ADDR_INVALID;
1052 request->epnum = musb_ep->current_epnum;
1053 request->ep = musb_ep;
1054 }
1055
1056 return &request->request;
1057}
1058
1059/*
1060 * Free a request
1061 * Reused by ep0 code.
1062 */
1063void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1064{
1065 kfree(to_musb_request(req));
1066}
1067
1068static LIST_HEAD(buffers);
1069
1070struct free_record {
1071 struct list_head list;
1072 struct device *dev;
1073 unsigned bytes;
1074 dma_addr_t dma;
1075};
1076
1077/*
1078 * Context: controller locked, IRQs blocked.
1079 */
1080static void musb_ep_restart(struct musb *musb, struct musb_request *req)
1081{
1082 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1083 req->tx ? "TX/IN" : "RX/OUT",
1084 &req->request, req->request.length, req->epnum);
1085
1086 musb_ep_select(musb->mregs, req->epnum);
1087 if (req->tx)
1088 txstate(musb, req);
1089 else
1090 rxstate(musb, req);
1091}
1092
1093static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1094 gfp_t gfp_flags)
1095{
1096 struct musb_ep *musb_ep;
1097 struct musb_request *request;
1098 struct musb *musb;
1099 int status = 0;
1100 unsigned long lockflags;
1101
1102 if (!ep || !req)
1103 return -EINVAL;
1104 if (!req->buf)
1105 return -ENODATA;
1106
1107 musb_ep = to_musb_ep(ep);
1108 musb = musb_ep->musb;
1109
1110 request = to_musb_request(req);
1111 request->musb = musb;
1112
1113 if (request->ep != musb_ep)
1114 return -EINVAL;
1115
1116 DBG(4, "<== to %s request=%p\n", ep->name, req);
1117
1118 /* request is mine now... */
1119 request->request.actual = 0;
1120 request->request.status = -EINPROGRESS;
1121 request->epnum = musb_ep->current_epnum;
1122 request->tx = musb_ep->is_in;
1123
1124 if (is_dma_capable() && musb_ep->dma) {
1125 if (request->request.dma == DMA_ADDR_INVALID) {
1126 request->request.dma = dma_map_single(
1127 musb->controller,
1128 request->request.buf,
1129 request->request.length,
1130 request->tx
1131 ? DMA_TO_DEVICE
1132 : DMA_FROM_DEVICE);
1133 request->mapped = 1;
1134 } else {
1135 dma_sync_single_for_device(musb->controller,
1136 request->request.dma,
1137 request->request.length,
1138 request->tx
1139 ? DMA_TO_DEVICE
1140 : DMA_FROM_DEVICE);
1141 request->mapped = 0;
1142 }
1143 } else if (!req->buf) {
1144 return -ENODATA;
1145 } else
1146 request->mapped = 0;
1147
1148 spin_lock_irqsave(&musb->lock, lockflags);
1149
1150 /* don't queue if the ep is down */
1151 if (!musb_ep->desc) {
1152 DBG(4, "req %p queued to %s while ep %s\n",
1153 req, ep->name, "disabled");
1154 status = -ESHUTDOWN;
1155 goto cleanup;
1156 }
1157
1158 /* add request to the list */
1159 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1160
1161 /* it this is the head of the queue, start i/o ... */
1162 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1163 musb_ep_restart(musb, request);
1164
1165cleanup:
1166 spin_unlock_irqrestore(&musb->lock, lockflags);
1167 return status;
1168}
1169
1170static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1171{
1172 struct musb_ep *musb_ep = to_musb_ep(ep);
1173 struct usb_request *r;
1174 unsigned long flags;
1175 int status = 0;
1176 struct musb *musb = musb_ep->musb;
1177
1178 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1179 return -EINVAL;
1180
1181 spin_lock_irqsave(&musb->lock, flags);
1182
1183 list_for_each_entry(r, &musb_ep->req_list, list) {
1184 if (r == request)
1185 break;
1186 }
1187 if (r != request) {
1188 DBG(3, "request %p not queued to %s\n", request, ep->name);
1189 status = -EINVAL;
1190 goto done;
1191 }
1192
1193 /* if the hardware doesn't have the request, easy ... */
1194 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1195 musb_g_giveback(musb_ep, request, -ECONNRESET);
1196
1197 /* ... else abort the dma transfer ... */
1198 else if (is_dma_capable() && musb_ep->dma) {
1199 struct dma_controller *c = musb->dma_controller;
1200
1201 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1202 if (c->channel_abort)
1203 status = c->channel_abort(musb_ep->dma);
1204 else
1205 status = -EBUSY;
1206 if (status == 0)
1207 musb_g_giveback(musb_ep, request, -ECONNRESET);
1208 } else {
1209 /* NOTE: by sticking to easily tested hardware/driver states,
1210 * we leave counting of in-flight packets imprecise.
1211 */
1212 musb_g_giveback(musb_ep, request, -ECONNRESET);
1213 }
1214
1215done:
1216 spin_unlock_irqrestore(&musb->lock, flags);
1217 return status;
1218}
1219
1220/*
1221 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1222 * data but will queue requests.
1223 *
1224 * exported to ep0 code
1225 */
1226int musb_gadget_set_halt(struct usb_ep *ep, int value)
1227{
1228 struct musb_ep *musb_ep = to_musb_ep(ep);
1229 u8 epnum = musb_ep->current_epnum;
1230 struct musb *musb = musb_ep->musb;
1231 void __iomem *epio = musb->endpoints[epnum].regs;
1232 void __iomem *mbase;
1233 unsigned long flags;
1234 u16 csr;
1235 struct musb_request *request = NULL;
1236 int status = 0;
1237
1238 if (!ep)
1239 return -EINVAL;
1240 mbase = musb->mregs;
1241
1242 spin_lock_irqsave(&musb->lock, flags);
1243
1244 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1245 status = -EINVAL;
1246 goto done;
1247 }
1248
1249 musb_ep_select(mbase, epnum);
1250
1251 /* cannot portably stall with non-empty FIFO */
1252 request = to_musb_request(next_request(musb_ep));
1253 if (value && musb_ep->is_in) {
1254 csr = musb_readw(epio, MUSB_TXCSR);
1255 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1256 DBG(3, "%s fifo busy, cannot halt\n", ep->name);
1257 spin_unlock_irqrestore(&musb->lock, flags);
1258 return -EAGAIN;
1259 }
1260
1261 }
1262
1263 /* set/clear the stall and toggle bits */
1264 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1265 if (musb_ep->is_in) {
1266 csr = musb_readw(epio, MUSB_TXCSR);
1267 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
1268 csr |= MUSB_TXCSR_FLUSHFIFO;
1269 csr |= MUSB_TXCSR_P_WZC_BITS
1270 | MUSB_TXCSR_CLRDATATOG;
1271 if (value)
1272 csr |= MUSB_TXCSR_P_SENDSTALL;
1273 else
1274 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1275 | MUSB_TXCSR_P_SENTSTALL);
1276 csr &= ~MUSB_TXCSR_TXPKTRDY;
1277 musb_writew(epio, MUSB_TXCSR, csr);
1278 } else {
1279 csr = musb_readw(epio, MUSB_RXCSR);
1280 csr |= MUSB_RXCSR_P_WZC_BITS
1281 | MUSB_RXCSR_FLUSHFIFO
1282 | MUSB_RXCSR_CLRDATATOG;
1283 if (value)
1284 csr |= MUSB_RXCSR_P_SENDSTALL;
1285 else
1286 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1287 | MUSB_RXCSR_P_SENTSTALL);
1288 musb_writew(epio, MUSB_RXCSR, csr);
1289 }
1290
1291done:
1292
1293 /* maybe start the first request in the queue */
1294 if (!musb_ep->busy && !value && request) {
1295 DBG(3, "restarting the request\n");
1296 musb_ep_restart(musb, request);
1297 }
1298
1299 spin_unlock_irqrestore(&musb->lock, flags);
1300 return status;
1301}
1302
1303static int musb_gadget_fifo_status(struct usb_ep *ep)
1304{
1305 struct musb_ep *musb_ep = to_musb_ep(ep);
1306 void __iomem *epio = musb_ep->hw_ep->regs;
1307 int retval = -EINVAL;
1308
1309 if (musb_ep->desc && !musb_ep->is_in) {
1310 struct musb *musb = musb_ep->musb;
1311 int epnum = musb_ep->current_epnum;
1312 void __iomem *mbase = musb->mregs;
1313 unsigned long flags;
1314
1315 spin_lock_irqsave(&musb->lock, flags);
1316
1317 musb_ep_select(mbase, epnum);
1318 /* FIXME return zero unless RXPKTRDY is set */
1319 retval = musb_readw(epio, MUSB_RXCOUNT);
1320
1321 spin_unlock_irqrestore(&musb->lock, flags);
1322 }
1323 return retval;
1324}
1325
1326static void musb_gadget_fifo_flush(struct usb_ep *ep)
1327{
1328 struct musb_ep *musb_ep = to_musb_ep(ep);
1329 struct musb *musb = musb_ep->musb;
1330 u8 epnum = musb_ep->current_epnum;
1331 void __iomem *epio = musb->endpoints[epnum].regs;
1332 void __iomem *mbase;
1333 unsigned long flags;
1334 u16 csr, int_txe;
1335
1336 mbase = musb->mregs;
1337
1338 spin_lock_irqsave(&musb->lock, flags);
1339 musb_ep_select(mbase, (u8) epnum);
1340
1341 /* disable interrupts */
1342 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1343 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1344
1345 if (musb_ep->is_in) {
1346 csr = musb_readw(epio, MUSB_TXCSR);
1347 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1348 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1349 musb_writew(epio, MUSB_TXCSR, csr);
1350 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1351 musb_writew(epio, MUSB_TXCSR, csr);
1352 }
1353 } else {
1354 csr = musb_readw(epio, MUSB_RXCSR);
1355 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1356 musb_writew(epio, MUSB_RXCSR, csr);
1357 musb_writew(epio, MUSB_RXCSR, csr);
1358 }
1359
1360 /* re-enable interrupt */
1361 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1362 spin_unlock_irqrestore(&musb->lock, flags);
1363}
1364
1365static const struct usb_ep_ops musb_ep_ops = {
1366 .enable = musb_gadget_enable,
1367 .disable = musb_gadget_disable,
1368 .alloc_request = musb_alloc_request,
1369 .free_request = musb_free_request,
1370 .queue = musb_gadget_queue,
1371 .dequeue = musb_gadget_dequeue,
1372 .set_halt = musb_gadget_set_halt,
1373 .fifo_status = musb_gadget_fifo_status,
1374 .fifo_flush = musb_gadget_fifo_flush
1375};
1376
1377/* ----------------------------------------------------------------------- */
1378
1379static int musb_gadget_get_frame(struct usb_gadget *gadget)
1380{
1381 struct musb *musb = gadget_to_musb(gadget);
1382
1383 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1384}
1385
1386static int musb_gadget_wakeup(struct usb_gadget *gadget)
1387{
1388 struct musb *musb = gadget_to_musb(gadget);
1389 void __iomem *mregs = musb->mregs;
1390 unsigned long flags;
1391 int status = -EINVAL;
1392 u8 power, devctl;
1393 int retries;
1394
1395 spin_lock_irqsave(&musb->lock, flags);
1396
1397 switch (musb->xceiv.state) {
1398 case OTG_STATE_B_PERIPHERAL:
1399 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1400 * that's part of the standard usb 1.1 state machine, and
1401 * doesn't affect OTG transitions.
1402 */
1403 if (musb->may_wakeup && musb->is_suspended)
1404 break;
1405 goto done;
1406 case OTG_STATE_B_IDLE:
1407 /* Start SRP ... OTG not required. */
1408 devctl = musb_readb(mregs, MUSB_DEVCTL);
1409 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1410 devctl |= MUSB_DEVCTL_SESSION;
1411 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1412 devctl = musb_readb(mregs, MUSB_DEVCTL);
1413 retries = 100;
1414 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1415 devctl = musb_readb(mregs, MUSB_DEVCTL);
1416 if (retries-- < 1)
1417 break;
1418 }
1419 retries = 10000;
1420 while (devctl & MUSB_DEVCTL_SESSION) {
1421 devctl = musb_readb(mregs, MUSB_DEVCTL);
1422 if (retries-- < 1)
1423 break;
1424 }
1425
1426 /* Block idling for at least 1s */
1427 musb_platform_try_idle(musb,
1428 jiffies + msecs_to_jiffies(1 * HZ));
1429
1430 status = 0;
1431 goto done;
1432 default:
1433 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1434 goto done;
1435 }
1436
1437 status = 0;
1438
1439 power = musb_readb(mregs, MUSB_POWER);
1440 power |= MUSB_POWER_RESUME;
1441 musb_writeb(mregs, MUSB_POWER, power);
1442 DBG(2, "issue wakeup\n");
1443
1444 /* FIXME do this next chunk in a timer callback, no udelay */
1445 mdelay(2);
1446
1447 power = musb_readb(mregs, MUSB_POWER);
1448 power &= ~MUSB_POWER_RESUME;
1449 musb_writeb(mregs, MUSB_POWER, power);
1450done:
1451 spin_unlock_irqrestore(&musb->lock, flags);
1452 return status;
1453}
1454
1455static int
1456musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1457{
1458 struct musb *musb = gadget_to_musb(gadget);
1459
1460 musb->is_self_powered = !!is_selfpowered;
1461 return 0;
1462}
1463
1464static void musb_pullup(struct musb *musb, int is_on)
1465{
1466 u8 power;
1467
1468 power = musb_readb(musb->mregs, MUSB_POWER);
1469 if (is_on)
1470 power |= MUSB_POWER_SOFTCONN;
1471 else
1472 power &= ~MUSB_POWER_SOFTCONN;
1473
1474 /* FIXME if on, HdrcStart; if off, HdrcStop */
1475
1476 DBG(3, "gadget %s D+ pullup %s\n",
1477 musb->gadget_driver->function, is_on ? "on" : "off");
1478 musb_writeb(musb->mregs, MUSB_POWER, power);
1479}
1480
1481#if 0
1482static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1483{
1484 DBG(2, "<= %s =>\n", __func__);
1485
1486 /*
1487 * FIXME iff driver's softconnect flag is set (as it is during probe,
1488 * though that can clear it), just musb_pullup().
1489 */
1490
1491 return -EINVAL;
1492}
1493#endif
1494
1495static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1496{
1497 struct musb *musb = gadget_to_musb(gadget);
1498
1499 if (!musb->xceiv.set_power)
1500 return -EOPNOTSUPP;
1501 return otg_set_power(&musb->xceiv, mA);
1502}
1503
1504static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1505{
1506 struct musb *musb = gadget_to_musb(gadget);
1507 unsigned long flags;
1508
1509 is_on = !!is_on;
1510
1511 /* NOTE: this assumes we are sensing vbus; we'd rather
1512 * not pullup unless the B-session is active.
1513 */
1514 spin_lock_irqsave(&musb->lock, flags);
1515 if (is_on != musb->softconnect) {
1516 musb->softconnect = is_on;
1517 musb_pullup(musb, is_on);
1518 }
1519 spin_unlock_irqrestore(&musb->lock, flags);
1520 return 0;
1521}
1522
1523static const struct usb_gadget_ops musb_gadget_operations = {
1524 .get_frame = musb_gadget_get_frame,
1525 .wakeup = musb_gadget_wakeup,
1526 .set_selfpowered = musb_gadget_set_self_powered,
1527 /* .vbus_session = musb_gadget_vbus_session, */
1528 .vbus_draw = musb_gadget_vbus_draw,
1529 .pullup = musb_gadget_pullup,
1530};
1531
1532/* ----------------------------------------------------------------------- */
1533
1534/* Registration */
1535
1536/* Only this registration code "knows" the rule (from USB standards)
1537 * about there being only one external upstream port. It assumes
1538 * all peripheral ports are external...
1539 */
1540static struct musb *the_gadget;
1541
1542static void musb_gadget_release(struct device *dev)
1543{
1544 /* kref_put(WHAT) */
1545 dev_dbg(dev, "%s\n", __func__);
1546}
1547
1548
1549static void __init
1550init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1551{
1552 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1553
1554 memset(ep, 0, sizeof *ep);
1555
1556 ep->current_epnum = epnum;
1557 ep->musb = musb;
1558 ep->hw_ep = hw_ep;
1559 ep->is_in = is_in;
1560
1561 INIT_LIST_HEAD(&ep->req_list);
1562
1563 sprintf(ep->name, "ep%d%s", epnum,
1564 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1565 is_in ? "in" : "out"));
1566 ep->end_point.name = ep->name;
1567 INIT_LIST_HEAD(&ep->end_point.ep_list);
1568 if (!epnum) {
1569 ep->end_point.maxpacket = 64;
1570 ep->end_point.ops = &musb_g_ep0_ops;
1571 musb->g.ep0 = &ep->end_point;
1572 } else {
1573 if (is_in)
1574 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1575 else
1576 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1577 ep->end_point.ops = &musb_ep_ops;
1578 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1579 }
1580}
1581
1582/*
1583 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1584 * to the rest of the driver state.
1585 */
1586static inline void __init musb_g_init_endpoints(struct musb *musb)
1587{
1588 u8 epnum;
1589 struct musb_hw_ep *hw_ep;
1590 unsigned count = 0;
1591
1592 /* intialize endpoint list just once */
1593 INIT_LIST_HEAD(&(musb->g.ep_list));
1594
1595 for (epnum = 0, hw_ep = musb->endpoints;
1596 epnum < musb->nr_endpoints;
1597 epnum++, hw_ep++) {
1598 if (hw_ep->is_shared_fifo /* || !epnum */) {
1599 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1600 count++;
1601 } else {
1602 if (hw_ep->max_packet_sz_tx) {
1603 init_peripheral_ep(musb, &hw_ep->ep_in,
1604 epnum, 1);
1605 count++;
1606 }
1607 if (hw_ep->max_packet_sz_rx) {
1608 init_peripheral_ep(musb, &hw_ep->ep_out,
1609 epnum, 0);
1610 count++;
1611 }
1612 }
1613 }
1614}
1615
1616/* called once during driver setup to initialize and link into
1617 * the driver model; memory is zeroed.
1618 */
1619int __init musb_gadget_setup(struct musb *musb)
1620{
1621 int status;
1622
1623 /* REVISIT minor race: if (erroneously) setting up two
1624 * musb peripherals at the same time, only the bus lock
1625 * is probably held.
1626 */
1627 if (the_gadget)
1628 return -EBUSY;
1629 the_gadget = musb;
1630
1631 musb->g.ops = &musb_gadget_operations;
1632 musb->g.is_dualspeed = 1;
1633 musb->g.speed = USB_SPEED_UNKNOWN;
1634
1635 /* this "gadget" abstracts/virtualizes the controller */
1636 strcpy(musb->g.dev.bus_id, "gadget");
1637 musb->g.dev.parent = musb->controller;
1638 musb->g.dev.dma_mask = musb->controller->dma_mask;
1639 musb->g.dev.release = musb_gadget_release;
1640 musb->g.name = musb_driver_name;
1641
1642 if (is_otg_enabled(musb))
1643 musb->g.is_otg = 1;
1644
1645 musb_g_init_endpoints(musb);
1646
1647 musb->is_active = 0;
1648 musb_platform_try_idle(musb, 0);
1649
1650 status = device_register(&musb->g.dev);
1651 if (status != 0)
1652 the_gadget = NULL;
1653 return status;
1654}
1655
1656void musb_gadget_cleanup(struct musb *musb)
1657{
1658 if (musb != the_gadget)
1659 return;
1660
1661 device_unregister(&musb->g.dev);
1662 the_gadget = NULL;
1663}
1664
1665/*
1666 * Register the gadget driver. Used by gadget drivers when
1667 * registering themselves with the controller.
1668 *
1669 * -EINVAL something went wrong (not driver)
1670 * -EBUSY another gadget is already using the controller
1671 * -ENOMEM no memeory to perform the operation
1672 *
1673 * @param driver the gadget driver
1674 * @return <0 if error, 0 if everything is fine
1675 */
1676int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1677{
1678 int retval;
1679 unsigned long flags;
1680 struct musb *musb = the_gadget;
1681
1682 if (!driver
1683 || driver->speed != USB_SPEED_HIGH
1684 || !driver->bind
1685 || !driver->setup)
1686 return -EINVAL;
1687
1688 /* driver must be initialized to support peripheral mode */
1689 if (!musb || !(musb->board_mode == MUSB_OTG
1690 || musb->board_mode != MUSB_OTG)) {
1691 DBG(1, "%s, no dev??\n", __func__);
1692 return -ENODEV;
1693 }
1694
1695 DBG(3, "registering driver %s\n", driver->function);
1696 spin_lock_irqsave(&musb->lock, flags);
1697
1698 if (musb->gadget_driver) {
1699 DBG(1, "%s is already bound to %s\n",
1700 musb_driver_name,
1701 musb->gadget_driver->driver.name);
1702 retval = -EBUSY;
1703 } else {
1704 musb->gadget_driver = driver;
1705 musb->g.dev.driver = &driver->driver;
1706 driver->driver.bus = NULL;
1707 musb->softconnect = 1;
1708 retval = 0;
1709 }
1710
1711 spin_unlock_irqrestore(&musb->lock, flags);
1712
1713 if (retval == 0)
1714 retval = driver->bind(&musb->g);
1715 if (retval != 0) {
1716 DBG(3, "bind to driver %s failed --> %d\n",
1717 driver->driver.name, retval);
1718 musb->gadget_driver = NULL;
1719 musb->g.dev.driver = NULL;
1720 }
1721
1722 /* start peripheral and/or OTG engines */
1723 if (retval == 0) {
1724 spin_lock_irqsave(&musb->lock, flags);
1725
1726 /* REVISIT always use otg_set_peripheral(), handling
1727 * issues including the root hub one below ...
1728 */
1729 musb->xceiv.gadget = &musb->g;
1730 musb->xceiv.state = OTG_STATE_B_IDLE;
1731 musb->is_active = 1;
1732
1733 /* FIXME this ignores the softconnect flag. Drivers are
1734 * allowed hold the peripheral inactive until for example
1735 * userspace hooks up printer hardware or DSP codecs, so
1736 * hosts only see fully functional devices.
1737 */
1738
1739 if (!is_otg_enabled(musb))
1740 musb_start(musb);
1741
1742 spin_unlock_irqrestore(&musb->lock, flags);
1743
1744 if (is_otg_enabled(musb)) {
1745 DBG(3, "OTG startup...\n");
1746
1747 /* REVISIT: funcall to other code, which also
1748 * handles power budgeting ... this way also
1749 * ensures HdrcStart is indirectly called.
1750 */
1751 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1752 if (retval < 0) {
1753 DBG(1, "add_hcd failed, %d\n", retval);
1754 spin_lock_irqsave(&musb->lock, flags);
1755 musb->xceiv.gadget = NULL;
1756 musb->xceiv.state = OTG_STATE_UNDEFINED;
1757 musb->gadget_driver = NULL;
1758 musb->g.dev.driver = NULL;
1759 spin_unlock_irqrestore(&musb->lock, flags);
1760 }
1761 }
1762 }
1763
1764 return retval;
1765}
1766EXPORT_SYMBOL(usb_gadget_register_driver);
1767
1768static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1769{
1770 int i;
1771 struct musb_hw_ep *hw_ep;
1772
1773 /* don't disconnect if it's not connected */
1774 if (musb->g.speed == USB_SPEED_UNKNOWN)
1775 driver = NULL;
1776 else
1777 musb->g.speed = USB_SPEED_UNKNOWN;
1778
1779 /* deactivate the hardware */
1780 if (musb->softconnect) {
1781 musb->softconnect = 0;
1782 musb_pullup(musb, 0);
1783 }
1784 musb_stop(musb);
1785
1786 /* killing any outstanding requests will quiesce the driver;
1787 * then report disconnect
1788 */
1789 if (driver) {
1790 for (i = 0, hw_ep = musb->endpoints;
1791 i < musb->nr_endpoints;
1792 i++, hw_ep++) {
1793 musb_ep_select(musb->mregs, i);
1794 if (hw_ep->is_shared_fifo /* || !epnum */) {
1795 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1796 } else {
1797 if (hw_ep->max_packet_sz_tx)
1798 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1799 if (hw_ep->max_packet_sz_rx)
1800 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1801 }
1802 }
1803
1804 spin_unlock(&musb->lock);
1805 driver->disconnect(&musb->g);
1806 spin_lock(&musb->lock);
1807 }
1808}
1809
1810/*
1811 * Unregister the gadget driver. Used by gadget drivers when
1812 * unregistering themselves from the controller.
1813 *
1814 * @param driver the gadget driver to unregister
1815 */
1816int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1817{
1818 unsigned long flags;
1819 int retval = 0;
1820 struct musb *musb = the_gadget;
1821
1822 if (!driver || !driver->unbind || !musb)
1823 return -EINVAL;
1824
1825 /* REVISIT always use otg_set_peripheral() here too;
1826 * this needs to shut down the OTG engine.
1827 */
1828
1829 spin_lock_irqsave(&musb->lock, flags);
1830
1831#ifdef CONFIG_USB_MUSB_OTG
1832 musb_hnp_stop(musb);
1833#endif
1834
1835 if (musb->gadget_driver == driver) {
1836
1837 (void) musb_gadget_vbus_draw(&musb->g, 0);
1838
1839 musb->xceiv.state = OTG_STATE_UNDEFINED;
1840 stop_activity(musb, driver);
1841
1842 DBG(3, "unregistering driver %s\n", driver->function);
1843 spin_unlock_irqrestore(&musb->lock, flags);
1844 driver->unbind(&musb->g);
1845 spin_lock_irqsave(&musb->lock, flags);
1846
1847 musb->gadget_driver = NULL;
1848 musb->g.dev.driver = NULL;
1849
1850 musb->is_active = 0;
1851 musb_platform_try_idle(musb, 0);
1852 } else
1853 retval = -EINVAL;
1854 spin_unlock_irqrestore(&musb->lock, flags);
1855
1856 if (is_otg_enabled(musb) && retval == 0) {
1857 usb_remove_hcd(musb_to_hcd(musb));
1858 /* FIXME we need to be able to register another
1859 * gadget driver here and have everything work;
1860 * that currently misbehaves.
1861 */
1862 }
1863
1864 return retval;
1865}
1866EXPORT_SYMBOL(usb_gadget_unregister_driver);
1867
1868
1869/* ----------------------------------------------------------------------- */
1870
1871/* lifecycle operations called through plat_uds.c */
1872
1873void musb_g_resume(struct musb *musb)
1874{
1875 musb->is_suspended = 0;
1876 switch (musb->xceiv.state) {
1877 case OTG_STATE_B_IDLE:
1878 break;
1879 case OTG_STATE_B_WAIT_ACON:
1880 case OTG_STATE_B_PERIPHERAL:
1881 musb->is_active = 1;
1882 if (musb->gadget_driver && musb->gadget_driver->resume) {
1883 spin_unlock(&musb->lock);
1884 musb->gadget_driver->resume(&musb->g);
1885 spin_lock(&musb->lock);
1886 }
1887 break;
1888 default:
1889 WARNING("unhandled RESUME transition (%s)\n",
1890 otg_state_string(musb));
1891 }
1892}
1893
1894/* called when SOF packets stop for 3+ msec */
1895void musb_g_suspend(struct musb *musb)
1896{
1897 u8 devctl;
1898
1899 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1900 DBG(3, "devctl %02x\n", devctl);
1901
1902 switch (musb->xceiv.state) {
1903 case OTG_STATE_B_IDLE:
1904 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1905 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
1906 break;
1907 case OTG_STATE_B_PERIPHERAL:
1908 musb->is_suspended = 1;
1909 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1910 spin_unlock(&musb->lock);
1911 musb->gadget_driver->suspend(&musb->g);
1912 spin_lock(&musb->lock);
1913 }
1914 break;
1915 default:
1916 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1917 * A_PERIPHERAL may need care too
1918 */
1919 WARNING("unhandled SUSPEND transition (%s)\n",
1920 otg_state_string(musb));
1921 }
1922}
1923
1924/* Called during SRP */
1925void musb_g_wakeup(struct musb *musb)
1926{
1927 musb_gadget_wakeup(&musb->g);
1928}
1929
1930/* called when VBUS drops below session threshold, and in other cases */
1931void musb_g_disconnect(struct musb *musb)
1932{
1933 void __iomem *mregs = musb->mregs;
1934 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1935
1936 DBG(3, "devctl %02x\n", devctl);
1937
1938 /* clear HR */
1939 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1940
1941 /* don't draw vbus until new b-default session */
1942 (void) musb_gadget_vbus_draw(&musb->g, 0);
1943
1944 musb->g.speed = USB_SPEED_UNKNOWN;
1945 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1946 spin_unlock(&musb->lock);
1947 musb->gadget_driver->disconnect(&musb->g);
1948 spin_lock(&musb->lock);
1949 }
1950
1951 switch (musb->xceiv.state) {
1952 default:
1953#ifdef CONFIG_USB_MUSB_OTG
1954 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1955 otg_state_string(musb));
1956 musb->xceiv.state = OTG_STATE_A_IDLE;
1957 break;
1958 case OTG_STATE_A_PERIPHERAL:
1959 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
1960 break;
1961 case OTG_STATE_B_WAIT_ACON:
1962 case OTG_STATE_B_HOST:
1963#endif
1964 case OTG_STATE_B_PERIPHERAL:
1965 case OTG_STATE_B_IDLE:
1966 musb->xceiv.state = OTG_STATE_B_IDLE;
1967 break;
1968 case OTG_STATE_B_SRP_INIT:
1969 break;
1970 }
1971
1972 musb->is_active = 0;
1973}
1974
1975void musb_g_reset(struct musb *musb)
1976__releases(musb->lock)
1977__acquires(musb->lock)
1978{
1979 void __iomem *mbase = musb->mregs;
1980 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
1981 u8 power;
1982
1983 DBG(3, "<== %s addr=%x driver '%s'\n",
1984 (devctl & MUSB_DEVCTL_BDEVICE)
1985 ? "B-Device" : "A-Device",
1986 musb_readb(mbase, MUSB_FADDR),
1987 musb->gadget_driver
1988 ? musb->gadget_driver->driver.name
1989 : NULL
1990 );
1991
1992 /* report disconnect, if we didn't already (flushing EP state) */
1993 if (musb->g.speed != USB_SPEED_UNKNOWN)
1994 musb_g_disconnect(musb);
1995
1996 /* clear HR */
1997 else if (devctl & MUSB_DEVCTL_HR)
1998 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
1999
2000
2001 /* what speed did we negotiate? */
2002 power = musb_readb(mbase, MUSB_POWER);
2003 musb->g.speed = (power & MUSB_POWER_HSMODE)
2004 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2005
2006 /* start in USB_STATE_DEFAULT */
2007 musb->is_active = 1;
2008 musb->is_suspended = 0;
2009 MUSB_DEV_MODE(musb);
2010 musb->address = 0;
2011 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2012
2013 musb->may_wakeup = 0;
2014 musb->g.b_hnp_enable = 0;
2015 musb->g.a_alt_hnp_support = 0;
2016 musb->g.a_hnp_support = 0;
2017
2018 /* Normal reset, as B-Device;
2019 * or else after HNP, as A-Device
2020 */
2021 if (devctl & MUSB_DEVCTL_BDEVICE) {
2022 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
2023 musb->g.is_a_peripheral = 0;
2024 } else if (is_otg_enabled(musb)) {
2025 musb->xceiv.state = OTG_STATE_A_PERIPHERAL;
2026 musb->g.is_a_peripheral = 1;
2027 } else
2028 WARN_ON(1);
2029
2030 /* start with default limits on VBUS power draw */
2031 (void) musb_gadget_vbus_draw(&musb->g,
2032 is_otg_enabled(musb) ? 8 : 100);
2033}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 10:48:04 -0500