6 files changed, 77 insertions, 95 deletions

diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
index b016d38199f2..eb009a457fb5 100644
--- a/drivers/usb/host/xhci-dbg.c
+++ b/drivers/usb/host/xhci-dbg.c
@@ -203,12 +203,12 @@ void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
                                 addr, (unsigned int)temp);
 
         addr = &ir_set->erst_base;
-        temp_64 = readq(addr);
+        temp_64 = xhci_read_64(xhci, addr);
         xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",
                         addr, temp_64);
 
         addr = &ir_set->erst_dequeue;
-        temp_64 = readq(addr);
+        temp_64 = xhci_read_64(xhci, addr);
         xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",
                         addr, temp_64);
 }
@@ -412,7 +412,7 @@ void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
 {
         u64 val;
 
-        val = readq(&xhci->op_regs->cmd_ring);
+        val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
         xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
                         lower_32_bits(val));
         xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 873c272b3ef5..bce4391a0e7d 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -1958,7 +1958,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
                 xhci_warn(xhci, "WARN something wrong with SW event ring "
                                 "dequeue ptr.\n");
         /* Update HC event ring dequeue pointer */
-        temp = readq(&xhci->ir_set->erst_dequeue);
+        temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
         temp &= ERST_PTR_MASK;
         /* Don't clear the EHB bit (which is RW1C) because
          * there might be more events to service.
@@ -1967,7 +1967,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
                         "// Write event ring dequeue pointer, "
                         "preserving EHB bit");
-        writeq(((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
+        xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
                         &xhci->ir_set->erst_dequeue);
 }
 
@@ -2269,7 +2269,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
                         "// Device context base array address = 0x%llx (DMA), %p (virt)",
                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
-        writeq(dma, &xhci->op_regs->dcbaa_ptr);
+        xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
 
         /*
          * Initialize the ring segment pool.  The ring must be a contiguous
@@ -2312,13 +2312,13 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
 
         /* Set the address in the Command Ring Control register */
-        val_64 = readq(&xhci->op_regs->cmd_ring);
+        val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
                 xhci->cmd_ring->cycle_state;
         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
                         "// Setting command ring address to 0x%x", val);
-        writeq(val_64, &xhci->op_regs->cmd_ring);
+        xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
         xhci_dbg_cmd_ptrs(xhci);
 
         xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
@@ -2396,10 +2396,10 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
                         "// Set ERST base address for ir_set 0 = 0x%llx",
                         (unsigned long long)xhci->erst.erst_dma_addr);
-        val_64 = readq(&xhci->ir_set->erst_base);
+        val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
         val_64 &= ERST_PTR_MASK;
         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
-        writeq(val_64, &xhci->ir_set->erst_base);
+        xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
 
         /* Set the event ring dequeue address */
         xhci_set_hc_event_deq(xhci);
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 3c898c12a06b..04f986d9234f 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -142,6 +142,11 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
                                 "QUIRK: Resetting on resume");
                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
         }
+        if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
+                        pdev->device == 0x0015 &&
+                        pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
+                        pdev->subsystem_device == 0xc0cd)
+                xhci->quirks |= XHCI_RESET_ON_RESUME;
         if (pdev->vendor == PCI_VENDOR_ID_VIA)
                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 }
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index a0b248c34526..0ed64eb68e48 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -307,13 +307,14 @@ static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
                 return 0;
         }
 
-        temp_64 = readq(&xhci->op_regs->cmd_ring);
+        temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
         if (!(temp_64 & CMD_RING_RUNNING)) {
                 xhci_dbg(xhci, "Command ring had been stopped\n");
                 return 0;
         }
         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
-        writeq(temp_64 | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
+        xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
+                        &xhci->op_regs->cmd_ring);
 
         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
          * time the completion od all xHCI commands, including
@@ -2864,8 +2865,9 @@ hw_died:
                 /* Clear the event handler busy flag (RW1C);
                  * the event ring should be empty.
                  */
-                temp_64 = readq(&xhci->ir_set->erst_dequeue);
-                writeq(temp_64 | ERST_EHB, &xhci->ir_set->erst_dequeue);
+                temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
+                xhci_write_64(xhci, temp_64 | ERST_EHB,
+                                &xhci->ir_set->erst_dequeue);
                 spin_unlock(&xhci->lock);
 
                 return IRQ_HANDLED;
@@ -2877,7 +2879,7 @@ hw_died:
          */
         while (xhci_handle_event(xhci) > 0) {}
 
-        temp_64 = readq(&xhci->ir_set->erst_dequeue);
+        temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
         /* If necessary, update the HW's version of the event ring deq ptr. */
         if (event_ring_deq != xhci->event_ring->dequeue) {
                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
@@ -2892,7 +2894,7 @@ hw_died:
 
         /* Clear the event handler busy flag (RW1C); event ring is empty. */
         temp_64 |= ERST_EHB;
-        writeq(temp_64, &xhci->ir_set->erst_dequeue);
+        xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
 
         spin_unlock(&xhci->lock);
 
@@ -2965,58 +2967,8 @@ static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
         }
 
         while (1) {
-                if (room_on_ring(xhci, ep_ring, num_trbs)) {
-                        union xhci_trb *trb = ep_ring->enqueue;
-                        unsigned int usable = ep_ring->enq_seg->trbs +
-                                        TRBS_PER_SEGMENT - 1 - trb;
-                        u32 nop_cmd;
-
-                        /*
-                         * Section 4.11.7.1 TD Fragments states that a link
-                         * TRB must only occur at the boundary between
-                         * data bursts (eg 512 bytes for 480M).
-                         * While it is possible to split a large fragment
-                         * we don't know the size yet.
-                         * Simplest solution is to fill the trb before the
-                         * LINK with nop commands.
-                         */
-                        if (num_trbs == 1 || num_trbs <= usable || usable == 0)
-                                break;
-
-                        if (ep_ring->type != TYPE_BULK)
-                                /*
-                                 * While isoc transfers might have a buffer that
-                                 * crosses a 64k boundary it is unlikely.
-                                 * Since we can't add NOPs without generating
-                                 * gaps in the traffic just hope it never
-                                 * happens at the end of the ring.
-                                 * This could be fixed by writing a LINK TRB
-                                 * instead of the first NOP - however the
-                                 * TRB_TYPE_LINK_LE32() calls would all need
-                                 * changing to check the ring length.
-                                 */
-                                break;
-
-                        if (num_trbs >= TRBS_PER_SEGMENT) {
-                                xhci_err(xhci, "Too many fragments %d, max %d\n",
-                                                num_trbs, TRBS_PER_SEGMENT - 1);
-                                return -EINVAL;
-                        }
-
-                        nop_cmd = cpu_to_le32(TRB_TYPE(TRB_TR_NOOP) |
-                                        ep_ring->cycle_state);
-                        ep_ring->num_trbs_free -= usable;
-                        do {
-                                trb->generic.field[0] = 0;
-                                trb->generic.field[1] = 0;
-                                trb->generic.field[2] = 0;
-                                trb->generic.field[3] = nop_cmd;
-                                trb++;
-                        } while (--usable);
-                        ep_ring->enqueue = trb;
-                        if (room_on_ring(xhci, ep_ring, num_trbs))
-                                break;
-                }
+                if (room_on_ring(xhci, ep_ring, num_trbs))
+                        break;
 
                 if (ep_ring == xhci->cmd_ring) {
                         xhci_err(xhci, "Do not support expand command ring\n");
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index ad364394885a..6fe577d46fa2 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -611,7 +611,7 @@ int xhci_run(struct usb_hcd *hcd)
         xhci_dbg(xhci, "Event ring:\n");
         xhci_debug_ring(xhci, xhci->event_ring);
         xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
-        temp_64 = readq(&xhci->ir_set->erst_dequeue);
+        temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
         temp_64 &= ~ERST_PTR_MASK;
         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
                         "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
@@ -756,11 +756,11 @@ static void xhci_save_registers(struct xhci_hcd *xhci)
 {
         xhci->s3.command = readl(&xhci->op_regs->command);
         xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
-        xhci->s3.dcbaa_ptr = readq(&xhci->op_regs->dcbaa_ptr);
+        xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
         xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
         xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
-        xhci->s3.erst_base = readq(&xhci->ir_set->erst_base);
-        xhci->s3.erst_dequeue = readq(&xhci->ir_set->erst_dequeue);
+        xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
+        xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
         xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
         xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
 }
@@ -769,11 +769,11 @@ static void xhci_restore_registers(struct xhci_hcd *xhci)
 {
         writel(xhci->s3.command, &xhci->op_regs->command);
         writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
-        writeq(xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
+        xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
         writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
         writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
-        writeq(xhci->s3.erst_base, &xhci->ir_set->erst_base);
-        writeq(xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
+        xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
+        xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
         writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
         writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
 }
@@ -783,7 +783,7 @@ static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
         u64     val_64;
 
         /* step 2: initialize command ring buffer */
-        val_64 = readq(&xhci->op_regs->cmd_ring);
+        val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
                 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
                                       xhci->cmd_ring->dequeue) &
@@ -792,7 +792,7 @@ static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
                         "// Setting command ring address to 0x%llx",
                         (long unsigned long) val_64);
-        writeq(val_64, &xhci->op_regs->cmd_ring);
+        xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
 }
 
 /*
@@ -3842,7 +3842,7 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
         if (ret) {
                 return ret;
         }
-        temp_64 = readq(&xhci->op_regs->dcbaa_ptr);
+        temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
         xhci_dbg_trace(xhci, trace_xhci_dbg_address,
                         "Op regs DCBAA ptr = %#016llx", temp_64);
         xhci_dbg_trace(xhci, trace_xhci_dbg_address,
@@ -4730,11 +4730,8 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
         struct device           *dev = hcd->self.controller;
         int                     retval;
 
-        /* Limit the block layer scatter-gather lists to half a segment. */
-        hcd->self.sg_tablesize = TRBS_PER_SEGMENT / 2;
-
-        /* support to build packet from discontinuous buffers */
-        hcd->self.no_sg_constraint = 1;
+        /* Accept arbitrarily long scatter-gather lists */
+        hcd->self.sg_tablesize = ~0;
 
         /* XHCI controllers don't stop the ep queue on short packets :| */
         hcd->self.no_stop_on_short = 1;
@@ -4760,6 +4757,14 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
                 /* xHCI private pointer was set in xhci_pci_probe for the second
                  * registered roothub.
                  */
+                xhci = hcd_to_xhci(hcd);
+                /*
+                 * Support arbitrarily aligned sg-list entries on hosts without
+                 * TD fragment rules (which are currently unsupported).
+                 */
+                if (xhci->hci_version < 0x100)
+                        hcd->self.no_sg_constraint = 1;
+
                 return 0;
         }
 
@@ -4788,6 +4793,9 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
         if (xhci->hci_version > 0x96)
                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 
+        if (xhci->hci_version < 0x100)
+                hcd->self.no_sg_constraint = 1;
+
         /* Make sure the HC is halted. */
         retval = xhci_halt(xhci);
         if (retval)
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index f8416639bf31..58ed9d088e63 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -28,17 +28,6 @@
 #include <linux/kernel.h>
 #include <linux/usb/hcd.h>
 
-/*
- * Registers should always be accessed with double word or quad word accesses.
- *
- * Some xHCI implementations may support 64-bit address pointers.  Registers
- * with 64-bit address pointers should be written to with dword accesses by
- * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
- * xHCI implementations that do not support 64-bit address pointers will ignore
- * the high dword, and write order is irrelevant.
- */
-#include <asm-generic/io-64-nonatomic-lo-hi.h>
-
 /* Code sharing between pci-quirks and xhci hcd */
 #include        "xhci-ext-caps.h"
 #include "pci-quirks.h"
@@ -1279,7 +1268,7 @@ union xhci_trb {
  * since the command ring is 64-byte aligned.
  * It must also be greater than 16.
  */
-#define TRBS_PER_SEGMENT        256
+#define TRBS_PER_SEGMENT        64
 /* Allow two commands + a link TRB, along with any reserved command TRBs */
 #define MAX_RSVD_CMD_TRBS       (TRBS_PER_SEGMENT - 3)
 #define TRB_SEGMENT_SIZE        (TRBS_PER_SEGMENT*16)
@@ -1614,6 +1603,34 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
 #define xhci_warn_ratelimited(xhci, fmt, args...) \
         dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
 
+/*
+ * Registers should always be accessed with double word or quad word accesses.
+ *
+ * Some xHCI implementations may support 64-bit address pointers.  Registers
+ * with 64-bit address pointers should be written to with dword accesses by
+ * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
+ * xHCI implementations that do not support 64-bit address pointers will ignore
+ * the high dword, and write order is irrelevant.
+ */
+static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
+                __le64 __iomem *regs)
+{
+        __u32 __iomem *ptr = (__u32 __iomem *) regs;
+        u64 val_lo = readl(ptr);
+        u64 val_hi = readl(ptr + 1);
+        return val_lo + (val_hi << 32);
+}
+static inline void xhci_write_64(struct xhci_hcd *xhci,
+                                 const u64 val, __le64 __iomem *regs)
+{
+        __u32 __iomem *ptr = (__u32 __iomem *) regs;
+        u32 val_lo = lower_32_bits(val);
+        u32 val_hi = upper_32_bits(val);
+
+        writel(val_lo, ptr);
+        writel(val_hi, ptr + 1);
+}
+
 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
 {
         return xhci->quirks & XHCI_LINK_TRB_QUIRK;