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-rw-r--r--drivers/usb/host/Kconfig39
-rw-r--r--drivers/usb/host/ehci-atmel.c6
-rw-r--r--drivers/usb/host/ehci-dbg.c4
-rw-r--r--drivers/usb/host/ehci-hcd.c29
-rw-r--r--drivers/usb/host/ehci-hub.c32
-rw-r--r--drivers/usb/host/ehci-lpm.c5
-rw-r--r--drivers/usb/host/ehci-msm.c96
-rw-r--r--drivers/usb/host/ehci-omap.c882
-rw-r--r--drivers/usb/host/ehci-orion.c5
-rw-r--r--drivers/usb/host/ehci-pci.c45
-rw-r--r--drivers/usb/host/ehci-pmcmsp.c383
-rw-r--r--drivers/usb/host/ehci-q.c18
-rw-r--r--drivers/usb/host/ehci-sched.c76
-rw-r--r--drivers/usb/host/ehci-tegra.c715
-rw-r--r--drivers/usb/host/ehci.h2
-rw-r--r--drivers/usb/host/imx21-hcd.c9
-rw-r--r--drivers/usb/host/isp116x-hcd.c6
-rw-r--r--drivers/usb/host/isp1362-hcd.c13
-rw-r--r--drivers/usb/host/isp1760-hcd.c1395
-rw-r--r--drivers/usb/host/isp1760-hcd.h56
-rw-r--r--drivers/usb/host/ohci-hcd.c18
-rw-r--r--drivers/usb/host/ohci-hub.c13
-rw-r--r--drivers/usb/host/ohci-omap3.c584
-rw-r--r--drivers/usb/host/ohci-pci.c114
-rw-r--r--drivers/usb/host/ohci-q.c4
-rw-r--r--drivers/usb/host/ohci.h4
-rw-r--r--drivers/usb/host/oxu210hp-hcd.c6
-rw-r--r--drivers/usb/host/pci-quirks.c258
-rw-r--r--drivers/usb/host/pci-quirks.h10
-rw-r--r--drivers/usb/host/r8a66597-hcd.c5
-rw-r--r--drivers/usb/host/sl811-hcd.c6
-rw-r--r--drivers/usb/host/u132-hcd.c11
-rw-r--r--drivers/usb/host/uhci-hcd.c2
-rw-r--r--drivers/usb/host/xhci-ext-caps.h4
-rw-r--r--drivers/usb/host/xhci-hub.c392
-rw-r--r--drivers/usb/host/xhci-mem.c93
-rw-r--r--drivers/usb/host/xhci-pci.c124
-rw-r--r--drivers/usb/host/xhci-ring.c195
-rw-r--r--drivers/usb/host/xhci.c129
-rw-r--r--drivers/usb/host/xhci.h53
40 files changed, 3089 insertions, 2752 deletions
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0e6afa260ed8..9483acdf2e9e 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -91,17 +91,28 @@ config USB_EHCI_TT_NEWSCHED
91 91
92 If unsure, say Y. 92 If unsure, say Y.
93 93
94config USB_EHCI_HCD_PMC_MSP
95 tristate "EHCI support for on-chip PMC MSP71xx USB controller"
96 depends on USB_EHCI_HCD && MSP_HAS_USB
97 default n
98 select USB_EHCI_BIG_ENDIAN_DESC
99 select USB_EHCI_BIG_ENDIAN_MMIO
100 ---help---
101 Enables support for the onchip USB controller on the PMC_MSP7100 Family SoC's.
102 If unsure, say N.
103
94config USB_EHCI_BIG_ENDIAN_MMIO 104config USB_EHCI_BIG_ENDIAN_MMIO
95 bool 105 bool
96 depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ 106 depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \
97 ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ 107 ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
98 PPC_MPC512x || CPU_CAVIUM_OCTEON) 108 PPC_MPC512x || CPU_CAVIUM_OCTEON || \
109 PMC_MSP)
99 default y 110 default y
100 111
101config USB_EHCI_BIG_ENDIAN_DESC 112config USB_EHCI_BIG_ENDIAN_DESC
102 bool 113 bool
103 depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ 114 depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
104 PPC_MPC512x) 115 PPC_MPC512x || PMC_MSP)
105 default y 116 default y
106 117
107config XPS_USB_HCD_XILINX 118config XPS_USB_HCD_XILINX
@@ -145,7 +156,7 @@ config USB_EHCI_MSM
145 bool "Support for MSM on-chip EHCI USB controller" 156 bool "Support for MSM on-chip EHCI USB controller"
146 depends on USB_EHCI_HCD && ARCH_MSM 157 depends on USB_EHCI_HCD && ARCH_MSM
147 select USB_EHCI_ROOT_HUB_TT 158 select USB_EHCI_ROOT_HUB_TT
148 select USB_MSM_OTG_72K 159 select USB_MSM_OTG
149 ---help--- 160 ---help---
150 Enables support for the USB Host controller present on the 161 Enables support for the USB Host controller present on the
151 Qualcomm chipsets. Root Hub has inbuilt TT. 162 Qualcomm chipsets. Root Hub has inbuilt TT.
@@ -154,6 +165,14 @@ config USB_EHCI_MSM
154 This driver is not supported on boards like trout which 165 This driver is not supported on boards like trout which
155 has an external PHY. 166 has an external PHY.
156 167
168config USB_EHCI_TEGRA
169 boolean "NVIDIA Tegra HCD support"
170 depends on USB_EHCI_HCD && ARCH_TEGRA
171 select USB_EHCI_ROOT_HUB_TT
172 help
173 This driver enables support for the internal USB Host Controllers
174 found in NVIDIA Tegra SoCs. The controllers are EHCI compliant.
175
157config USB_EHCI_HCD_PPC_OF 176config USB_EHCI_HCD_PPC_OF
158 bool "EHCI support for PPC USB controller on OF platform bus" 177 bool "EHCI support for PPC USB controller on OF platform bus"
159 depends on USB_EHCI_HCD && PPC_OF 178 depends on USB_EHCI_HCD && PPC_OF
@@ -162,6 +181,13 @@ config USB_EHCI_HCD_PPC_OF
162 Enables support for the USB controller present on the PowerPC 181 Enables support for the USB controller present on the PowerPC
163 OpenFirmware platform bus. 182 OpenFirmware platform bus.
164 183
184config USB_EHCI_SH
185 bool "EHCI support for SuperH USB controller"
186 depends on USB_EHCI_HCD && SUPERH
187 ---help---
188 Enables support for the on-chip EHCI controller on the SuperH.
189 If you use the PCI EHCI controller, this option is not necessary.
190
165config USB_W90X900_EHCI 191config USB_W90X900_EHCI
166 bool "W90X900(W90P910) EHCI support" 192 bool "W90X900(W90P910) EHCI support"
167 depends on USB_EHCI_HCD && ARCH_W90X900 193 depends on USB_EHCI_HCD && ARCH_W90X900
@@ -315,6 +341,13 @@ config USB_OHCI_HCD_SSB
315 341
316 If unsure, say N. 342 If unsure, say N.
317 343
344config USB_OHCI_SH
345 bool "OHCI support for SuperH USB controller"
346 depends on USB_OHCI_HCD && SUPERH
347 ---help---
348 Enables support for the on-chip OHCI controller on the SuperH.
349 If you use the PCI OHCI controller, this option is not necessary.
350
318config USB_CNS3XXX_OHCI 351config USB_CNS3XXX_OHCI
319 bool "Cavium CNS3XXX OHCI Module" 352 bool "Cavium CNS3XXX OHCI Module"
320 depends on USB_OHCI_HCD && ARCH_CNS3XXX 353 depends on USB_OHCI_HCD && ARCH_CNS3XXX
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index d6a69d514a84..b2ed55cb811d 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -115,7 +115,7 @@ static const struct hc_driver ehci_atmel_hc_driver = {
115 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 115 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
116}; 116};
117 117
118static int __init ehci_atmel_drv_probe(struct platform_device *pdev) 118static int __devinit ehci_atmel_drv_probe(struct platform_device *pdev)
119{ 119{
120 struct usb_hcd *hcd; 120 struct usb_hcd *hcd;
121 const struct hc_driver *driver = &ehci_atmel_hc_driver; 121 const struct hc_driver *driver = &ehci_atmel_hc_driver;
@@ -207,7 +207,7 @@ fail_create_hcd:
207 return retval; 207 return retval;
208} 208}
209 209
210static int __exit ehci_atmel_drv_remove(struct platform_device *pdev) 210static int __devexit ehci_atmel_drv_remove(struct platform_device *pdev)
211{ 211{
212 struct usb_hcd *hcd = platform_get_drvdata(pdev); 212 struct usb_hcd *hcd = platform_get_drvdata(pdev);
213 213
@@ -227,7 +227,7 @@ static int __exit ehci_atmel_drv_remove(struct platform_device *pdev)
227 227
228static struct platform_driver ehci_atmel_driver = { 228static struct platform_driver ehci_atmel_driver = {
229 .probe = ehci_atmel_drv_probe, 229 .probe = ehci_atmel_drv_probe,
230 .remove = __exit_p(ehci_atmel_drv_remove), 230 .remove = __devexit_p(ehci_atmel_drv_remove),
231 .shutdown = usb_hcd_platform_shutdown, 231 .shutdown = usb_hcd_platform_shutdown,
232 .driver.name = "atmel-ehci", 232 .driver.name = "atmel-ehci",
233}; 233};
diff --git a/drivers/usb/host/ehci-dbg.c b/drivers/usb/host/ehci-dbg.c
index 3be238a24cc5..693c29b30521 100644
--- a/drivers/usb/host/ehci-dbg.c
+++ b/drivers/usb/host/ehci-dbg.c
@@ -28,11 +28,9 @@
28 dev_warn (ehci_to_hcd(ehci)->self.controller , fmt , ## args ) 28 dev_warn (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
29 29
30#ifdef VERBOSE_DEBUG 30#ifdef VERBOSE_DEBUG
31# define vdbg dbg
32# define ehci_vdbg ehci_dbg 31# define ehci_vdbg ehci_dbg
33#else 32#else
34# define vdbg(fmt,args...) do { } while (0) 33 static inline void ehci_vdbg(struct ehci_hcd *ehci, ...) {}
35# define ehci_vdbg(ehci, fmt, args...) do { } while (0)
36#endif 34#endif
37 35
38#ifdef DEBUG 36#ifdef DEBUG
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 74dcf49bd015..d30c4e08c137 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -114,13 +114,11 @@ MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n");
114 114
115#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 115#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
116 116
117/* for ASPM quirk of ISOC on AMD SB800 */
118static struct pci_dev *amd_nb_dev;
119
120/*-------------------------------------------------------------------------*/ 117/*-------------------------------------------------------------------------*/
121 118
122#include "ehci.h" 119#include "ehci.h"
123#include "ehci-dbg.c" 120#include "ehci-dbg.c"
121#include "pci-quirks.h"
124 122
125/*-------------------------------------------------------------------------*/ 123/*-------------------------------------------------------------------------*/
126 124
@@ -532,10 +530,8 @@ static void ehci_stop (struct usb_hcd *hcd)
532 spin_unlock_irq (&ehci->lock); 530 spin_unlock_irq (&ehci->lock);
533 ehci_mem_cleanup (ehci); 531 ehci_mem_cleanup (ehci);
534 532
535 if (amd_nb_dev) { 533 if (ehci->amd_pll_fix == 1)
536 pci_dev_put(amd_nb_dev); 534 usb_amd_dev_put();
537 amd_nb_dev = NULL;
538 }
539 535
540#ifdef EHCI_STATS 536#ifdef EHCI_STATS
541 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 537 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
@@ -679,7 +675,12 @@ static int ehci_run (struct usb_hcd *hcd)
679 hcd->uses_new_polling = 1; 675 hcd->uses_new_polling = 1;
680 676
681 /* EHCI spec section 4.1 */ 677 /* EHCI spec section 4.1 */
682 if ((retval = ehci_reset(ehci)) != 0) { 678 /*
679 * TDI driver does the ehci_reset in their reset callback.
680 * Don't reset here, because configuration settings will
681 * vanish.
682 */
683 if (!ehci_is_TDI(ehci) && (retval = ehci_reset(ehci)) != 0) {
683 ehci_mem_cleanup(ehci); 684 ehci_mem_cleanup(ehci);
684 return retval; 685 return retval;
685 } 686 }
@@ -1179,7 +1180,7 @@ MODULE_LICENSE ("GPL");
1179#define PLATFORM_DRIVER ehci_mxc_driver 1180#define PLATFORM_DRIVER ehci_mxc_driver
1180#endif 1181#endif
1181 1182
1182#ifdef CONFIG_CPU_SUBTYPE_SH7786 1183#ifdef CONFIG_USB_EHCI_SH
1183#include "ehci-sh.c" 1184#include "ehci-sh.c"
1184#define PLATFORM_DRIVER ehci_hcd_sh_driver 1185#define PLATFORM_DRIVER ehci_hcd_sh_driver
1185#endif 1186#endif
@@ -1254,6 +1255,16 @@ MODULE_LICENSE ("GPL");
1254#define PLATFORM_DRIVER ehci_msm_driver 1255#define PLATFORM_DRIVER ehci_msm_driver
1255#endif 1256#endif
1256 1257
1258#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1259#include "ehci-pmcmsp.c"
1260#define PLATFORM_DRIVER ehci_hcd_msp_driver
1261#endif
1262
1263#ifdef CONFIG_USB_EHCI_TEGRA
1264#include "ehci-tegra.c"
1265#define PLATFORM_DRIVER tegra_ehci_driver
1266#endif
1267
1257#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1268#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1258 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1269 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1259 !defined(XILINX_OF_PLATFORM_DRIVER) 1270 !defined(XILINX_OF_PLATFORM_DRIVER)
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index 8a515f0d5988..d05ea03cfb4d 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -106,6 +106,27 @@ static void ehci_handover_companion_ports(struct ehci_hcd *ehci)
106 ehci->owned_ports = 0; 106 ehci->owned_ports = 0;
107} 107}
108 108
109static int ehci_port_change(struct ehci_hcd *ehci)
110{
111 int i = HCS_N_PORTS(ehci->hcs_params);
112
113 /* First check if the controller indicates a change event */
114
115 if (ehci_readl(ehci, &ehci->regs->status) & STS_PCD)
116 return 1;
117
118 /*
119 * Not all controllers appear to update this while going from D3 to D0,
120 * so check the individual port status registers as well
121 */
122
123 while (i--)
124 if (ehci_readl(ehci, &ehci->regs->port_status[i]) & PORT_CSC)
125 return 1;
126
127 return 0;
128}
129
109static void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, 130static void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
110 bool suspending, bool do_wakeup) 131 bool suspending, bool do_wakeup)
111{ 132{
@@ -173,7 +194,7 @@ static void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
173 } 194 }
174 195
175 /* Does the root hub have a port wakeup pending? */ 196 /* Does the root hub have a port wakeup pending? */
176 if (!suspending && (ehci_readl(ehci, &ehci->regs->status) & STS_PCD)) 197 if (!suspending && ehci_port_change(ehci))
177 usb_hcd_resume_root_hub(ehci_to_hcd(ehci)); 198 usb_hcd_resume_root_hub(ehci_to_hcd(ehci));
178 199
179 spin_unlock_irqrestore(&ehci->lock, flags); 200 spin_unlock_irqrestore(&ehci->lock, flags);
@@ -538,14 +559,15 @@ static ssize_t store_companion(struct device *dev,
538} 559}
539static DEVICE_ATTR(companion, 0644, show_companion, store_companion); 560static DEVICE_ATTR(companion, 0644, show_companion, store_companion);
540 561
541static inline void create_companion_file(struct ehci_hcd *ehci) 562static inline int create_companion_file(struct ehci_hcd *ehci)
542{ 563{
543 int i; 564 int i = 0;
544 565
545 /* with integrated TT there is no companion! */ 566 /* with integrated TT there is no companion! */
546 if (!ehci_is_TDI(ehci)) 567 if (!ehci_is_TDI(ehci))
547 i = device_create_file(ehci_to_hcd(ehci)->self.controller, 568 i = device_create_file(ehci_to_hcd(ehci)->self.controller,
548 &dev_attr_companion); 569 &dev_attr_companion);
570 return i;
549} 571}
550 572
551static inline void remove_companion_file(struct ehci_hcd *ehci) 573static inline void remove_companion_file(struct ehci_hcd *ehci)
@@ -695,8 +717,8 @@ ehci_hub_descriptor (
695 desc->bDescLength = 7 + 2 * temp; 717 desc->bDescLength = 7 + 2 * temp;
696 718
697 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 719 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
698 memset (&desc->bitmap [0], 0, temp); 720 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
699 memset (&desc->bitmap [temp], 0xff, temp); 721 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
700 722
701 temp = 0x0008; /* per-port overcurrent reporting */ 723 temp = 0x0008; /* per-port overcurrent reporting */
702 if (HCS_PPC (ehci->hcs_params)) 724 if (HCS_PPC (ehci->hcs_params))
diff --git a/drivers/usb/host/ehci-lpm.c b/drivers/usb/host/ehci-lpm.c
index b4d4d63c13ed..2111627a19de 100644
--- a/drivers/usb/host/ehci-lpm.c
+++ b/drivers/usb/host/ehci-lpm.c
@@ -17,7 +17,8 @@
17*/ 17*/
18 18
19/* this file is part of ehci-hcd.c */ 19/* this file is part of ehci-hcd.c */
20static int ehci_lpm_set_da(struct ehci_hcd *ehci, int dev_addr, int port_num) 20static int __maybe_unused ehci_lpm_set_da(struct ehci_hcd *ehci,
21 int dev_addr, int port_num)
21{ 22{
22 u32 __iomem portsc; 23 u32 __iomem portsc;
23 24
@@ -37,7 +38,7 @@ static int ehci_lpm_set_da(struct ehci_hcd *ehci, int dev_addr, int port_num)
37 * this function is used to check if the device support LPM 38 * this function is used to check if the device support LPM
38 * if yes, mark the PORTSC register with PORT_LPM bit 39 * if yes, mark the PORTSC register with PORT_LPM bit
39 */ 40 */
40static int ehci_lpm_check(struct ehci_hcd *ehci, int port) 41static int __maybe_unused ehci_lpm_check(struct ehci_hcd *ehci, int port)
41{ 42{
42 u32 __iomem *portsc ; 43 u32 __iomem *portsc ;
43 u32 val32; 44 u32 val32;
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index 413f4deca532..9ce1b0bc186d 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -1,6 +1,6 @@
1/* ehci-msm.c - HSUSB Host Controller Driver Implementation 1/* ehci-msm.c - HSUSB Host Controller Driver Implementation
2 * 2 *
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * 4 *
5 * Partly derived from ehci-fsl.c and ehci-hcd.c 5 * Partly derived from ehci-fsl.c and ehci-hcd.c
6 * Copyright (c) 2000-2004 by David Brownell 6 * Copyright (c) 2000-2004 by David Brownell
@@ -34,92 +34,6 @@
34 34
35static struct otg_transceiver *otg; 35static struct otg_transceiver *otg;
36 36
37/*
38 * ehci_run defined in drivers/usb/host/ehci-hcd.c reset the controller and
39 * the configuration settings in ehci_msm_reset vanish after controller is
40 * reset. Resetting the controler in ehci_run seems to be un-necessary
41 * provided HCD reset the controller before calling ehci_run. Most of the HCD
42 * do but some are not. So this function is same as ehci_run but we don't
43 * reset the controller here.
44 */
45static int ehci_msm_run(struct usb_hcd *hcd)
46{
47 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
48 u32 temp;
49 u32 hcc_params;
50
51 hcd->uses_new_polling = 1;
52
53 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
54 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
55
56 /*
57 * hcc_params controls whether ehci->regs->segment must (!!!)
58 * be used; it constrains QH/ITD/SITD and QTD locations.
59 * pci_pool consistent memory always uses segment zero.
60 * streaming mappings for I/O buffers, like pci_map_single(),
61 * can return segments above 4GB, if the device allows.
62 *
63 * NOTE: the dma mask is visible through dma_supported(), so
64 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
65 * Scsi_Host.highmem_io, and so forth. It's readonly to all
66 * host side drivers though.
67 */
68 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
69 if (HCC_64BIT_ADDR(hcc_params))
70 ehci_writel(ehci, 0, &ehci->regs->segment);
71
72 /*
73 * Philips, Intel, and maybe others need CMD_RUN before the
74 * root hub will detect new devices (why?); NEC doesn't
75 */
76 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
77 ehci->command |= CMD_RUN;
78 ehci_writel(ehci, ehci->command, &ehci->regs->command);
79 dbg_cmd(ehci, "init", ehci->command);
80
81 /*
82 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
83 * are explicitly handed to companion controller(s), so no TT is
84 * involved with the root hub. (Except where one is integrated,
85 * and there's no companion controller unless maybe for USB OTG.)
86 *
87 * Turning on the CF flag will transfer ownership of all ports
88 * from the companions to the EHCI controller. If any of the
89 * companions are in the middle of a port reset at the time, it
90 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
91 * guarantees that no resets are in progress. After we set CF,
92 * a short delay lets the hardware catch up; new resets shouldn't
93 * be started before the port switching actions could complete.
94 */
95 down_write(&ehci_cf_port_reset_rwsem);
96 hcd->state = HC_STATE_RUNNING;
97 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
98 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
99 usleep_range(5000, 5500);
100 up_write(&ehci_cf_port_reset_rwsem);
101 ehci->last_periodic_enable = ktime_get_real();
102
103 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
104 ehci_info(ehci,
105 "USB %x.%x started, EHCI %x.%02x%s\n",
106 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
107 temp >> 8, temp & 0xff,
108 ignore_oc ? ", overcurrent ignored" : "");
109
110 ehci_writel(ehci, INTR_MASK,
111 &ehci->regs->intr_enable); /* Turn On Interrupts */
112
113 /* GRR this is run-once init(), being done every time the HC starts.
114 * So long as they're part of class devices, we can't do it init()
115 * since the class device isn't created that early.
116 */
117 create_debug_files(ehci);
118 create_companion_file(ehci);
119
120 return 0;
121}
122
123static int ehci_msm_reset(struct usb_hcd *hcd) 37static int ehci_msm_reset(struct usb_hcd *hcd)
124{ 38{
125 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 39 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
@@ -128,6 +42,8 @@ static int ehci_msm_reset(struct usb_hcd *hcd)
128 ehci->caps = USB_CAPLENGTH; 42 ehci->caps = USB_CAPLENGTH;
129 ehci->regs = USB_CAPLENGTH + 43 ehci->regs = USB_CAPLENGTH +
130 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); 44 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
45 dbg_hcs_params(ehci, "reset");
46 dbg_hcc_params(ehci, "reset");
131 47
132 /* cache the data to minimize the chip reads*/ 48 /* cache the data to minimize the chip reads*/
133 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 49 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
@@ -135,6 +51,10 @@ static int ehci_msm_reset(struct usb_hcd *hcd)
135 hcd->has_tt = 1; 51 hcd->has_tt = 1;
136 ehci->sbrn = HCD_USB2; 52 ehci->sbrn = HCD_USB2;
137 53
54 retval = ehci_halt(ehci);
55 if (retval)
56 return retval;
57
138 /* data structure init */ 58 /* data structure init */
139 retval = ehci_init(hcd); 59 retval = ehci_init(hcd);
140 if (retval) 60 if (retval)
@@ -167,7 +87,7 @@ static struct hc_driver msm_hc_driver = {
167 .flags = HCD_USB2 | HCD_MEMORY, 87 .flags = HCD_USB2 | HCD_MEMORY,
168 88
169 .reset = ehci_msm_reset, 89 .reset = ehci_msm_reset,
170 .start = ehci_msm_run, 90 .start = ehci_run,
171 91
172 .stop = ehci_stop, 92 .stop = ehci_stop,
173 .shutdown = ehci_shutdown, 93 .shutdown = ehci_shutdown,
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index f784ceb862a3..7e41a95c5ceb 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -4,9 +4,10 @@
4 * Bus Glue for the EHCI controllers in OMAP3/4 4 * Bus Glue for the EHCI controllers in OMAP3/4
5 * Tested on several OMAP3 boards, and OMAP4 Pandaboard 5 * Tested on several OMAP3 boards, and OMAP4 Pandaboard
6 * 6 *
7 * Copyright (C) 2007-2010 Texas Instruments, Inc. 7 * Copyright (C) 2007-2011 Texas Instruments, Inc.
8 * Author: Vikram Pandita <vikram.pandita@ti.com> 8 * Author: Vikram Pandita <vikram.pandita@ti.com>
9 * Author: Anand Gadiyar <gadiyar@ti.com> 9 * Author: Anand Gadiyar <gadiyar@ti.com>
10 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
10 * 11 *
11 * Copyright (C) 2009 Nokia Corporation 12 * Copyright (C) 2009 Nokia Corporation
12 * Contact: Felipe Balbi <felipe.balbi@nokia.com> 13 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
@@ -27,116 +28,19 @@
27 * along with this program; if not, write to the Free Software 28 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 * 30 *
30 * TODO (last updated Nov 21, 2010): 31 * TODO (last updated Feb 27, 2010):
31 * - add kernel-doc 32 * - add kernel-doc
32 * - enable AUTOIDLE 33 * - enable AUTOIDLE
33 * - add suspend/resume 34 * - add suspend/resume
34 * - move workarounds to board-files
35 * - factor out code common to OHCI
36 * - add HSIC and TLL support 35 * - add HSIC and TLL support
37 * - convert to use hwmod and runtime PM 36 * - convert to use hwmod and runtime PM
38 */ 37 */
39 38
40#include <linux/platform_device.h> 39#include <linux/platform_device.h>
41#include <linux/clk.h>
42#include <linux/gpio.h>
43#include <linux/regulator/consumer.h>
44#include <linux/slab.h> 40#include <linux/slab.h>
45#include <linux/usb/ulpi.h> 41#include <linux/usb/ulpi.h>
46#include <plat/usb.h> 42#include <plat/usb.h>
47 43
48/*
49 * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
50 * Use ehci_omap_readl()/ehci_omap_writel() functions
51 */
52
53/* TLL Register Set */
54#define OMAP_USBTLL_REVISION (0x00)
55#define OMAP_USBTLL_SYSCONFIG (0x10)
56#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
57#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
58#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
59#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
60#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
61
62#define OMAP_USBTLL_SYSSTATUS (0x14)
63#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
64
65#define OMAP_USBTLL_IRQSTATUS (0x18)
66#define OMAP_USBTLL_IRQENABLE (0x1C)
67
68#define OMAP_TLL_SHARED_CONF (0x30)
69#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
70#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
71#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
72#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
73#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
74
75#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
76#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
77#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
78#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
79#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
80#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
81
82#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
83#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
84#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
85#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
86#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
87#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
88#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
89#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
90#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
91
92#define OMAP_TLL_CHANNEL_COUNT 3
93#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
94#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
95#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
96
97/* UHH Register Set */
98#define OMAP_UHH_REVISION (0x00)
99#define OMAP_UHH_SYSCONFIG (0x10)
100#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
101#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
102#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
103#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
104#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
105#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
106
107#define OMAP_UHH_SYSSTATUS (0x14)
108#define OMAP_UHH_HOSTCONFIG (0x40)
109#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
110#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
111#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
112#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
113#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
114#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
115#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
116#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
117#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
118#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
119#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
120
121/* OMAP4-specific defines */
122#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
123#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
124
125#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
126#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
127#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
128
129#define OMAP4_P1_MODE_CLEAR (3 << 16)
130#define OMAP4_P1_MODE_TLL (1 << 16)
131#define OMAP4_P1_MODE_HSIC (3 << 16)
132#define OMAP4_P2_MODE_CLEAR (3 << 18)
133#define OMAP4_P2_MODE_TLL (1 << 18)
134#define OMAP4_P2_MODE_HSIC (3 << 18)
135
136#define OMAP_REV2_TLL_CHANNEL_COUNT 2
137
138#define OMAP_UHH_DEBUG_CSR (0x44)
139
140/* EHCI Register Set */ 44/* EHCI Register Set */
141#define EHCI_INSNREG04 (0xA0) 45#define EHCI_INSNREG04 (0xA0)
142#define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5) 46#define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5)
@@ -148,137 +52,24 @@
148#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8 52#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8
149#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0 53#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0
150 54
151/* Values of UHH_REVISION - Note: these are not given in the TRM */ 55/*-------------------------------------------------------------------------*/
152#define OMAP_EHCI_REV1 0x00000010 /* OMAP3 */
153#define OMAP_EHCI_REV2 0x50700100 /* OMAP4 */
154
155#define is_omap_ehci_rev1(x) (x->omap_ehci_rev == OMAP_EHCI_REV1)
156#define is_omap_ehci_rev2(x) (x->omap_ehci_rev == OMAP_EHCI_REV2)
157 56
158#define is_ehci_phy_mode(x) (x == EHCI_HCD_OMAP_MODE_PHY) 57static const struct hc_driver ehci_omap_hc_driver;
159#define is_ehci_tll_mode(x) (x == EHCI_HCD_OMAP_MODE_TLL)
160#define is_ehci_hsic_mode(x) (x == EHCI_HCD_OMAP_MODE_HSIC)
161 58
162/*-------------------------------------------------------------------------*/
163 59
164static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val) 60static inline void ehci_write(void __iomem *base, u32 reg, u32 val)
165{ 61{
166 __raw_writel(val, base + reg); 62 __raw_writel(val, base + reg);
167} 63}
168 64
169static inline u32 ehci_omap_readl(void __iomem *base, u32 reg) 65static inline u32 ehci_read(void __iomem *base, u32 reg)
170{ 66{
171 return __raw_readl(base + reg); 67 return __raw_readl(base + reg);
172} 68}
173 69
174static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val) 70static void omap_ehci_soft_phy_reset(struct platform_device *pdev, u8 port)
175{
176 __raw_writeb(val, base + reg);
177}
178
179static inline u8 ehci_omap_readb(void __iomem *base, u8 reg)
180{
181 return __raw_readb(base + reg);
182}
183
184/*-------------------------------------------------------------------------*/
185
186struct ehci_hcd_omap {
187 struct ehci_hcd *ehci;
188 struct device *dev;
189
190 struct clk *usbhost_ick;
191 struct clk *usbhost_hs_fck;
192 struct clk *usbhost_fs_fck;
193 struct clk *usbtll_fck;
194 struct clk *usbtll_ick;
195 struct clk *xclk60mhsp1_ck;
196 struct clk *xclk60mhsp2_ck;
197 struct clk *utmi_p1_fck;
198 struct clk *utmi_p2_fck;
199
200 /* FIXME the following two workarounds are
201 * board specific not silicon-specific so these
202 * should be moved to board-file instead.
203 *
204 * Maybe someone from TI will know better which
205 * board is affected and needs the workarounds
206 * to be applied
207 */
208
209 /* gpio for resetting phy */
210 int reset_gpio_port[OMAP3_HS_USB_PORTS];
211
212 /* phy reset workaround */
213 int phy_reset;
214
215 /* IP revision */
216 u32 omap_ehci_rev;
217
218 /* desired phy_mode: TLL, PHY */
219 enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
220
221 void __iomem *uhh_base;
222 void __iomem *tll_base;
223 void __iomem *ehci_base;
224
225 /* Regulators for USB PHYs.
226 * Each PHY can have a separate regulator.
227 */
228 struct regulator *regulator[OMAP3_HS_USB_PORTS];
229};
230
231/*-------------------------------------------------------------------------*/
232
233static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask,
234 u8 tll_channel_count)
235{
236 unsigned reg;
237 int i;
238
239 /* Program the 3 TLL channels upfront */
240 for (i = 0; i < tll_channel_count; i++) {
241 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
242
243 /* Disable AutoIdle, BitStuffing and use SDR Mode */
244 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
245 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
246 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
247 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
248 }
249
250 /* Program Common TLL register */
251 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
252 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
253 | OMAP_TLL_SHARED_CONF_USB_DIVRATION
254 | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
255 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
256
257 ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
258
259 /* Enable channels now */
260 for (i = 0; i < tll_channel_count; i++) {
261 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
262
263 /* Enable only the reg that is needed */
264 if (!(tll_channel_mask & 1<<i))
265 continue;
266
267 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
268 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
269
270 ehci_omap_writeb(omap->tll_base,
271 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
272 dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
273 i+1, ehci_omap_readb(omap->tll_base,
274 OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
275 }
276}
277
278/*-------------------------------------------------------------------------*/
279
280static void omap_ehci_soft_phy_reset(struct ehci_hcd_omap *omap, u8 port)
281{ 71{
72 struct usb_hcd *hcd = dev_get_drvdata(&pdev->dev);
282 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 73 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
283 unsigned reg = 0; 74 unsigned reg = 0;
284 75
@@ -292,266 +83,87 @@ static void omap_ehci_soft_phy_reset(struct ehci_hcd_omap *omap, u8 port)
292 /* start ULPI access*/ 83 /* start ULPI access*/
293 | (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT); 84 | (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT);
294 85
295 ehci_omap_writel(omap->ehci_base, EHCI_INSNREG05_ULPI, reg); 86 ehci_write(hcd->regs, EHCI_INSNREG05_ULPI, reg);
296 87
297 /* Wait for ULPI access completion */ 88 /* Wait for ULPI access completion */
298 while ((ehci_omap_readl(omap->ehci_base, EHCI_INSNREG05_ULPI) 89 while ((ehci_read(hcd->regs, EHCI_INSNREG05_ULPI)
299 & (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT))) { 90 & (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT))) {
300 cpu_relax(); 91 cpu_relax();
301 92
302 if (time_after(jiffies, timeout)) { 93 if (time_after(jiffies, timeout)) {
303 dev_dbg(omap->dev, "phy reset operation timed out\n"); 94 dev_dbg(&pdev->dev, "phy reset operation timed out\n");
304 break; 95 break;
305 } 96 }
306 } 97 }
307} 98}
308 99
309/* omap_start_ehc
310 * - Start the TI USBHOST controller
311 */
312static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
313{
314 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
315 u8 tll_ch_mask = 0;
316 unsigned reg = 0;
317 int ret = 0;
318
319 dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
320 100
321 /* Enable Clocks for USBHOST */ 101/* configure so an HC device and id are always provided */
322 omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick"); 102/* always called with process context; sleeping is OK */
323 if (IS_ERR(omap->usbhost_ick)) {
324 ret = PTR_ERR(omap->usbhost_ick);
325 goto err_host_ick;
326 }
327 clk_enable(omap->usbhost_ick);
328
329 omap->usbhost_hs_fck = clk_get(omap->dev, "hs_fck");
330 if (IS_ERR(omap->usbhost_hs_fck)) {
331 ret = PTR_ERR(omap->usbhost_hs_fck);
332 goto err_host_120m_fck;
333 }
334 clk_enable(omap->usbhost_hs_fck);
335 103
336 omap->usbhost_fs_fck = clk_get(omap->dev, "fs_fck"); 104/**
337 if (IS_ERR(omap->usbhost_fs_fck)) { 105 * ehci_hcd_omap_probe - initialize TI-based HCDs
338 ret = PTR_ERR(omap->usbhost_fs_fck); 106 *
339 goto err_host_48m_fck; 107 * Allocates basic resources for this USB host controller, and
340 } 108 * then invokes the start() method for the HCD associated with it
341 clk_enable(omap->usbhost_fs_fck); 109 * through the hotplug entry's driver_data.
342 110 */
343 if (omap->phy_reset) { 111static int ehci_hcd_omap_probe(struct platform_device *pdev)
344 /* Refer: ISSUE1 */ 112{
345 if (gpio_is_valid(omap->reset_gpio_port[0])) { 113 struct device *dev = &pdev->dev;
346 gpio_request(omap->reset_gpio_port[0], 114 struct ehci_hcd_omap_platform_data *pdata = dev->platform_data;
347 "USB1 PHY reset"); 115 struct resource *res;
348 gpio_direction_output(omap->reset_gpio_port[0], 0); 116 struct usb_hcd *hcd;
349 } 117 void __iomem *regs;
118 struct ehci_hcd *omap_ehci;
119 int ret = -ENODEV;
120 int irq;
350 121
351 if (gpio_is_valid(omap->reset_gpio_port[1])) { 122 if (usb_disabled())
352 gpio_request(omap->reset_gpio_port[1], 123 return -ENODEV;
353 "USB2 PHY reset");
354 gpio_direction_output(omap->reset_gpio_port[1], 0);
355 }
356 124
357 /* Hold the PHY in RESET for enough time till DIR is high */ 125 if (!dev->parent) {
358 udelay(10); 126 dev_err(dev, "Missing parent device\n");
127 return -ENODEV;
359 } 128 }
360 129
361 /* Configure TLL for 60Mhz clk for ULPI */ 130 irq = platform_get_irq_byname(pdev, "ehci-irq");
362 omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck"); 131 if (irq < 0) {
363 if (IS_ERR(omap->usbtll_fck)) { 132 dev_err(dev, "EHCI irq failed\n");
364 ret = PTR_ERR(omap->usbtll_fck); 133 return -ENODEV;
365 goto err_tll_fck;
366 } 134 }
367 clk_enable(omap->usbtll_fck);
368 135
369 omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick"); 136 res = platform_get_resource_byname(pdev,
370 if (IS_ERR(omap->usbtll_ick)) { 137 IORESOURCE_MEM, "ehci");
371 ret = PTR_ERR(omap->usbtll_ick); 138 if (!res) {
372 goto err_tll_ick; 139 dev_err(dev, "UHH EHCI get resource failed\n");
140 return -ENODEV;
373 } 141 }
374 clk_enable(omap->usbtll_ick);
375
376 omap->omap_ehci_rev = ehci_omap_readl(omap->uhh_base,
377 OMAP_UHH_REVISION);
378 dev_dbg(omap->dev, "OMAP UHH_REVISION 0x%x\n",
379 omap->omap_ehci_rev);
380 142
381 /* 143 regs = ioremap(res->start, resource_size(res));
382 * Enable per-port clocks as needed (newer controllers only). 144 if (!regs) {
383 * - External ULPI clock for PHY mode 145 dev_err(dev, "UHH EHCI ioremap failed\n");
384 * - Internal clocks for TLL and HSIC modes (TODO) 146 return -ENOMEM;
385 */
386 if (is_omap_ehci_rev2(omap)) {
387 switch (omap->port_mode[0]) {
388 case EHCI_HCD_OMAP_MODE_PHY:
389 omap->xclk60mhsp1_ck = clk_get(omap->dev,
390 "xclk60mhsp1_ck");
391 if (IS_ERR(omap->xclk60mhsp1_ck)) {
392 ret = PTR_ERR(omap->xclk60mhsp1_ck);
393 dev_err(omap->dev,
394 "Unable to get Port1 ULPI clock\n");
395 }
396
397 omap->utmi_p1_fck = clk_get(omap->dev,
398 "utmi_p1_gfclk");
399 if (IS_ERR(omap->utmi_p1_fck)) {
400 ret = PTR_ERR(omap->utmi_p1_fck);
401 dev_err(omap->dev,
402 "Unable to get utmi_p1_fck\n");
403 }
404
405 ret = clk_set_parent(omap->utmi_p1_fck,
406 omap->xclk60mhsp1_ck);
407 if (ret != 0) {
408 dev_err(omap->dev,
409 "Unable to set P1 f-clock\n");
410 }
411 break;
412 case EHCI_HCD_OMAP_MODE_TLL:
413 /* TODO */
414 default:
415 break;
416 }
417 switch (omap->port_mode[1]) {
418 case EHCI_HCD_OMAP_MODE_PHY:
419 omap->xclk60mhsp2_ck = clk_get(omap->dev,
420 "xclk60mhsp2_ck");
421 if (IS_ERR(omap->xclk60mhsp2_ck)) {
422 ret = PTR_ERR(omap->xclk60mhsp2_ck);
423 dev_err(omap->dev,
424 "Unable to get Port2 ULPI clock\n");
425 }
426
427 omap->utmi_p2_fck = clk_get(omap->dev,
428 "utmi_p2_gfclk");
429 if (IS_ERR(omap->utmi_p2_fck)) {
430 ret = PTR_ERR(omap->utmi_p2_fck);
431 dev_err(omap->dev,
432 "Unable to get utmi_p2_fck\n");
433 }
434
435 ret = clk_set_parent(omap->utmi_p2_fck,
436 omap->xclk60mhsp2_ck);
437 if (ret != 0) {
438 dev_err(omap->dev,
439 "Unable to set P2 f-clock\n");
440 }
441 break;
442 case EHCI_HCD_OMAP_MODE_TLL:
443 /* TODO */
444 default:
445 break;
446 }
447 } 147 }
448 148
449 149 hcd = usb_create_hcd(&ehci_omap_hc_driver, dev,
450 /* perform TLL soft reset, and wait until reset is complete */ 150 dev_name(dev));
451 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, 151 if (!hcd) {
452 OMAP_USBTLL_SYSCONFIG_SOFTRESET); 152 dev_err(dev, "failed to create hcd with err %d\n", ret);
453 153 ret = -ENOMEM;
454 /* Wait for TLL reset to complete */ 154 goto err_io;
455 while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
456 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
457 cpu_relax();
458
459 if (time_after(jiffies, timeout)) {
460 dev_dbg(omap->dev, "operation timed out\n");
461 ret = -EINVAL;
462 goto err_sys_status;
463 }
464 } 155 }
465 156
466 dev_dbg(omap->dev, "TLL RESET DONE\n"); 157 hcd->rsrc_start = res->start;
467 158 hcd->rsrc_len = resource_size(res);
468 /* (1<<3) = no idle mode only for initial debugging */ 159 hcd->regs = regs;
469 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
470 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
471 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
472 OMAP_USBTLL_SYSCONFIG_CACTIVITY);
473
474
475 /* Put UHH in NoIdle/NoStandby mode */
476 reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
477 if (is_omap_ehci_rev1(omap)) {
478 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
479 | OMAP_UHH_SYSCONFIG_SIDLEMODE
480 | OMAP_UHH_SYSCONFIG_CACTIVITY
481 | OMAP_UHH_SYSCONFIG_MIDLEMODE);
482 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
483
484 160
485 } else if (is_omap_ehci_rev2(omap)) { 161 ret = omap_usbhs_enable(dev);
486 reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR; 162 if (ret) {
487 reg |= OMAP4_UHH_SYSCONFIG_NOIDLE; 163 dev_err(dev, "failed to start usbhs with err %d\n", ret);
488 reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR; 164 goto err_enable;
489 reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
490 }
491 ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
492
493 reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
494
495 /* setup ULPI bypass and burst configurations */
496 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
497 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
498 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
499 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
500
501 if (is_omap_ehci_rev1(omap)) {
502 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
503 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
504 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
505 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
506 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
507 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
508
509 /* Bypass the TLL module for PHY mode operation */
510 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
511 dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n");
512 if (is_ehci_phy_mode(omap->port_mode[0]) ||
513 is_ehci_phy_mode(omap->port_mode[1]) ||
514 is_ehci_phy_mode(omap->port_mode[2]))
515 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
516 else
517 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
518 } else {
519 dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
520 if (is_ehci_phy_mode(omap->port_mode[0]))
521 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
522 else if (is_ehci_tll_mode(omap->port_mode[0]))
523 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
524
525 if (is_ehci_phy_mode(omap->port_mode[1]))
526 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
527 else if (is_ehci_tll_mode(omap->port_mode[1]))
528 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
529
530 if (is_ehci_phy_mode(omap->port_mode[2]))
531 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
532 else if (is_ehci_tll_mode(omap->port_mode[2]))
533 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
534 }
535 } else if (is_omap_ehci_rev2(omap)) {
536 /* Clear port mode fields for PHY mode*/
537 reg &= ~OMAP4_P1_MODE_CLEAR;
538 reg &= ~OMAP4_P2_MODE_CLEAR;
539
540 if (is_ehci_tll_mode(omap->port_mode[0]))
541 reg |= OMAP4_P1_MODE_TLL;
542 else if (is_ehci_hsic_mode(omap->port_mode[0]))
543 reg |= OMAP4_P1_MODE_HSIC;
544
545 if (is_ehci_tll_mode(omap->port_mode[1]))
546 reg |= OMAP4_P2_MODE_TLL;
547 else if (is_ehci_hsic_mode(omap->port_mode[1]))
548 reg |= OMAP4_P2_MODE_HSIC;
549 } 165 }
550 166
551 ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
552 dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
553
554
555 /* 167 /*
556 * An undocumented "feature" in the OMAP3 EHCI controller, 168 * An undocumented "feature" in the OMAP3 EHCI controller,
557 * causes suspended ports to be taken out of suspend when 169 * causes suspended ports to be taken out of suspend when
@@ -561,363 +173,50 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
561 * to suspend. Writing 1 to this undocumented register bit 173 * to suspend. Writing 1 to this undocumented register bit
562 * disables this feature and restores normal behavior. 174 * disables this feature and restores normal behavior.
563 */ 175 */
564 ehci_omap_writel(omap->ehci_base, EHCI_INSNREG04, 176 ehci_write(regs, EHCI_INSNREG04,
565 EHCI_INSNREG04_DISABLE_UNSUSPEND); 177 EHCI_INSNREG04_DISABLE_UNSUSPEND);
566 178
567 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
568 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
569 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
570
571 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
572 tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
573 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
574 tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
575 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
576 tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
577
578 /* Enable UTMI mode for required TLL channels */
579 omap_usb_utmi_init(omap, tll_ch_mask, OMAP_TLL_CHANNEL_COUNT);
580 }
581
582 if (omap->phy_reset) {
583 /* Refer ISSUE1:
584 * Hold the PHY in RESET for enough time till
585 * PHY is settled and ready
586 */
587 udelay(10);
588
589 if (gpio_is_valid(omap->reset_gpio_port[0]))
590 gpio_set_value(omap->reset_gpio_port[0], 1);
591
592 if (gpio_is_valid(omap->reset_gpio_port[1]))
593 gpio_set_value(omap->reset_gpio_port[1], 1);
594 }
595
596 /* Soft reset the PHY using PHY reset command over ULPI */ 179 /* Soft reset the PHY using PHY reset command over ULPI */
597 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) 180 if (pdata->port_mode[0] == OMAP_EHCI_PORT_MODE_PHY)
598 omap_ehci_soft_phy_reset(omap, 0); 181 omap_ehci_soft_phy_reset(pdev, 0);
599 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) 182 if (pdata->port_mode[1] == OMAP_EHCI_PORT_MODE_PHY)
600 omap_ehci_soft_phy_reset(omap, 1); 183 omap_ehci_soft_phy_reset(pdev, 1);
601
602 return 0;
603
604err_sys_status:
605 clk_disable(omap->utmi_p2_fck);
606 clk_put(omap->utmi_p2_fck);
607 clk_disable(omap->xclk60mhsp2_ck);
608 clk_put(omap->xclk60mhsp2_ck);
609 clk_disable(omap->utmi_p1_fck);
610 clk_put(omap->utmi_p1_fck);
611 clk_disable(omap->xclk60mhsp1_ck);
612 clk_put(omap->xclk60mhsp1_ck);
613 clk_disable(omap->usbtll_ick);
614 clk_put(omap->usbtll_ick);
615
616err_tll_ick:
617 clk_disable(omap->usbtll_fck);
618 clk_put(omap->usbtll_fck);
619
620err_tll_fck:
621 clk_disable(omap->usbhost_fs_fck);
622 clk_put(omap->usbhost_fs_fck);
623
624 if (omap->phy_reset) {
625 if (gpio_is_valid(omap->reset_gpio_port[0]))
626 gpio_free(omap->reset_gpio_port[0]);
627
628 if (gpio_is_valid(omap->reset_gpio_port[1]))
629 gpio_free(omap->reset_gpio_port[1]);
630 }
631
632err_host_48m_fck:
633 clk_disable(omap->usbhost_hs_fck);
634 clk_put(omap->usbhost_hs_fck);
635 184
636err_host_120m_fck: 185 omap_ehci = hcd_to_ehci(hcd);
637 clk_disable(omap->usbhost_ick); 186 omap_ehci->sbrn = 0x20;
638 clk_put(omap->usbhost_ick);
639
640err_host_ick:
641 return ret;
642}
643
644static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
645{
646 unsigned long timeout = jiffies + msecs_to_jiffies(100);
647
648 dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
649
650 /* Reset OMAP modules for insmod/rmmod to work */
651 ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
652 is_omap_ehci_rev2(omap) ?
653 OMAP4_UHH_SYSCONFIG_SOFTRESET :
654 OMAP_UHH_SYSCONFIG_SOFTRESET);
655 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
656 & (1 << 0))) {
657 cpu_relax();
658
659 if (time_after(jiffies, timeout))
660 dev_dbg(omap->dev, "operation timed out\n");
661 }
662
663 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
664 & (1 << 1))) {
665 cpu_relax();
666
667 if (time_after(jiffies, timeout))
668 dev_dbg(omap->dev, "operation timed out\n");
669 }
670
671 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
672 & (1 << 2))) {
673 cpu_relax();
674
675 if (time_after(jiffies, timeout))
676 dev_dbg(omap->dev, "operation timed out\n");
677 }
678
679 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
680
681 while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
682 & (1 << 0))) {
683 cpu_relax();
684
685 if (time_after(jiffies, timeout))
686 dev_dbg(omap->dev, "operation timed out\n");
687 }
688
689 if (omap->usbtll_fck != NULL) {
690 clk_disable(omap->usbtll_fck);
691 clk_put(omap->usbtll_fck);
692 omap->usbtll_fck = NULL;
693 }
694
695 if (omap->usbhost_ick != NULL) {
696 clk_disable(omap->usbhost_ick);
697 clk_put(omap->usbhost_ick);
698 omap->usbhost_ick = NULL;
699 }
700
701 if (omap->usbhost_fs_fck != NULL) {
702 clk_disable(omap->usbhost_fs_fck);
703 clk_put(omap->usbhost_fs_fck);
704 omap->usbhost_fs_fck = NULL;
705 }
706
707 if (omap->usbhost_hs_fck != NULL) {
708 clk_disable(omap->usbhost_hs_fck);
709 clk_put(omap->usbhost_hs_fck);
710 omap->usbhost_hs_fck = NULL;
711 }
712
713 if (omap->usbtll_ick != NULL) {
714 clk_disable(omap->usbtll_ick);
715 clk_put(omap->usbtll_ick);
716 omap->usbtll_ick = NULL;
717 }
718
719 if (is_omap_ehci_rev2(omap)) {
720 if (omap->xclk60mhsp1_ck != NULL) {
721 clk_disable(omap->xclk60mhsp1_ck);
722 clk_put(omap->xclk60mhsp1_ck);
723 omap->xclk60mhsp1_ck = NULL;
724 }
725
726 if (omap->utmi_p1_fck != NULL) {
727 clk_disable(omap->utmi_p1_fck);
728 clk_put(omap->utmi_p1_fck);
729 omap->utmi_p1_fck = NULL;
730 }
731
732 if (omap->xclk60mhsp2_ck != NULL) {
733 clk_disable(omap->xclk60mhsp2_ck);
734 clk_put(omap->xclk60mhsp2_ck);
735 omap->xclk60mhsp2_ck = NULL;
736 }
737
738 if (omap->utmi_p2_fck != NULL) {
739 clk_disable(omap->utmi_p2_fck);
740 clk_put(omap->utmi_p2_fck);
741 omap->utmi_p2_fck = NULL;
742 }
743 }
744
745 if (omap->phy_reset) {
746 if (gpio_is_valid(omap->reset_gpio_port[0]))
747 gpio_free(omap->reset_gpio_port[0]);
748
749 if (gpio_is_valid(omap->reset_gpio_port[1]))
750 gpio_free(omap->reset_gpio_port[1]);
751 }
752
753 dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
754}
755
756/*-------------------------------------------------------------------------*/
757
758static const struct hc_driver ehci_omap_hc_driver;
759
760/* configure so an HC device and id are always provided */
761/* always called with process context; sleeping is OK */
762
763/**
764 * ehci_hcd_omap_probe - initialize TI-based HCDs
765 *
766 * Allocates basic resources for this USB host controller, and
767 * then invokes the start() method for the HCD associated with it
768 * through the hotplug entry's driver_data.
769 */
770static int ehci_hcd_omap_probe(struct platform_device *pdev)
771{
772 struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data;
773 struct ehci_hcd_omap *omap;
774 struct resource *res;
775 struct usb_hcd *hcd;
776
777 int irq = platform_get_irq(pdev, 0);
778 int ret = -ENODEV;
779 int i;
780 char supply[7];
781
782 if (!pdata) {
783 dev_dbg(&pdev->dev, "missing platform_data\n");
784 goto err_pdata;
785 }
786
787 if (usb_disabled())
788 goto err_disabled;
789
790 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
791 if (!omap) {
792 ret = -ENOMEM;
793 goto err_disabled;
794 }
795
796 hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev,
797 dev_name(&pdev->dev));
798 if (!hcd) {
799 dev_err(&pdev->dev, "failed to create hcd with err %d\n", ret);
800 ret = -ENOMEM;
801 goto err_create_hcd;
802 }
803
804 platform_set_drvdata(pdev, omap);
805 omap->dev = &pdev->dev;
806 omap->phy_reset = pdata->phy_reset;
807 omap->reset_gpio_port[0] = pdata->reset_gpio_port[0];
808 omap->reset_gpio_port[1] = pdata->reset_gpio_port[1];
809 omap->reset_gpio_port[2] = pdata->reset_gpio_port[2];
810 omap->port_mode[0] = pdata->port_mode[0];
811 omap->port_mode[1] = pdata->port_mode[1];
812 omap->port_mode[2] = pdata->port_mode[2];
813 omap->ehci = hcd_to_ehci(hcd);
814 omap->ehci->sbrn = 0x20;
815
816 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
817
818 hcd->rsrc_start = res->start;
819 hcd->rsrc_len = resource_size(res);
820
821 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
822 if (!hcd->regs) {
823 dev_err(&pdev->dev, "EHCI ioremap failed\n");
824 ret = -ENOMEM;
825 goto err_ioremap;
826 }
827 187
828 /* we know this is the memory we want, no need to ioremap again */ 188 /* we know this is the memory we want, no need to ioremap again */
829 omap->ehci->caps = hcd->regs; 189 omap_ehci->caps = hcd->regs;
830 omap->ehci_base = hcd->regs; 190 omap_ehci->regs = hcd->regs
831 191 + HC_LENGTH(readl(&omap_ehci->caps->hc_capbase));
832 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
833 omap->uhh_base = ioremap(res->start, resource_size(res));
834 if (!omap->uhh_base) {
835 dev_err(&pdev->dev, "UHH ioremap failed\n");
836 ret = -ENOMEM;
837 goto err_uhh_ioremap;
838 }
839
840 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
841 omap->tll_base = ioremap(res->start, resource_size(res));
842 if (!omap->tll_base) {
843 dev_err(&pdev->dev, "TLL ioremap failed\n");
844 ret = -ENOMEM;
845 goto err_tll_ioremap;
846 }
847
848 /* get ehci regulator and enable */
849 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
850 if (omap->port_mode[i] != EHCI_HCD_OMAP_MODE_PHY) {
851 omap->regulator[i] = NULL;
852 continue;
853 }
854 snprintf(supply, sizeof(supply), "hsusb%d", i);
855 omap->regulator[i] = regulator_get(omap->dev, supply);
856 if (IS_ERR(omap->regulator[i])) {
857 omap->regulator[i] = NULL;
858 dev_dbg(&pdev->dev,
859 "failed to get ehci port%d regulator\n", i);
860 } else {
861 regulator_enable(omap->regulator[i]);
862 }
863 }
864
865 ret = omap_start_ehc(omap, hcd);
866 if (ret) {
867 dev_err(&pdev->dev, "failed to start ehci with err %d\n", ret);
868 goto err_start;
869 }
870 192
871 omap->ehci->regs = hcd->regs 193 dbg_hcs_params(omap_ehci, "reset");
872 + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase)); 194 dbg_hcc_params(omap_ehci, "reset");
873
874 dbg_hcs_params(omap->ehci, "reset");
875 dbg_hcc_params(omap->ehci, "reset");
876 195
877 /* cache this readonly data; minimize chip reads */ 196 /* cache this readonly data; minimize chip reads */
878 omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params); 197 omap_ehci->hcs_params = readl(&omap_ehci->caps->hcs_params);
879 198
880 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); 199 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
881 if (ret) { 200 if (ret) {
882 dev_err(&pdev->dev, "failed to add hcd with err %d\n", ret); 201 dev_err(dev, "failed to add hcd with err %d\n", ret);
883 goto err_add_hcd; 202 goto err_add_hcd;
884 } 203 }
885 204
886 /* root ports should always stay powered */ 205 /* root ports should always stay powered */
887 ehci_port_power(omap->ehci, 1); 206 ehci_port_power(omap_ehci, 1);
888 207
889 return 0; 208 return 0;
890 209
891err_add_hcd: 210err_add_hcd:
892 omap_stop_ehc(omap, hcd); 211 omap_usbhs_disable(dev);
893 212
894err_start: 213err_enable:
895 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
896 if (omap->regulator[i]) {
897 regulator_disable(omap->regulator[i]);
898 regulator_put(omap->regulator[i]);
899 }
900 }
901 iounmap(omap->tll_base);
902
903err_tll_ioremap:
904 iounmap(omap->uhh_base);
905
906err_uhh_ioremap:
907 iounmap(hcd->regs);
908
909err_ioremap:
910 usb_put_hcd(hcd); 214 usb_put_hcd(hcd);
911 215
912err_create_hcd: 216err_io:
913 kfree(omap);
914err_disabled:
915err_pdata:
916 return ret; 217 return ret;
917} 218}
918 219
919/* may be called without controller electrically present */
920/* may be called with controller, bus, and devices active */
921 220
922/** 221/**
923 * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs 222 * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs
@@ -929,31 +228,18 @@ err_pdata:
929 */ 228 */
930static int ehci_hcd_omap_remove(struct platform_device *pdev) 229static int ehci_hcd_omap_remove(struct platform_device *pdev)
931{ 230{
932 struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); 231 struct device *dev = &pdev->dev;
933 struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); 232 struct usb_hcd *hcd = dev_get_drvdata(dev);
934 int i;
935 233
936 usb_remove_hcd(hcd); 234 usb_remove_hcd(hcd);
937 omap_stop_ehc(omap, hcd); 235 omap_usbhs_disable(dev);
938 iounmap(hcd->regs);
939 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
940 if (omap->regulator[i]) {
941 regulator_disable(omap->regulator[i]);
942 regulator_put(omap->regulator[i]);
943 }
944 }
945 iounmap(omap->tll_base);
946 iounmap(omap->uhh_base);
947 usb_put_hcd(hcd); 236 usb_put_hcd(hcd);
948 kfree(omap);
949
950 return 0; 237 return 0;
951} 238}
952 239
953static void ehci_hcd_omap_shutdown(struct platform_device *pdev) 240static void ehci_hcd_omap_shutdown(struct platform_device *pdev)
954{ 241{
955 struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); 242 struct usb_hcd *hcd = dev_get_drvdata(&pdev->dev);
956 struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
957 243
958 if (hcd->driver->shutdown) 244 if (hcd->driver->shutdown)
959 hcd->driver->shutdown(hcd); 245 hcd->driver->shutdown(hcd);
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index 0f87dc72820a..281e094e1c18 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -105,7 +105,8 @@ static int ehci_orion_setup(struct usb_hcd *hcd)
105 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 105 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
106 int retval; 106 int retval;
107 107
108 ehci_reset(ehci); 108 hcd->has_tt = 1;
109
109 retval = ehci_halt(ehci); 110 retval = ehci_halt(ehci);
110 if (retval) 111 if (retval)
111 return retval; 112 return retval;
@@ -117,7 +118,7 @@ static int ehci_orion_setup(struct usb_hcd *hcd)
117 if (retval) 118 if (retval)
118 return retval; 119 return retval;
119 120
120 hcd->has_tt = 1; 121 ehci_reset(ehci);
121 122
122 ehci_port_power(ehci, 0); 123 ehci_port_power(ehci, 0);
123 124
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 07bb982e59f6..d5eaea7caf89 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -44,42 +44,6 @@ static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
44 return 0; 44 return 0;
45} 45}
46 46
47static int ehci_quirk_amd_hudson(struct ehci_hcd *ehci)
48{
49 struct pci_dev *amd_smbus_dev;
50 u8 rev = 0;
51
52 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
53 if (amd_smbus_dev) {
54 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
55 if (rev < 0x40) {
56 pci_dev_put(amd_smbus_dev);
57 amd_smbus_dev = NULL;
58 return 0;
59 }
60 } else {
61 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x780b, NULL);
62 if (!amd_smbus_dev)
63 return 0;
64 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
65 if (rev < 0x11 || rev > 0x18) {
66 pci_dev_put(amd_smbus_dev);
67 amd_smbus_dev = NULL;
68 return 0;
69 }
70 }
71
72 if (!amd_nb_dev)
73 amd_nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
74
75 ehci_info(ehci, "QUIRK: Enable exception for AMD Hudson ASPM\n");
76
77 pci_dev_put(amd_smbus_dev);
78 amd_smbus_dev = NULL;
79
80 return 1;
81}
82
83/* called during probe() after chip reset completes */ 47/* called during probe() after chip reset completes */
84static int ehci_pci_setup(struct usb_hcd *hcd) 48static int ehci_pci_setup(struct usb_hcd *hcd)
85{ 49{
@@ -138,9 +102,6 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
138 /* cache this readonly data; minimize chip reads */ 102 /* cache this readonly data; minimize chip reads */
139 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 103 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
140 104
141 if (ehci_quirk_amd_hudson(ehci))
142 ehci->amd_l1_fix = 1;
143
144 retval = ehci_halt(ehci); 105 retval = ehci_halt(ehci);
145 if (retval) 106 if (retval)
146 return retval; 107 return retval;
@@ -191,6 +152,9 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
191 } 152 }
192 break; 153 break;
193 case PCI_VENDOR_ID_AMD: 154 case PCI_VENDOR_ID_AMD:
155 /* AMD PLL quirk */
156 if (usb_amd_find_chipset_info())
157 ehci->amd_pll_fix = 1;
194 /* AMD8111 EHCI doesn't work, according to AMD errata */ 158 /* AMD8111 EHCI doesn't work, according to AMD errata */
195 if (pdev->device == 0x7463) { 159 if (pdev->device == 0x7463) {
196 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 160 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
@@ -236,6 +200,9 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
236 } 200 }
237 break; 201 break;
238 case PCI_VENDOR_ID_ATI: 202 case PCI_VENDOR_ID_ATI:
203 /* AMD PLL quirk */
204 if (usb_amd_find_chipset_info())
205 ehci->amd_pll_fix = 1;
239 /* SB600 and old version of SB700 have a bug in EHCI controller, 206 /* SB600 and old version of SB700 have a bug in EHCI controller,
240 * which causes usb devices lose response in some cases. 207 * which causes usb devices lose response in some cases.
241 */ 208 */
diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c
new file mode 100644
index 000000000000..a2168642175b
--- /dev/null
+++ b/drivers/usb/host/ehci-pmcmsp.c
@@ -0,0 +1,383 @@
1/*
2 * PMC MSP EHCI (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 2006-2010 PMC-Sierra Inc
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 */
11
12/* includes */
13#include <linux/platform_device.h>
14#include <linux/gpio.h>
15#include <linux/usb.h>
16#include <msp_usb.h>
17
18/* stream disable*/
19#define USB_CTRL_MODE_STREAM_DISABLE 0x10
20
21/* threshold */
22#define USB_CTRL_FIFO_THRESH 0x00300000
23
24/* register offset for usb_mode */
25#define USB_EHCI_REG_USB_MODE 0x68
26
27/* register offset for usb fifo */
28#define USB_EHCI_REG_USB_FIFO 0x24
29
30/* register offset for usb status */
31#define USB_EHCI_REG_USB_STATUS 0x44
32
33/* serial/parallel transceiver */
34#define USB_EHCI_REG_BIT_STAT_STS (1<<29)
35
36/* TWI USB0 host device pin */
37#define MSP_PIN_USB0_HOST_DEV 49
38
39/* TWI USB1 host device pin */
40#define MSP_PIN_USB1_HOST_DEV 50
41
42
43static void usb_hcd_tdi_set_mode(struct ehci_hcd *ehci)
44{
45 u8 *base;
46 u8 *statreg;
47 u8 *fiforeg;
48 u32 val;
49 struct ehci_regs *reg_base = ehci->regs;
50
51 /* get register base */
52 base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE;
53 statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS;
54 fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO;
55
56 /* Disable controller mode stream */
57 val = ehci_readl(ehci, (u32 *)base);
58 ehci_writel(ehci, (val | USB_CTRL_MODE_STREAM_DISABLE),
59 (u32 *)base);
60
61 /* clear STS to select parallel transceiver interface */
62 val = ehci_readl(ehci, (u32 *)statreg);
63 val = val & ~USB_EHCI_REG_BIT_STAT_STS;
64 ehci_writel(ehci, val, (u32 *)statreg);
65
66 /* write to set the proper fifo threshold */
67 ehci_writel(ehci, USB_CTRL_FIFO_THRESH, (u32 *)fiforeg);
68
69 /* set TWI GPIO USB_HOST_DEV pin high */
70 gpio_direction_output(MSP_PIN_USB0_HOST_DEV, 1);
71#ifdef CONFIG_MSP_HAS_DUAL_USB
72 gpio_direction_output(MSP_PIN_USB1_HOST_DEV, 1);
73#endif
74}
75
76/* called during probe() after chip reset completes */
77static int ehci_msp_setup(struct usb_hcd *hcd)
78{
79 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
80 int retval;
81 ehci->big_endian_mmio = 1;
82 ehci->big_endian_desc = 1;
83
84 ehci->caps = hcd->regs;
85 ehci->regs = hcd->regs +
86 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
87 dbg_hcs_params(ehci, "reset");
88 dbg_hcc_params(ehci, "reset");
89
90 /* cache this readonly data; minimize chip reads */
91 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
92 hcd->has_tt = 1;
93
94 retval = ehci_halt(ehci);
95 if (retval)
96 return retval;
97
98 ehci_reset(ehci);
99
100 /* data structure init */
101 retval = ehci_init(hcd);
102 if (retval)
103 return retval;
104
105 usb_hcd_tdi_set_mode(ehci);
106 ehci_port_power(ehci, 0);
107
108 return retval;
109}
110
111
112/* configure so an HC device and id are always provided
113 * always called with process context; sleeping is OK
114 */
115
116static int usb_hcd_msp_map_regs(struct mspusb_device *dev)
117{
118 struct resource *res;
119 struct platform_device *pdev = &dev->dev;
120 u32 res_len;
121 int retval;
122
123 /* MAB register space */
124 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
125 if (res == NULL)
126 return -ENOMEM;
127 res_len = res->end - res->start + 1;
128 if (!request_mem_region(res->start, res_len, "mab regs"))
129 return -EBUSY;
130
131 dev->mab_regs = ioremap_nocache(res->start, res_len);
132 if (dev->mab_regs == NULL) {
133 retval = -ENOMEM;
134 goto err1;
135 }
136
137 /* MSP USB register space */
138 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
139 if (res == NULL) {
140 retval = -ENOMEM;
141 goto err2;
142 }
143 res_len = res->end - res->start + 1;
144 if (!request_mem_region(res->start, res_len, "usbid regs")) {
145 retval = -EBUSY;
146 goto err2;
147 }
148 dev->usbid_regs = ioremap_nocache(res->start, res_len);
149 if (dev->usbid_regs == NULL) {
150 retval = -ENOMEM;
151 goto err3;
152 }
153
154 return 0;
155err3:
156 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
157 res_len = res->end - res->start + 1;
158 release_mem_region(res->start, res_len);
159err2:
160 iounmap(dev->mab_regs);
161err1:
162 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
163 res_len = res->end - res->start + 1;
164 release_mem_region(res->start, res_len);
165 dev_err(&pdev->dev, "Failed to map non-EHCI regs.\n");
166 return retval;
167}
168
169/**
170 * usb_hcd_msp_probe - initialize PMC MSP-based HCDs
171 * Context: !in_interrupt()
172 *
173 * Allocates basic resources for this USB host controller, and
174 * then invokes the start() method for the HCD associated with it
175 * through the hotplug entry's driver_data.
176 *
177 */
178int usb_hcd_msp_probe(const struct hc_driver *driver,
179 struct platform_device *dev)
180{
181 int retval;
182 struct usb_hcd *hcd;
183 struct resource *res;
184 struct ehci_hcd *ehci ;
185
186 hcd = usb_create_hcd(driver, &dev->dev, "pmcmsp");
187 if (!hcd)
188 return -ENOMEM;
189
190 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
191 if (res == NULL) {
192 pr_debug("No IOMEM resource info for %s.\n", dev->name);
193 retval = -ENOMEM;
194 goto err1;
195 }
196 hcd->rsrc_start = res->start;
197 hcd->rsrc_len = res->end - res->start + 1;
198 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, dev->name)) {
199 retval = -EBUSY;
200 goto err1;
201 }
202 hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len);
203 if (!hcd->regs) {
204 pr_debug("ioremap failed");
205 retval = -ENOMEM;
206 goto err2;
207 }
208
209 res = platform_get_resource(dev, IORESOURCE_IRQ, 0);
210 if (res == NULL) {
211 dev_err(&dev->dev, "No IRQ resource info for %s.\n", dev->name);
212 retval = -ENOMEM;
213 goto err3;
214 }
215
216 /* Map non-EHCI register spaces */
217 retval = usb_hcd_msp_map_regs(to_mspusb_device(dev));
218 if (retval != 0)
219 goto err3;
220
221 ehci = hcd_to_ehci(hcd);
222 ehci->big_endian_mmio = 1;
223 ehci->big_endian_desc = 1;
224
225
226 retval = usb_add_hcd(hcd, res->start, IRQF_SHARED);
227 if (retval == 0)
228 return 0;
229
230 usb_remove_hcd(hcd);
231err3:
232 iounmap(hcd->regs);
233err2:
234 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
235err1:
236 usb_put_hcd(hcd);
237
238 return retval;
239}
240
241
242
243/**
244 * usb_hcd_msp_remove - shutdown processing for PMC MSP-based HCDs
245 * @dev: USB Host Controller being removed
246 * Context: !in_interrupt()
247 *
248 * Reverses the effect of usb_hcd_msp_probe(), first invoking
249 * the HCD's stop() method. It is always called from a thread
250 * context, normally "rmmod", "apmd", or something similar.
251 *
252 * may be called without controller electrically present
253 * may be called with controller, bus, and devices active
254 */
255void usb_hcd_msp_remove(struct usb_hcd *hcd, struct platform_device *dev)
256{
257 usb_remove_hcd(hcd);
258 iounmap(hcd->regs);
259 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
260 usb_put_hcd(hcd);
261}
262
263#ifdef CONFIG_MSP_HAS_DUAL_USB
264/*
265 * Wrapper around the main ehci_irq. Since both USB host controllers are
266 * sharing the same IRQ, need to first determine whether we're the intended
267 * recipient of this interrupt.
268 */
269static irqreturn_t ehci_msp_irq(struct usb_hcd *hcd)
270{
271 u32 int_src;
272 struct device *dev = hcd->self.controller;
273 struct platform_device *pdev;
274 struct mspusb_device *mdev;
275 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
276 /* need to reverse-map a couple of containers to get our device */
277 pdev = to_platform_device(dev);
278 mdev = to_mspusb_device(pdev);
279
280 /* Check to see if this interrupt is for this host controller */
281 int_src = ehci_readl(ehci, &mdev->mab_regs->int_stat);
282 if (int_src & (1 << pdev->id))
283 return ehci_irq(hcd);
284
285 /* Not for this device */
286 return IRQ_NONE;
287}
288#endif /* DUAL_USB */
289
290static const struct hc_driver ehci_msp_hc_driver = {
291 .description = hcd_name,
292 .product_desc = "PMC MSP EHCI",
293 .hcd_priv_size = sizeof(struct ehci_hcd),
294
295 /*
296 * generic hardware linkage
297 */
298#ifdef CONFIG_MSP_HAS_DUAL_USB
299 .irq = ehci_msp_irq,
300#else
301 .irq = ehci_irq,
302#endif
303 .flags = HCD_MEMORY | HCD_USB2,
304
305 /*
306 * basic lifecycle operations
307 */
308 .reset = ehci_msp_setup,
309 .start = ehci_run,
310 .shutdown = ehci_shutdown,
311 .start = ehci_run,
312 .stop = ehci_stop,
313
314 /*
315 * managing i/o requests and associated device resources
316 */
317 .urb_enqueue = ehci_urb_enqueue,
318 .urb_dequeue = ehci_urb_dequeue,
319 .endpoint_disable = ehci_endpoint_disable,
320 .endpoint_reset = ehci_endpoint_reset,
321
322 /*
323 * scheduling support
324 */
325 .get_frame_number = ehci_get_frame,
326
327 /*
328 * root hub support
329 */
330 .hub_status_data = ehci_hub_status_data,
331 .hub_control = ehci_hub_control,
332 .bus_suspend = ehci_bus_suspend,
333 .bus_resume = ehci_bus_resume,
334 .relinquish_port = ehci_relinquish_port,
335 .port_handed_over = ehci_port_handed_over,
336
337 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
338};
339
340static int ehci_hcd_msp_drv_probe(struct platform_device *pdev)
341{
342 int ret;
343
344 pr_debug("In ehci_hcd_msp_drv_probe");
345
346 if (usb_disabled())
347 return -ENODEV;
348
349 gpio_request(MSP_PIN_USB0_HOST_DEV, "USB0_HOST_DEV_GPIO");
350#ifdef CONFIG_MSP_HAS_DUAL_USB
351 gpio_request(MSP_PIN_USB1_HOST_DEV, "USB1_HOST_DEV_GPIO");
352#endif
353
354 ret = usb_hcd_msp_probe(&ehci_msp_hc_driver, pdev);
355
356 return ret;
357}
358
359static int ehci_hcd_msp_drv_remove(struct platform_device *pdev)
360{
361 struct usb_hcd *hcd = platform_get_drvdata(pdev);
362
363 usb_hcd_msp_remove(hcd, pdev);
364
365 /* free TWI GPIO USB_HOST_DEV pin */
366 gpio_free(MSP_PIN_USB0_HOST_DEV);
367#ifdef CONFIG_MSP_HAS_DUAL_USB
368 gpio_free(MSP_PIN_USB1_HOST_DEV);
369#endif
370
371 return 0;
372}
373
374MODULE_ALIAS("pmcmsp-ehci");
375
376static struct platform_driver ehci_hcd_msp_driver = {
377 .probe = ehci_hcd_msp_drv_probe,
378 .remove = ehci_hcd_msp_drv_remove,
379 .driver = {
380 .name = "pmcmsp-ehci",
381 .owner = THIS_MODULE,
382 },
383};
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
index 233c288e3f93..fe99895fb098 100644
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -1107,22 +1107,24 @@ submit_async (
1107 struct list_head *qtd_list, 1107 struct list_head *qtd_list,
1108 gfp_t mem_flags 1108 gfp_t mem_flags
1109) { 1109) {
1110 struct ehci_qtd *qtd;
1111 int epnum; 1110 int epnum;
1112 unsigned long flags; 1111 unsigned long flags;
1113 struct ehci_qh *qh = NULL; 1112 struct ehci_qh *qh = NULL;
1114 int rc; 1113 int rc;
1115 1114
1116 qtd = list_entry (qtd_list->next, struct ehci_qtd, qtd_list);
1117 epnum = urb->ep->desc.bEndpointAddress; 1115 epnum = urb->ep->desc.bEndpointAddress;
1118 1116
1119#ifdef EHCI_URB_TRACE 1117#ifdef EHCI_URB_TRACE
1120 ehci_dbg (ehci, 1118 {
1121 "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", 1119 struct ehci_qtd *qtd;
1122 __func__, urb->dev->devpath, urb, 1120 qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
1123 epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", 1121 ehci_dbg(ehci,
1124 urb->transfer_buffer_length, 1122 "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
1125 qtd, urb->ep->hcpriv); 1123 __func__, urb->dev->devpath, urb,
1124 epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
1125 urb->transfer_buffer_length,
1126 qtd, urb->ep->hcpriv);
1127 }
1126#endif 1128#endif
1127 1129
1128 spin_lock_irqsave (&ehci->lock, flags); 1130 spin_lock_irqsave (&ehci->lock, flags);
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
index aa46f57f9ec8..1543c838b3d1 100644
--- a/drivers/usb/host/ehci-sched.c
+++ b/drivers/usb/host/ehci-sched.c
@@ -1048,8 +1048,6 @@ iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1048 * not like a QH -- no persistent state (toggle, halt) 1048 * not like a QH -- no persistent state (toggle, halt)
1049 */ 1049 */
1050 if (stream->refcount == 1) { 1050 if (stream->refcount == 1) {
1051 int is_in;
1052
1053 // BUG_ON (!list_empty(&stream->td_list)); 1051 // BUG_ON (!list_empty(&stream->td_list));
1054 1052
1055 while (!list_empty (&stream->free_list)) { 1053 while (!list_empty (&stream->free_list)) {
@@ -1076,7 +1074,6 @@ iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1076 } 1074 }
1077 } 1075 }
1078 1076
1079 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1080 stream->bEndpointAddress &= 0x0f; 1077 stream->bEndpointAddress &= 0x0f;
1081 if (stream->ep) 1078 if (stream->ep)
1082 stream->ep->hcpriv = NULL; 1079 stream->ep->hcpriv = NULL;
@@ -1590,63 +1587,6 @@ itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1590 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD); 1587 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1591} 1588}
1592 1589
1593#define AB_REG_BAR_LOW 0xe0
1594#define AB_REG_BAR_HIGH 0xe1
1595#define AB_INDX(addr) ((addr) + 0x00)
1596#define AB_DATA(addr) ((addr) + 0x04)
1597#define NB_PCIE_INDX_ADDR 0xe0
1598#define NB_PCIE_INDX_DATA 0xe4
1599#define NB_PIF0_PWRDOWN_0 0x01100012
1600#define NB_PIF0_PWRDOWN_1 0x01100013
1601
1602static void ehci_quirk_amd_L1(struct ehci_hcd *ehci, int disable)
1603{
1604 u32 addr, addr_low, addr_high, val;
1605
1606 outb_p(AB_REG_BAR_LOW, 0xcd6);
1607 addr_low = inb_p(0xcd7);
1608 outb_p(AB_REG_BAR_HIGH, 0xcd6);
1609 addr_high = inb_p(0xcd7);
1610 addr = addr_high << 8 | addr_low;
1611 outl_p(0x30, AB_INDX(addr));
1612 outl_p(0x40, AB_DATA(addr));
1613 outl_p(0x34, AB_INDX(addr));
1614 val = inl_p(AB_DATA(addr));
1615
1616 if (disable) {
1617 val &= ~0x8;
1618 val |= (1 << 4) | (1 << 9);
1619 } else {
1620 val |= 0x8;
1621 val &= ~((1 << 4) | (1 << 9));
1622 }
1623 outl_p(val, AB_DATA(addr));
1624
1625 if (amd_nb_dev) {
1626 addr = NB_PIF0_PWRDOWN_0;
1627 pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_ADDR, addr);
1628 pci_read_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, &val);
1629 if (disable)
1630 val &= ~(0x3f << 7);
1631 else
1632 val |= 0x3f << 7;
1633
1634 pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, val);
1635
1636 addr = NB_PIF0_PWRDOWN_1;
1637 pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_ADDR, addr);
1638 pci_read_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, &val);
1639 if (disable)
1640 val &= ~(0x3f << 7);
1641 else
1642 val |= 0x3f << 7;
1643
1644 pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, val);
1645 }
1646
1647 return;
1648}
1649
1650/* fit urb's itds into the selected schedule slot; activate as needed */ 1590/* fit urb's itds into the selected schedule slot; activate as needed */
1651static int 1591static int
1652itd_link_urb ( 1592itd_link_urb (
@@ -1675,8 +1615,8 @@ itd_link_urb (
1675 } 1615 }
1676 1616
1677 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { 1617 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1678 if (ehci->amd_l1_fix == 1) 1618 if (ehci->amd_pll_fix == 1)
1679 ehci_quirk_amd_L1(ehci, 1); 1619 usb_amd_quirk_pll_disable();
1680 } 1620 }
1681 1621
1682 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; 1622 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
@@ -1804,8 +1744,8 @@ itd_complete (
1804 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; 1744 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1805 1745
1806 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { 1746 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1807 if (ehci->amd_l1_fix == 1) 1747 if (ehci->amd_pll_fix == 1)
1808 ehci_quirk_amd_L1(ehci, 0); 1748 usb_amd_quirk_pll_enable();
1809 } 1749 }
1810 1750
1811 if (unlikely(list_is_singular(&stream->td_list))) { 1751 if (unlikely(list_is_singular(&stream->td_list))) {
@@ -2095,8 +2035,8 @@ sitd_link_urb (
2095 } 2035 }
2096 2036
2097 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { 2037 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2098 if (ehci->amd_l1_fix == 1) 2038 if (ehci->amd_pll_fix == 1)
2099 ehci_quirk_amd_L1(ehci, 1); 2039 usb_amd_quirk_pll_disable();
2100 } 2040 }
2101 2041
2102 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; 2042 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
@@ -2200,8 +2140,8 @@ sitd_complete (
2200 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; 2140 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2201 2141
2202 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { 2142 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2203 if (ehci->amd_l1_fix == 1) 2143 if (ehci->amd_pll_fix == 1)
2204 ehci_quirk_amd_L1(ehci, 0); 2144 usb_amd_quirk_pll_enable();
2205 } 2145 }
2206 2146
2207 if (list_is_singular(&stream->td_list)) { 2147 if (list_is_singular(&stream->td_list)) {
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
new file mode 100644
index 000000000000..a516af28c29b
--- /dev/null
+++ b/drivers/usb/host/ehci-tegra.c
@@ -0,0 +1,715 @@
1/*
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/platform_device.h>
21#include <linux/platform_data/tegra_usb.h>
22#include <linux/irq.h>
23#include <linux/usb/otg.h>
24#include <mach/usb_phy.h>
25
26#define TEGRA_USB_DMA_ALIGN 32
27
28struct tegra_ehci_hcd {
29 struct ehci_hcd *ehci;
30 struct tegra_usb_phy *phy;
31 struct clk *clk;
32 struct clk *emc_clk;
33 struct otg_transceiver *transceiver;
34 int host_resumed;
35 int bus_suspended;
36 int port_resuming;
37 int power_down_on_bus_suspend;
38 enum tegra_usb_phy_port_speed port_speed;
39};
40
41static void tegra_ehci_power_up(struct usb_hcd *hcd)
42{
43 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
44
45 clk_enable(tegra->emc_clk);
46 clk_enable(tegra->clk);
47 tegra_usb_phy_power_on(tegra->phy);
48 tegra->host_resumed = 1;
49}
50
51static void tegra_ehci_power_down(struct usb_hcd *hcd)
52{
53 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
54
55 tegra->host_resumed = 0;
56 tegra_usb_phy_power_off(tegra->phy);
57 clk_disable(tegra->clk);
58 clk_disable(tegra->emc_clk);
59}
60
61static int tegra_ehci_hub_control(
62 struct usb_hcd *hcd,
63 u16 typeReq,
64 u16 wValue,
65 u16 wIndex,
66 char *buf,
67 u16 wLength
68)
69{
70 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
71 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
72 u32 __iomem *status_reg;
73 u32 temp;
74 unsigned long flags;
75 int retval = 0;
76
77 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
78
79 spin_lock_irqsave(&ehci->lock, flags);
80
81 /*
82 * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
83 * that are write on clear, by writing back the register read value, so
84 * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
85 */
86 if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
87 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
88 ehci_writel(ehci, temp & ~PORT_PE, status_reg);
89 goto done;
90 }
91
92 else if (typeReq == GetPortStatus) {
93 temp = ehci_readl(ehci, status_reg);
94 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
95 /* Resume completed, re-enable disconnect detection */
96 tegra->port_resuming = 0;
97 tegra_usb_phy_postresume(tegra->phy);
98 }
99 }
100
101 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
102 temp = ehci_readl(ehci, status_reg);
103 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
104 retval = -EPIPE;
105 goto done;
106 }
107
108 temp &= ~PORT_WKCONN_E;
109 temp |= PORT_WKDISC_E | PORT_WKOC_E;
110 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
111
112 /*
113 * If a transaction is in progress, there may be a delay in
114 * suspending the port. Poll until the port is suspended.
115 */
116 if (handshake(ehci, status_reg, PORT_SUSPEND,
117 PORT_SUSPEND, 5000))
118 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
119
120 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
121 goto done;
122 }
123
124 /*
125 * Tegra host controller will time the resume operation to clear the bit
126 * when the port control state switches to HS or FS Idle. This behavior
127 * is different from EHCI where the host controller driver is required
128 * to set this bit to a zero after the resume duration is timed in the
129 * driver.
130 */
131 else if (typeReq == ClearPortFeature &&
132 wValue == USB_PORT_FEAT_SUSPEND) {
133 temp = ehci_readl(ehci, status_reg);
134 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
135 retval = -EPIPE;
136 goto done;
137 }
138
139 if (!(temp & PORT_SUSPEND))
140 goto done;
141
142 /* Disable disconnect detection during port resume */
143 tegra_usb_phy_preresume(tegra->phy);
144
145 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
146
147 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
148 /* start resume signalling */
149 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
150
151 spin_unlock_irqrestore(&ehci->lock, flags);
152 msleep(20);
153 spin_lock_irqsave(&ehci->lock, flags);
154
155 /* Poll until the controller clears RESUME and SUSPEND */
156 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
157 pr_err("%s: timeout waiting for RESUME\n", __func__);
158 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
159 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
160
161 ehci->reset_done[wIndex-1] = 0;
162
163 tegra->port_resuming = 1;
164 goto done;
165 }
166
167 spin_unlock_irqrestore(&ehci->lock, flags);
168
169 /* Handle the hub control events here */
170 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
171done:
172 spin_unlock_irqrestore(&ehci->lock, flags);
173 return retval;
174}
175
176static void tegra_ehci_restart(struct usb_hcd *hcd)
177{
178 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
179
180 ehci_reset(ehci);
181
182 /* setup the frame list and Async q heads */
183 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
184 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
185 /* setup the command register and set the controller in RUN mode */
186 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
187 ehci->command |= CMD_RUN;
188 ehci_writel(ehci, ehci->command, &ehci->regs->command);
189
190 down_write(&ehci_cf_port_reset_rwsem);
191 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
192 /* flush posted writes */
193 ehci_readl(ehci, &ehci->regs->command);
194 up_write(&ehci_cf_port_reset_rwsem);
195}
196
197static int tegra_usb_suspend(struct usb_hcd *hcd)
198{
199 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
200 struct ehci_regs __iomem *hw = tegra->ehci->regs;
201 unsigned long flags;
202
203 spin_lock_irqsave(&tegra->ehci->lock, flags);
204
205 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
206 ehci_halt(tegra->ehci);
207 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
208
209 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
210
211 tegra_ehci_power_down(hcd);
212 return 0;
213}
214
215static int tegra_usb_resume(struct usb_hcd *hcd)
216{
217 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
218 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
219 struct ehci_regs __iomem *hw = ehci->regs;
220 unsigned long val;
221
222 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
223 tegra_ehci_power_up(hcd);
224
225 if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
226 /* Wait for the phy to detect new devices
227 * before we restart the controller */
228 msleep(10);
229 goto restart;
230 }
231
232 /* Force the phy to keep data lines in suspend state */
233 tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
234
235 /* Enable host mode */
236 tdi_reset(ehci);
237
238 /* Enable Port Power */
239 val = readl(&hw->port_status[0]);
240 val |= PORT_POWER;
241 writel(val, &hw->port_status[0]);
242 udelay(10);
243
244 /* Check if the phy resume from LP0. When the phy resume from LP0
245 * USB register will be reset. */
246 if (!readl(&hw->async_next)) {
247 /* Program the field PTC based on the saved speed mode */
248 val = readl(&hw->port_status[0]);
249 val &= ~PORT_TEST(~0);
250 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
251 val |= PORT_TEST_FORCE;
252 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
253 val |= PORT_TEST(6);
254 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
255 val |= PORT_TEST(7);
256 writel(val, &hw->port_status[0]);
257 udelay(10);
258
259 /* Disable test mode by setting PTC field to NORMAL_OP */
260 val = readl(&hw->port_status[0]);
261 val &= ~PORT_TEST(~0);
262 writel(val, &hw->port_status[0]);
263 udelay(10);
264 }
265
266 /* Poll until CCS is enabled */
267 if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
268 PORT_CONNECT, 2000)) {
269 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
270 goto restart;
271 }
272
273 /* Poll until PE is enabled */
274 if (handshake(ehci, &hw->port_status[0], PORT_PE,
275 PORT_PE, 2000)) {
276 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
277 goto restart;
278 }
279
280 /* Clear the PCI status, to avoid an interrupt taken upon resume */
281 val = readl(&hw->status);
282 val |= STS_PCD;
283 writel(val, &hw->status);
284
285 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
286 val = readl(&hw->port_status[0]);
287 if ((val & PORT_POWER) && (val & PORT_PE)) {
288 val |= PORT_SUSPEND;
289 writel(val, &hw->port_status[0]);
290
291 /* Wait until port suspend completes */
292 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
293 PORT_SUSPEND, 1000)) {
294 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
295 __func__);
296 goto restart;
297 }
298 }
299
300 tegra_ehci_phy_restore_end(tegra->phy);
301 return 0;
302
303restart:
304 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
305 tegra_ehci_phy_restore_end(tegra->phy);
306
307 tegra_ehci_restart(hcd);
308 return 0;
309}
310
311static void tegra_ehci_shutdown(struct usb_hcd *hcd)
312{
313 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
314
315 /* ehci_shutdown touches the USB controller registers, make sure
316 * controller has clocks to it */
317 if (!tegra->host_resumed)
318 tegra_ehci_power_up(hcd);
319
320 ehci_shutdown(hcd);
321}
322
323static int tegra_ehci_setup(struct usb_hcd *hcd)
324{
325 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
326 int retval;
327
328 /* EHCI registers start at offset 0x100 */
329 ehci->caps = hcd->regs + 0x100;
330 ehci->regs = hcd->regs + 0x100 +
331 HC_LENGTH(readl(&ehci->caps->hc_capbase));
332
333 dbg_hcs_params(ehci, "reset");
334 dbg_hcc_params(ehci, "reset");
335
336 /* cache this readonly data; minimize chip reads */
337 ehci->hcs_params = readl(&ehci->caps->hcs_params);
338
339 /* switch to host mode */
340 hcd->has_tt = 1;
341 ehci_reset(ehci);
342
343 retval = ehci_halt(ehci);
344 if (retval)
345 return retval;
346
347 /* data structure init */
348 retval = ehci_init(hcd);
349 if (retval)
350 return retval;
351
352 ehci->sbrn = 0x20;
353
354 ehci_port_power(ehci, 1);
355 return retval;
356}
357
358#ifdef CONFIG_PM
359static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
360{
361 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
362 int error_status = 0;
363
364 error_status = ehci_bus_suspend(hcd);
365 if (!error_status && tegra->power_down_on_bus_suspend) {
366 tegra_usb_suspend(hcd);
367 tegra->bus_suspended = 1;
368 }
369
370 return error_status;
371}
372
373static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
374{
375 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
376
377 if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
378 tegra_usb_resume(hcd);
379 tegra->bus_suspended = 0;
380 }
381
382 tegra_usb_phy_preresume(tegra->phy);
383 tegra->port_resuming = 1;
384 return ehci_bus_resume(hcd);
385}
386#endif
387
388struct temp_buffer {
389 void *kmalloc_ptr;
390 void *old_xfer_buffer;
391 u8 data[0];
392};
393
394static void free_temp_buffer(struct urb *urb)
395{
396 enum dma_data_direction dir;
397 struct temp_buffer *temp;
398
399 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
400 return;
401
402 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
403
404 temp = container_of(urb->transfer_buffer, struct temp_buffer,
405 data);
406
407 if (dir == DMA_FROM_DEVICE)
408 memcpy(temp->old_xfer_buffer, temp->data,
409 urb->transfer_buffer_length);
410 urb->transfer_buffer = temp->old_xfer_buffer;
411 kfree(temp->kmalloc_ptr);
412
413 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
414}
415
416static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
417{
418 enum dma_data_direction dir;
419 struct temp_buffer *temp, *kmalloc_ptr;
420 size_t kmalloc_size;
421
422 if (urb->num_sgs || urb->sg ||
423 urb->transfer_buffer_length == 0 ||
424 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
425 return 0;
426
427 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
428
429 /* Allocate a buffer with enough padding for alignment */
430 kmalloc_size = urb->transfer_buffer_length +
431 sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1;
432
433 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
434 if (!kmalloc_ptr)
435 return -ENOMEM;
436
437 /* Position our struct temp_buffer such that data is aligned */
438 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
439
440 temp->kmalloc_ptr = kmalloc_ptr;
441 temp->old_xfer_buffer = urb->transfer_buffer;
442 if (dir == DMA_TO_DEVICE)
443 memcpy(temp->data, urb->transfer_buffer,
444 urb->transfer_buffer_length);
445 urb->transfer_buffer = temp->data;
446
447 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
448
449 return 0;
450}
451
452static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
453 gfp_t mem_flags)
454{
455 int ret;
456
457 ret = alloc_temp_buffer(urb, mem_flags);
458 if (ret)
459 return ret;
460
461 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
462 if (ret)
463 free_temp_buffer(urb);
464
465 return ret;
466}
467
468static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
469{
470 usb_hcd_unmap_urb_for_dma(hcd, urb);
471 free_temp_buffer(urb);
472}
473
474static const struct hc_driver tegra_ehci_hc_driver = {
475 .description = hcd_name,
476 .product_desc = "Tegra EHCI Host Controller",
477 .hcd_priv_size = sizeof(struct ehci_hcd),
478
479 .flags = HCD_USB2 | HCD_MEMORY,
480
481 .reset = tegra_ehci_setup,
482 .irq = ehci_irq,
483
484 .start = ehci_run,
485 .stop = ehci_stop,
486 .shutdown = tegra_ehci_shutdown,
487 .urb_enqueue = ehci_urb_enqueue,
488 .urb_dequeue = ehci_urb_dequeue,
489 .map_urb_for_dma = tegra_ehci_map_urb_for_dma,
490 .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma,
491 .endpoint_disable = ehci_endpoint_disable,
492 .endpoint_reset = ehci_endpoint_reset,
493 .get_frame_number = ehci_get_frame,
494 .hub_status_data = ehci_hub_status_data,
495 .hub_control = tegra_ehci_hub_control,
496 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
497#ifdef CONFIG_PM
498 .bus_suspend = tegra_ehci_bus_suspend,
499 .bus_resume = tegra_ehci_bus_resume,
500#endif
501 .relinquish_port = ehci_relinquish_port,
502 .port_handed_over = ehci_port_handed_over,
503};
504
505static int tegra_ehci_probe(struct platform_device *pdev)
506{
507 struct resource *res;
508 struct usb_hcd *hcd;
509 struct tegra_ehci_hcd *tegra;
510 struct tegra_ehci_platform_data *pdata;
511 int err = 0;
512 int irq;
513 int instance = pdev->id;
514
515 pdata = pdev->dev.platform_data;
516 if (!pdata) {
517 dev_err(&pdev->dev, "Platform data missing\n");
518 return -EINVAL;
519 }
520
521 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
522 if (!tegra)
523 return -ENOMEM;
524
525 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
526 dev_name(&pdev->dev));
527 if (!hcd) {
528 dev_err(&pdev->dev, "Unable to create HCD\n");
529 err = -ENOMEM;
530 goto fail_hcd;
531 }
532
533 platform_set_drvdata(pdev, tegra);
534
535 tegra->clk = clk_get(&pdev->dev, NULL);
536 if (IS_ERR(tegra->clk)) {
537 dev_err(&pdev->dev, "Can't get ehci clock\n");
538 err = PTR_ERR(tegra->clk);
539 goto fail_clk;
540 }
541
542 err = clk_enable(tegra->clk);
543 if (err)
544 goto fail_clken;
545
546 tegra->emc_clk = clk_get(&pdev->dev, "emc");
547 if (IS_ERR(tegra->emc_clk)) {
548 dev_err(&pdev->dev, "Can't get emc clock\n");
549 err = PTR_ERR(tegra->emc_clk);
550 goto fail_emc_clk;
551 }
552
553 clk_enable(tegra->emc_clk);
554 clk_set_rate(tegra->emc_clk, 400000000);
555
556 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
557 if (!res) {
558 dev_err(&pdev->dev, "Failed to get I/O memory\n");
559 err = -ENXIO;
560 goto fail_io;
561 }
562 hcd->rsrc_start = res->start;
563 hcd->rsrc_len = resource_size(res);
564 hcd->regs = ioremap(res->start, resource_size(res));
565 if (!hcd->regs) {
566 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
567 err = -ENOMEM;
568 goto fail_io;
569 }
570
571 tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
572 TEGRA_USB_PHY_MODE_HOST);
573 if (IS_ERR(tegra->phy)) {
574 dev_err(&pdev->dev, "Failed to open USB phy\n");
575 err = -ENXIO;
576 goto fail_phy;
577 }
578
579 err = tegra_usb_phy_power_on(tegra->phy);
580 if (err) {
581 dev_err(&pdev->dev, "Failed to power on the phy\n");
582 goto fail;
583 }
584
585 tegra->host_resumed = 1;
586 tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
587 tegra->ehci = hcd_to_ehci(hcd);
588
589 irq = platform_get_irq(pdev, 0);
590 if (!irq) {
591 dev_err(&pdev->dev, "Failed to get IRQ\n");
592 err = -ENODEV;
593 goto fail;
594 }
595 set_irq_flags(irq, IRQF_VALID);
596
597#ifdef CONFIG_USB_OTG_UTILS
598 if (pdata->operating_mode == TEGRA_USB_OTG) {
599 tegra->transceiver = otg_get_transceiver();
600 if (tegra->transceiver)
601 otg_set_host(tegra->transceiver, &hcd->self);
602 }
603#endif
604
605 err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
606 if (err) {
607 dev_err(&pdev->dev, "Failed to add USB HCD\n");
608 goto fail;
609 }
610
611 return err;
612
613fail:
614#ifdef CONFIG_USB_OTG_UTILS
615 if (tegra->transceiver) {
616 otg_set_host(tegra->transceiver, NULL);
617 otg_put_transceiver(tegra->transceiver);
618 }
619#endif
620 tegra_usb_phy_close(tegra->phy);
621fail_phy:
622 iounmap(hcd->regs);
623fail_io:
624 clk_disable(tegra->emc_clk);
625 clk_put(tegra->emc_clk);
626fail_emc_clk:
627 clk_disable(tegra->clk);
628fail_clken:
629 clk_put(tegra->clk);
630fail_clk:
631 usb_put_hcd(hcd);
632fail_hcd:
633 kfree(tegra);
634 return err;
635}
636
637#ifdef CONFIG_PM
638static int tegra_ehci_resume(struct platform_device *pdev)
639{
640 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
641 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
642
643 if (tegra->bus_suspended)
644 return 0;
645
646 return tegra_usb_resume(hcd);
647}
648
649static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
650{
651 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
652 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
653
654 if (tegra->bus_suspended)
655 return 0;
656
657 if (time_before(jiffies, tegra->ehci->next_statechange))
658 msleep(10);
659
660 return tegra_usb_suspend(hcd);
661}
662#endif
663
664static int tegra_ehci_remove(struct platform_device *pdev)
665{
666 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
667 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
668
669 if (tegra == NULL || hcd == NULL)
670 return -EINVAL;
671
672#ifdef CONFIG_USB_OTG_UTILS
673 if (tegra->transceiver) {
674 otg_set_host(tegra->transceiver, NULL);
675 otg_put_transceiver(tegra->transceiver);
676 }
677#endif
678
679 usb_remove_hcd(hcd);
680 usb_put_hcd(hcd);
681
682 tegra_usb_phy_close(tegra->phy);
683 iounmap(hcd->regs);
684
685 clk_disable(tegra->clk);
686 clk_put(tegra->clk);
687
688 clk_disable(tegra->emc_clk);
689 clk_put(tegra->emc_clk);
690
691 kfree(tegra);
692 return 0;
693}
694
695static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
696{
697 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
698 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
699
700 if (hcd->driver->shutdown)
701 hcd->driver->shutdown(hcd);
702}
703
704static struct platform_driver tegra_ehci_driver = {
705 .probe = tegra_ehci_probe,
706 .remove = tegra_ehci_remove,
707#ifdef CONFIG_PM
708 .suspend = tegra_ehci_suspend,
709 .resume = tegra_ehci_resume,
710#endif
711 .shutdown = tegra_ehci_hcd_shutdown,
712 .driver = {
713 .name = "tegra-ehci",
714 }
715};
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 799ac16a54b4..f86d3fa20214 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -131,7 +131,7 @@ struct ehci_hcd { /* one per controller */
131 unsigned has_amcc_usb23:1; 131 unsigned has_amcc_usb23:1;
132 unsigned need_io_watchdog:1; 132 unsigned need_io_watchdog:1;
133 unsigned broken_periodic:1; 133 unsigned broken_periodic:1;
134 unsigned amd_l1_fix:1; 134 unsigned amd_pll_fix:1;
135 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 135 unsigned fs_i_thresh:1; /* Intel iso scheduling */
136 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 136 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
137 137
diff --git a/drivers/usb/host/imx21-hcd.c b/drivers/usb/host/imx21-hcd.c
index f90d003f2302..2562e92e3178 100644
--- a/drivers/usb/host/imx21-hcd.c
+++ b/drivers/usb/host/imx21-hcd.c
@@ -927,7 +927,8 @@ static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb)
927 if (state == US_CTRL_SETUP) { 927 if (state == US_CTRL_SETUP) {
928 dir = TD_DIR_SETUP; 928 dir = TD_DIR_SETUP;
929 if (unsuitable_for_dma(urb->setup_dma)) 929 if (unsuitable_for_dma(urb->setup_dma))
930 unmap_urb_setup_for_dma(imx21->hcd, urb); 930 usb_hcd_unmap_urb_setup_for_dma(imx21->hcd,
931 urb);
931 etd->dma_handle = urb->setup_dma; 932 etd->dma_handle = urb->setup_dma;
932 etd->cpu_buffer = urb->setup_packet; 933 etd->cpu_buffer = urb->setup_packet;
933 bufround = 0; 934 bufround = 0;
@@ -943,7 +944,7 @@ static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb)
943 dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN; 944 dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN;
944 bufround = (dir == TD_DIR_IN) ? 1 : 0; 945 bufround = (dir == TD_DIR_IN) ? 1 : 0;
945 if (unsuitable_for_dma(urb->transfer_dma)) 946 if (unsuitable_for_dma(urb->transfer_dma))
946 unmap_urb_for_dma(imx21->hcd, urb); 947 usb_hcd_unmap_urb_for_dma(imx21->hcd, urb);
947 948
948 etd->dma_handle = urb->transfer_dma; 949 etd->dma_handle = urb->transfer_dma;
949 etd->cpu_buffer = urb->transfer_buffer; 950 etd->cpu_buffer = urb->transfer_buffer;
@@ -1471,8 +1472,8 @@ static int get_hub_descriptor(struct usb_hcd *hcd,
1471 0x0010 | /* No over current protection */ 1472 0x0010 | /* No over current protection */
1472 0); 1473 0);
1473 1474
1474 desc->bitmap[0] = 1 << 1; 1475 desc->u.hs.DeviceRemovable[0] = 1 << 1;
1475 desc->bitmap[1] = ~0; 1476 desc->u.hs.DeviceRemovable[1] = ~0;
1476 return 0; 1477 return 0;
1477} 1478}
1478 1479
diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
index 0da7fc05f453..c0e22f26da19 100644
--- a/drivers/usb/host/isp116x-hcd.c
+++ b/drivers/usb/host/isp116x-hcd.c
@@ -951,9 +951,9 @@ static void isp116x_hub_descriptor(struct isp116x *isp116x,
951 /* Power switching, device type, overcurrent. */ 951 /* Power switching, device type, overcurrent. */
952 desc->wHubCharacteristics = cpu_to_le16((u16) ((reg >> 8) & 0x1f)); 952 desc->wHubCharacteristics = cpu_to_le16((u16) ((reg >> 8) & 0x1f));
953 desc->bPwrOn2PwrGood = (u8) ((reg >> 24) & 0xff); 953 desc->bPwrOn2PwrGood = (u8) ((reg >> 24) & 0xff);
954 /* two bitmaps: ports removable, and legacy PortPwrCtrlMask */ 954 /* ports removable, and legacy PortPwrCtrlMask */
955 desc->bitmap[0] = 0; 955 desc->u.hs.DeviceRemovable[0] = 0;
956 desc->bitmap[1] = ~0; 956 desc->u.hs.DeviceRemovable[1] = ~0;
957} 957}
958 958
959/* Perform reset of a given port. 959/* Perform reset of a given port.
diff --git a/drivers/usb/host/isp1362-hcd.c b/drivers/usb/host/isp1362-hcd.c
index 43a39eb56cc6..662cd002adfc 100644
--- a/drivers/usb/host/isp1362-hcd.c
+++ b/drivers/usb/host/isp1362-hcd.c
@@ -226,7 +226,6 @@ static int claim_ptd_buffers(struct isp1362_ep_queue *epq,
226 226
227static inline void release_ptd_buffers(struct isp1362_ep_queue *epq, struct isp1362_ep *ep) 227static inline void release_ptd_buffers(struct isp1362_ep_queue *epq, struct isp1362_ep *ep)
228{ 228{
229 int index = ep->ptd_index;
230 int last = ep->ptd_index + ep->num_ptds; 229 int last = ep->ptd_index + ep->num_ptds;
231 230
232 if (last > epq->buf_count) 231 if (last > epq->buf_count)
@@ -236,10 +235,8 @@ static inline void release_ptd_buffers(struct isp1362_ep_queue *epq, struct isp1
236 epq->buf_map, epq->skip_map); 235 epq->buf_map, epq->skip_map);
237 BUG_ON(last > epq->buf_count); 236 BUG_ON(last > epq->buf_count);
238 237
239 for (; index < last; index++) { 238 bitmap_clear(&epq->buf_map, ep->ptd_index, ep->num_ptds);
240 __clear_bit(index, &epq->buf_map); 239 bitmap_set(&epq->skip_map, ep->ptd_index, ep->num_ptds);
241 __set_bit(index, &epq->skip_map);
242 }
243 epq->buf_avail += ep->num_ptds; 240 epq->buf_avail += ep->num_ptds;
244 epq->ptd_count--; 241 epq->ptd_count--;
245 242
@@ -1555,9 +1552,9 @@ static void isp1362_hub_descriptor(struct isp1362_hcd *isp1362_hcd,
1555 desc->wHubCharacteristics = cpu_to_le16((reg >> 8) & 0x1f); 1552 desc->wHubCharacteristics = cpu_to_le16((reg >> 8) & 0x1f);
1556 DBG(0, "%s: hubcharacteristics = %02x\n", __func__, cpu_to_le16((reg >> 8) & 0x1f)); 1553 DBG(0, "%s: hubcharacteristics = %02x\n", __func__, cpu_to_le16((reg >> 8) & 0x1f));
1557 desc->bPwrOn2PwrGood = (reg >> 24) & 0xff; 1554 desc->bPwrOn2PwrGood = (reg >> 24) & 0xff;
1558 /* two bitmaps: ports removable, and legacy PortPwrCtrlMask */ 1555 /* ports removable, and legacy PortPwrCtrlMask */
1559 desc->bitmap[0] = desc->bNbrPorts == 1 ? 1 << 1 : 3 << 1; 1556 desc->u.hs.DeviceRemovable[0] = desc->bNbrPorts == 1 ? 1 << 1 : 3 << 1;
1560 desc->bitmap[1] = ~0; 1557 desc->u.hs.DeviceRemovable[1] = ~0;
1561 1558
1562 DBG(3, "%s: exit\n", __func__); 1559 DBG(3, "%s: exit\n", __func__);
1563} 1560}
diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c
index bdba8c5d844a..f50e84ac570a 100644
--- a/drivers/usb/host/isp1760-hcd.c
+++ b/drivers/usb/host/isp1760-hcd.c
@@ -33,6 +33,7 @@ struct isp1760_hcd {
33 struct inter_packet_info atl_ints[32]; 33 struct inter_packet_info atl_ints[32];
34 struct inter_packet_info int_ints[32]; 34 struct inter_packet_info int_ints[32];
35 struct memory_chunk memory_pool[BLOCKS]; 35 struct memory_chunk memory_pool[BLOCKS];
36 u32 atl_queued;
36 37
37 /* periodic schedule support */ 38 /* periodic schedule support */
38#define DEFAULT_I_TDPS 1024 39#define DEFAULT_I_TDPS 1024
@@ -47,10 +48,6 @@ static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
47{ 48{
48 return (struct isp1760_hcd *) (hcd->hcd_priv); 49 return (struct isp1760_hcd *) (hcd->hcd_priv);
49} 50}
50static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
51{
52 return container_of((void *) priv, struct usb_hcd, hcd_priv);
53}
54 51
55/* Section 2.2 Host Controller Capability Registers */ 52/* Section 2.2 Host Controller Capability Registers */
56#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 53#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
@@ -80,11 +77,10 @@ static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
80#define PORT_RWC_BITS (PORT_CSC) 77#define PORT_RWC_BITS (PORT_CSC)
81 78
82struct isp1760_qtd { 79struct isp1760_qtd {
83 struct isp1760_qtd *hw_next;
84 u8 packet_type; 80 u8 packet_type;
85 u8 toggle;
86
87 void *data_buffer; 81 void *data_buffer;
82 u32 payload_addr;
83
88 /* the rest is HCD-private */ 84 /* the rest is HCD-private */
89 struct list_head qtd_list; 85 struct list_head qtd_list;
90 struct urb *urb; 86 struct urb *urb;
@@ -92,205 +88,267 @@ struct isp1760_qtd {
92 88
93 /* isp special*/ 89 /* isp special*/
94 u32 status; 90 u32 status;
95#define URB_COMPLETE_NOTIFY (1 << 0)
96#define URB_ENQUEUED (1 << 1) 91#define URB_ENQUEUED (1 << 1)
97#define URB_TYPE_ATL (1 << 2)
98#define URB_TYPE_INT (1 << 3)
99}; 92};
100 93
101struct isp1760_qh { 94struct isp1760_qh {
102 /* first part defined by EHCI spec */ 95 /* first part defined by EHCI spec */
103 struct list_head qtd_list; 96 struct list_head qtd_list;
104 struct isp1760_hcd *priv;
105
106 /* periodic schedule info */
107 unsigned short period; /* polling interval */
108 struct usb_device *dev;
109 97
110 u32 toggle; 98 u32 toggle;
111 u32 ping; 99 u32 ping;
112}; 100};
113 101
114#define ehci_port_speed(priv, portsc) USB_PORT_STAT_HIGH_SPEED 102/*
115 103 * Access functions for isp176x registers (addresses 0..0x03FF).
116static unsigned int isp1760_readl(__u32 __iomem *regs) 104 */
105static u32 reg_read32(void __iomem *base, u32 reg)
117{ 106{
118 return readl(regs); 107 return readl(base + reg);
119} 108}
120 109
121static void isp1760_writel(const unsigned int val, __u32 __iomem *regs) 110static void reg_write32(void __iomem *base, u32 reg, u32 val)
122{ 111{
123 writel(val, regs); 112 writel(val, base + reg);
124} 113}
125 114
126/* 115/*
127 * The next two copy via MMIO data to/from the device. memcpy_{to|from}io() 116 * Access functions for isp176x memory (offset >= 0x0400).
117 *
118 * bank_reads8() reads memory locations prefetched by an earlier write to
119 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
120 * bank optimizations, you should use the more generic mem_reads8() below.
121 *
122 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
123 * below.
124 *
125 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
128 * doesn't quite work because some people have to enforce 32-bit access 126 * doesn't quite work because some people have to enforce 32-bit access
129 */ 127 */
130static void priv_read_copy(struct isp1760_hcd *priv, u32 *src, 128static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
131 __u32 __iomem *dst, u32 len) 129 __u32 *dst, u32 bytes)
132{ 130{
131 __u32 __iomem *src;
133 u32 val; 132 u32 val;
134 u8 *buff8; 133 __u8 *src_byteptr;
134 __u8 *dst_byteptr;
135 135
136 if (!src) { 136 src = src_base + (bank_addr | src_offset);
137 printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
138 return;
139 }
140 137
141 while (len >= 4) { 138 if (src_offset < PAYLOAD_OFFSET) {
142 *src = __raw_readl(dst); 139 while (bytes >= 4) {
143 len -= 4; 140 *dst = le32_to_cpu(__raw_readl(src));
144 src++; 141 bytes -= 4;
145 dst++; 142 src++;
143 dst++;
144 }
145 } else {
146 while (bytes >= 4) {
147 *dst = __raw_readl(src);
148 bytes -= 4;
149 src++;
150 dst++;
151 }
146 } 152 }
147 153
148 if (!len) 154 if (!bytes)
149 return; 155 return;
150 156
151 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully 157 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
152 * allocated. 158 * allocated.
153 */ 159 */
154 val = isp1760_readl(dst); 160 if (src_offset < PAYLOAD_OFFSET)
155 161 val = le32_to_cpu(__raw_readl(src));
156 buff8 = (u8 *)src; 162 else
157 while (len) { 163 val = __raw_readl(src);
158 164
159 *buff8 = val; 165 dst_byteptr = (void *) dst;
160 val >>= 8; 166 src_byteptr = (void *) &val;
161 len--; 167 while (bytes > 0) {
162 buff8++; 168 *dst_byteptr = *src_byteptr;
169 dst_byteptr++;
170 src_byteptr++;
171 bytes--;
163 } 172 }
164} 173}
165 174
166static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src, 175static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
167 __u32 __iomem *dst, u32 len) 176 u32 bytes)
168{ 177{
169 while (len >= 4) { 178 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
170 __raw_writel(*src, dst); 179 ndelay(90);
171 len -= 4; 180 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
172 src++; 181}
173 dst++; 182
183static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
184 __u32 const *src, u32 bytes)
185{
186 __u32 __iomem *dst;
187
188 dst = dst_base + dst_offset;
189
190 if (dst_offset < PAYLOAD_OFFSET) {
191 while (bytes >= 4) {
192 __raw_writel(cpu_to_le32(*src), dst);
193 bytes -= 4;
194 src++;
195 dst++;
196 }
197 } else {
198 while (bytes >= 4) {
199 __raw_writel(*src, dst);
200 bytes -= 4;
201 src++;
202 dst++;
203 }
174 } 204 }
175 205
176 if (!len) 206 if (!bytes)
177 return; 207 return;
178 /* in case we have 3, 2 or 1 by left. The buffer is allocated and the 208 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
179 * extra bytes should not be read by the HW 209 * extra bytes should not be read by the HW.
180 */ 210 */
181 211
182 __raw_writel(*src, dst); 212 if (dst_offset < PAYLOAD_OFFSET)
213 __raw_writel(cpu_to_le32(*src), dst);
214 else
215 __raw_writel(*src, dst);
216}
217
218/*
219 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
220 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
221 */
222static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
223 struct ptd *ptd)
224{
225 reg_write32(base, HC_MEMORY_REG,
226 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
227 ndelay(90);
228 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
229 (void *) ptd, sizeof(*ptd));
230}
231
232static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
233 struct ptd *ptd)
234{
235 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
236 &ptd->dw1, 7*sizeof(ptd->dw1));
237 /* Make sure dw0 gets written last (after other dw's and after payload)
238 since it contains the enable bit */
239 wmb();
240 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
241 sizeof(ptd->dw0));
183} 242}
184 243
244
185/* memory management of the 60kb on the chip from 0x1000 to 0xffff */ 245/* memory management of the 60kb on the chip from 0x1000 to 0xffff */
186static void init_memory(struct isp1760_hcd *priv) 246static void init_memory(struct isp1760_hcd *priv)
187{ 247{
188 int i; 248 int i, curr;
189 u32 payload; 249 u32 payload_addr;
190 250
191 payload = 0x1000; 251 payload_addr = PAYLOAD_OFFSET;
192 for (i = 0; i < BLOCK_1_NUM; i++) { 252 for (i = 0; i < BLOCK_1_NUM; i++) {
193 priv->memory_pool[i].start = payload; 253 priv->memory_pool[i].start = payload_addr;
194 priv->memory_pool[i].size = BLOCK_1_SIZE; 254 priv->memory_pool[i].size = BLOCK_1_SIZE;
195 priv->memory_pool[i].free = 1; 255 priv->memory_pool[i].free = 1;
196 payload += priv->memory_pool[i].size; 256 payload_addr += priv->memory_pool[i].size;
197 } 257 }
198 258
199 259 curr = i;
200 for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) { 260 for (i = 0; i < BLOCK_2_NUM; i++) {
201 priv->memory_pool[i].start = payload; 261 priv->memory_pool[curr + i].start = payload_addr;
202 priv->memory_pool[i].size = BLOCK_2_SIZE; 262 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
203 priv->memory_pool[i].free = 1; 263 priv->memory_pool[curr + i].free = 1;
204 payload += priv->memory_pool[i].size; 264 payload_addr += priv->memory_pool[curr + i].size;
205 } 265 }
206 266
207 267 curr = i;
208 for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) { 268 for (i = 0; i < BLOCK_3_NUM; i++) {
209 priv->memory_pool[i].start = payload; 269 priv->memory_pool[curr + i].start = payload_addr;
210 priv->memory_pool[i].size = BLOCK_3_SIZE; 270 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
211 priv->memory_pool[i].free = 1; 271 priv->memory_pool[curr + i].free = 1;
212 payload += priv->memory_pool[i].size; 272 payload_addr += priv->memory_pool[curr + i].size;
213 } 273 }
214 274
215 BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE); 275 BUG_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
216} 276}
217 277
218static u32 alloc_mem(struct isp1760_hcd *priv, u32 size) 278static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
219{ 279{
280 struct isp1760_hcd *priv = hcd_to_priv(hcd);
220 int i; 281 int i;
221 282
222 if (!size) 283 BUG_ON(qtd->payload_addr);
223 return ISP1760_NULL_POINTER; 284
285 if (!qtd->length)
286 return;
224 287
225 for (i = 0; i < BLOCKS; i++) { 288 for (i = 0; i < BLOCKS; i++) {
226 if (priv->memory_pool[i].size >= size && 289 if (priv->memory_pool[i].size >= qtd->length &&
227 priv->memory_pool[i].free) { 290 priv->memory_pool[i].free) {
228
229 priv->memory_pool[i].free = 0; 291 priv->memory_pool[i].free = 0;
230 return priv->memory_pool[i].start; 292 qtd->payload_addr = priv->memory_pool[i].start;
293 return;
231 } 294 }
232 } 295 }
233 296
234 printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n", 297 dev_err(hcd->self.controller,
235 size); 298 "%s: Can not allocate %lu bytes of memory\n"
236 printk(KERN_ERR "Current memory map:\n"); 299 "Current memory map:\n",
300 __func__, qtd->length);
237 for (i = 0; i < BLOCKS; i++) { 301 for (i = 0; i < BLOCKS; i++) {
238 printk(KERN_ERR "Pool %2d size %4d status: %d\n", 302 dev_err(hcd->self.controller, "Pool %2d size %4d status: %d\n",
239 i, priv->memory_pool[i].size, 303 i, priv->memory_pool[i].size,
240 priv->memory_pool[i].free); 304 priv->memory_pool[i].free);
241 } 305 }
242 /* XXX maybe -ENOMEM could be possible */ 306 /* XXX maybe -ENOMEM could be possible */
243 BUG(); 307 BUG();
244 return 0; 308 return;
245} 309}
246 310
247static void free_mem(struct isp1760_hcd *priv, u32 mem) 311static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
248{ 312{
313 struct isp1760_hcd *priv = hcd_to_priv(hcd);
249 int i; 314 int i;
250 315
251 if (mem == ISP1760_NULL_POINTER) 316 if (!qtd->payload_addr)
252 return; 317 return;
253 318
254 for (i = 0; i < BLOCKS; i++) { 319 for (i = 0; i < BLOCKS; i++) {
255 if (priv->memory_pool[i].start == mem) { 320 if (priv->memory_pool[i].start == qtd->payload_addr) {
256
257 BUG_ON(priv->memory_pool[i].free); 321 BUG_ON(priv->memory_pool[i].free);
258
259 priv->memory_pool[i].free = 1; 322 priv->memory_pool[i].free = 1;
260 return ; 323 qtd->payload_addr = 0;
324 return;
261 } 325 }
262 } 326 }
263 327
264 printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n", 328 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
265 mem); 329 __func__, qtd->payload_addr);
266 BUG(); 330 BUG();
267} 331}
268 332
269static void isp1760_init_regs(struct usb_hcd *hcd) 333static void isp1760_init_regs(struct usb_hcd *hcd)
270{ 334{
271 isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG); 335 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
272 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + 336 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
273 HC_ATL_PTD_SKIPMAP_REG); 337 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
274 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + 338 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
275 HC_INT_PTD_SKIPMAP_REG); 339
276 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + 340 reg_write32(hcd->regs, HC_ATL_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
277 HC_ISO_PTD_SKIPMAP_REG); 341 reg_write32(hcd->regs, HC_INT_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
278 342 reg_write32(hcd->regs, HC_ISO_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
279 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
280 HC_ATL_PTD_DONEMAP_REG);
281 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
282 HC_INT_PTD_DONEMAP_REG);
283 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
284 HC_ISO_PTD_DONEMAP_REG);
285} 343}
286 344
287static int handshake(struct isp1760_hcd *priv, void __iomem *ptr, 345static int handshake(struct usb_hcd *hcd, u32 reg,
288 u32 mask, u32 done, int usec) 346 u32 mask, u32 done, int usec)
289{ 347{
290 u32 result; 348 u32 result;
291 349
292 do { 350 do {
293 result = isp1760_readl(ptr); 351 result = reg_read32(hcd->regs, reg);
294 if (result == ~0) 352 if (result == ~0)
295 return -ENODEV; 353 return -ENODEV;
296 result &= mask; 354 result &= mask;
@@ -303,17 +361,18 @@ static int handshake(struct isp1760_hcd *priv, void __iomem *ptr,
303} 361}
304 362
305/* reset a non-running (STS_HALT == 1) controller */ 363/* reset a non-running (STS_HALT == 1) controller */
306static int ehci_reset(struct isp1760_hcd *priv) 364static int ehci_reset(struct usb_hcd *hcd)
307{ 365{
308 int retval; 366 int retval;
309 struct usb_hcd *hcd = priv_to_hcd(priv); 367 struct isp1760_hcd *priv = hcd_to_priv(hcd);
310 u32 command = isp1760_readl(hcd->regs + HC_USBCMD); 368
369 u32 command = reg_read32(hcd->regs, HC_USBCMD);
311 370
312 command |= CMD_RESET; 371 command |= CMD_RESET;
313 isp1760_writel(command, hcd->regs + HC_USBCMD); 372 reg_write32(hcd->regs, HC_USBCMD, command);
314 hcd->state = HC_STATE_HALT; 373 hcd->state = HC_STATE_HALT;
315 priv->next_statechange = jiffies; 374 priv->next_statechange = jiffies;
316 retval = handshake(priv, hcd->regs + HC_USBCMD, 375 retval = handshake(hcd, HC_USBCMD,
317 CMD_RESET, 0, 250 * 1000); 376 CMD_RESET, 0, 250 * 1000);
318 return retval; 377 return retval;
319} 378}
@@ -324,8 +383,7 @@ static void qh_destroy(struct isp1760_qh *qh)
324 kmem_cache_free(qh_cachep, qh); 383 kmem_cache_free(qh_cachep, qh);
325} 384}
326 385
327static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv, 386static struct isp1760_qh *isp1760_qh_alloc(gfp_t flags)
328 gfp_t flags)
329{ 387{
330 struct isp1760_qh *qh; 388 struct isp1760_qh *qh;
331 389
@@ -334,7 +392,6 @@ static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv,
334 return qh; 392 return qh;
335 393
336 INIT_LIST_HEAD(&qh->qtd_list); 394 INIT_LIST_HEAD(&qh->qtd_list);
337 qh->priv = priv;
338 return qh; 395 return qh;
339} 396}
340 397
@@ -361,7 +418,7 @@ static int priv_init(struct usb_hcd *hcd)
361 priv->periodic_size = DEFAULT_I_TDPS; 418 priv->periodic_size = DEFAULT_I_TDPS;
362 419
363 /* controllers may cache some of the periodic schedule ... */ 420 /* controllers may cache some of the periodic schedule ... */
364 hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS); 421 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
365 /* full frame cache */ 422 /* full frame cache */
366 if (HCC_ISOC_CACHE(hcc_params)) 423 if (HCC_ISOC_CACHE(hcc_params))
367 priv->i_thresh = 8; 424 priv->i_thresh = 8;
@@ -398,15 +455,15 @@ static int isp1760_hc_setup(struct usb_hcd *hcd)
398 * Write it twice to ensure correct upper bits if switching 455 * Write it twice to ensure correct upper bits if switching
399 * to 16-bit mode. 456 * to 16-bit mode.
400 */ 457 */
401 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); 458 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
402 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); 459 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
403 460
404 isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG); 461 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
405 /* Change bus pattern */ 462 /* Change bus pattern */
406 scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); 463 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
407 scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG); 464 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
408 if (scratch != 0xdeadbabe) { 465 if (scratch != 0xdeadbabe) {
409 printk(KERN_ERR "ISP1760: Scratch test failed.\n"); 466 dev_err(hcd->self.controller, "Scratch test failed.\n");
410 return -ENODEV; 467 return -ENODEV;
411 } 468 }
412 469
@@ -414,30 +471,30 @@ static int isp1760_hc_setup(struct usb_hcd *hcd)
414 isp1760_init_regs(hcd); 471 isp1760_init_regs(hcd);
415 472
416 /* reset */ 473 /* reset */
417 isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG); 474 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
418 mdelay(100); 475 mdelay(100);
419 476
420 isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG); 477 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
421 mdelay(100); 478 mdelay(100);
422 479
423 result = ehci_reset(priv); 480 result = ehci_reset(hcd);
424 if (result) 481 if (result)
425 return result; 482 return result;
426 483
427 /* Step 11 passed */ 484 /* Step 11 passed */
428 485
429 isp1760_info(priv, "bus width: %d, oc: %s\n", 486 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
430 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? 487 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
431 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? 488 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
432 "analog" : "digital"); 489 "analog" : "digital");
433 490
434 /* ATL reset */ 491 /* ATL reset */
435 isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL); 492 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
436 mdelay(10); 493 mdelay(10);
437 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); 494 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
438 495
439 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG); 496 reg_write32(hcd->regs, HC_INTERRUPT_REG, INTERRUPT_ENABLE_MASK);
440 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE); 497 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
441 498
442 /* 499 /*
443 * PORT 1 Control register of the ISP1760 is the OTG control 500 * PORT 1 Control register of the ISP1760 is the OTG control
@@ -445,11 +502,10 @@ static int isp1760_hc_setup(struct usb_hcd *hcd)
445 * support in this driver, we use port 1 as a "normal" USB host port on 502 * support in this driver, we use port 1 as a "normal" USB host port on
446 * both chips. 503 * both chips.
447 */ 504 */
448 isp1760_writel(PORT1_POWER | PORT1_INIT2, 505 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
449 hcd->regs + HC_PORT1_CTRL);
450 mdelay(10); 506 mdelay(10);
451 507
452 priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS); 508 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
453 509
454 return priv_init(hcd); 510 return priv_init(hcd);
455} 511}
@@ -457,25 +513,24 @@ static int isp1760_hc_setup(struct usb_hcd *hcd)
457static void isp1760_init_maps(struct usb_hcd *hcd) 513static void isp1760_init_maps(struct usb_hcd *hcd)
458{ 514{
459 /*set last maps, for iso its only 1, else 32 tds bitmap*/ 515 /*set last maps, for iso its only 1, else 32 tds bitmap*/
460 isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG); 516 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
461 isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG); 517 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
462 isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG); 518 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
463} 519}
464 520
465static void isp1760_enable_interrupts(struct usb_hcd *hcd) 521static void isp1760_enable_interrupts(struct usb_hcd *hcd)
466{ 522{
467 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG); 523 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
468 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 524 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0);
469 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG); 525 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
470 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG); 526 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0);
471 isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG); 527 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
472 isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG); 528 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
473 /* step 23 passed */ 529 /* step 23 passed */
474} 530}
475 531
476static int isp1760_run(struct usb_hcd *hcd) 532static int isp1760_run(struct usb_hcd *hcd)
477{ 533{
478 struct isp1760_hcd *priv = hcd_to_priv(hcd);
479 int retval; 534 int retval;
480 u32 temp; 535 u32 temp;
481 u32 command; 536 u32 command;
@@ -485,15 +540,15 @@ static int isp1760_run(struct usb_hcd *hcd)
485 540
486 hcd->state = HC_STATE_RUNNING; 541 hcd->state = HC_STATE_RUNNING;
487 isp1760_enable_interrupts(hcd); 542 isp1760_enable_interrupts(hcd);
488 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); 543 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
489 isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); 544 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
490 545
491 command = isp1760_readl(hcd->regs + HC_USBCMD); 546 command = reg_read32(hcd->regs, HC_USBCMD);
492 command &= ~(CMD_LRESET|CMD_RESET); 547 command &= ~(CMD_LRESET|CMD_RESET);
493 command |= CMD_RUN; 548 command |= CMD_RUN;
494 isp1760_writel(command, hcd->regs + HC_USBCMD); 549 reg_write32(hcd->regs, HC_USBCMD, command);
495 550
496 retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN, 551 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN,
497 250 * 1000); 552 250 * 1000);
498 if (retval) 553 if (retval)
499 return retval; 554 return retval;
@@ -504,17 +559,16 @@ static int isp1760_run(struct usb_hcd *hcd)
504 * the semaphore while doing so. 559 * the semaphore while doing so.
505 */ 560 */
506 down_write(&ehci_cf_port_reset_rwsem); 561 down_write(&ehci_cf_port_reset_rwsem);
507 isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG); 562 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
508 563
509 retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 564 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
510 250 * 1000);
511 up_write(&ehci_cf_port_reset_rwsem); 565 up_write(&ehci_cf_port_reset_rwsem);
512 if (retval) 566 if (retval)
513 return retval; 567 return retval;
514 568
515 chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); 569 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
516 isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff, 570 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
517 chipid >> 16); 571 chipid & 0xffff, chipid >> 16);
518 572
519 /* PTD Register Init Part 2, Step 28 */ 573 /* PTD Register Init Part 2, Step 28 */
520 /* enable INTs */ 574 /* enable INTs */
@@ -532,160 +586,156 @@ static u32 base_to_chip(u32 base)
532 return ((base - 0x400) >> 3); 586 return ((base - 0x400) >> 3);
533} 587}
534 588
535static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh, 589static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
536 struct isp1760_qtd *qtd, struct urb *urb, 590{
537 u32 payload, struct ptd *ptd) 591 struct urb *urb;
592
593 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
594 return 1;
595
596 urb = qtd->urb;
597 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
598 return (qtd->urb != urb);
599}
600
601static void transform_into_atl(struct isp1760_qh *qh,
602 struct isp1760_qtd *qtd, struct ptd *ptd)
538{ 603{
539 u32 dw0;
540 u32 dw1;
541 u32 dw2;
542 u32 dw3;
543 u32 maxpacket; 604 u32 maxpacket;
544 u32 multi; 605 u32 multi;
545 u32 pid_code; 606 u32 pid_code;
546 u32 rl = RL_COUNTER; 607 u32 rl = RL_COUNTER;
547 u32 nak = NAK_COUNTER; 608 u32 nak = NAK_COUNTER;
548 609
610 memset(ptd, 0, sizeof(*ptd));
611
549 /* according to 3.6.2, max packet len can not be > 0x400 */ 612 /* according to 3.6.2, max packet len can not be > 0x400 */
550 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); 613 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
614 usb_pipeout(qtd->urb->pipe));
551 multi = 1 + ((maxpacket >> 11) & 0x3); 615 multi = 1 + ((maxpacket >> 11) & 0x3);
552 maxpacket &= 0x7ff; 616 maxpacket &= 0x7ff;
553 617
554 /* DW0 */ 618 /* DW0 */
555 dw0 = PTD_VALID; 619 ptd->dw0 = PTD_VALID;
556 dw0 |= PTD_LENGTH(qtd->length); 620 ptd->dw0 |= PTD_LENGTH(qtd->length);
557 dw0 |= PTD_MAXPACKET(maxpacket); 621 ptd->dw0 |= PTD_MAXPACKET(maxpacket);
558 dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe)); 622 ptd->dw0 |= PTD_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
559 dw1 = usb_pipeendpoint(urb->pipe) >> 1;
560 623
561 /* DW1 */ 624 /* DW1 */
562 dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe)); 625 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
626 ptd->dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
563 627
564 pid_code = qtd->packet_type; 628 pid_code = qtd->packet_type;
565 dw1 |= PTD_PID_TOKEN(pid_code); 629 ptd->dw1 |= PTD_PID_TOKEN(pid_code);
566 630
567 if (usb_pipebulk(urb->pipe)) 631 if (usb_pipebulk(qtd->urb->pipe))
568 dw1 |= PTD_TRANS_BULK; 632 ptd->dw1 |= PTD_TRANS_BULK;
569 else if (usb_pipeint(urb->pipe)) 633 else if (usb_pipeint(qtd->urb->pipe))
570 dw1 |= PTD_TRANS_INT; 634 ptd->dw1 |= PTD_TRANS_INT;
571 635
572 if (urb->dev->speed != USB_SPEED_HIGH) { 636 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
573 /* split transaction */ 637 /* split transaction */
574 638
575 dw1 |= PTD_TRANS_SPLIT; 639 ptd->dw1 |= PTD_TRANS_SPLIT;
576 if (urb->dev->speed == USB_SPEED_LOW) 640 if (qtd->urb->dev->speed == USB_SPEED_LOW)
577 dw1 |= PTD_SE_USB_LOSPEED; 641 ptd->dw1 |= PTD_SE_USB_LOSPEED;
578 642
579 dw1 |= PTD_PORT_NUM(urb->dev->ttport); 643 ptd->dw1 |= PTD_PORT_NUM(qtd->urb->dev->ttport);
580 dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum); 644 ptd->dw1 |= PTD_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
581 645
582 /* SE bit for Split INT transfers */ 646 /* SE bit for Split INT transfers */
583 if (usb_pipeint(urb->pipe) && 647 if (usb_pipeint(qtd->urb->pipe) &&
584 (urb->dev->speed == USB_SPEED_LOW)) 648 (qtd->urb->dev->speed == USB_SPEED_LOW))
585 dw1 |= 2 << 16; 649 ptd->dw1 |= 2 << 16;
586 650
587 dw3 = 0; 651 ptd->dw3 = 0;
588 rl = 0; 652 rl = 0;
589 nak = 0; 653 nak = 0;
590 } else { 654 } else {
591 dw0 |= PTD_MULTI(multi); 655 ptd->dw0 |= PTD_MULTI(multi);
592 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) 656 if (usb_pipecontrol(qtd->urb->pipe) ||
593 dw3 = qh->ping; 657 usb_pipebulk(qtd->urb->pipe))
658 ptd->dw3 = qh->ping;
594 else 659 else
595 dw3 = 0; 660 ptd->dw3 = 0;
596 } 661 }
597 /* DW2 */ 662 /* DW2 */
598 dw2 = 0; 663 ptd->dw2 = 0;
599 dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload)); 664 ptd->dw2 |= PTD_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
600 dw2 |= PTD_RL_CNT(rl); 665 ptd->dw2 |= PTD_RL_CNT(rl);
601 dw3 |= PTD_NAC_CNT(nak); 666 ptd->dw3 |= PTD_NAC_CNT(nak);
602 667
603 /* DW3 */ 668 /* DW3 */
604 if (usb_pipecontrol(urb->pipe)) 669 ptd->dw3 |= qh->toggle;
605 dw3 |= PTD_DATA_TOGGLE(qtd->toggle); 670 if (usb_pipecontrol(qtd->urb->pipe)) {
606 else 671 if (qtd->data_buffer == qtd->urb->setup_packet)
607 dw3 |= qh->toggle; 672 ptd->dw3 &= ~PTD_DATA_TOGGLE(1);
608 673 else if (last_qtd_of_urb(qtd, qh))
674 ptd->dw3 |= PTD_DATA_TOGGLE(1);
675 }
609 676
610 dw3 |= PTD_ACTIVE; 677 ptd->dw3 |= PTD_ACTIVE;
611 /* Cerr */ 678 /* Cerr */
612 dw3 |= PTD_CERR(ERR_COUNTER); 679 ptd->dw3 |= PTD_CERR(ERR_COUNTER);
613
614 memset(ptd, 0, sizeof(*ptd));
615
616 ptd->dw0 = cpu_to_le32(dw0);
617 ptd->dw1 = cpu_to_le32(dw1);
618 ptd->dw2 = cpu_to_le32(dw2);
619 ptd->dw3 = cpu_to_le32(dw3);
620} 680}
621 681
622static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, 682static void transform_add_int(struct isp1760_qh *qh,
623 struct isp1760_qtd *qtd, struct urb *urb, 683 struct isp1760_qtd *qtd, struct ptd *ptd)
624 u32 payload, struct ptd *ptd)
625{ 684{
626 u32 maxpacket; 685 u32 usof;
627 u32 multi;
628 u32 numberofusofs;
629 u32 i;
630 u32 usofmask, usof;
631 u32 period; 686 u32 period;
632 687
633 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); 688 /*
634 multi = 1 + ((maxpacket >> 11) & 0x3); 689 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
635 maxpacket &= 0x7ff; 690 * the algorithm from the original Philips driver code, which was
636 /* length of the data per uframe */ 691 * pretty much used in this driver before as well, is quite horrendous
637 maxpacket = multi * maxpacket; 692 * and, i believe, incorrect. The code below follows the datasheet and
638 693 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
639 numberofusofs = urb->transfer_buffer_length / maxpacket; 694 * more reliable this way (fingers crossed...).
640 if (urb->transfer_buffer_length % maxpacket) 695 */
641 numberofusofs += 1;
642
643 usofmask = 1;
644 usof = 0;
645 for (i = 0; i < numberofusofs; i++) {
646 usof |= usofmask;
647 usofmask <<= 1;
648 }
649
650 if (urb->dev->speed != USB_SPEED_HIGH) {
651 /* split */
652 ptd->dw5 = cpu_to_le32(0x1c);
653 696
654 if (qh->period >= 32) 697 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
655 period = qh->period / 2; 698 /* urb->interval is in units of microframes (1/8 ms) */
699 period = qtd->urb->interval >> 3;
700
701 if (qtd->urb->interval > 4)
702 usof = 0x01; /* One bit set =>
703 interval 1 ms * uFrame-match */
704 else if (qtd->urb->interval > 2)
705 usof = 0x22; /* Two bits set => interval 1/2 ms */
706 else if (qtd->urb->interval > 1)
707 usof = 0x55; /* Four bits set => interval 1/4 ms */
656 else 708 else
657 period = qh->period; 709 usof = 0xff; /* All bits set => interval 1/8 ms */
658
659 } else { 710 } else {
711 /* urb->interval is in units of frames (1 ms) */
712 period = qtd->urb->interval;
713 usof = 0x0f; /* Execute Start Split on any of the
714 four first uFrames */
660 715
661 if (qh->period >= 8) 716 /*
662 period = qh->period/8; 717 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
663 else 718 * complete split needs to be sent. Valid only for IN." Also,
664 period = qh->period; 719 * "All bits can be set to one for every transfer." (p 82,
665 720 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
666 if (period >= 32) 721 * that number come from? 0xff seems to work fine...
667 period = 16; 722 */
668 723 /* ptd->dw5 = 0x1c; */
669 if (qh->period >= 8) { 724 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
670 /* millisecond period */
671 period = (period << 3);
672 } else {
673 /* usof based tranmsfers */
674 /* minimum 4 usofs */
675 usof = 0x11;
676 }
677 } 725 }
678 726
679 ptd->dw2 |= cpu_to_le32(period); 727 period = period >> 1;/* Ensure equal or shorter period than requested */
680 ptd->dw4 = cpu_to_le32(usof); 728 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
729
730 ptd->dw2 |= period;
731 ptd->dw4 = usof;
681} 732}
682 733
683static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, 734static void transform_into_int(struct isp1760_qh *qh,
684 struct isp1760_qtd *qtd, struct urb *urb, 735 struct isp1760_qtd *qtd, struct ptd *ptd)
685 u32 payload, struct ptd *ptd)
686{ 736{
687 transform_into_atl(priv, qh, qtd, urb, payload, ptd); 737 transform_into_atl(qh, qtd, ptd);
688 transform_add_int(priv, qh, qtd, urb, payload, ptd); 738 transform_add_int(qh, qtd, ptd);
689} 739}
690 740
691static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len, 741static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
@@ -695,10 +745,9 @@ static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
695 745
696 qtd->data_buffer = databuffer; 746 qtd->data_buffer = databuffer;
697 qtd->packet_type = GET_QTD_TOKEN_TYPE(token); 747 qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
698 qtd->toggle = GET_DATA_TOGGLE(token);
699 748
700 if (len > HC_ATL_PL_SIZE) 749 if (len > MAX_PAYLOAD_SIZE)
701 count = HC_ATL_PL_SIZE; 750 count = MAX_PAYLOAD_SIZE;
702 else 751 else
703 count = len; 752 count = len;
704 753
@@ -706,29 +755,27 @@ static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
706 return count; 755 return count;
707} 756}
708 757
709static int check_error(struct ptd *ptd) 758static int check_error(struct usb_hcd *hcd, struct ptd *ptd)
710{ 759{
711 int error = 0; 760 int error = 0;
712 u32 dw3;
713 761
714 dw3 = le32_to_cpu(ptd->dw3); 762 if (ptd->dw3 & DW3_HALT_BIT) {
715 if (dw3 & DW3_HALT_BIT) {
716 error = -EPIPE; 763 error = -EPIPE;
717 764
718 if (dw3 & DW3_ERROR_BIT) 765 if (ptd->dw3 & DW3_ERROR_BIT)
719 pr_err("error bit is set in DW3\n"); 766 pr_err("error bit is set in DW3\n");
720 } 767 }
721 768
722 if (dw3 & DW3_QTD_ACTIVE) { 769 if (ptd->dw3 & DW3_QTD_ACTIVE) {
723 printk(KERN_ERR "transfer active bit is set DW3\n"); 770 dev_err(hcd->self.controller, "Transfer active bit is set DW3\n"
724 printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf, 771 "nak counter: %d, rl: %d\n",
725 (le32_to_cpu(ptd->dw2) >> 25) & 0xf); 772 (ptd->dw3 >> 19) & 0xf, (ptd->dw2 >> 25) & 0xf);
726 } 773 }
727 774
728 return error; 775 return error;
729} 776}
730 777
731static void check_int_err_status(u32 dw4) 778static void check_int_err_status(struct usb_hcd *hcd, u32 dw4)
732{ 779{
733 u32 i; 780 u32 i;
734 781
@@ -737,79 +784,67 @@ static void check_int_err_status(u32 dw4)
737 for (i = 0; i < 8; i++) { 784 for (i = 0; i < 8; i++) {
738 switch (dw4 & 0x7) { 785 switch (dw4 & 0x7) {
739 case INT_UNDERRUN: 786 case INT_UNDERRUN:
740 printk(KERN_ERR "ERROR: under run , %d\n", i); 787 dev_err(hcd->self.controller, "Underrun (%d)\n", i);
741 break; 788 break;
742 789
743 case INT_EXACT: 790 case INT_EXACT:
744 printk(KERN_ERR "ERROR: transaction error, %d\n", i); 791 dev_err(hcd->self.controller,
792 "Transaction error (%d)\n", i);
745 break; 793 break;
746 794
747 case INT_BABBLE: 795 case INT_BABBLE:
748 printk(KERN_ERR "ERROR: babble error, %d\n", i); 796 dev_err(hcd->self.controller, "Babble error (%d)\n", i);
749 break; 797 break;
750 } 798 }
751 dw4 >>= 3; 799 dw4 >>= 3;
752 } 800 }
753} 801}
754 802
755static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv, 803static void enqueue_one_qtd(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
756 u32 payload)
757{ 804{
758 u32 token; 805 if (qtd->length && (qtd->length <= MAX_PAYLOAD_SIZE)) {
759 struct usb_hcd *hcd = priv_to_hcd(priv); 806 switch (qtd->packet_type) {
760
761 token = qtd->packet_type;
762
763 if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) {
764 switch (token) {
765 case IN_PID: 807 case IN_PID:
766 break; 808 break;
767 case OUT_PID: 809 case OUT_PID:
768 case SETUP_PID: 810 case SETUP_PID:
769 priv_write_copy(priv, qtd->data_buffer, 811 mem_writes8(hcd->regs, qtd->payload_addr,
770 hcd->regs + payload, 812 qtd->data_buffer, qtd->length);
771 qtd->length);
772 } 813 }
773 } 814 }
774} 815}
775 816
776static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload, 817static void enqueue_one_atl_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
777 struct isp1760_hcd *priv, struct isp1760_qh *qh, 818 u32 slot, struct isp1760_qtd *qtd)
778 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
779{ 819{
820 struct isp1760_hcd *priv = hcd_to_priv(hcd);
780 struct ptd ptd; 821 struct ptd ptd;
781 struct usb_hcd *hcd = priv_to_hcd(priv);
782 822
783 transform_into_atl(priv, qh, qtd, urb, payload, &ptd); 823 alloc_mem(hcd, qtd);
784 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd)); 824 transform_into_atl(qh, qtd, &ptd);
785 enqueue_one_qtd(qtd, priv, payload); 825 ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
826 enqueue_one_qtd(hcd, qtd);
786 827
787 priv->atl_ints[slot].urb = urb;
788 priv->atl_ints[slot].qh = qh; 828 priv->atl_ints[slot].qh = qh;
789 priv->atl_ints[slot].qtd = qtd; 829 priv->atl_ints[slot].qtd = qtd;
790 priv->atl_ints[slot].data_buffer = qtd->data_buffer; 830 qtd->status |= URB_ENQUEUED;
791 priv->atl_ints[slot].payload = payload;
792 qtd->status |= URB_ENQUEUED | URB_TYPE_ATL;
793 qtd->status |= slot << 16; 831 qtd->status |= slot << 16;
794} 832}
795 833
796static void enqueue_one_int_qtd(u32 int_regs, u32 payload, 834static void enqueue_one_int_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
797 struct isp1760_hcd *priv, struct isp1760_qh *qh, 835 u32 slot, struct isp1760_qtd *qtd)
798 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
799{ 836{
837 struct isp1760_hcd *priv = hcd_to_priv(hcd);
800 struct ptd ptd; 838 struct ptd ptd;
801 struct usb_hcd *hcd = priv_to_hcd(priv);
802 839
803 transform_into_int(priv, qh, qtd, urb, payload, &ptd); 840 alloc_mem(hcd, qtd);
804 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd)); 841 transform_into_int(qh, qtd, &ptd);
805 enqueue_one_qtd(qtd, priv, payload); 842 ptd_write(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
843 enqueue_one_qtd(hcd, qtd);
806 844
807 priv->int_ints[slot].urb = urb;
808 priv->int_ints[slot].qh = qh; 845 priv->int_ints[slot].qh = qh;
809 priv->int_ints[slot].qtd = qtd; 846 priv->int_ints[slot].qtd = qtd;
810 priv->int_ints[slot].data_buffer = qtd->data_buffer; 847 qtd->status |= URB_ENQUEUED;
811 priv->int_ints[slot].payload = payload;
812 qtd->status |= URB_ENQUEUED | URB_TYPE_INT;
813 qtd->status |= slot << 16; 848 qtd->status |= slot << 16;
814} 849}
815 850
@@ -818,9 +853,7 @@ static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
818{ 853{
819 struct isp1760_hcd *priv = hcd_to_priv(hcd); 854 struct isp1760_hcd *priv = hcd_to_priv(hcd);
820 u32 skip_map, or_map; 855 u32 skip_map, or_map;
821 u32 queue_entry;
822 u32 slot; 856 u32 slot;
823 u32 atl_regs, payload;
824 u32 buffstatus; 857 u32 buffstatus;
825 858
826 /* 859 /*
@@ -831,38 +864,35 @@ static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
831 */ 864 */
832 mmiowb(); 865 mmiowb();
833 ndelay(195); 866 ndelay(195);
834 skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG); 867 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
835 868
836 BUG_ON(!skip_map); 869 BUG_ON(!skip_map);
837 slot = __ffs(skip_map); 870 slot = __ffs(skip_map);
838 queue_entry = 1 << slot;
839
840 atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd);
841 871
842 payload = alloc_mem(priv, qtd->length); 872 enqueue_one_atl_qtd(hcd, qh, slot, qtd);
843 873
844 enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd); 874 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
875 or_map |= (1 << slot);
876 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
845 877
846 or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 878 skip_map &= ~(1 << slot);
847 or_map |= queue_entry; 879 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
848 isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
849 880
850 skip_map &= ~queue_entry; 881 priv->atl_queued++;
851 isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG); 882 if (priv->atl_queued == 2)
883 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
884 INTERRUPT_ENABLE_SOT_MASK);
852 885
853 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); 886 buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
854 buffstatus |= ATL_BUFFER; 887 buffstatus |= ATL_BUFFER;
855 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); 888 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
856} 889}
857 890
858static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, 891static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
859 struct isp1760_qtd *qtd) 892 struct isp1760_qtd *qtd)
860{ 893{
861 struct isp1760_hcd *priv = hcd_to_priv(hcd);
862 u32 skip_map, or_map; 894 u32 skip_map, or_map;
863 u32 queue_entry;
864 u32 slot; 895 u32 slot;
865 u32 int_regs, payload;
866 u32 buffstatus; 896 u32 buffstatus;
867 897
868 /* 898 /*
@@ -873,37 +903,34 @@ static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
873 */ 903 */
874 mmiowb(); 904 mmiowb();
875 ndelay(195); 905 ndelay(195);
876 skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG); 906 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
877 907
878 BUG_ON(!skip_map); 908 BUG_ON(!skip_map);
879 slot = __ffs(skip_map); 909 slot = __ffs(skip_map);
880 queue_entry = 1 << slot;
881
882 int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd);
883 910
884 payload = alloc_mem(priv, qtd->length); 911 enqueue_one_int_qtd(hcd, qh, slot, qtd);
885 912
886 enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd); 913 or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
914 or_map |= (1 << slot);
915 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
887 916
888 or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG); 917 skip_map &= ~(1 << slot);
889 or_map |= queue_entry; 918 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
890 isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
891 919
892 skip_map &= ~queue_entry; 920 buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
893 isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG);
894
895 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
896 buffstatus |= INT_BUFFER; 921 buffstatus |= INT_BUFFER;
897 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); 922 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
898} 923}
899 924
900static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status) 925static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
901__releases(priv->lock) 926__releases(priv->lock)
902__acquires(priv->lock) 927__acquires(priv->lock)
903{ 928{
929 struct isp1760_hcd *priv = hcd_to_priv(hcd);
930
904 if (!urb->unlinked) { 931 if (!urb->unlinked) {
905 if (status == -EINPROGRESS) 932 if (urb->status == -EINPROGRESS)
906 status = 0; 933 urb->status = 0;
907 } 934 }
908 935
909 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { 936 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
@@ -915,22 +942,28 @@ __acquires(priv->lock)
915 } 942 }
916 943
917 /* complete() can reenter this HCD */ 944 /* complete() can reenter this HCD */
918 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); 945 usb_hcd_unlink_urb_from_ep(hcd, urb);
919 spin_unlock(&priv->lock); 946 spin_unlock(&priv->lock);
920 usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status); 947 usb_hcd_giveback_urb(hcd, urb, urb->status);
921 spin_lock(&priv->lock); 948 spin_lock(&priv->lock);
922} 949}
923 950
924static void isp1760_qtd_free(struct isp1760_qtd *qtd) 951static void isp1760_qtd_free(struct isp1760_qtd *qtd)
925{ 952{
953 BUG_ON(qtd->payload_addr);
926 kmem_cache_free(qtd_cachep, qtd); 954 kmem_cache_free(qtd_cachep, qtd);
927} 955}
928 956
929static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd) 957static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd,
958 struct isp1760_qh *qh)
930{ 959{
931 struct isp1760_qtd *tmp_qtd; 960 struct isp1760_qtd *tmp_qtd;
932 961
933 tmp_qtd = qtd->hw_next; 962 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
963 tmp_qtd = NULL;
964 else
965 tmp_qtd = list_entry(qtd->qtd_list.next, struct isp1760_qtd,
966 qtd_list);
934 list_del(&qtd->qtd_list); 967 list_del(&qtd->qtd_list);
935 isp1760_qtd_free(qtd); 968 isp1760_qtd_free(qtd);
936 return tmp_qtd; 969 return tmp_qtd;
@@ -941,32 +974,26 @@ static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd)
941 * isn't the last one than remove also his successor(s). 974 * isn't the last one than remove also his successor(s).
942 * Returns the QTD which is part of an new URB and should be enqueued. 975 * Returns the QTD which is part of an new URB and should be enqueued.
943 */ 976 */
944static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd) 977static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd,
978 struct isp1760_qh *qh)
945{ 979{
946 struct isp1760_qtd *tmp_qtd; 980 struct urb *urb;
947 int last_one;
948 981
982 urb = qtd->urb;
949 do { 983 do {
950 tmp_qtd = qtd->hw_next; 984 qtd = clean_this_qtd(qtd, qh);
951 last_one = qtd->status & URB_COMPLETE_NOTIFY; 985 } while (qtd && (qtd->urb == urb));
952 list_del(&qtd->qtd_list);
953 isp1760_qtd_free(qtd);
954 qtd = tmp_qtd;
955 } while (!last_one && qtd);
956 986
957 return qtd; 987 return qtd;
958} 988}
959 989
960static void do_atl_int(struct usb_hcd *usb_hcd) 990static void do_atl_int(struct usb_hcd *hcd)
961{ 991{
962 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); 992 struct isp1760_hcd *priv = hcd_to_priv(hcd);
963 u32 done_map, skip_map; 993 u32 done_map, skip_map;
964 struct ptd ptd; 994 struct ptd ptd;
965 struct urb *urb = NULL; 995 struct urb *urb;
966 u32 atl_regs_base; 996 u32 slot;
967 u32 atl_regs;
968 u32 queue_entry;
969 u32 payload;
970 u32 length; 997 u32 length;
971 u32 or_map; 998 u32 or_map;
972 u32 status = -EINVAL; 999 u32 status = -EINVAL;
@@ -976,62 +1003,36 @@ static void do_atl_int(struct usb_hcd *usb_hcd)
976 u32 rl; 1003 u32 rl;
977 u32 nakcount; 1004 u32 nakcount;
978 1005
979 done_map = isp1760_readl(usb_hcd->regs + 1006 done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
980 HC_ATL_PTD_DONEMAP_REG); 1007 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
981 skip_map = isp1760_readl(usb_hcd->regs +
982 HC_ATL_PTD_SKIPMAP_REG);
983 1008
984 or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 1009 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
985 or_map &= ~done_map; 1010 or_map &= ~done_map;
986 isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 1011 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
987 1012
988 atl_regs_base = ATL_REGS_OFFSET;
989 while (done_map) { 1013 while (done_map) {
990 u32 dw1;
991 u32 dw2;
992 u32 dw3;
993
994 status = 0; 1014 status = 0;
1015 priv->atl_queued--;
995 1016
996 queue_entry = __ffs(done_map); 1017 slot = __ffs(done_map);
997 done_map &= ~(1 << queue_entry); 1018 done_map &= ~(1 << slot);
998 skip_map |= 1 << queue_entry; 1019 skip_map |= (1 << slot);
999
1000 atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd);
1001 1020
1002 urb = priv->atl_ints[queue_entry].urb; 1021 qtd = priv->atl_ints[slot].qtd;
1003 qtd = priv->atl_ints[queue_entry].qtd; 1022 qh = priv->atl_ints[slot].qh;
1004 qh = priv->atl_ints[queue_entry].qh;
1005 payload = priv->atl_ints[queue_entry].payload;
1006 1023
1007 if (!qh) { 1024 if (!qh) {
1008 printk(KERN_ERR "qh is 0\n"); 1025 dev_err(hcd->self.controller, "qh is 0\n");
1009 continue; 1026 continue;
1010 } 1027 }
1011 isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs + 1028 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1012 HC_MEMORY_REG);
1013 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1014 HC_MEMORY_REG);
1015 /*
1016 * write bank1 address twice to ensure the 90ns delay (time
1017 * between BANK0 write and the priv_read_copy() call is at
1018 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns)
1019 */
1020 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1021 HC_MEMORY_REG);
1022 1029
1023 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs + 1030 rl = (ptd.dw2 >> 25) & 0x0f;
1024 ISP_BANK(0), sizeof(ptd)); 1031 nakcount = (ptd.dw3 >> 19) & 0xf;
1025
1026 dw1 = le32_to_cpu(ptd.dw1);
1027 dw2 = le32_to_cpu(ptd.dw2);
1028 dw3 = le32_to_cpu(ptd.dw3);
1029 rl = (dw2 >> 25) & 0x0f;
1030 nakcount = (dw3 >> 19) & 0xf;
1031 1032
1032 /* Transfer Error, *but* active and no HALT -> reload */ 1033 /* Transfer Error, *but* active and no HALT -> reload */
1033 if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) && 1034 if ((ptd.dw3 & DW3_ERROR_BIT) && (ptd.dw3 & DW3_QTD_ACTIVE) &&
1034 !(dw3 & DW3_HALT_BIT)) { 1035 !(ptd.dw3 & DW3_HALT_BIT)) {
1035 1036
1036 /* according to ppriv code, we have to 1037 /* according to ppriv code, we have to
1037 * reload this one if trasfered bytes != requested bytes 1038 * reload this one if trasfered bytes != requested bytes
@@ -1040,13 +1041,14 @@ static void do_atl_int(struct usb_hcd *usb_hcd)
1040 * triggered so far. 1041 * triggered so far.
1041 */ 1042 */
1042 1043
1043 length = PTD_XFERRED_LENGTH(dw3); 1044 length = PTD_XFERRED_LENGTH(ptd.dw3);
1044 printk(KERN_ERR "Should reload now.... transfered %d " 1045 dev_err(hcd->self.controller,
1046 "Should reload now... transferred %d "
1045 "of %zu\n", length, qtd->length); 1047 "of %zu\n", length, qtd->length);
1046 BUG(); 1048 BUG();
1047 } 1049 }
1048 1050
1049 if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) { 1051 if (!nakcount && (ptd.dw3 & DW3_QTD_ACTIVE)) {
1050 u32 buffstatus; 1052 u32 buffstatus;
1051 1053
1052 /* 1054 /*
@@ -1054,52 +1056,45 @@ static void do_atl_int(struct usb_hcd *usb_hcd)
1054 * device is not able to send data fast enough. 1056 * device is not able to send data fast enough.
1055 * This happens mostly on slower hardware. 1057 * This happens mostly on slower hardware.
1056 */ 1058 */
1057 printk(KERN_NOTICE "Reloading ptd %p/%p... qh %p read: "
1058 "%d of %zu done: %08x cur: %08x\n", qtd,
1059 urb, qh, PTD_XFERRED_LENGTH(dw3),
1060 qtd->length, done_map,
1061 (1 << queue_entry));
1062 1059
1063 /* RL counter = ERR counter */ 1060 /* RL counter = ERR counter */
1064 dw3 &= ~(0xf << 19); 1061 ptd.dw3 &= ~(0xf << 19);
1065 dw3 |= rl << 19; 1062 ptd.dw3 |= rl << 19;
1066 dw3 &= ~(3 << (55 - 32)); 1063 ptd.dw3 &= ~(3 << (55 - 32));
1067 dw3 |= ERR_COUNTER << (55 - 32); 1064 ptd.dw3 |= ERR_COUNTER << (55 - 32);
1068 1065
1069 /* 1066 /*
1070 * It is not needed to write skip map back because it 1067 * It is not needed to write skip map back because it
1071 * is unchanged. Just make sure that this entry is 1068 * is unchanged. Just make sure that this entry is
1072 * unskipped once it gets written to the HW. 1069 * unskipped once it gets written to the HW.
1073 */ 1070 */
1074 skip_map &= ~(1 << queue_entry); 1071 skip_map &= ~(1 << slot);
1075 or_map = isp1760_readl(usb_hcd->regs + 1072 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1076 HC_ATL_IRQ_MASK_OR_REG); 1073 or_map |= 1 << slot;
1077 or_map |= 1 << queue_entry; 1074 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1078 isp1760_writel(or_map, usb_hcd->regs + 1075
1079 HC_ATL_IRQ_MASK_OR_REG); 1076 ptd.dw0 |= PTD_VALID;
1080 1077 ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1081 ptd.dw3 = cpu_to_le32(dw3); 1078
1082 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + 1079 priv->atl_queued++;
1083 atl_regs, sizeof(ptd)); 1080 if (priv->atl_queued == 2)
1084 1081 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1085 ptd.dw0 |= cpu_to_le32(PTD_VALID); 1082 INTERRUPT_ENABLE_SOT_MASK);
1086 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + 1083
1087 atl_regs, sizeof(ptd)); 1084 buffstatus = reg_read32(hcd->regs,
1088 1085 HC_BUFFER_STATUS_REG);
1089 buffstatus = isp1760_readl(usb_hcd->regs +
1090 HC_BUFFER_STATUS_REG);
1091 buffstatus |= ATL_BUFFER; 1086 buffstatus |= ATL_BUFFER;
1092 isp1760_writel(buffstatus, usb_hcd->regs + 1087 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1093 HC_BUFFER_STATUS_REG); 1088 buffstatus);
1094 continue; 1089 continue;
1095 } 1090 }
1096 1091
1097 error = check_error(&ptd); 1092 error = check_error(hcd, &ptd);
1098 if (error) { 1093 if (error) {
1099 status = error; 1094 status = error;
1100 priv->atl_ints[queue_entry].qh->toggle = 0; 1095 priv->atl_ints[slot].qh->toggle = 0;
1101 priv->atl_ints[queue_entry].qh->ping = 0; 1096 priv->atl_ints[slot].qh->ping = 0;
1102 urb->status = -EPIPE; 1097 qtd->urb->status = -EPIPE;
1103 1098
1104#if 0 1099#if 0
1105 printk(KERN_ERR "Error in %s().\n", __func__); 1100 printk(KERN_ERR "Error in %s().\n", __func__);
@@ -1110,154 +1105,123 @@ static void do_atl_int(struct usb_hcd *usb_hcd)
1110 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); 1105 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1111#endif 1106#endif
1112 } else { 1107 } else {
1113 if (usb_pipetype(urb->pipe) == PIPE_BULK) { 1108 priv->atl_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
1114 priv->atl_ints[queue_entry].qh->toggle = dw3 & 1109 priv->atl_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
1115 (1 << 25);
1116 priv->atl_ints[queue_entry].qh->ping = dw3 &
1117 (1 << 26);
1118 }
1119 } 1110 }
1120 1111
1121 length = PTD_XFERRED_LENGTH(dw3); 1112 length = PTD_XFERRED_LENGTH(ptd.dw3);
1122 if (length) { 1113 if (length) {
1123 switch (DW1_GET_PID(dw1)) { 1114 switch (DW1_GET_PID(ptd.dw1)) {
1124 case IN_PID: 1115 case IN_PID:
1125 priv_read_copy(priv, 1116 mem_reads8(hcd->regs, qtd->payload_addr,
1126 priv->atl_ints[queue_entry].data_buffer, 1117 qtd->data_buffer, length);
1127 usb_hcd->regs + payload + ISP_BANK(1),
1128 length);
1129 1118
1130 case OUT_PID: 1119 case OUT_PID:
1131 1120
1132 urb->actual_length += length; 1121 qtd->urb->actual_length += length;
1133 1122
1134 case SETUP_PID: 1123 case SETUP_PID:
1135 break; 1124 break;
1136 } 1125 }
1137 } 1126 }
1138 1127
1139 priv->atl_ints[queue_entry].data_buffer = NULL; 1128 priv->atl_ints[slot].qtd = NULL;
1140 priv->atl_ints[queue_entry].urb = NULL; 1129 priv->atl_ints[slot].qh = NULL;
1141 priv->atl_ints[queue_entry].qtd = NULL;
1142 priv->atl_ints[queue_entry].qh = NULL;
1143 1130
1144 free_mem(priv, payload); 1131 free_mem(hcd, qtd);
1145 1132
1146 isp1760_writel(skip_map, usb_hcd->regs + 1133 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1147 HC_ATL_PTD_SKIPMAP_REG);
1148 1134
1149 if (urb->status == -EPIPE) { 1135 if (qtd->urb->status == -EPIPE) {
1150 /* HALT was received */ 1136 /* HALT was received */
1151 1137
1152 qtd = clean_up_qtdlist(qtd); 1138 urb = qtd->urb;
1153 isp1760_urb_done(priv, urb, urb->status); 1139 qtd = clean_up_qtdlist(qtd, qh);
1140 isp1760_urb_done(hcd, urb);
1154 1141
1155 } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) { 1142 } else if (usb_pipebulk(qtd->urb->pipe) &&
1143 (length < qtd->length)) {
1156 /* short BULK received */ 1144 /* short BULK received */
1157 1145
1158 if (urb->transfer_flags & URB_SHORT_NOT_OK) { 1146 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) {
1159 urb->status = -EREMOTEIO; 1147 qtd->urb->status = -EREMOTEIO;
1160 isp1760_dbg(priv, "short bulk, %d instead %zu " 1148 dev_dbg(hcd->self.controller,
1161 "with URB_SHORT_NOT_OK flag.\n", 1149 "short bulk, %d instead %zu "
1162 length, qtd->length); 1150 "with URB_SHORT_NOT_OK flag.\n",
1151 length, qtd->length);
1163 } 1152 }
1164 1153
1165 if (urb->status == -EINPROGRESS) 1154 if (qtd->urb->status == -EINPROGRESS)
1166 urb->status = 0; 1155 qtd->urb->status = 0;
1167
1168 qtd = clean_up_qtdlist(qtd);
1169 1156
1170 isp1760_urb_done(priv, urb, urb->status); 1157 urb = qtd->urb;
1158 qtd = clean_up_qtdlist(qtd, qh);
1159 isp1760_urb_done(hcd, urb);
1171 1160
1172 } else if (qtd->status & URB_COMPLETE_NOTIFY) { 1161 } else if (last_qtd_of_urb(qtd, qh)) {
1173 /* that was the last qtd of that URB */ 1162 /* that was the last qtd of that URB */
1174 1163
1175 if (urb->status == -EINPROGRESS) 1164 if (qtd->urb->status == -EINPROGRESS)
1176 urb->status = 0; 1165 qtd->urb->status = 0;
1177 1166
1178 qtd = clean_this_qtd(qtd); 1167 urb = qtd->urb;
1179 isp1760_urb_done(priv, urb, urb->status); 1168 qtd = clean_up_qtdlist(qtd, qh);
1169 isp1760_urb_done(hcd, urb);
1180 1170
1181 } else { 1171 } else {
1182 /* next QTD of this URB */ 1172 /* next QTD of this URB */
1183 1173
1184 qtd = clean_this_qtd(qtd); 1174 qtd = clean_this_qtd(qtd, qh);
1185 BUG_ON(!qtd); 1175 BUG_ON(!qtd);
1186 } 1176 }
1187 1177
1188 if (qtd) 1178 if (qtd)
1189 enqueue_an_ATL_packet(usb_hcd, qh, qtd); 1179 enqueue_an_ATL_packet(hcd, qh, qtd);
1190 1180
1191 skip_map = isp1760_readl(usb_hcd->regs + 1181 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1192 HC_ATL_PTD_SKIPMAP_REG);
1193 } 1182 }
1183 if (priv->atl_queued <= 1)
1184 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1185 INTERRUPT_ENABLE_MASK);
1194} 1186}
1195 1187
1196static void do_intl_int(struct usb_hcd *usb_hcd) 1188static void do_intl_int(struct usb_hcd *hcd)
1197{ 1189{
1198 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); 1190 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1199 u32 done_map, skip_map; 1191 u32 done_map, skip_map;
1200 struct ptd ptd; 1192 struct ptd ptd;
1201 struct urb *urb = NULL; 1193 struct urb *urb;
1202 u32 int_regs;
1203 u32 int_regs_base;
1204 u32 payload;
1205 u32 length; 1194 u32 length;
1206 u32 or_map; 1195 u32 or_map;
1207 int error; 1196 int error;
1208 u32 queue_entry; 1197 u32 slot;
1209 struct isp1760_qtd *qtd; 1198 struct isp1760_qtd *qtd;
1210 struct isp1760_qh *qh; 1199 struct isp1760_qh *qh;
1211 1200
1212 done_map = isp1760_readl(usb_hcd->regs + 1201 done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1213 HC_INT_PTD_DONEMAP_REG); 1202 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1214 skip_map = isp1760_readl(usb_hcd->regs +
1215 HC_INT_PTD_SKIPMAP_REG);
1216 1203
1217 or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); 1204 or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
1218 or_map &= ~done_map; 1205 or_map &= ~done_map;
1219 isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); 1206 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
1220
1221 int_regs_base = INT_REGS_OFFSET;
1222 1207
1223 while (done_map) { 1208 while (done_map) {
1224 u32 dw1; 1209 slot = __ffs(done_map);
1225 u32 dw3; 1210 done_map &= ~(1 << slot);
1211 skip_map |= (1 << slot);
1226 1212
1227 queue_entry = __ffs(done_map); 1213 qtd = priv->int_ints[slot].qtd;
1228 done_map &= ~(1 << queue_entry); 1214 qh = priv->int_ints[slot].qh;
1229 skip_map |= 1 << queue_entry;
1230
1231 int_regs = int_regs_base + queue_entry * sizeof(struct ptd);
1232 urb = priv->int_ints[queue_entry].urb;
1233 qtd = priv->int_ints[queue_entry].qtd;
1234 qh = priv->int_ints[queue_entry].qh;
1235 payload = priv->int_ints[queue_entry].payload;
1236 1215
1237 if (!qh) { 1216 if (!qh) {
1238 printk(KERN_ERR "(INT) qh is 0\n"); 1217 dev_err(hcd->self.controller, "(INT) qh is 0\n");
1239 continue; 1218 continue;
1240 } 1219 }
1241 1220
1242 isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs + 1221 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1243 HC_MEMORY_REG); 1222 check_int_err_status(hcd, ptd.dw4);
1244 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1245 HC_MEMORY_REG);
1246 /*
1247 * write bank1 address twice to ensure the 90ns delay (time
1248 * between BANK0 write and the priv_read_copy() call is at
1249 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
1250 */
1251 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1252 HC_MEMORY_REG);
1253 1223
1254 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs + 1224 error = check_error(hcd, &ptd);
1255 ISP_BANK(0), sizeof(ptd));
1256 dw1 = le32_to_cpu(ptd.dw1);
1257 dw3 = le32_to_cpu(ptd.dw3);
1258 check_int_err_status(le32_to_cpu(ptd.dw4));
1259
1260 error = check_error(&ptd);
1261 if (error) { 1225 if (error) {
1262#if 0 1226#if 0
1263 printk(KERN_ERR "Error in %s().\n", __func__); 1227 printk(KERN_ERR "Error in %s().\n", __func__);
@@ -1267,83 +1231,77 @@ static void do_intl_int(struct usb_hcd *usb_hcd)
1267 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, 1231 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1268 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); 1232 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1269#endif 1233#endif
1270 urb->status = -EPIPE; 1234 qtd->urb->status = -EPIPE;
1271 priv->int_ints[queue_entry].qh->toggle = 0; 1235 priv->int_ints[slot].qh->toggle = 0;
1272 priv->int_ints[queue_entry].qh->ping = 0; 1236 priv->int_ints[slot].qh->ping = 0;
1273 1237
1274 } else { 1238 } else {
1275 priv->int_ints[queue_entry].qh->toggle = 1239 priv->int_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
1276 dw3 & (1 << 25); 1240 priv->int_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
1277 priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26);
1278 } 1241 }
1279 1242
1280 if (urb->dev->speed != USB_SPEED_HIGH) 1243 if (qtd->urb->dev->speed != USB_SPEED_HIGH)
1281 length = PTD_XFERRED_LENGTH_LO(dw3); 1244 length = PTD_XFERRED_LENGTH_LO(ptd.dw3);
1282 else 1245 else
1283 length = PTD_XFERRED_LENGTH(dw3); 1246 length = PTD_XFERRED_LENGTH(ptd.dw3);
1284 1247
1285 if (length) { 1248 if (length) {
1286 switch (DW1_GET_PID(dw1)) { 1249 switch (DW1_GET_PID(ptd.dw1)) {
1287 case IN_PID: 1250 case IN_PID:
1288 priv_read_copy(priv, 1251 mem_reads8(hcd->regs, qtd->payload_addr,
1289 priv->int_ints[queue_entry].data_buffer, 1252 qtd->data_buffer, length);
1290 usb_hcd->regs + payload + ISP_BANK(1),
1291 length);
1292 case OUT_PID: 1253 case OUT_PID:
1293 1254
1294 urb->actual_length += length; 1255 qtd->urb->actual_length += length;
1295 1256
1296 case SETUP_PID: 1257 case SETUP_PID:
1297 break; 1258 break;
1298 } 1259 }
1299 } 1260 }
1300 1261
1301 priv->int_ints[queue_entry].data_buffer = NULL; 1262 priv->int_ints[slot].qtd = NULL;
1302 priv->int_ints[queue_entry].urb = NULL; 1263 priv->int_ints[slot].qh = NULL;
1303 priv->int_ints[queue_entry].qtd = NULL;
1304 priv->int_ints[queue_entry].qh = NULL;
1305 1264
1306 isp1760_writel(skip_map, usb_hcd->regs + 1265 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1307 HC_INT_PTD_SKIPMAP_REG); 1266 free_mem(hcd, qtd);
1308 free_mem(priv, payload);
1309 1267
1310 if (urb->status == -EPIPE) { 1268 if (qtd->urb->status == -EPIPE) {
1311 /* HALT received */ 1269 /* HALT received */
1312 1270
1313 qtd = clean_up_qtdlist(qtd); 1271 urb = qtd->urb;
1314 isp1760_urb_done(priv, urb, urb->status); 1272 qtd = clean_up_qtdlist(qtd, qh);
1273 isp1760_urb_done(hcd, urb);
1315 1274
1316 } else if (qtd->status & URB_COMPLETE_NOTIFY) { 1275 } else if (last_qtd_of_urb(qtd, qh)) {
1317 1276
1318 if (urb->status == -EINPROGRESS) 1277 if (qtd->urb->status == -EINPROGRESS)
1319 urb->status = 0; 1278 qtd->urb->status = 0;
1320 1279
1321 qtd = clean_this_qtd(qtd); 1280 urb = qtd->urb;
1322 isp1760_urb_done(priv, urb, urb->status); 1281 qtd = clean_up_qtdlist(qtd, qh);
1282 isp1760_urb_done(hcd, urb);
1323 1283
1324 } else { 1284 } else {
1325 /* next QTD of this URB */ 1285 /* next QTD of this URB */
1326 1286
1327 qtd = clean_this_qtd(qtd); 1287 qtd = clean_this_qtd(qtd, qh);
1328 BUG_ON(!qtd); 1288 BUG_ON(!qtd);
1329 } 1289 }
1330 1290
1331 if (qtd) 1291 if (qtd)
1332 enqueue_an_INT_packet(usb_hcd, qh, qtd); 1292 enqueue_an_INT_packet(hcd, qh, qtd);
1333 1293
1334 skip_map = isp1760_readl(usb_hcd->regs + 1294 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1335 HC_INT_PTD_SKIPMAP_REG);
1336 } 1295 }
1337} 1296}
1338 1297
1339#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 1298static struct isp1760_qh *qh_make(struct usb_hcd *hcd, struct urb *urb,
1340static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
1341 gfp_t flags) 1299 gfp_t flags)
1342{ 1300{
1343 struct isp1760_qh *qh; 1301 struct isp1760_qh *qh;
1344 int is_input, type; 1302 int is_input, type;
1345 1303
1346 qh = isp1760_qh_alloc(priv, flags); 1304 qh = isp1760_qh_alloc(flags);
1347 if (!qh) 1305 if (!qh)
1348 return qh; 1306 return qh;
1349 1307
@@ -1353,29 +1311,6 @@ static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
1353 is_input = usb_pipein(urb->pipe); 1311 is_input = usb_pipein(urb->pipe);
1354 type = usb_pipetype(urb->pipe); 1312 type = usb_pipetype(urb->pipe);
1355 1313
1356 if (type == PIPE_INTERRUPT) {
1357
1358 if (urb->dev->speed == USB_SPEED_HIGH) {
1359
1360 qh->period = urb->interval >> 3;
1361 if (qh->period == 0 && urb->interval != 1) {
1362 /* NOTE interval 2 or 4 uframes could work.
1363 * But interval 1 scheduling is simpler, and
1364 * includes high bandwidth.
1365 */
1366 printk(KERN_ERR "intr period %d uframes, NYET!",
1367 urb->interval);
1368 qh_destroy(qh);
1369 return NULL;
1370 }
1371 } else {
1372 qh->period = urb->interval;
1373 }
1374 }
1375
1376 /* support for tt scheduling, and access to toggles */
1377 qh->dev = urb->dev;
1378
1379 if (!usb_pipecontrol(urb->pipe)) 1314 if (!usb_pipecontrol(urb->pipe))
1380 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1315 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1381 1); 1316 1);
@@ -1388,43 +1323,27 @@ static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
1388 * Returns null if it can't allocate a QH it needs to. 1323 * Returns null if it can't allocate a QH it needs to.
1389 * If the QH has TDs (urbs) already, that's great. 1324 * If the QH has TDs (urbs) already, that's great.
1390 */ 1325 */
1391static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv, 1326static struct isp1760_qh *qh_append_tds(struct usb_hcd *hcd,
1392 struct urb *urb, struct list_head *qtd_list, int epnum, 1327 struct urb *urb, struct list_head *qtd_list, int epnum,
1393 void **ptr) 1328 void **ptr)
1394{ 1329{
1395 struct isp1760_qh *qh; 1330 struct isp1760_qh *qh;
1396 struct isp1760_qtd *qtd;
1397 struct isp1760_qtd *prev_qtd;
1398 1331
1399 qh = (struct isp1760_qh *)*ptr; 1332 qh = (struct isp1760_qh *)*ptr;
1400 if (!qh) { 1333 if (!qh) {
1401 /* can't sleep here, we have priv->lock... */ 1334 /* can't sleep here, we have priv->lock... */
1402 qh = qh_make(priv, urb, GFP_ATOMIC); 1335 qh = qh_make(hcd, urb, GFP_ATOMIC);
1403 if (!qh) 1336 if (!qh)
1404 return qh; 1337 return qh;
1405 *ptr = qh; 1338 *ptr = qh;
1406 } 1339 }
1407 1340
1408 qtd = list_entry(qtd_list->next, struct isp1760_qtd,
1409 qtd_list);
1410 if (!list_empty(&qh->qtd_list))
1411 prev_qtd = list_entry(qh->qtd_list.prev,
1412 struct isp1760_qtd, qtd_list);
1413 else
1414 prev_qtd = NULL;
1415
1416 list_splice(qtd_list, qh->qtd_list.prev); 1341 list_splice(qtd_list, qh->qtd_list.prev);
1417 if (prev_qtd) {
1418 BUG_ON(prev_qtd->hw_next);
1419 prev_qtd->hw_next = qtd;
1420 }
1421 1342
1422 urb->hcpriv = qh;
1423 return qh; 1343 return qh;
1424} 1344}
1425 1345
1426static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb, 1346static void qtd_list_free(struct urb *urb, struct list_head *qtd_list)
1427 struct list_head *qtd_list)
1428{ 1347{
1429 struct list_head *entry, *temp; 1348 struct list_head *entry, *temp;
1430 1349
@@ -1437,9 +1356,10 @@ static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb,
1437 } 1356 }
1438} 1357}
1439 1358
1440static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb, 1359static int isp1760_prepare_enqueue(struct usb_hcd *hcd, struct urb *urb,
1441 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p) 1360 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1442{ 1361{
1362 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1443 struct isp1760_qtd *qtd; 1363 struct isp1760_qtd *qtd;
1444 int epnum; 1364 int epnum;
1445 unsigned long flags; 1365 unsigned long flags;
@@ -1451,11 +1371,11 @@ static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
1451 epnum = urb->ep->desc.bEndpointAddress; 1371 epnum = urb->ep->desc.bEndpointAddress;
1452 1372
1453 spin_lock_irqsave(&priv->lock, flags); 1373 spin_lock_irqsave(&priv->lock, flags);
1454 if (!HCD_HW_ACCESSIBLE(priv_to_hcd(priv))) { 1374 if (!HCD_HW_ACCESSIBLE(hcd)) {
1455 rc = -ESHUTDOWN; 1375 rc = -ESHUTDOWN;
1456 goto done; 1376 goto done;
1457 } 1377 }
1458 rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb); 1378 rc = usb_hcd_link_urb_to_ep(hcd, urb);
1459 if (rc) 1379 if (rc)
1460 goto done; 1380 goto done;
1461 1381
@@ -1465,25 +1385,24 @@ static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
1465 else 1385 else
1466 qh_busy = 0; 1386 qh_busy = 0;
1467 1387
1468 qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv); 1388 qh = qh_append_tds(hcd, urb, qtd_list, epnum, &urb->ep->hcpriv);
1469 if (!qh) { 1389 if (!qh) {
1470 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); 1390 usb_hcd_unlink_urb_from_ep(hcd, urb);
1471 rc = -ENOMEM; 1391 rc = -ENOMEM;
1472 goto done; 1392 goto done;
1473 } 1393 }
1474 1394
1475 if (!qh_busy) 1395 if (!qh_busy)
1476 p(priv_to_hcd(priv), qh, qtd); 1396 p(hcd, qh, qtd);
1477 1397
1478done: 1398done:
1479 spin_unlock_irqrestore(&priv->lock, flags); 1399 spin_unlock_irqrestore(&priv->lock, flags);
1480 if (!qh) 1400 if (!qh)
1481 qtd_list_free(priv, urb, qtd_list); 1401 qtd_list_free(urb, qtd_list);
1482 return rc; 1402 return rc;
1483} 1403}
1484 1404
1485static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv, 1405static struct isp1760_qtd *isp1760_qtd_alloc(gfp_t flags)
1486 gfp_t flags)
1487{ 1406{
1488 struct isp1760_qtd *qtd; 1407 struct isp1760_qtd *qtd;
1489 1408
@@ -1497,10 +1416,11 @@ static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv,
1497/* 1416/*
1498 * create a list of filled qtds for this URB; won't link into qh. 1417 * create a list of filled qtds for this URB; won't link into qh.
1499 */ 1418 */
1500static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv, 1419#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1420static struct list_head *qh_urb_transaction(struct usb_hcd *hcd,
1501 struct urb *urb, struct list_head *head, gfp_t flags) 1421 struct urb *urb, struct list_head *head, gfp_t flags)
1502{ 1422{
1503 struct isp1760_qtd *qtd, *qtd_prev; 1423 struct isp1760_qtd *qtd;
1504 void *buf; 1424 void *buf;
1505 int len, maxpacket; 1425 int len, maxpacket;
1506 int is_input; 1426 int is_input;
@@ -1509,7 +1429,7 @@ static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1509 /* 1429 /*
1510 * URBs map to sequences of QTDs: one logical transaction 1430 * URBs map to sequences of QTDs: one logical transaction
1511 */ 1431 */
1512 qtd = isp1760_qtd_alloc(priv, flags); 1432 qtd = isp1760_qtd_alloc(flags);
1513 if (!qtd) 1433 if (!qtd)
1514 return NULL; 1434 return NULL;
1515 1435
@@ -1529,13 +1449,10 @@ static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1529 token | SETUP_PID); 1449 token | SETUP_PID);
1530 1450
1531 /* ... and always at least one more pid */ 1451 /* ... and always at least one more pid */
1532 token ^= DATA_TOGGLE; 1452 qtd = isp1760_qtd_alloc(flags);
1533 qtd_prev = qtd;
1534 qtd = isp1760_qtd_alloc(priv, flags);
1535 if (!qtd) 1453 if (!qtd)
1536 goto cleanup; 1454 goto cleanup;
1537 qtd->urb = urb; 1455 qtd->urb = urb;
1538 qtd_prev->hw_next = qtd;
1539 list_add_tail(&qtd->qtd_list, head); 1456 list_add_tail(&qtd->qtd_list, head);
1540 1457
1541 /* for zero length DATA stages, STATUS is always IN */ 1458 /* for zero length DATA stages, STATUS is always IN */
@@ -1565,7 +1482,7 @@ static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1565 1482
1566 if (!buf && len) { 1483 if (!buf && len) {
1567 /* XXX This looks like usb storage / SCSI bug */ 1484 /* XXX This looks like usb storage / SCSI bug */
1568 printk(KERN_ERR "buf is null, dma is %08lx len is %d\n", 1485 dev_err(hcd->self.controller, "buf is null, dma is %08lx len is %d\n",
1569 (long unsigned)urb->transfer_dma, len); 1486 (long unsigned)urb->transfer_dma, len);
1570 WARN_ON(1); 1487 WARN_ON(1);
1571 } 1488 }
@@ -1574,19 +1491,13 @@ static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1574 len -= this_qtd_len; 1491 len -= this_qtd_len;
1575 buf += this_qtd_len; 1492 buf += this_qtd_len;
1576 1493
1577 /* qh makes control packets use qtd toggle; maybe switch it */
1578 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1579 token ^= DATA_TOGGLE;
1580
1581 if (len <= 0) 1494 if (len <= 0)
1582 break; 1495 break;
1583 1496
1584 qtd_prev = qtd; 1497 qtd = isp1760_qtd_alloc(flags);
1585 qtd = isp1760_qtd_alloc(priv, flags);
1586 if (!qtd) 1498 if (!qtd)
1587 goto cleanup; 1499 goto cleanup;
1588 qtd->urb = urb; 1500 qtd->urb = urb;
1589 qtd_prev->hw_next = qtd;
1590 list_add_tail(&qtd->qtd_list, head); 1501 list_add_tail(&qtd->qtd_list, head);
1591 } 1502 }
1592 1503
@@ -1601,20 +1512,16 @@ static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1601 one_more = 1; 1512 one_more = 1;
1602 /* "in" <--> "out" */ 1513 /* "in" <--> "out" */
1603 token ^= IN_PID; 1514 token ^= IN_PID;
1604 /* force DATA1 */
1605 token |= DATA_TOGGLE;
1606 } else if (usb_pipebulk(urb->pipe) 1515 } else if (usb_pipebulk(urb->pipe)
1607 && (urb->transfer_flags & URB_ZERO_PACKET) 1516 && (urb->transfer_flags & URB_ZERO_PACKET)
1608 && !(urb->transfer_buffer_length % maxpacket)) { 1517 && !(urb->transfer_buffer_length % maxpacket)) {
1609 one_more = 1; 1518 one_more = 1;
1610 } 1519 }
1611 if (one_more) { 1520 if (one_more) {
1612 qtd_prev = qtd; 1521 qtd = isp1760_qtd_alloc(flags);
1613 qtd = isp1760_qtd_alloc(priv, flags);
1614 if (!qtd) 1522 if (!qtd)
1615 goto cleanup; 1523 goto cleanup;
1616 qtd->urb = urb; 1524 qtd->urb = urb;
1617 qtd_prev->hw_next = qtd;
1618 list_add_tail(&qtd->qtd_list, head); 1525 list_add_tail(&qtd->qtd_list, head);
1619 1526
1620 /* never any data in such packets */ 1527 /* never any data in such packets */
@@ -1622,18 +1529,17 @@ static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1622 } 1529 }
1623 } 1530 }
1624 1531
1625 qtd->status = URB_COMPLETE_NOTIFY; 1532 qtd->status = 0;
1626 return head; 1533 return head;
1627 1534
1628cleanup: 1535cleanup:
1629 qtd_list_free(priv, urb, head); 1536 qtd_list_free(urb, head);
1630 return NULL; 1537 return NULL;
1631} 1538}
1632 1539
1633static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 1540static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1634 gfp_t mem_flags) 1541 gfp_t mem_flags)
1635{ 1542{
1636 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1637 struct list_head qtd_list; 1543 struct list_head qtd_list;
1638 packet_enqueue *pe; 1544 packet_enqueue *pe;
1639 1545
@@ -1642,29 +1548,27 @@ static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1642 switch (usb_pipetype(urb->pipe)) { 1548 switch (usb_pipetype(urb->pipe)) {
1643 case PIPE_CONTROL: 1549 case PIPE_CONTROL:
1644 case PIPE_BULK: 1550 case PIPE_BULK:
1645 1551 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1646 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1647 return -ENOMEM; 1552 return -ENOMEM;
1648 pe = enqueue_an_ATL_packet; 1553 pe = enqueue_an_ATL_packet;
1649 break; 1554 break;
1650 1555
1651 case PIPE_INTERRUPT: 1556 case PIPE_INTERRUPT:
1652 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) 1557 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1653 return -ENOMEM; 1558 return -ENOMEM;
1654 pe = enqueue_an_INT_packet; 1559 pe = enqueue_an_INT_packet;
1655 break; 1560 break;
1656 1561
1657 case PIPE_ISOCHRONOUS: 1562 case PIPE_ISOCHRONOUS:
1658 printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n"); 1563 dev_err(hcd->self.controller, "PIPE_ISOCHRONOUS ain't supported\n");
1659 default: 1564 default:
1660 return -EPIPE; 1565 return -EPIPE;
1661 } 1566 }
1662 1567
1663 return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe); 1568 return isp1760_prepare_enqueue(hcd, urb, &qtd_list, mem_flags, pe);
1664} 1569}
1665 1570
1666static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 1571static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1667 int status)
1668{ 1572{
1669 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1573 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1670 struct inter_packet_info *ints; 1574 struct inter_packet_info *ints;
@@ -1681,7 +1585,7 @@ static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1681 1585
1682 case PIPE_INTERRUPT: 1586 case PIPE_INTERRUPT:
1683 ints = priv->int_ints; 1587 ints = priv->int_ints;
1684 reg_base = INT_REGS_OFFSET; 1588 reg_base = INT_PTD_OFFSET;
1685 or_reg = HC_INT_IRQ_MASK_OR_REG; 1589 or_reg = HC_INT_IRQ_MASK_OR_REG;
1686 skip_reg = HC_INT_PTD_SKIPMAP_REG; 1590 skip_reg = HC_INT_PTD_SKIPMAP_REG;
1687 pe = enqueue_an_INT_packet; 1591 pe = enqueue_an_INT_packet;
@@ -1689,7 +1593,7 @@ static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1689 1593
1690 default: 1594 default:
1691 ints = priv->atl_ints; 1595 ints = priv->atl_ints;
1692 reg_base = ATL_REGS_OFFSET; 1596 reg_base = ATL_PTD_OFFSET;
1693 or_reg = HC_ATL_IRQ_MASK_OR_REG; 1597 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1694 skip_reg = HC_ATL_PTD_SKIPMAP_REG; 1598 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
1695 pe = enqueue_an_ATL_packet; 1599 pe = enqueue_an_ATL_packet;
@@ -1700,81 +1604,84 @@ static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1700 spin_lock_irqsave(&priv->lock, flags); 1604 spin_lock_irqsave(&priv->lock, flags);
1701 1605
1702 for (i = 0; i < 32; i++) { 1606 for (i = 0; i < 32; i++) {
1703 if (ints->urb == urb) { 1607 if (!ints[i].qh)
1608 continue;
1609 BUG_ON(!ints[i].qtd);
1610
1611 if (ints[i].qtd->urb == urb) {
1704 u32 skip_map; 1612 u32 skip_map;
1705 u32 or_map; 1613 u32 or_map;
1706 struct isp1760_qtd *qtd; 1614 struct isp1760_qtd *qtd;
1707 struct isp1760_qh *qh = ints->qh; 1615 struct isp1760_qh *qh;
1708 1616
1709 skip_map = isp1760_readl(hcd->regs + skip_reg); 1617 skip_map = reg_read32(hcd->regs, skip_reg);
1710 skip_map |= 1 << i; 1618 skip_map |= 1 << i;
1711 isp1760_writel(skip_map, hcd->regs + skip_reg); 1619 reg_write32(hcd->regs, skip_reg, skip_map);
1712 1620
1713 or_map = isp1760_readl(hcd->regs + or_reg); 1621 or_map = reg_read32(hcd->regs, or_reg);
1714 or_map &= ~(1 << i); 1622 or_map &= ~(1 << i);
1715 isp1760_writel(or_map, hcd->regs + or_reg); 1623 reg_write32(hcd->regs, or_reg, or_map);
1624
1625 ptd_write(hcd->regs, reg_base, i, &ptd);
1716 1626
1717 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base 1627 qtd = ints[i].qtd;
1718 + i * sizeof(ptd), sizeof(ptd)); 1628 qh = ints[i].qh;
1719 qtd = ints->qtd;
1720 qtd = clean_up_qtdlist(qtd);
1721 1629
1722 free_mem(priv, ints->payload); 1630 free_mem(hcd, qtd);
1631 qtd = clean_up_qtdlist(qtd, qh);
1723 1632
1724 ints->urb = NULL; 1633 ints[i].qh = NULL;
1725 ints->qh = NULL; 1634 ints[i].qtd = NULL;
1726 ints->qtd = NULL;
1727 ints->data_buffer = NULL;
1728 ints->payload = 0;
1729 1635
1730 isp1760_urb_done(priv, urb, status); 1636 isp1760_urb_done(hcd, urb);
1731 if (qtd) 1637 if (qtd)
1732 pe(hcd, qh, qtd); 1638 pe(hcd, qh, qtd);
1733 break; 1639 break;
1734 1640
1735 } else if (ints->qtd) { 1641 } else {
1736 struct isp1760_qtd *qtd, *prev_qtd = ints->qtd; 1642 struct isp1760_qtd *qtd;
1737 1643
1738 for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) { 1644 list_for_each_entry(qtd, &ints[i].qtd->qtd_list,
1645 qtd_list) {
1739 if (qtd->urb == urb) { 1646 if (qtd->urb == urb) {
1740 prev_qtd->hw_next = clean_up_qtdlist(qtd); 1647 clean_up_qtdlist(qtd, ints[i].qh);
1741 isp1760_urb_done(priv, urb, status); 1648 isp1760_urb_done(hcd, urb);
1649 qtd = NULL;
1742 break; 1650 break;
1743 } 1651 }
1744 prev_qtd = qtd;
1745 } 1652 }
1746 /* we found the urb before the end of the list */ 1653
1747 if (qtd) 1654 /* We found the urb before the last slot */
1655 if (!qtd)
1748 break; 1656 break;
1749 } 1657 }
1750 ints++;
1751 } 1658 }
1752 1659
1753 spin_unlock_irqrestore(&priv->lock, flags); 1660 spin_unlock_irqrestore(&priv->lock, flags);
1754 return 0; 1661 return 0;
1755} 1662}
1756 1663
1757static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd) 1664static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1758{ 1665{
1759 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); 1666 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1760 u32 imask; 1667 u32 imask;
1761 irqreturn_t irqret = IRQ_NONE; 1668 irqreturn_t irqret = IRQ_NONE;
1762 1669
1763 spin_lock(&priv->lock); 1670 spin_lock(&priv->lock);
1764 1671
1765 if (!(usb_hcd->state & HC_STATE_RUNNING)) 1672 if (!(hcd->state & HC_STATE_RUNNING))
1766 goto leave; 1673 goto leave;
1767 1674
1768 imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG); 1675 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1769 if (unlikely(!imask)) 1676 if (unlikely(!imask))
1770 goto leave; 1677 goto leave;
1771 1678
1772 isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG); 1679 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask);
1773 if (imask & HC_ATL_INT) 1680 if (imask & (HC_ATL_INT | HC_SOT_INT))
1774 do_atl_int(usb_hcd); 1681 do_atl_int(hcd);
1775 1682
1776 if (imask & HC_INTL_INT) 1683 if (imask & HC_INTL_INT)
1777 do_intl_int(usb_hcd); 1684 do_intl_int(hcd);
1778 1685
1779 irqret = IRQ_HANDLED; 1686 irqret = IRQ_HANDLED;
1780leave: 1687leave:
@@ -1799,12 +1706,12 @@ static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1799 mask = PORT_CSC; 1706 mask = PORT_CSC;
1800 1707
1801 spin_lock_irqsave(&priv->lock, flags); 1708 spin_lock_irqsave(&priv->lock, flags);
1802 temp = isp1760_readl(hcd->regs + HC_PORTSC1); 1709 temp = reg_read32(hcd->regs, HC_PORTSC1);
1803 1710
1804 if (temp & PORT_OWNER) { 1711 if (temp & PORT_OWNER) {
1805 if (temp & PORT_CSC) { 1712 if (temp & PORT_CSC) {
1806 temp &= ~PORT_CSC; 1713 temp &= ~PORT_CSC;
1807 isp1760_writel(temp, hcd->regs + HC_PORTSC1); 1714 reg_write32(hcd->regs, HC_PORTSC1, temp);
1808 goto done; 1715 goto done;
1809 } 1716 }
1810 } 1717 }
@@ -1844,9 +1751,9 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1844 temp = 1 + (ports / 8); 1751 temp = 1 + (ports / 8);
1845 desc->bDescLength = 7 + 2 * temp; 1752 desc->bDescLength = 7 + 2 * temp;
1846 1753
1847 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 1754 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1848 memset(&desc->bitmap[0], 0, temp); 1755 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1849 memset(&desc->bitmap[temp], 0xff, temp); 1756 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1850 1757
1851 /* per-port overcurrent reporting */ 1758 /* per-port overcurrent reporting */
1852 temp = 0x0008; 1759 temp = 0x0008;
@@ -1861,8 +1768,8 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1861 1768
1862#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) 1769#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1863 1770
1864static int check_reset_complete(struct isp1760_hcd *priv, int index, 1771static int check_reset_complete(struct usb_hcd *hcd, int index,
1865 u32 __iomem *status_reg, int port_status) 1772 int port_status)
1866{ 1773{
1867 if (!(port_status & PORT_CONNECT)) 1774 if (!(port_status & PORT_CONNECT))
1868 return port_status; 1775 return port_status;
@@ -1870,15 +1777,17 @@ static int check_reset_complete(struct isp1760_hcd *priv, int index,
1870 /* if reset finished and it's still not enabled -- handoff */ 1777 /* if reset finished and it's still not enabled -- handoff */
1871 if (!(port_status & PORT_PE)) { 1778 if (!(port_status & PORT_PE)) {
1872 1779
1873 printk(KERN_ERR "port %d full speed --> companion\n", 1780 dev_err(hcd->self.controller,
1874 index + 1); 1781 "port %d full speed --> companion\n",
1782 index + 1);
1875 1783
1876 port_status |= PORT_OWNER; 1784 port_status |= PORT_OWNER;
1877 port_status &= ~PORT_RWC_BITS; 1785 port_status &= ~PORT_RWC_BITS;
1878 isp1760_writel(port_status, status_reg); 1786 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1879 1787
1880 } else 1788 } else
1881 printk(KERN_ERR "port %d high speed\n", index + 1); 1789 dev_err(hcd->self.controller, "port %d high speed\n",
1790 index + 1);
1882 1791
1883 return port_status; 1792 return port_status;
1884} 1793}
@@ -1888,7 +1797,6 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1888{ 1797{
1889 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1798 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1890 int ports = HCS_N_PORTS(priv->hcs_params); 1799 int ports = HCS_N_PORTS(priv->hcs_params);
1891 u32 __iomem *status_reg = hcd->regs + HC_PORTSC1;
1892 u32 temp, status; 1800 u32 temp, status;
1893 unsigned long flags; 1801 unsigned long flags;
1894 int retval = 0; 1802 int retval = 0;
@@ -1917,7 +1825,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1917 if (!wIndex || wIndex > ports) 1825 if (!wIndex || wIndex > ports)
1918 goto error; 1826 goto error;
1919 wIndex--; 1827 wIndex--;
1920 temp = isp1760_readl(status_reg); 1828 temp = reg_read32(hcd->regs, HC_PORTSC1);
1921 1829
1922 /* 1830 /*
1923 * Even if OWNER is set, so the port is owned by the 1831 * Even if OWNER is set, so the port is owned by the
@@ -1928,7 +1836,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1928 1836
1929 switch (wValue) { 1837 switch (wValue) {
1930 case USB_PORT_FEAT_ENABLE: 1838 case USB_PORT_FEAT_ENABLE:
1931 isp1760_writel(temp & ~PORT_PE, status_reg); 1839 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1932 break; 1840 break;
1933 case USB_PORT_FEAT_C_ENABLE: 1841 case USB_PORT_FEAT_C_ENABLE:
1934 /* XXX error? */ 1842 /* XXX error? */
@@ -1942,8 +1850,8 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1942 goto error; 1850 goto error;
1943 /* resume signaling for 20 msec */ 1851 /* resume signaling for 20 msec */
1944 temp &= ~(PORT_RWC_BITS); 1852 temp &= ~(PORT_RWC_BITS);
1945 isp1760_writel(temp | PORT_RESUME, 1853 reg_write32(hcd->regs, HC_PORTSC1,
1946 status_reg); 1854 temp | PORT_RESUME);
1947 priv->reset_done = jiffies + 1855 priv->reset_done = jiffies +
1948 msecs_to_jiffies(20); 1856 msecs_to_jiffies(20);
1949 } 1857 }
@@ -1953,11 +1861,11 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1953 break; 1861 break;
1954 case USB_PORT_FEAT_POWER: 1862 case USB_PORT_FEAT_POWER:
1955 if (HCS_PPC(priv->hcs_params)) 1863 if (HCS_PPC(priv->hcs_params))
1956 isp1760_writel(temp & ~PORT_POWER, status_reg); 1864 reg_write32(hcd->regs, HC_PORTSC1,
1865 temp & ~PORT_POWER);
1957 break; 1866 break;
1958 case USB_PORT_FEAT_C_CONNECTION: 1867 case USB_PORT_FEAT_C_CONNECTION:
1959 isp1760_writel(temp | PORT_CSC, 1868 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1960 status_reg);
1961 break; 1869 break;
1962 case USB_PORT_FEAT_C_OVER_CURRENT: 1870 case USB_PORT_FEAT_C_OVER_CURRENT:
1963 /* XXX error ?*/ 1871 /* XXX error ?*/
@@ -1968,7 +1876,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1968 default: 1876 default:
1969 goto error; 1877 goto error;
1970 } 1878 }
1971 isp1760_readl(hcd->regs + HC_USBCMD); 1879 reg_read32(hcd->regs, HC_USBCMD);
1972 break; 1880 break;
1973 case GetHubDescriptor: 1881 case GetHubDescriptor:
1974 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) 1882 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
@@ -1983,7 +1891,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1983 goto error; 1891 goto error;
1984 wIndex--; 1892 wIndex--;
1985 status = 0; 1893 status = 0;
1986 temp = isp1760_readl(status_reg); 1894 temp = reg_read32(hcd->regs, HC_PORTSC1);
1987 1895
1988 /* wPortChange bits */ 1896 /* wPortChange bits */
1989 if (temp & PORT_CSC) 1897 if (temp & PORT_CSC)
@@ -1992,7 +1900,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1992 1900
1993 /* whoever resumes must GetPortStatus to complete it!! */ 1901 /* whoever resumes must GetPortStatus to complete it!! */
1994 if (temp & PORT_RESUME) { 1902 if (temp & PORT_RESUME) {
1995 printk(KERN_ERR "Port resume should be skipped.\n"); 1903 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1996 1904
1997 /* Remote Wakeup received? */ 1905 /* Remote Wakeup received? */
1998 if (!priv->reset_done) { 1906 if (!priv->reset_done) {
@@ -2000,8 +1908,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2000 priv->reset_done = jiffies 1908 priv->reset_done = jiffies
2001 + msecs_to_jiffies(20); 1909 + msecs_to_jiffies(20);
2002 /* check the port again */ 1910 /* check the port again */
2003 mod_timer(&priv_to_hcd(priv)->rh_timer, 1911 mod_timer(&hcd->rh_timer, priv->reset_done);
2004 priv->reset_done);
2005 } 1912 }
2006 1913
2007 /* resume completed? */ 1914 /* resume completed? */
@@ -2011,14 +1918,13 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2011 priv->reset_done = 0; 1918 priv->reset_done = 0;
2012 1919
2013 /* stop resume signaling */ 1920 /* stop resume signaling */
2014 temp = isp1760_readl(status_reg); 1921 temp = reg_read32(hcd->regs, HC_PORTSC1);
2015 isp1760_writel( 1922 reg_write32(hcd->regs, HC_PORTSC1,
2016 temp & ~(PORT_RWC_BITS | PORT_RESUME), 1923 temp & ~(PORT_RWC_BITS | PORT_RESUME));
2017 status_reg); 1924 retval = handshake(hcd, HC_PORTSC1,
2018 retval = handshake(priv, status_reg,
2019 PORT_RESUME, 0, 2000 /* 2msec */); 1925 PORT_RESUME, 0, 2000 /* 2msec */);
2020 if (retval != 0) { 1926 if (retval != 0) {
2021 isp1760_err(priv, 1927 dev_err(hcd->self.controller,
2022 "port %d resume error %d\n", 1928 "port %d resume error %d\n",
2023 wIndex + 1, retval); 1929 wIndex + 1, retval);
2024 goto error; 1930 goto error;
@@ -2035,22 +1941,21 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2035 priv->reset_done = 0; 1941 priv->reset_done = 0;
2036 1942
2037 /* force reset to complete */ 1943 /* force reset to complete */
2038 isp1760_writel(temp & ~PORT_RESET, 1944 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
2039 status_reg);
2040 /* REVISIT: some hardware needs 550+ usec to clear 1945 /* REVISIT: some hardware needs 550+ usec to clear
2041 * this bit; seems too long to spin routinely... 1946 * this bit; seems too long to spin routinely...
2042 */ 1947 */
2043 retval = handshake(priv, status_reg, 1948 retval = handshake(hcd, HC_PORTSC1,
2044 PORT_RESET, 0, 750); 1949 PORT_RESET, 0, 750);
2045 if (retval != 0) { 1950 if (retval != 0) {
2046 isp1760_err(priv, "port %d reset error %d\n", 1951 dev_err(hcd->self.controller, "port %d reset error %d\n",
2047 wIndex + 1, retval); 1952 wIndex + 1, retval);
2048 goto error; 1953 goto error;
2049 } 1954 }
2050 1955
2051 /* see what we found out */ 1956 /* see what we found out */
2052 temp = check_reset_complete(priv, wIndex, status_reg, 1957 temp = check_reset_complete(hcd, wIndex,
2053 isp1760_readl(status_reg)); 1958 reg_read32(hcd->regs, HC_PORTSC1));
2054 } 1959 }
2055 /* 1960 /*
2056 * Even if OWNER is set, there's no harm letting khubd 1961 * Even if OWNER is set, there's no harm letting khubd
@@ -2059,12 +1964,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2059 */ 1964 */
2060 1965
2061 if (temp & PORT_OWNER) 1966 if (temp & PORT_OWNER)
2062 printk(KERN_ERR "Warning: PORT_OWNER is set\n"); 1967 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2063 1968
2064 if (temp & PORT_CONNECT) { 1969 if (temp & PORT_CONNECT) {
2065 status |= USB_PORT_STAT_CONNECTION; 1970 status |= USB_PORT_STAT_CONNECTION;
2066 /* status may be from integrated TT */ 1971 /* status may be from integrated TT */
2067 status |= ehci_port_speed(priv, temp); 1972 status |= USB_PORT_STAT_HIGH_SPEED;
2068 } 1973 }
2069 if (temp & PORT_PE) 1974 if (temp & PORT_PE)
2070 status |= USB_PORT_STAT_ENABLE; 1975 status |= USB_PORT_STAT_ENABLE;
@@ -2093,14 +1998,14 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2093 if (!wIndex || wIndex > ports) 1998 if (!wIndex || wIndex > ports)
2094 goto error; 1999 goto error;
2095 wIndex--; 2000 wIndex--;
2096 temp = isp1760_readl(status_reg); 2001 temp = reg_read32(hcd->regs, HC_PORTSC1);
2097 if (temp & PORT_OWNER) 2002 if (temp & PORT_OWNER)
2098 break; 2003 break;
2099 2004
2100/* temp &= ~PORT_RWC_BITS; */ 2005/* temp &= ~PORT_RWC_BITS; */
2101 switch (wValue) { 2006 switch (wValue) {
2102 case USB_PORT_FEAT_ENABLE: 2007 case USB_PORT_FEAT_ENABLE:
2103 isp1760_writel(temp | PORT_PE, status_reg); 2008 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2104 break; 2009 break;
2105 2010
2106 case USB_PORT_FEAT_SUSPEND: 2011 case USB_PORT_FEAT_SUSPEND:
@@ -2108,12 +2013,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2108 || (temp & PORT_RESET) != 0) 2013 || (temp & PORT_RESET) != 0)
2109 goto error; 2014 goto error;
2110 2015
2111 isp1760_writel(temp | PORT_SUSPEND, status_reg); 2016 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2112 break; 2017 break;
2113 case USB_PORT_FEAT_POWER: 2018 case USB_PORT_FEAT_POWER:
2114 if (HCS_PPC(priv->hcs_params)) 2019 if (HCS_PPC(priv->hcs_params))
2115 isp1760_writel(temp | PORT_POWER, 2020 reg_write32(hcd->regs, HC_PORTSC1,
2116 status_reg); 2021 temp | PORT_POWER);
2117 break; 2022 break;
2118 case USB_PORT_FEAT_RESET: 2023 case USB_PORT_FEAT_RESET:
2119 if (temp & PORT_RESUME) 2024 if (temp & PORT_RESUME)
@@ -2136,12 +2041,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
2136 priv->reset_done = jiffies + 2041 priv->reset_done = jiffies +
2137 msecs_to_jiffies(50); 2042 msecs_to_jiffies(50);
2138 } 2043 }
2139 isp1760_writel(temp, status_reg); 2044 reg_write32(hcd->regs, HC_PORTSC1, temp);
2140 break; 2045 break;
2141 default: 2046 default:
2142 goto error; 2047 goto error;
2143 } 2048 }
2144 isp1760_readl(hcd->regs + HC_USBCMD); 2049 reg_read32(hcd->regs, HC_USBCMD);
2145 break; 2050 break;
2146 2051
2147 default: 2052 default:
@@ -2153,10 +2058,10 @@ error:
2153 return retval; 2058 return retval;
2154} 2059}
2155 2060
2156static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd, 2061static void isp1760_endpoint_disable(struct usb_hcd *hcd,
2157 struct usb_host_endpoint *ep) 2062 struct usb_host_endpoint *ep)
2158{ 2063{
2159 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); 2064 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2160 struct isp1760_qh *qh; 2065 struct isp1760_qh *qh;
2161 struct isp1760_qtd *qtd; 2066 struct isp1760_qtd *qtd;
2162 unsigned long flags; 2067 unsigned long flags;
@@ -2176,16 +2081,16 @@ static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd,
2176 qtd_list); 2081 qtd_list);
2177 2082
2178 if (qtd->status & URB_ENQUEUED) { 2083 if (qtd->status & URB_ENQUEUED) {
2179
2180 spin_unlock_irqrestore(&priv->lock, flags); 2084 spin_unlock_irqrestore(&priv->lock, flags);
2181 isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET); 2085 isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET);
2182 spin_lock_irqsave(&priv->lock, flags); 2086 spin_lock_irqsave(&priv->lock, flags);
2183 } else { 2087 } else {
2184 struct urb *urb; 2088 struct urb *urb;
2185 2089
2186 urb = qtd->urb; 2090 urb = qtd->urb;
2187 clean_up_qtdlist(qtd); 2091 clean_up_qtdlist(qtd, qh);
2188 isp1760_urb_done(priv, urb, -ECONNRESET); 2092 urb->status = -ECONNRESET;
2093 isp1760_urb_done(hcd, urb);
2189 } 2094 }
2190 } while (1); 2095 } while (1);
2191 2096
@@ -2203,7 +2108,7 @@ static int isp1760_get_frame(struct usb_hcd *hcd)
2203 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2108 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2204 u32 fr; 2109 u32 fr;
2205 2110
2206 fr = isp1760_readl(hcd->regs + HC_FRINDEX); 2111 fr = reg_read32(hcd->regs, HC_FRINDEX);
2207 return (fr >> 3) % priv->periodic_size; 2112 return (fr >> 3) % priv->periodic_size;
2208} 2113}
2209 2114
@@ -2217,13 +2122,13 @@ static void isp1760_stop(struct usb_hcd *hcd)
2217 mdelay(20); 2122 mdelay(20);
2218 2123
2219 spin_lock_irq(&priv->lock); 2124 spin_lock_irq(&priv->lock);
2220 ehci_reset(priv); 2125 ehci_reset(hcd);
2221 /* Disable IRQ */ 2126 /* Disable IRQ */
2222 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); 2127 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2223 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); 2128 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2224 spin_unlock_irq(&priv->lock); 2129 spin_unlock_irq(&priv->lock);
2225 2130
2226 isp1760_writel(0, hcd->regs + HC_CONFIGFLAG); 2131 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2227} 2132}
2228 2133
2229static void isp1760_shutdown(struct usb_hcd *hcd) 2134static void isp1760_shutdown(struct usb_hcd *hcd)
@@ -2231,12 +2136,12 @@ static void isp1760_shutdown(struct usb_hcd *hcd)
2231 u32 command, temp; 2136 u32 command, temp;
2232 2137
2233 isp1760_stop(hcd); 2138 isp1760_stop(hcd);
2234 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); 2139 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2235 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); 2140 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2236 2141
2237 command = isp1760_readl(hcd->regs + HC_USBCMD); 2142 command = reg_read32(hcd->regs, HC_USBCMD);
2238 command &= ~CMD_RUN; 2143 command &= ~CMD_RUN;
2239 isp1760_writel(command, hcd->regs + HC_USBCMD); 2144 reg_write32(hcd->regs, HC_USBCMD, command);
2240} 2145}
2241 2146
2242static const struct hc_driver isp1760_hc_driver = { 2147static const struct hc_driver isp1760_hc_driver = {
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h
index 6931ef5c9650..870507690607 100644
--- a/drivers/usb/host/isp1760-hcd.h
+++ b/drivers/usb/host/isp1760-hcd.h
@@ -69,6 +69,7 @@ void deinit_kmem_cache(void);
69 69
70#define HC_INTERRUPT_ENABLE 0x314 70#define HC_INTERRUPT_ENABLE 0x314
71#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT) 71#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT)
72#define INTERRUPT_ENABLE_SOT_MASK (HC_INTL_INT | HC_SOT_INT | HC_EOT_INT)
72 73
73#define HC_ISO_INT (1 << 9) 74#define HC_ISO_INT (1 << 9)
74#define HC_ATL_INT (1 << 8) 75#define HC_ATL_INT (1 << 8)
@@ -83,37 +84,29 @@ void deinit_kmem_cache(void);
83#define HC_INT_IRQ_MASK_AND_REG 0x328 84#define HC_INT_IRQ_MASK_AND_REG 0x328
84#define HC_ATL_IRQ_MASK_AND_REG 0x32C 85#define HC_ATL_IRQ_MASK_AND_REG 0x32C
85 86
86/* Register sets */
87#define HC_BEGIN_OF_ATL 0x0c00
88#define HC_BEGIN_OF_INT 0x0800
89#define HC_BEGIN_OF_ISO 0x0400
90#define HC_BEGIN_OF_PAYLOAD 0x1000
91
92/* urb state*/ 87/* urb state*/
93#define DELETE_URB (0x0008) 88#define DELETE_URB (0x0008)
94#define NO_TRANSFER_ACTIVE (0xffffffff) 89#define NO_TRANSFER_ACTIVE (0xffffffff)
95 90
96#define ATL_REGS_OFFSET (0xc00) 91/* Philips Proprietary Transfer Descriptor (PTD) */
97#define INT_REGS_OFFSET (0x800) 92typedef __u32 __bitwise __dw;
98
99/* Philips Transfer Descriptor (PTD) */
100struct ptd { 93struct ptd {
101 __le32 dw0; 94 __dw dw0;
102 __le32 dw1; 95 __dw dw1;
103 __le32 dw2; 96 __dw dw2;
104 __le32 dw3; 97 __dw dw3;
105 __le32 dw4; 98 __dw dw4;
106 __le32 dw5; 99 __dw dw5;
107 __le32 dw6; 100 __dw dw6;
108 __le32 dw7; 101 __dw dw7;
109}; 102};
103#define PTD_OFFSET 0x0400
104#define ISO_PTD_OFFSET 0x0400
105#define INT_PTD_OFFSET 0x0800
106#define ATL_PTD_OFFSET 0x0c00
107#define PAYLOAD_OFFSET 0x1000
110 108
111struct inter_packet_info { 109struct inter_packet_info {
112 void *data_buffer;
113 u32 payload;
114#define PTD_FIRE_NEXT (1 << 0)
115#define PTD_URB_FINISHED (1 << 1)
116 struct urb *urb;
117 struct isp1760_qh *qh; 110 struct isp1760_qh *qh;
118 struct isp1760_qtd *qtd; 111 struct isp1760_qtd *qtd;
119}; 112};
@@ -122,15 +115,6 @@ struct inter_packet_info {
122typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 115typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
123 struct isp1760_qtd *qtd); 116 struct isp1760_qtd *qtd);
124 117
125#define isp1760_dbg(priv, fmt, args...) \
126 dev_dbg(priv_to_hcd(priv)->self.controller, fmt, ##args)
127
128#define isp1760_info(priv, fmt, args...) \
129 dev_info(priv_to_hcd(priv)->self.controller, fmt, ##args)
130
131#define isp1760_err(priv, fmt, args...) \
132 dev_err(priv_to_hcd(priv)->self.controller, fmt, ##args)
133
134/* 118/*
135 * Device flags that can vary from board to board. All of these 119 * Device flags that can vary from board to board. All of these
136 * indicate the most "atypical" case, so that a devflags of 0 is 120 * indicate the most "atypical" case, so that a devflags of 0 is
@@ -167,10 +151,8 @@ struct memory_chunk {
167#define BLOCK_2_SIZE 1024 151#define BLOCK_2_SIZE 1024
168#define BLOCK_3_SIZE 8192 152#define BLOCK_3_SIZE 8192
169#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) 153#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
170#define PAYLOAD_SIZE 0xf000 154#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
171 155#define PAYLOAD_AREA_SIZE 0xf000
172/* I saw if some reloads if the pointer was negative */
173#define ISP1760_NULL_POINTER (0x400)
174 156
175/* ATL */ 157/* ATL */
176/* DW0 */ 158/* DW0 */
@@ -224,6 +206,4 @@ struct memory_chunk {
224#define NAK_COUNTER (0) 206#define NAK_COUNTER (0)
225#define ERR_COUNTER (2) 207#define ERR_COUNTER (2)
226 208
227#define HC_ATL_PL_SIZE (8192)
228
229#endif 209#endif
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 759a12ff8048..fb035751e4b2 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -75,6 +75,7 @@ static const char hcd_name [] = "ohci_hcd";
75#define STATECHANGE_DELAY msecs_to_jiffies(300) 75#define STATECHANGE_DELAY msecs_to_jiffies(300)
76 76
77#include "ohci.h" 77#include "ohci.h"
78#include "pci-quirks.h"
78 79
79static void ohci_dump (struct ohci_hcd *ohci, int verbose); 80static void ohci_dump (struct ohci_hcd *ohci, int verbose);
80static int ohci_init (struct ohci_hcd *ohci); 81static int ohci_init (struct ohci_hcd *ohci);
@@ -85,18 +86,8 @@ static int ohci_restart (struct ohci_hcd *ohci);
85#endif 86#endif
86 87
87#ifdef CONFIG_PCI 88#ifdef CONFIG_PCI
88static void quirk_amd_pll(int state);
89static void amd_iso_dev_put(void);
90static void sb800_prefetch(struct ohci_hcd *ohci, int on); 89static void sb800_prefetch(struct ohci_hcd *ohci, int on);
91#else 90#else
92static inline void quirk_amd_pll(int state)
93{
94 return;
95}
96static inline void amd_iso_dev_put(void)
97{
98 return;
99}
100static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) 91static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
101{ 92{
102 return; 93 return;
@@ -912,7 +903,7 @@ static void ohci_stop (struct usb_hcd *hcd)
912 if (quirk_zfmicro(ohci)) 903 if (quirk_zfmicro(ohci))
913 del_timer(&ohci->unlink_watchdog); 904 del_timer(&ohci->unlink_watchdog);
914 if (quirk_amdiso(ohci)) 905 if (quirk_amdiso(ohci))
915 amd_iso_dev_put(); 906 usb_amd_dev_put();
916 907
917 remove_debug_files (ohci); 908 remove_debug_files (ohci);
918 ohci_mem_cleanup (ohci); 909 ohci_mem_cleanup (ohci);
@@ -1068,10 +1059,7 @@ MODULE_LICENSE ("GPL");
1068#define PLATFORM_DRIVER ohci_hcd_da8xx_driver 1059#define PLATFORM_DRIVER ohci_hcd_da8xx_driver
1069#endif 1060#endif
1070 1061
1071#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 1062#ifdef CONFIG_USB_OHCI_SH
1072 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
1073 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1074 defined(CONFIG_CPU_SUBTYPE_SH7786)
1075#include "ohci-sh.c" 1063#include "ohci-sh.c"
1076#define PLATFORM_DRIVER ohci_hcd_sh_driver 1064#define PLATFORM_DRIVER ohci_hcd_sh_driver
1077#endif 1065#endif
diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c
index cddcda95b579..9154615292db 100644
--- a/drivers/usb/host/ohci-hub.c
+++ b/drivers/usb/host/ohci-hub.c
@@ -580,15 +580,16 @@ ohci_hub_descriptor (
580 temp |= 0x0008; 580 temp |= 0x0008;
581 desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ohci, temp); 581 desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ohci, temp);
582 582
583 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 583 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
584 rh = roothub_b (ohci); 584 rh = roothub_b (ohci);
585 memset(desc->bitmap, 0xff, sizeof(desc->bitmap)); 585 memset(desc->u.hs.DeviceRemovable, 0xff,
586 desc->bitmap [0] = rh & RH_B_DR; 586 sizeof(desc->u.hs.DeviceRemovable));
587 desc->u.hs.DeviceRemovable[0] = rh & RH_B_DR;
587 if (ohci->num_ports > 7) { 588 if (ohci->num_ports > 7) {
588 desc->bitmap [1] = (rh & RH_B_DR) >> 8; 589 desc->u.hs.DeviceRemovable[1] = (rh & RH_B_DR) >> 8;
589 desc->bitmap [2] = 0xff; 590 desc->u.hs.DeviceRemovable[2] = 0xff;
590 } else 591 } else
591 desc->bitmap [1] = 0xff; 592 desc->u.hs.DeviceRemovable[1] = 0xff;
592} 593}
593 594
594/*-------------------------------------------------------------------------*/ 595/*-------------------------------------------------------------------------*/
diff --git a/drivers/usb/host/ohci-omap3.c b/drivers/usb/host/ohci-omap3.c
index a37d5993e4e3..6048f2f64f73 100644
--- a/drivers/usb/host/ohci-omap3.c
+++ b/drivers/usb/host/ohci-omap3.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 2007-2010 Texas Instruments, Inc. 7 * Copyright (C) 2007-2010 Texas Instruments, Inc.
8 * Author: Vikram Pandita <vikram.pandita@ti.com> 8 * Author: Vikram Pandita <vikram.pandita@ti.com>
9 * Author: Anand Gadiyar <gadiyar@ti.com> 9 * Author: Anand Gadiyar <gadiyar@ti.com>
10 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
10 * 11 *
11 * Based on ehci-omap.c and some other ohci glue layers 12 * Based on ehci-omap.c and some other ohci glue layers
12 * 13 *
@@ -24,150 +25,15 @@
24 * along with this program; if not, write to the Free Software 25 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * 27 *
27 * TODO (last updated Mar 10th, 2010): 28 * TODO (last updated Feb 27, 2011):
28 * - add kernel-doc 29 * - add kernel-doc
29 * - Factor out code common to EHCI to a separate file
30 * - Make EHCI and OHCI coexist together
31 * - needs newer silicon versions to actually work
32 * - the last one to be loaded currently steps on the other's toes
33 * - Add hooks for configuring transceivers, etc. at init/exit
34 * - Add aggressive clock-management code
35 */ 30 */
36 31
37#include <linux/platform_device.h> 32#include <linux/platform_device.h>
38#include <linux/clk.h>
39
40#include <plat/usb.h> 33#include <plat/usb.h>
41 34
42/*
43 * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
44 * Use ohci_omap_readl()/ohci_omap_writel() functions
45 */
46
47/* TLL Register Set */
48#define OMAP_USBTLL_REVISION (0x00)
49#define OMAP_USBTLL_SYSCONFIG (0x10)
50#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
51#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
52#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
53#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
54#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
55
56#define OMAP_USBTLL_SYSSTATUS (0x14)
57#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
58
59#define OMAP_USBTLL_IRQSTATUS (0x18)
60#define OMAP_USBTLL_IRQENABLE (0x1C)
61
62#define OMAP_TLL_SHARED_CONF (0x30)
63#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
64#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
65#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
66#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
67#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
68
69#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
70#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
71#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
72#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
73#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
74#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
75#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
76#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
77
78#define OMAP_TLL_CHANNEL_COUNT 3
79
80/* UHH Register Set */
81#define OMAP_UHH_REVISION (0x00)
82#define OMAP_UHH_SYSCONFIG (0x10)
83#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
84#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
85#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
86#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
87#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
88#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
89
90#define OMAP_UHH_SYSSTATUS (0x14)
91#define OMAP_UHH_SYSSTATUS_UHHRESETDONE (1 << 0)
92#define OMAP_UHH_SYSSTATUS_OHCIRESETDONE (1 << 1)
93#define OMAP_UHH_SYSSTATUS_EHCIRESETDONE (1 << 2)
94#define OMAP_UHH_HOSTCONFIG (0x40)
95#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
96#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
97#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
98#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
99#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
100#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
101#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
102#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
103#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
104#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
105#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
106
107#define OMAP_UHH_DEBUG_CSR (0x44)
108
109/*-------------------------------------------------------------------------*/ 35/*-------------------------------------------------------------------------*/
110 36
111static inline void ohci_omap_writel(void __iomem *base, u32 reg, u32 val)
112{
113 __raw_writel(val, base + reg);
114}
115
116static inline u32 ohci_omap_readl(void __iomem *base, u32 reg)
117{
118 return __raw_readl(base + reg);
119}
120
121static inline void ohci_omap_writeb(void __iomem *base, u8 reg, u8 val)
122{
123 __raw_writeb(val, base + reg);
124}
125
126static inline u8 ohci_omap_readb(void __iomem *base, u8 reg)
127{
128 return __raw_readb(base + reg);
129}
130
131/*-------------------------------------------------------------------------*/
132
133struct ohci_hcd_omap3 {
134 struct ohci_hcd *ohci;
135 struct device *dev;
136
137 struct clk *usbhost_ick;
138 struct clk *usbhost2_120m_fck;
139 struct clk *usbhost1_48m_fck;
140 struct clk *usbtll_fck;
141 struct clk *usbtll_ick;
142
143 /* port_mode: TLL/PHY, 2/3/4/6-PIN, DP-DM/DAT-SE0 */
144 enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS];
145 void __iomem *uhh_base;
146 void __iomem *tll_base;
147 void __iomem *ohci_base;
148
149 unsigned es2_compatibility:1;
150};
151
152/*-------------------------------------------------------------------------*/
153
154static void ohci_omap3_clock_power(struct ohci_hcd_omap3 *omap, int on)
155{
156 if (on) {
157 clk_enable(omap->usbtll_ick);
158 clk_enable(omap->usbtll_fck);
159 clk_enable(omap->usbhost_ick);
160 clk_enable(omap->usbhost1_48m_fck);
161 clk_enable(omap->usbhost2_120m_fck);
162 } else {
163 clk_disable(omap->usbhost2_120m_fck);
164 clk_disable(omap->usbhost1_48m_fck);
165 clk_disable(omap->usbhost_ick);
166 clk_disable(omap->usbtll_fck);
167 clk_disable(omap->usbtll_ick);
168 }
169}
170
171static int ohci_omap3_init(struct usb_hcd *hcd) 37static int ohci_omap3_init(struct usb_hcd *hcd)
172{ 38{
173 dev_dbg(hcd->self.controller, "starting OHCI controller\n"); 39 dev_dbg(hcd->self.controller, "starting OHCI controller\n");
@@ -175,7 +41,6 @@ static int ohci_omap3_init(struct usb_hcd *hcd)
175 return ohci_init(hcd_to_ohci(hcd)); 41 return ohci_init(hcd_to_ohci(hcd));
176} 42}
177 43
178
179/*-------------------------------------------------------------------------*/ 44/*-------------------------------------------------------------------------*/
180 45
181static int ohci_omap3_start(struct usb_hcd *hcd) 46static int ohci_omap3_start(struct usb_hcd *hcd)
@@ -202,325 +67,6 @@ static int ohci_omap3_start(struct usb_hcd *hcd)
202 67
203/*-------------------------------------------------------------------------*/ 68/*-------------------------------------------------------------------------*/
204 69
205/*
206 * convert the port-mode enum to a value we can use in the FSLSMODE
207 * field of USBTLL_CHANNEL_CONF
208 */
209static unsigned ohci_omap3_fslsmode(enum ohci_omap3_port_mode mode)
210{
211 switch (mode) {
212 case OMAP_OHCI_PORT_MODE_UNUSED:
213 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
214 return 0x0;
215
216 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
217 return 0x1;
218
219 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
220 return 0x2;
221
222 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
223 return 0x3;
224
225 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
226 return 0x4;
227
228 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
229 return 0x5;
230
231 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
232 return 0x6;
233
234 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
235 return 0x7;
236
237 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
238 return 0xA;
239
240 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
241 return 0xB;
242 default:
243 pr_warning("Invalid port mode, using default\n");
244 return 0x0;
245 }
246}
247
248static void ohci_omap3_tll_config(struct ohci_hcd_omap3 *omap)
249{
250 u32 reg;
251 int i;
252
253 /* Program TLL SHARED CONF */
254 reg = ohci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
255 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
256 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
257 reg |= OMAP_TLL_SHARED_CONF_USB_DIVRATION;
258 reg |= OMAP_TLL_SHARED_CONF_FCLK_IS_ON;
259 ohci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
260
261 /* Program each TLL channel */
262 /*
263 * REVISIT: Only the 3-pin and 4-pin PHY modes have
264 * actually been tested.
265 */
266 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
267
268 /* Enable only those channels that are actually used */
269 if (omap->port_mode[i] == OMAP_OHCI_PORT_MODE_UNUSED)
270 continue;
271
272 reg = ohci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
273 reg |= ohci_omap3_fslsmode(omap->port_mode[i])
274 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
275 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
276 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
277 ohci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
278 }
279}
280
281/* omap3_start_ohci
282 * - Start the TI USBHOST controller
283 */
284static int omap3_start_ohci(struct ohci_hcd_omap3 *omap, struct usb_hcd *hcd)
285{
286 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
287 u32 reg = 0;
288 int ret = 0;
289
290 dev_dbg(omap->dev, "starting TI OHCI USB Controller\n");
291
292 /* Get all the clock handles we need */
293 omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
294 if (IS_ERR(omap->usbhost_ick)) {
295 dev_err(omap->dev, "could not get usbhost_ick\n");
296 ret = PTR_ERR(omap->usbhost_ick);
297 goto err_host_ick;
298 }
299
300 omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck");
301 if (IS_ERR(omap->usbhost2_120m_fck)) {
302 dev_err(omap->dev, "could not get usbhost_120m_fck\n");
303 ret = PTR_ERR(omap->usbhost2_120m_fck);
304 goto err_host_120m_fck;
305 }
306
307 omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck");
308 if (IS_ERR(omap->usbhost1_48m_fck)) {
309 dev_err(omap->dev, "could not get usbhost_48m_fck\n");
310 ret = PTR_ERR(omap->usbhost1_48m_fck);
311 goto err_host_48m_fck;
312 }
313
314 omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
315 if (IS_ERR(omap->usbtll_fck)) {
316 dev_err(omap->dev, "could not get usbtll_fck\n");
317 ret = PTR_ERR(omap->usbtll_fck);
318 goto err_tll_fck;
319 }
320
321 omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
322 if (IS_ERR(omap->usbtll_ick)) {
323 dev_err(omap->dev, "could not get usbtll_ick\n");
324 ret = PTR_ERR(omap->usbtll_ick);
325 goto err_tll_ick;
326 }
327
328 /* Now enable all the clocks in the correct order */
329 ohci_omap3_clock_power(omap, 1);
330
331 /* perform TLL soft reset, and wait until reset is complete */
332 ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
333 OMAP_USBTLL_SYSCONFIG_SOFTRESET);
334
335 /* Wait for TLL reset to complete */
336 while (!(ohci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
337 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
338 cpu_relax();
339
340 if (time_after(jiffies, timeout)) {
341 dev_dbg(omap->dev, "operation timed out\n");
342 ret = -EINVAL;
343 goto err_sys_status;
344 }
345 }
346
347 dev_dbg(omap->dev, "TLL reset done\n");
348
349 /* (1<<3) = no idle mode only for initial debugging */
350 ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
351 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
352 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
353 OMAP_USBTLL_SYSCONFIG_CACTIVITY);
354
355
356 /* Put UHH in NoIdle/NoStandby mode */
357 reg = ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
358 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
359 | OMAP_UHH_SYSCONFIG_SIDLEMODE
360 | OMAP_UHH_SYSCONFIG_CACTIVITY
361 | OMAP_UHH_SYSCONFIG_MIDLEMODE);
362 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
363 reg &= ~OMAP_UHH_SYSCONFIG_SOFTRESET;
364
365 ohci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
366
367 reg = ohci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
368
369 /* setup ULPI bypass and burst configurations */
370 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
371 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
372 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
373 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
374
375 /*
376 * REVISIT: Pi_CONNECT_STATUS controls MStandby
377 * assertion and Swakeup generation - let us not
378 * worry about this for now. OMAP HWMOD framework
379 * might take care of this later. If not, we can
380 * update these registers when adding aggressive
381 * clock management code.
382 *
383 * For now, turn off all the Pi_CONNECT_STATUS bits
384 *
385 if (omap->port_mode[0] == OMAP_OHCI_PORT_MODE_UNUSED)
386 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
387 if (omap->port_mode[1] == OMAP_OHCI_PORT_MODE_UNUSED)
388 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
389 if (omap->port_mode[2] == OMAP_OHCI_PORT_MODE_UNUSED)
390 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
391 */
392 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
393 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
394 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
395
396 if (omap->es2_compatibility) {
397 /*
398 * All OHCI modes need to go through the TLL,
399 * unlike in the EHCI case. So use UTMI mode
400 * for all ports for OHCI, on ES2.x silicon
401 */
402 dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n");
403 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
404 } else {
405 dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
406 if (omap->port_mode[0] == OMAP_OHCI_PORT_MODE_UNUSED)
407 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
408 else
409 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
410
411 if (omap->port_mode[1] == OMAP_OHCI_PORT_MODE_UNUSED)
412 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
413 else
414 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
415
416 if (omap->port_mode[2] == OMAP_OHCI_PORT_MODE_UNUSED)
417 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
418 else
419 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
420
421 }
422 ohci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
423 dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
424
425 ohci_omap3_tll_config(omap);
426
427 return 0;
428
429err_sys_status:
430 ohci_omap3_clock_power(omap, 0);
431 clk_put(omap->usbtll_ick);
432
433err_tll_ick:
434 clk_put(omap->usbtll_fck);
435
436err_tll_fck:
437 clk_put(omap->usbhost1_48m_fck);
438
439err_host_48m_fck:
440 clk_put(omap->usbhost2_120m_fck);
441
442err_host_120m_fck:
443 clk_put(omap->usbhost_ick);
444
445err_host_ick:
446 return ret;
447}
448
449static void omap3_stop_ohci(struct ohci_hcd_omap3 *omap, struct usb_hcd *hcd)
450{
451 unsigned long timeout = jiffies + msecs_to_jiffies(100);
452
453 dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
454
455 /* Reset USBHOST for insmod/rmmod to work */
456 ohci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
457 OMAP_UHH_SYSCONFIG_SOFTRESET);
458 while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
459 & OMAP_UHH_SYSSTATUS_UHHRESETDONE)) {
460 cpu_relax();
461
462 if (time_after(jiffies, timeout))
463 dev_dbg(omap->dev, "operation timed out\n");
464 }
465
466 while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
467 & OMAP_UHH_SYSSTATUS_OHCIRESETDONE)) {
468 cpu_relax();
469
470 if (time_after(jiffies, timeout))
471 dev_dbg(omap->dev, "operation timed out\n");
472 }
473
474 while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
475 & OMAP_UHH_SYSSTATUS_EHCIRESETDONE)) {
476 cpu_relax();
477
478 if (time_after(jiffies, timeout))
479 dev_dbg(omap->dev, "operation timed out\n");
480 }
481
482 ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
483
484 while (!(ohci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
485 & (1 << 0))) {
486 cpu_relax();
487
488 if (time_after(jiffies, timeout))
489 dev_dbg(omap->dev, "operation timed out\n");
490 }
491
492 ohci_omap3_clock_power(omap, 0);
493
494 if (omap->usbtll_fck != NULL) {
495 clk_put(omap->usbtll_fck);
496 omap->usbtll_fck = NULL;
497 }
498
499 if (omap->usbhost_ick != NULL) {
500 clk_put(omap->usbhost_ick);
501 omap->usbhost_ick = NULL;
502 }
503
504 if (omap->usbhost1_48m_fck != NULL) {
505 clk_put(omap->usbhost1_48m_fck);
506 omap->usbhost1_48m_fck = NULL;
507 }
508
509 if (omap->usbhost2_120m_fck != NULL) {
510 clk_put(omap->usbhost2_120m_fck);
511 omap->usbhost2_120m_fck = NULL;
512 }
513
514 if (omap->usbtll_ick != NULL) {
515 clk_put(omap->usbtll_ick);
516 omap->usbtll_ick = NULL;
517 }
518
519 dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
520}
521
522/*-------------------------------------------------------------------------*/
523
524static const struct hc_driver ohci_omap3_hc_driver = { 70static const struct hc_driver ohci_omap3_hc_driver = {
525 .description = hcd_name, 71 .description = hcd_name,
526 .product_desc = "OMAP3 OHCI Host Controller", 72 .product_desc = "OMAP3 OHCI Host Controller",
@@ -580,107 +126,77 @@ static const struct hc_driver ohci_omap3_hc_driver = {
580 */ 126 */
581static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev) 127static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev)
582{ 128{
583 struct ohci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; 129 struct device *dev = &pdev->dev;
584 struct ohci_hcd_omap3 *omap; 130 struct usb_hcd *hcd = NULL;
585 struct resource *res; 131 void __iomem *regs = NULL;
586 struct usb_hcd *hcd; 132 struct resource *res;
587 int ret = -ENODEV; 133 int ret = -ENODEV;
588 int irq; 134 int irq;
589 135
590 if (usb_disabled()) 136 if (usb_disabled())
591 goto err_disabled; 137 goto err_end;
592 138
593 if (!pdata) { 139 if (!dev->parent) {
594 dev_dbg(&pdev->dev, "missing platform_data\n"); 140 dev_err(dev, "Missing parent device\n");
595 goto err_pdata; 141 return -ENODEV;
596 } 142 }
597 143
598 irq = platform_get_irq(pdev, 0); 144 irq = platform_get_irq_byname(pdev, "ohci-irq");
145 if (irq < 0) {
146 dev_err(dev, "OHCI irq failed\n");
147 return -ENODEV;
148 }
599 149
600 omap = kzalloc(sizeof(*omap), GFP_KERNEL); 150 res = platform_get_resource_byname(pdev,
601 if (!omap) { 151 IORESOURCE_MEM, "ohci");
602 ret = -ENOMEM; 152 if (!ret) {
603 goto err_disabled; 153 dev_err(dev, "UHH OHCI get resource failed\n");
154 return -ENOMEM;
604 } 155 }
605 156
606 hcd = usb_create_hcd(&ohci_omap3_hc_driver, &pdev->dev, 157 regs = ioremap(res->start, resource_size(res));
607 dev_name(&pdev->dev)); 158 if (!regs) {
608 if (!hcd) { 159 dev_err(dev, "UHH OHCI ioremap failed\n");
609 ret = -ENOMEM; 160 return -ENOMEM;
610 goto err_create_hcd;
611 } 161 }
612 162
613 platform_set_drvdata(pdev, omap);
614 omap->dev = &pdev->dev;
615 omap->port_mode[0] = pdata->port_mode[0];
616 omap->port_mode[1] = pdata->port_mode[1];
617 omap->port_mode[2] = pdata->port_mode[2];
618 omap->es2_compatibility = pdata->es2_compatibility;
619 omap->ohci = hcd_to_ohci(hcd);
620 163
621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 164 hcd = usb_create_hcd(&ohci_omap3_hc_driver, dev,
165 dev_name(dev));
166 if (!hcd) {
167 dev_err(dev, "usb_create_hcd failed\n");
168 goto err_io;
169 }
622 170
623 hcd->rsrc_start = res->start; 171 hcd->rsrc_start = res->start;
624 hcd->rsrc_len = resource_size(res); 172 hcd->rsrc_len = resource_size(res);
173 hcd->regs = regs;
625 174
626 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); 175 ret = omap_usbhs_enable(dev);
627 if (!hcd->regs) {
628 dev_err(&pdev->dev, "OHCI ioremap failed\n");
629 ret = -ENOMEM;
630 goto err_ioremap;
631 }
632
633 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
634 omap->uhh_base = ioremap(res->start, resource_size(res));
635 if (!omap->uhh_base) {
636 dev_err(&pdev->dev, "UHH ioremap failed\n");
637 ret = -ENOMEM;
638 goto err_uhh_ioremap;
639 }
640
641 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
642 omap->tll_base = ioremap(res->start, resource_size(res));
643 if (!omap->tll_base) {
644 dev_err(&pdev->dev, "TLL ioremap failed\n");
645 ret = -ENOMEM;
646 goto err_tll_ioremap;
647 }
648
649 ret = omap3_start_ohci(omap, hcd);
650 if (ret) { 176 if (ret) {
651 dev_dbg(&pdev->dev, "failed to start ohci\n"); 177 dev_dbg(dev, "failed to start ohci\n");
652 goto err_start; 178 goto err_end;
653 } 179 }
654 180
655 ohci_hcd_init(omap->ohci); 181 ohci_hcd_init(hcd_to_ohci(hcd));
656 182
657 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); 183 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED);
658 if (ret) { 184 if (ret) {
659 dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); 185 dev_dbg(dev, "failed to add hcd with err %d\n", ret);
660 goto err_add_hcd; 186 goto err_add_hcd;
661 } 187 }
662 188
663 return 0; 189 return 0;
664 190
665err_add_hcd: 191err_add_hcd:
666 omap3_stop_ohci(omap, hcd); 192 omap_usbhs_disable(dev);
667
668err_start:
669 iounmap(omap->tll_base);
670
671err_tll_ioremap:
672 iounmap(omap->uhh_base);
673
674err_uhh_ioremap:
675 iounmap(hcd->regs);
676 193
677err_ioremap: 194err_end:
678 usb_put_hcd(hcd); 195 usb_put_hcd(hcd);
679 196
680err_create_hcd: 197err_io:
681 kfree(omap); 198 iounmap(regs);
682err_pdata: 199
683err_disabled:
684 return ret; 200 return ret;
685} 201}
686 202
@@ -699,24 +215,20 @@ err_disabled:
699 */ 215 */
700static int __devexit ohci_hcd_omap3_remove(struct platform_device *pdev) 216static int __devexit ohci_hcd_omap3_remove(struct platform_device *pdev)
701{ 217{
702 struct ohci_hcd_omap3 *omap = platform_get_drvdata(pdev); 218 struct device *dev = &pdev->dev;
703 struct usb_hcd *hcd = ohci_to_hcd(omap->ohci); 219 struct usb_hcd *hcd = dev_get_drvdata(dev);
704 220
705 usb_remove_hcd(hcd);
706 omap3_stop_ohci(omap, hcd);
707 iounmap(hcd->regs); 221 iounmap(hcd->regs);
708 iounmap(omap->tll_base); 222 usb_remove_hcd(hcd);
709 iounmap(omap->uhh_base); 223 omap_usbhs_disable(dev);
710 usb_put_hcd(hcd); 224 usb_put_hcd(hcd);
711 kfree(omap);
712 225
713 return 0; 226 return 0;
714} 227}
715 228
716static void ohci_hcd_omap3_shutdown(struct platform_device *pdev) 229static void ohci_hcd_omap3_shutdown(struct platform_device *pdev)
717{ 230{
718 struct ohci_hcd_omap3 *omap = platform_get_drvdata(pdev); 231 struct usb_hcd *hcd = dev_get_drvdata(&pdev->dev);
719 struct usb_hcd *hcd = ohci_to_hcd(omap->ohci);
720 232
721 if (hcd->driver->shutdown) 233 if (hcd->driver->shutdown)
722 hcd->driver->shutdown(hcd); 234 hcd->driver->shutdown(hcd);
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index 36ee9a666e93..d84d6f0314f9 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -22,24 +22,6 @@
22#include <linux/io.h> 22#include <linux/io.h>
23 23
24 24
25/* constants used to work around PM-related transfer
26 * glitches in some AMD 700 series southbridges
27 */
28#define AB_REG_BAR 0xf0
29#define AB_INDX(addr) ((addr) + 0x00)
30#define AB_DATA(addr) ((addr) + 0x04)
31#define AX_INDXC 0X30
32#define AX_DATAC 0x34
33
34#define NB_PCIE_INDX_ADDR 0xe0
35#define NB_PCIE_INDX_DATA 0xe4
36#define PCIE_P_CNTL 0x10040
37#define BIF_NB 0x10002
38
39static struct pci_dev *amd_smbus_dev;
40static struct pci_dev *amd_hb_dev;
41static int amd_ohci_iso_count;
42
43/*-------------------------------------------------------------------------*/ 25/*-------------------------------------------------------------------------*/
44 26
45static int broken_suspend(struct usb_hcd *hcd) 27static int broken_suspend(struct usb_hcd *hcd)
@@ -168,15 +150,18 @@ static int ohci_quirk_nec(struct usb_hcd *hcd)
168static int ohci_quirk_amd700(struct usb_hcd *hcd) 150static int ohci_quirk_amd700(struct usb_hcd *hcd)
169{ 151{
170 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 152 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
171 u8 rev = 0; 153 struct pci_dev *amd_smbus_dev;
154 u8 rev;
172 155
173 if (!amd_smbus_dev) 156 if (usb_amd_find_chipset_info())
174 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 157 ohci->flags |= OHCI_QUIRK_AMD_PLL;
175 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); 158
159 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
160 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
176 if (!amd_smbus_dev) 161 if (!amd_smbus_dev)
177 return 0; 162 return 0;
178 163
179 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev); 164 rev = amd_smbus_dev->revision;
180 165
181 /* SB800 needs pre-fetch fix */ 166 /* SB800 needs pre-fetch fix */
182 if ((rev >= 0x40) && (rev <= 0x4f)) { 167 if ((rev >= 0x40) && (rev <= 0x4f)) {
@@ -184,19 +169,8 @@ static int ohci_quirk_amd700(struct usb_hcd *hcd)
184 ohci_dbg(ohci, "enabled AMD prefetch quirk\n"); 169 ohci_dbg(ohci, "enabled AMD prefetch quirk\n");
185 } 170 }
186 171
187 if ((rev > 0x3b) || (rev < 0x30)) { 172 pci_dev_put(amd_smbus_dev);
188 pci_dev_put(amd_smbus_dev); 173 amd_smbus_dev = NULL;
189 amd_smbus_dev = NULL;
190 return 0;
191 }
192
193 amd_ohci_iso_count++;
194
195 if (!amd_hb_dev)
196 amd_hb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9600, NULL);
197
198 ohci->flags |= OHCI_QUIRK_AMD_ISO;
199 ohci_dbg(ohci, "enabled AMD ISO transfers quirk\n");
200 174
201 return 0; 175 return 0;
202} 176}
@@ -215,74 +189,6 @@ static int ohci_quirk_nvidia_shutdown(struct usb_hcd *hcd)
215 return 0; 189 return 0;
216} 190}
217 191
218/*
219 * The hardware normally enables the A-link power management feature, which
220 * lets the system lower the power consumption in idle states.
221 *
222 * Assume the system is configured to have USB 1.1 ISO transfers going
223 * to or from a USB device. Without this quirk, that stream may stutter
224 * or have breaks occasionally. For transfers going to speakers, this
225 * makes a very audible mess...
226 *
227 * That audio playback corruption is due to the audio stream getting
228 * interrupted occasionally when the link goes in lower power state
229 * This USB quirk prevents the link going into that lower power state
230 * during audio playback or other ISO operations.
231 */
232static void quirk_amd_pll(int on)
233{
234 u32 addr;
235 u32 val;
236 u32 bit = (on > 0) ? 1 : 0;
237
238 pci_read_config_dword(amd_smbus_dev, AB_REG_BAR, &addr);
239
240 /* BIT names/meanings are NDA-protected, sorry ... */
241
242 outl(AX_INDXC, AB_INDX(addr));
243 outl(0x40, AB_DATA(addr));
244 outl(AX_DATAC, AB_INDX(addr));
245 val = inl(AB_DATA(addr));
246 val &= ~((1 << 3) | (1 << 4) | (1 << 9));
247 val |= (bit << 3) | ((!bit) << 4) | ((!bit) << 9);
248 outl(val, AB_DATA(addr));
249
250 if (amd_hb_dev) {
251 addr = PCIE_P_CNTL;
252 pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr);
253
254 pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val);
255 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
256 val |= bit | (bit << 3) | (bit << 12);
257 val |= ((!bit) << 4) | ((!bit) << 9);
258 pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val);
259
260 addr = BIF_NB;
261 pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr);
262
263 pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val);
264 val &= ~(1 << 8);
265 val |= bit << 8;
266 pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val);
267 }
268}
269
270static void amd_iso_dev_put(void)
271{
272 amd_ohci_iso_count--;
273 if (amd_ohci_iso_count == 0) {
274 if (amd_smbus_dev) {
275 pci_dev_put(amd_smbus_dev);
276 amd_smbus_dev = NULL;
277 }
278 if (amd_hb_dev) {
279 pci_dev_put(amd_hb_dev);
280 amd_hb_dev = NULL;
281 }
282 }
283
284}
285
286static void sb800_prefetch(struct ohci_hcd *ohci, int on) 192static void sb800_prefetch(struct ohci_hcd *ohci, int on)
287{ 193{
288 struct pci_dev *pdev; 194 struct pci_dev *pdev;
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index 83094d067e0f..dd24fc115e48 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -52,7 +52,7 @@ __acquires(ohci->lock)
52 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--; 52 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
53 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { 53 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
54 if (quirk_amdiso(ohci)) 54 if (quirk_amdiso(ohci))
55 quirk_amd_pll(1); 55 usb_amd_quirk_pll_enable();
56 if (quirk_amdprefetch(ohci)) 56 if (quirk_amdprefetch(ohci))
57 sb800_prefetch(ohci, 0); 57 sb800_prefetch(ohci, 0);
58 } 58 }
@@ -686,7 +686,7 @@ static void td_submit_urb (
686 } 686 }
687 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { 687 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
688 if (quirk_amdiso(ohci)) 688 if (quirk_amdiso(ohci))
689 quirk_amd_pll(0); 689 usb_amd_quirk_pll_disable();
690 if (quirk_amdprefetch(ohci)) 690 if (quirk_amdprefetch(ohci))
691 sb800_prefetch(ohci, 1); 691 sb800_prefetch(ohci, 1);
692 } 692 }
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index 51facb985c84..bad11a72c202 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -401,7 +401,7 @@ struct ohci_hcd {
401#define OHCI_QUIRK_NEC 0x40 /* lost interrupts */ 401#define OHCI_QUIRK_NEC 0x40 /* lost interrupts */
402#define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */ 402#define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */
403#define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ 403#define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */
404#define OHCI_QUIRK_AMD_ISO 0x200 /* ISO transfers*/ 404#define OHCI_QUIRK_AMD_PLL 0x200 /* AMD PLL quirk*/
405#define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */ 405#define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */
406#define OHCI_QUIRK_SHUTDOWN 0x800 /* nVidia power bug */ 406#define OHCI_QUIRK_SHUTDOWN 0x800 /* nVidia power bug */
407 // there are also chip quirks/bugs in init logic 407 // there are also chip quirks/bugs in init logic
@@ -433,7 +433,7 @@ static inline int quirk_zfmicro(struct ohci_hcd *ohci)
433} 433}
434static inline int quirk_amdiso(struct ohci_hcd *ohci) 434static inline int quirk_amdiso(struct ohci_hcd *ohci)
435{ 435{
436 return ohci->flags & OHCI_QUIRK_AMD_ISO; 436 return ohci->flags & OHCI_QUIRK_AMD_PLL;
437} 437}
438static inline int quirk_amdprefetch(struct ohci_hcd *ohci) 438static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
439{ 439{
diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c
index e0cb12b573f9..38193f4e980e 100644
--- a/drivers/usb/host/oxu210hp-hcd.c
+++ b/drivers/usb/host/oxu210hp-hcd.c
@@ -451,9 +451,9 @@ static void ehci_hub_descriptor(struct oxu_hcd *oxu,
451 temp = 1 + (ports / 8); 451 temp = 1 + (ports / 8);
452 desc->bDescLength = 7 + 2 * temp; 452 desc->bDescLength = 7 + 2 * temp;
453 453
454 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 454 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
455 memset(&desc->bitmap[0], 0, temp); 455 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
456 memset(&desc->bitmap[temp], 0xff, temp); 456 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
457 457
458 temp = 0x0008; /* per-port overcurrent reporting */ 458 temp = 0x0008; /* per-port overcurrent reporting */
459 if (HCS_PPC(oxu->hcs_params)) 459 if (HCS_PPC(oxu->hcs_params))
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 4c502c890ebd..1d586d4f7b56 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -52,6 +52,264 @@
52#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 52#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
53#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 53#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
54 54
55/* AMD quirk use */
56#define AB_REG_BAR_LOW 0xe0
57#define AB_REG_BAR_HIGH 0xe1
58#define AB_REG_BAR_SB700 0xf0
59#define AB_INDX(addr) ((addr) + 0x00)
60#define AB_DATA(addr) ((addr) + 0x04)
61#define AX_INDXC 0x30
62#define AX_DATAC 0x34
63
64#define NB_PCIE_INDX_ADDR 0xe0
65#define NB_PCIE_INDX_DATA 0xe4
66#define PCIE_P_CNTL 0x10040
67#define BIF_NB 0x10002
68#define NB_PIF0_PWRDOWN_0 0x01100012
69#define NB_PIF0_PWRDOWN_1 0x01100013
70
71static struct amd_chipset_info {
72 struct pci_dev *nb_dev;
73 struct pci_dev *smbus_dev;
74 int nb_type;
75 int sb_type;
76 int isoc_reqs;
77 int probe_count;
78 int probe_result;
79} amd_chipset;
80
81static DEFINE_SPINLOCK(amd_lock);
82
83int usb_amd_find_chipset_info(void)
84{
85 u8 rev = 0;
86 unsigned long flags;
87
88 spin_lock_irqsave(&amd_lock, flags);
89
90 amd_chipset.probe_count++;
91 /* probe only once */
92 if (amd_chipset.probe_count > 1) {
93 spin_unlock_irqrestore(&amd_lock, flags);
94 return amd_chipset.probe_result;
95 }
96
97 amd_chipset.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
98 if (amd_chipset.smbus_dev) {
99 rev = amd_chipset.smbus_dev->revision;
100 if (rev >= 0x40)
101 amd_chipset.sb_type = 1;
102 else if (rev >= 0x30 && rev <= 0x3b)
103 amd_chipset.sb_type = 3;
104 } else {
105 amd_chipset.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
106 0x780b, NULL);
107 if (!amd_chipset.smbus_dev) {
108 spin_unlock_irqrestore(&amd_lock, flags);
109 return 0;
110 }
111 rev = amd_chipset.smbus_dev->revision;
112 if (rev >= 0x11 && rev <= 0x18)
113 amd_chipset.sb_type = 2;
114 }
115
116 if (amd_chipset.sb_type == 0) {
117 if (amd_chipset.smbus_dev) {
118 pci_dev_put(amd_chipset.smbus_dev);
119 amd_chipset.smbus_dev = NULL;
120 }
121 spin_unlock_irqrestore(&amd_lock, flags);
122 return 0;
123 }
124
125 amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
126 if (amd_chipset.nb_dev) {
127 amd_chipset.nb_type = 1;
128 } else {
129 amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
130 0x1510, NULL);
131 if (amd_chipset.nb_dev) {
132 amd_chipset.nb_type = 2;
133 } else {
134 amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
135 0x9600, NULL);
136 if (amd_chipset.nb_dev)
137 amd_chipset.nb_type = 3;
138 }
139 }
140
141 amd_chipset.probe_result = 1;
142 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
143
144 spin_unlock_irqrestore(&amd_lock, flags);
145 return amd_chipset.probe_result;
146}
147EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
148
149/*
150 * The hardware normally enables the A-link power management feature, which
151 * lets the system lower the power consumption in idle states.
152 *
153 * This USB quirk prevents the link going into that lower power state
154 * during isochronous transfers.
155 *
156 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
157 * some AMD platforms may stutter or have breaks occasionally.
158 */
159static void usb_amd_quirk_pll(int disable)
160{
161 u32 addr, addr_low, addr_high, val;
162 u32 bit = disable ? 0 : 1;
163 unsigned long flags;
164
165 spin_lock_irqsave(&amd_lock, flags);
166
167 if (disable) {
168 amd_chipset.isoc_reqs++;
169 if (amd_chipset.isoc_reqs > 1) {
170 spin_unlock_irqrestore(&amd_lock, flags);
171 return;
172 }
173 } else {
174 amd_chipset.isoc_reqs--;
175 if (amd_chipset.isoc_reqs > 0) {
176 spin_unlock_irqrestore(&amd_lock, flags);
177 return;
178 }
179 }
180
181 if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
182 outb_p(AB_REG_BAR_LOW, 0xcd6);
183 addr_low = inb_p(0xcd7);
184 outb_p(AB_REG_BAR_HIGH, 0xcd6);
185 addr_high = inb_p(0xcd7);
186 addr = addr_high << 8 | addr_low;
187
188 outl_p(0x30, AB_INDX(addr));
189 outl_p(0x40, AB_DATA(addr));
190 outl_p(0x34, AB_INDX(addr));
191 val = inl_p(AB_DATA(addr));
192 } else if (amd_chipset.sb_type == 3) {
193 pci_read_config_dword(amd_chipset.smbus_dev,
194 AB_REG_BAR_SB700, &addr);
195 outl(AX_INDXC, AB_INDX(addr));
196 outl(0x40, AB_DATA(addr));
197 outl(AX_DATAC, AB_INDX(addr));
198 val = inl(AB_DATA(addr));
199 } else {
200 spin_unlock_irqrestore(&amd_lock, flags);
201 return;
202 }
203
204 if (disable) {
205 val &= ~0x08;
206 val |= (1 << 4) | (1 << 9);
207 } else {
208 val |= 0x08;
209 val &= ~((1 << 4) | (1 << 9));
210 }
211 outl_p(val, AB_DATA(addr));
212
213 if (!amd_chipset.nb_dev) {
214 spin_unlock_irqrestore(&amd_lock, flags);
215 return;
216 }
217
218 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
219 addr = PCIE_P_CNTL;
220 pci_write_config_dword(amd_chipset.nb_dev,
221 NB_PCIE_INDX_ADDR, addr);
222 pci_read_config_dword(amd_chipset.nb_dev,
223 NB_PCIE_INDX_DATA, &val);
224
225 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
226 val |= bit | (bit << 3) | (bit << 12);
227 val |= ((!bit) << 4) | ((!bit) << 9);
228 pci_write_config_dword(amd_chipset.nb_dev,
229 NB_PCIE_INDX_DATA, val);
230
231 addr = BIF_NB;
232 pci_write_config_dword(amd_chipset.nb_dev,
233 NB_PCIE_INDX_ADDR, addr);
234 pci_read_config_dword(amd_chipset.nb_dev,
235 NB_PCIE_INDX_DATA, &val);
236 val &= ~(1 << 8);
237 val |= bit << 8;
238
239 pci_write_config_dword(amd_chipset.nb_dev,
240 NB_PCIE_INDX_DATA, val);
241 } else if (amd_chipset.nb_type == 2) {
242 addr = NB_PIF0_PWRDOWN_0;
243 pci_write_config_dword(amd_chipset.nb_dev,
244 NB_PCIE_INDX_ADDR, addr);
245 pci_read_config_dword(amd_chipset.nb_dev,
246 NB_PCIE_INDX_DATA, &val);
247 if (disable)
248 val &= ~(0x3f << 7);
249 else
250 val |= 0x3f << 7;
251
252 pci_write_config_dword(amd_chipset.nb_dev,
253 NB_PCIE_INDX_DATA, val);
254
255 addr = NB_PIF0_PWRDOWN_1;
256 pci_write_config_dword(amd_chipset.nb_dev,
257 NB_PCIE_INDX_ADDR, addr);
258 pci_read_config_dword(amd_chipset.nb_dev,
259 NB_PCIE_INDX_DATA, &val);
260 if (disable)
261 val &= ~(0x3f << 7);
262 else
263 val |= 0x3f << 7;
264
265 pci_write_config_dword(amd_chipset.nb_dev,
266 NB_PCIE_INDX_DATA, val);
267 }
268
269 spin_unlock_irqrestore(&amd_lock, flags);
270 return;
271}
272
273void usb_amd_quirk_pll_disable(void)
274{
275 usb_amd_quirk_pll(1);
276}
277EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
278
279void usb_amd_quirk_pll_enable(void)
280{
281 usb_amd_quirk_pll(0);
282}
283EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
284
285void usb_amd_dev_put(void)
286{
287 unsigned long flags;
288
289 spin_lock_irqsave(&amd_lock, flags);
290
291 amd_chipset.probe_count--;
292 if (amd_chipset.probe_count > 0) {
293 spin_unlock_irqrestore(&amd_lock, flags);
294 return;
295 }
296
297 if (amd_chipset.nb_dev) {
298 pci_dev_put(amd_chipset.nb_dev);
299 amd_chipset.nb_dev = NULL;
300 }
301 if (amd_chipset.smbus_dev) {
302 pci_dev_put(amd_chipset.smbus_dev);
303 amd_chipset.smbus_dev = NULL;
304 }
305 amd_chipset.nb_type = 0;
306 amd_chipset.sb_type = 0;
307 amd_chipset.isoc_reqs = 0;
308 amd_chipset.probe_result = 0;
309
310 spin_unlock_irqrestore(&amd_lock, flags);
311}
312EXPORT_SYMBOL_GPL(usb_amd_dev_put);
55 313
56/* 314/*
57 * Make sure the controller is completely inactive, unable to 315 * Make sure the controller is completely inactive, unable to
diff --git a/drivers/usb/host/pci-quirks.h b/drivers/usb/host/pci-quirks.h
index 1564edfff6fe..6ae9f78e9938 100644
--- a/drivers/usb/host/pci-quirks.h
+++ b/drivers/usb/host/pci-quirks.h
@@ -1,7 +1,17 @@
1#ifndef __LINUX_USB_PCI_QUIRKS_H 1#ifndef __LINUX_USB_PCI_QUIRKS_H
2#define __LINUX_USB_PCI_QUIRKS_H 2#define __LINUX_USB_PCI_QUIRKS_H
3 3
4#ifdef CONFIG_PCI
4void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); 5void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
5int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); 6int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
7int usb_amd_find_chipset_info(void);
8void usb_amd_dev_put(void);
9void usb_amd_quirk_pll_disable(void);
10void usb_amd_quirk_pll_enable(void);
11#else
12static inline void usb_amd_quirk_pll_disable(void) {}
13static inline void usb_amd_quirk_pll_enable(void) {}
14static inline void usb_amd_dev_put(void) {}
15#endif /* CONFIG_PCI */
6 16
7#endif /* __LINUX_USB_PCI_QUIRKS_H */ 17#endif /* __LINUX_USB_PCI_QUIRKS_H */
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index 3076b1cc05df..db6f8b9c19b6 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -2150,8 +2150,9 @@ static void r8a66597_hub_descriptor(struct r8a66597 *r8a66597,
2150 desc->bDescLength = 9; 2150 desc->bDescLength = 9;
2151 desc->bPwrOn2PwrGood = 0; 2151 desc->bPwrOn2PwrGood = 0;
2152 desc->wHubCharacteristics = cpu_to_le16(0x0011); 2152 desc->wHubCharacteristics = cpu_to_le16(0x0011);
2153 desc->bitmap[0] = ((1 << r8a66597->max_root_hub) - 1) << 1; 2153 desc->u.hs.DeviceRemovable[0] =
2154 desc->bitmap[1] = ~0; 2154 ((1 << r8a66597->max_root_hub) - 1) << 1;
2155 desc->u.hs.DeviceRemovable[1] = ~0;
2155} 2156}
2156 2157
2157static int r8a66597_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 2158static int r8a66597_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c
index 2e9602a10e9b..18b7099a8125 100644
--- a/drivers/usb/host/sl811-hcd.c
+++ b/drivers/usb/host/sl811-hcd.c
@@ -1111,9 +1111,9 @@ sl811h_hub_descriptor (
1111 1111
1112 desc->wHubCharacteristics = cpu_to_le16(temp); 1112 desc->wHubCharacteristics = cpu_to_le16(temp);
1113 1113
1114 /* two bitmaps: ports removable, and legacy PortPwrCtrlMask */ 1114 /* ports removable, and legacy PortPwrCtrlMask */
1115 desc->bitmap[0] = 0 << 1; 1115 desc->u.hs.DeviceRemovable[0] = 0 << 1;
1116 desc->bitmap[1] = ~0; 1116 desc->u.hs.DeviceRemovable[1] = ~0;
1117} 1117}
1118 1118
1119static void 1119static void
diff --git a/drivers/usb/host/u132-hcd.c b/drivers/usb/host/u132-hcd.c
index fab764946c74..b4785934e091 100644
--- a/drivers/usb/host/u132-hcd.c
+++ b/drivers/usb/host/u132-hcd.c
@@ -2604,13 +2604,14 @@ static int u132_roothub_descriptor(struct u132 *u132,
2604 retval = u132_read_pcimem(u132, roothub.b, &rh_b); 2604 retval = u132_read_pcimem(u132, roothub.b, &rh_b);
2605 if (retval) 2605 if (retval)
2606 return retval; 2606 return retval;
2607 memset(desc->bitmap, 0xff, sizeof(desc->bitmap)); 2607 memset(desc->u.hs.DeviceRemovable, 0xff,
2608 desc->bitmap[0] = rh_b & RH_B_DR; 2608 sizeof(desc->u.hs.DeviceRemovable));
2609 desc->u.hs.DeviceRemovable[0] = rh_b & RH_B_DR;
2609 if (u132->num_ports > 7) { 2610 if (u132->num_ports > 7) {
2610 desc->bitmap[1] = (rh_b & RH_B_DR) >> 8; 2611 desc->u.hs.DeviceRemovable[1] = (rh_b & RH_B_DR) >> 8;
2611 desc->bitmap[2] = 0xff; 2612 desc->u.hs.DeviceRemovable[2] = 0xff;
2612 } else 2613 } else
2613 desc->bitmap[1] = 0xff; 2614 desc->u.hs.DeviceRemovable[1] = 0xff;
2614 return 0; 2615 return 0;
2615} 2616}
2616 2617
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index cee867829ec9..4f65b14e5e08 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -471,7 +471,7 @@ static irqreturn_t uhci_irq(struct usb_hcd *hcd)
471 471
472/* 472/*
473 * Store the current frame number in uhci->frame_number if the controller 473 * Store the current frame number in uhci->frame_number if the controller
474 * is runnning. Expand from 11 bits (of which we use only 10) to a 474 * is running. Expand from 11 bits (of which we use only 10) to a
475 * full-sized integer. 475 * full-sized integer.
476 * 476 *
477 * Like many other parts of the driver, this code relies on being polled 477 * Like many other parts of the driver, this code relies on being polled
diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
index 78c4edac1db1..ce5c9e51748e 100644
--- a/drivers/usb/host/xhci-ext-caps.h
+++ b/drivers/usb/host/xhci-ext-caps.h
@@ -19,8 +19,8 @@
19 * along with this program; if not, write to the Free Software Foundation, 19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 21 */
22/* Up to 16 microframes to halt an HC - one microframe is 125 microsectonds */ 22/* Up to 16 ms to halt an HC */
23#define XHCI_MAX_HALT_USEC (16*125) 23#define XHCI_MAX_HALT_USEC (16*1000)
24/* HC not running - set to 1 when run/stop bit is cleared. */ 24/* HC not running - set to 1 when run/stop bit is cleared. */
25#define XHCI_STS_HALT (1<<0) 25#define XHCI_STS_HALT (1<<0)
26 26
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 5d963e350494..a78f2ebd11b7 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -28,27 +28,15 @@
28#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 28#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
29 PORT_RC | PORT_PLC | PORT_PE) 29 PORT_RC | PORT_PLC | PORT_PE)
30 30
31static void xhci_hub_descriptor(struct xhci_hcd *xhci, 31static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
32 struct usb_hub_descriptor *desc) 32 struct usb_hub_descriptor *desc, int ports)
33{ 33{
34 int ports;
35 u16 temp; 34 u16 temp;
36 35
37 ports = HCS_MAX_PORTS(xhci->hcs_params1);
38
39 /* USB 3.0 hubs have a different descriptor, but we fake this for now */
40 desc->bDescriptorType = 0x29;
41 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ 36 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
42 desc->bHubContrCurrent = 0; 37 desc->bHubContrCurrent = 0;
43 38
44 desc->bNbrPorts = ports; 39 desc->bNbrPorts = ports;
45 temp = 1 + (ports / 8);
46 desc->bDescLength = 7 + 2 * temp;
47
48 /* Why does core/hcd.h define bitmap? It's just confusing. */
49 memset(&desc->DeviceRemovable[0], 0, temp);
50 memset(&desc->DeviceRemovable[temp], 0xff, temp);
51
52 /* Ugh, these should be #defines, FIXME */ 40 /* Ugh, these should be #defines, FIXME */
53 /* Using table 11-13 in USB 2.0 spec. */ 41 /* Using table 11-13 in USB 2.0 spec. */
54 temp = 0; 42 temp = 0;
@@ -65,14 +53,108 @@ static void xhci_hub_descriptor(struct xhci_hcd *xhci,
65 desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp); 53 desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp);
66} 54}
67 55
56/* Fill in the USB 2.0 roothub descriptor */
57static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
58 struct usb_hub_descriptor *desc)
59{
60 int ports;
61 u16 temp;
62 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
63 u32 portsc;
64 unsigned int i;
65
66 ports = xhci->num_usb2_ports;
67
68 xhci_common_hub_descriptor(xhci, desc, ports);
69 desc->bDescriptorType = 0x29;
70 temp = 1 + (ports / 8);
71 desc->bDescLength = 7 + 2 * temp;
72
73 /* The Device Removable bits are reported on a byte granularity.
74 * If the port doesn't exist within that byte, the bit is set to 0.
75 */
76 memset(port_removable, 0, sizeof(port_removable));
77 for (i = 0; i < ports; i++) {
78 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
79 /* If a device is removable, PORTSC reports a 0, same as in the
80 * hub descriptor DeviceRemovable bits.
81 */
82 if (portsc & PORT_DEV_REMOVE)
83 /* This math is hairy because bit 0 of DeviceRemovable
84 * is reserved, and bit 1 is for port 1, etc.
85 */
86 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
87 }
88
89 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
90 * ports on it. The USB 2.0 specification says that there are two
91 * variable length fields at the end of the hub descriptor:
92 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
93 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
94 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
95 * 0xFF, so we initialize the both arrays (DeviceRemovable and
96 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
97 * set of ports that actually exist.
98 */
99 memset(desc->u.hs.DeviceRemovable, 0xff,
100 sizeof(desc->u.hs.DeviceRemovable));
101 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
102 sizeof(desc->u.hs.PortPwrCtrlMask));
103
104 for (i = 0; i < (ports + 1 + 7) / 8; i++)
105 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
106 sizeof(__u8));
107}
108
109/* Fill in the USB 3.0 roothub descriptor */
110static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
111 struct usb_hub_descriptor *desc)
112{
113 int ports;
114 u16 port_removable;
115 u32 portsc;
116 unsigned int i;
117
118 ports = xhci->num_usb3_ports;
119 xhci_common_hub_descriptor(xhci, desc, ports);
120 desc->bDescriptorType = 0x2a;
121 desc->bDescLength = 12;
122
123 /* header decode latency should be zero for roothubs,
124 * see section 4.23.5.2.
125 */
126 desc->u.ss.bHubHdrDecLat = 0;
127 desc->u.ss.wHubDelay = 0;
128
129 port_removable = 0;
130 /* bit 0 is reserved, bit 1 is for port 1, etc. */
131 for (i = 0; i < ports; i++) {
132 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
133 if (portsc & PORT_DEV_REMOVE)
134 port_removable |= 1 << (i + 1);
135 }
136 memset(&desc->u.ss.DeviceRemovable,
137 (__force __u16) cpu_to_le16(port_removable),
138 sizeof(__u16));
139}
140
141static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
142 struct usb_hub_descriptor *desc)
143{
144
145 if (hcd->speed == HCD_USB3)
146 xhci_usb3_hub_descriptor(hcd, xhci, desc);
147 else
148 xhci_usb2_hub_descriptor(hcd, xhci, desc);
149
150}
151
68static unsigned int xhci_port_speed(unsigned int port_status) 152static unsigned int xhci_port_speed(unsigned int port_status)
69{ 153{
70 if (DEV_LOWSPEED(port_status)) 154 if (DEV_LOWSPEED(port_status))
71 return USB_PORT_STAT_LOW_SPEED; 155 return USB_PORT_STAT_LOW_SPEED;
72 if (DEV_HIGHSPEED(port_status)) 156 if (DEV_HIGHSPEED(port_status))
73 return USB_PORT_STAT_HIGH_SPEED; 157 return USB_PORT_STAT_HIGH_SPEED;
74 if (DEV_SUPERSPEED(port_status))
75 return USB_PORT_STAT_SUPER_SPEED;
76 /* 158 /*
77 * FIXME: Yes, we should check for full speed, but the core uses that as 159 * FIXME: Yes, we should check for full speed, but the core uses that as
78 * a default in portspeed() in usb/core/hub.c (which is the only place 160 * a default in portspeed() in usb/core/hub.c (which is the only place
@@ -135,17 +217,22 @@ u32 xhci_port_state_to_neutral(u32 state)
135 217
136/* 218/*
137 * find slot id based on port number. 219 * find slot id based on port number.
220 * @port: The one-based port number from one of the two split roothubs.
138 */ 221 */
139int xhci_find_slot_id_by_port(struct xhci_hcd *xhci, u16 port) 222int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
223 u16 port)
140{ 224{
141 int slot_id; 225 int slot_id;
142 int i; 226 int i;
227 enum usb_device_speed speed;
143 228
144 slot_id = 0; 229 slot_id = 0;
145 for (i = 0; i < MAX_HC_SLOTS; i++) { 230 for (i = 0; i < MAX_HC_SLOTS; i++) {
146 if (!xhci->devs[i]) 231 if (!xhci->devs[i])
147 continue; 232 continue;
148 if (xhci->devs[i]->port == port) { 233 speed = xhci->devs[i]->udev->speed;
234 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
235 && xhci->devs[i]->port == port) {
149 slot_id = i; 236 slot_id = i;
150 break; 237 break;
151 } 238 }
@@ -226,11 +313,11 @@ void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
226 return; 313 return;
227} 314}
228 315
229static void xhci_disable_port(struct xhci_hcd *xhci, u16 wIndex, 316static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
230 u32 __iomem *addr, u32 port_status) 317 u16 wIndex, u32 __iomem *addr, u32 port_status)
231{ 318{
232 /* Don't allow the USB core to disable SuperSpeed ports. */ 319 /* Don't allow the USB core to disable SuperSpeed ports. */
233 if (xhci->port_array[wIndex] == 0x03) { 320 if (hcd->speed == HCD_USB3) {
234 xhci_dbg(xhci, "Ignoring request to disable " 321 xhci_dbg(xhci, "Ignoring request to disable "
235 "SuperSpeed port.\n"); 322 "SuperSpeed port.\n");
236 return; 323 return;
@@ -289,10 +376,18 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
289 unsigned long flags; 376 unsigned long flags;
290 u32 temp, temp1, status; 377 u32 temp, temp1, status;
291 int retval = 0; 378 int retval = 0;
292 u32 __iomem *addr; 379 u32 __iomem **port_array;
293 int slot_id; 380 int slot_id;
294 381 struct xhci_bus_state *bus_state;
295 ports = HCS_MAX_PORTS(xhci->hcs_params1); 382
383 if (hcd->speed == HCD_USB3) {
384 ports = xhci->num_usb3_ports;
385 port_array = xhci->usb3_ports;
386 } else {
387 ports = xhci->num_usb2_ports;
388 port_array = xhci->usb2_ports;
389 }
390 bus_state = &xhci->bus_state[hcd_index(hcd)];
296 391
297 spin_lock_irqsave(&xhci->lock, flags); 392 spin_lock_irqsave(&xhci->lock, flags);
298 switch (typeReq) { 393 switch (typeReq) {
@@ -301,17 +396,35 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
301 memset(buf, 0, 4); 396 memset(buf, 0, 4);
302 break; 397 break;
303 case GetHubDescriptor: 398 case GetHubDescriptor:
304 xhci_hub_descriptor(xhci, (struct usb_hub_descriptor *) buf); 399 /* Check to make sure userspace is asking for the USB 3.0 hub
400 * descriptor for the USB 3.0 roothub. If not, we stall the
401 * endpoint, like external hubs do.
402 */
403 if (hcd->speed == HCD_USB3 &&
404 (wLength < USB_DT_SS_HUB_SIZE ||
405 wValue != (USB_DT_SS_HUB << 8))) {
406 xhci_dbg(xhci, "Wrong hub descriptor type for "
407 "USB 3.0 roothub.\n");
408 goto error;
409 }
410 xhci_hub_descriptor(hcd, xhci,
411 (struct usb_hub_descriptor *) buf);
305 break; 412 break;
306 case GetPortStatus: 413 case GetPortStatus:
307 if (!wIndex || wIndex > ports) 414 if (!wIndex || wIndex > ports)
308 goto error; 415 goto error;
309 wIndex--; 416 wIndex--;
310 status = 0; 417 status = 0;
311 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff); 418 temp = xhci_readl(xhci, port_array[wIndex]);
312 temp = xhci_readl(xhci, addr); 419 if (temp == 0xffffffff) {
420 retval = -ENODEV;
421 break;
422 }
313 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); 423 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
314 424
425 /* FIXME - should we return a port status value like the USB
426 * 3.0 external hubs do?
427 */
315 /* wPortChange bits */ 428 /* wPortChange bits */
316 if (temp & PORT_CSC) 429 if (temp & PORT_CSC)
317 status |= USB_PORT_STAT_C_CONNECTION << 16; 430 status |= USB_PORT_STAT_C_CONNECTION << 16;
@@ -330,38 +443,33 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
330 if ((temp & PORT_RESET) || !(temp & PORT_PE)) 443 if ((temp & PORT_RESET) || !(temp & PORT_PE))
331 goto error; 444 goto error;
332 if (!DEV_SUPERSPEED(temp) && time_after_eq(jiffies, 445 if (!DEV_SUPERSPEED(temp) && time_after_eq(jiffies,
333 xhci->resume_done[wIndex])) { 446 bus_state->resume_done[wIndex])) {
334 xhci_dbg(xhci, "Resume USB2 port %d\n", 447 xhci_dbg(xhci, "Resume USB2 port %d\n",
335 wIndex + 1); 448 wIndex + 1);
336 xhci->resume_done[wIndex] = 0; 449 bus_state->resume_done[wIndex] = 0;
337 temp1 = xhci_port_state_to_neutral(temp); 450 temp1 = xhci_port_state_to_neutral(temp);
338 temp1 &= ~PORT_PLS_MASK; 451 temp1 &= ~PORT_PLS_MASK;
339 temp1 |= PORT_LINK_STROBE | XDEV_U0; 452 temp1 |= PORT_LINK_STROBE | XDEV_U0;
340 xhci_writel(xhci, temp1, addr); 453 xhci_writel(xhci, temp1, port_array[wIndex]);
341 454
342 xhci_dbg(xhci, "set port %d resume\n", 455 xhci_dbg(xhci, "set port %d resume\n",
343 wIndex + 1); 456 wIndex + 1);
344 slot_id = xhci_find_slot_id_by_port(xhci, 457 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
345 wIndex + 1); 458 wIndex + 1);
346 if (!slot_id) { 459 if (!slot_id) {
347 xhci_dbg(xhci, "slot_id is zero\n"); 460 xhci_dbg(xhci, "slot_id is zero\n");
348 goto error; 461 goto error;
349 } 462 }
350 xhci_ring_device(xhci, slot_id); 463 xhci_ring_device(xhci, slot_id);
351 xhci->port_c_suspend[wIndex >> 5] |= 464 bus_state->port_c_suspend |= 1 << wIndex;
352 1 << (wIndex & 31); 465 bus_state->suspended_ports &= ~(1 << wIndex);
353 xhci->suspended_ports[wIndex >> 5] &=
354 ~(1 << (wIndex & 31));
355 } 466 }
356 } 467 }
357 if ((temp & PORT_PLS_MASK) == XDEV_U0 468 if ((temp & PORT_PLS_MASK) == XDEV_U0
358 && (temp & PORT_POWER) 469 && (temp & PORT_POWER)
359 && (xhci->suspended_ports[wIndex >> 5] & 470 && (bus_state->suspended_ports & (1 << wIndex))) {
360 (1 << (wIndex & 31)))) { 471 bus_state->suspended_ports &= ~(1 << wIndex);
361 xhci->suspended_ports[wIndex >> 5] &= 472 bus_state->port_c_suspend |= 1 << wIndex;
362 ~(1 << (wIndex & 31));
363 xhci->port_c_suspend[wIndex >> 5] |=
364 1 << (wIndex & 31);
365 } 473 }
366 if (temp & PORT_CONNECT) { 474 if (temp & PORT_CONNECT) {
367 status |= USB_PORT_STAT_CONNECTION; 475 status |= USB_PORT_STAT_CONNECTION;
@@ -375,7 +483,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
375 status |= USB_PORT_STAT_RESET; 483 status |= USB_PORT_STAT_RESET;
376 if (temp & PORT_POWER) 484 if (temp & PORT_POWER)
377 status |= USB_PORT_STAT_POWER; 485 status |= USB_PORT_STAT_POWER;
378 if (xhci->port_c_suspend[wIndex >> 5] & (1 << (wIndex & 31))) 486 if (bus_state->port_c_suspend & (1 << wIndex))
379 status |= 1 << USB_PORT_FEAT_C_SUSPEND; 487 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
380 xhci_dbg(xhci, "Get port status returned 0x%x\n", status); 488 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
381 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 489 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
@@ -385,12 +493,16 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
385 if (!wIndex || wIndex > ports) 493 if (!wIndex || wIndex > ports)
386 goto error; 494 goto error;
387 wIndex--; 495 wIndex--;
388 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff); 496 temp = xhci_readl(xhci, port_array[wIndex]);
389 temp = xhci_readl(xhci, addr); 497 if (temp == 0xffffffff) {
498 retval = -ENODEV;
499 break;
500 }
390 temp = xhci_port_state_to_neutral(temp); 501 temp = xhci_port_state_to_neutral(temp);
502 /* FIXME: What new port features do we need to support? */
391 switch (wValue) { 503 switch (wValue) {
392 case USB_PORT_FEAT_SUSPEND: 504 case USB_PORT_FEAT_SUSPEND:
393 temp = xhci_readl(xhci, addr); 505 temp = xhci_readl(xhci, port_array[wIndex]);
394 /* In spec software should not attempt to suspend 506 /* In spec software should not attempt to suspend
395 * a port unless the port reports that it is in the 507 * a port unless the port reports that it is in the
396 * enabled (PED = ‘1’,PLS < ‘3’) state. 508 * enabled (PED = ‘1’,PLS < ‘3’) state.
@@ -402,7 +514,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
402 goto error; 514 goto error;
403 } 515 }
404 516
405 slot_id = xhci_find_slot_id_by_port(xhci, wIndex + 1); 517 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
518 wIndex + 1);
406 if (!slot_id) { 519 if (!slot_id) {
407 xhci_warn(xhci, "slot_id is zero\n"); 520 xhci_warn(xhci, "slot_id is zero\n");
408 goto error; 521 goto error;
@@ -415,15 +528,14 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
415 temp = xhci_port_state_to_neutral(temp); 528 temp = xhci_port_state_to_neutral(temp);
416 temp &= ~PORT_PLS_MASK; 529 temp &= ~PORT_PLS_MASK;
417 temp |= PORT_LINK_STROBE | XDEV_U3; 530 temp |= PORT_LINK_STROBE | XDEV_U3;
418 xhci_writel(xhci, temp, addr); 531 xhci_writel(xhci, temp, port_array[wIndex]);
419 532
420 spin_unlock_irqrestore(&xhci->lock, flags); 533 spin_unlock_irqrestore(&xhci->lock, flags);
421 msleep(10); /* wait device to enter */ 534 msleep(10); /* wait device to enter */
422 spin_lock_irqsave(&xhci->lock, flags); 535 spin_lock_irqsave(&xhci->lock, flags);
423 536
424 temp = xhci_readl(xhci, addr); 537 temp = xhci_readl(xhci, port_array[wIndex]);
425 xhci->suspended_ports[wIndex >> 5] |= 538 bus_state->suspended_ports |= 1 << wIndex;
426 1 << (wIndex & (31));
427 break; 539 break;
428 case USB_PORT_FEAT_POWER: 540 case USB_PORT_FEAT_POWER:
429 /* 541 /*
@@ -432,34 +544,39 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
432 * However, khubd will ignore the roothub events until 544 * However, khubd will ignore the roothub events until
433 * the roothub is registered. 545 * the roothub is registered.
434 */ 546 */
435 xhci_writel(xhci, temp | PORT_POWER, addr); 547 xhci_writel(xhci, temp | PORT_POWER,
548 port_array[wIndex]);
436 549
437 temp = xhci_readl(xhci, addr); 550 temp = xhci_readl(xhci, port_array[wIndex]);
438 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); 551 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
439 break; 552 break;
440 case USB_PORT_FEAT_RESET: 553 case USB_PORT_FEAT_RESET:
441 temp = (temp | PORT_RESET); 554 temp = (temp | PORT_RESET);
442 xhci_writel(xhci, temp, addr); 555 xhci_writel(xhci, temp, port_array[wIndex]);
443 556
444 temp = xhci_readl(xhci, addr); 557 temp = xhci_readl(xhci, port_array[wIndex]);
445 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); 558 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
446 break; 559 break;
447 default: 560 default:
448 goto error; 561 goto error;
449 } 562 }
450 temp = xhci_readl(xhci, addr); /* unblock any posted writes */ 563 /* unblock any posted writes */
564 temp = xhci_readl(xhci, port_array[wIndex]);
451 break; 565 break;
452 case ClearPortFeature: 566 case ClearPortFeature:
453 if (!wIndex || wIndex > ports) 567 if (!wIndex || wIndex > ports)
454 goto error; 568 goto error;
455 wIndex--; 569 wIndex--;
456 addr = &xhci->op_regs->port_status_base + 570 temp = xhci_readl(xhci, port_array[wIndex]);
457 NUM_PORT_REGS*(wIndex & 0xff); 571 if (temp == 0xffffffff) {
458 temp = xhci_readl(xhci, addr); 572 retval = -ENODEV;
573 break;
574 }
575 /* FIXME: What new port features do we need to support? */
459 temp = xhci_port_state_to_neutral(temp); 576 temp = xhci_port_state_to_neutral(temp);
460 switch (wValue) { 577 switch (wValue) {
461 case USB_PORT_FEAT_SUSPEND: 578 case USB_PORT_FEAT_SUSPEND:
462 temp = xhci_readl(xhci, addr); 579 temp = xhci_readl(xhci, port_array[wIndex]);
463 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 580 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
464 xhci_dbg(xhci, "PORTSC %04x\n", temp); 581 xhci_dbg(xhci, "PORTSC %04x\n", temp);
465 if (temp & PORT_RESET) 582 if (temp & PORT_RESET)
@@ -471,30 +588,34 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
471 temp = xhci_port_state_to_neutral(temp); 588 temp = xhci_port_state_to_neutral(temp);
472 temp &= ~PORT_PLS_MASK; 589 temp &= ~PORT_PLS_MASK;
473 temp |= PORT_LINK_STROBE | XDEV_U0; 590 temp |= PORT_LINK_STROBE | XDEV_U0;
474 xhci_writel(xhci, temp, addr); 591 xhci_writel(xhci, temp,
475 xhci_readl(xhci, addr); 592 port_array[wIndex]);
593 xhci_readl(xhci, port_array[wIndex]);
476 } else { 594 } else {
477 temp = xhci_port_state_to_neutral(temp); 595 temp = xhci_port_state_to_neutral(temp);
478 temp &= ~PORT_PLS_MASK; 596 temp &= ~PORT_PLS_MASK;
479 temp |= PORT_LINK_STROBE | XDEV_RESUME; 597 temp |= PORT_LINK_STROBE | XDEV_RESUME;
480 xhci_writel(xhci, temp, addr); 598 xhci_writel(xhci, temp,
599 port_array[wIndex]);
481 600
482 spin_unlock_irqrestore(&xhci->lock, 601 spin_unlock_irqrestore(&xhci->lock,
483 flags); 602 flags);
484 msleep(20); 603 msleep(20);
485 spin_lock_irqsave(&xhci->lock, flags); 604 spin_lock_irqsave(&xhci->lock, flags);
486 605
487 temp = xhci_readl(xhci, addr); 606 temp = xhci_readl(xhci,
607 port_array[wIndex]);
488 temp = xhci_port_state_to_neutral(temp); 608 temp = xhci_port_state_to_neutral(temp);
489 temp &= ~PORT_PLS_MASK; 609 temp &= ~PORT_PLS_MASK;
490 temp |= PORT_LINK_STROBE | XDEV_U0; 610 temp |= PORT_LINK_STROBE | XDEV_U0;
491 xhci_writel(xhci, temp, addr); 611 xhci_writel(xhci, temp,
612 port_array[wIndex]);
492 } 613 }
493 xhci->port_c_suspend[wIndex >> 5] |= 614 bus_state->port_c_suspend |= 1 << wIndex;
494 1 << (wIndex & 31);
495 } 615 }
496 616
497 slot_id = xhci_find_slot_id_by_port(xhci, wIndex + 1); 617 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
618 wIndex + 1);
498 if (!slot_id) { 619 if (!slot_id) {
499 xhci_dbg(xhci, "slot_id is zero\n"); 620 xhci_dbg(xhci, "slot_id is zero\n");
500 goto error; 621 goto error;
@@ -502,17 +623,17 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
502 xhci_ring_device(xhci, slot_id); 623 xhci_ring_device(xhci, slot_id);
503 break; 624 break;
504 case USB_PORT_FEAT_C_SUSPEND: 625 case USB_PORT_FEAT_C_SUSPEND:
505 xhci->port_c_suspend[wIndex >> 5] &= 626 bus_state->port_c_suspend &= ~(1 << wIndex);
506 ~(1 << (wIndex & 31));
507 case USB_PORT_FEAT_C_RESET: 627 case USB_PORT_FEAT_C_RESET:
508 case USB_PORT_FEAT_C_CONNECTION: 628 case USB_PORT_FEAT_C_CONNECTION:
509 case USB_PORT_FEAT_C_OVER_CURRENT: 629 case USB_PORT_FEAT_C_OVER_CURRENT:
510 case USB_PORT_FEAT_C_ENABLE: 630 case USB_PORT_FEAT_C_ENABLE:
511 xhci_clear_port_change_bit(xhci, wValue, wIndex, 631 xhci_clear_port_change_bit(xhci, wValue, wIndex,
512 addr, temp); 632 port_array[wIndex], temp);
513 break; 633 break;
514 case USB_PORT_FEAT_ENABLE: 634 case USB_PORT_FEAT_ENABLE:
515 xhci_disable_port(xhci, wIndex, addr, temp); 635 xhci_disable_port(hcd, xhci, wIndex,
636 port_array[wIndex], temp);
516 break; 637 break;
517 default: 638 default:
518 goto error; 639 goto error;
@@ -543,9 +664,17 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
543 int i, retval; 664 int i, retval;
544 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 665 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
545 int ports; 666 int ports;
546 u32 __iomem *addr; 667 u32 __iomem **port_array;
547 668 struct xhci_bus_state *bus_state;
548 ports = HCS_MAX_PORTS(xhci->hcs_params1); 669
670 if (hcd->speed == HCD_USB3) {
671 ports = xhci->num_usb3_ports;
672 port_array = xhci->usb3_ports;
673 } else {
674 ports = xhci->num_usb2_ports;
675 port_array = xhci->usb2_ports;
676 }
677 bus_state = &xhci->bus_state[hcd_index(hcd)];
549 678
550 /* Initial status is no changes */ 679 /* Initial status is no changes */
551 retval = (ports + 8) / 8; 680 retval = (ports + 8) / 8;
@@ -557,13 +686,15 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
557 spin_lock_irqsave(&xhci->lock, flags); 686 spin_lock_irqsave(&xhci->lock, flags);
558 /* For each port, did anything change? If so, set that bit in buf. */ 687 /* For each port, did anything change? If so, set that bit in buf. */
559 for (i = 0; i < ports; i++) { 688 for (i = 0; i < ports; i++) {
560 addr = &xhci->op_regs->port_status_base + 689 temp = xhci_readl(xhci, port_array[i]);
561 NUM_PORT_REGS*i; 690 if (temp == 0xffffffff) {
562 temp = xhci_readl(xhci, addr); 691 retval = -ENODEV;
692 break;
693 }
563 if ((temp & mask) != 0 || 694 if ((temp & mask) != 0 ||
564 (xhci->port_c_suspend[i >> 5] & 1 << (i & 31)) || 695 (bus_state->port_c_suspend & 1 << i) ||
565 (xhci->resume_done[i] && time_after_eq( 696 (bus_state->resume_done[i] && time_after_eq(
566 jiffies, xhci->resume_done[i]))) { 697 jiffies, bus_state->resume_done[i]))) {
567 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 698 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
568 status = 1; 699 status = 1;
569 } 700 }
@@ -577,42 +708,51 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
577int xhci_bus_suspend(struct usb_hcd *hcd) 708int xhci_bus_suspend(struct usb_hcd *hcd)
578{ 709{
579 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 710 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
580 int port; 711 int max_ports, port_index;
712 u32 __iomem **port_array;
713 struct xhci_bus_state *bus_state;
581 unsigned long flags; 714 unsigned long flags;
582 715
583 xhci_dbg(xhci, "suspend root hub\n"); 716 if (hcd->speed == HCD_USB3) {
717 max_ports = xhci->num_usb3_ports;
718 port_array = xhci->usb3_ports;
719 xhci_dbg(xhci, "suspend USB 3.0 root hub\n");
720 } else {
721 max_ports = xhci->num_usb2_ports;
722 port_array = xhci->usb2_ports;
723 xhci_dbg(xhci, "suspend USB 2.0 root hub\n");
724 }
725 bus_state = &xhci->bus_state[hcd_index(hcd)];
584 726
585 spin_lock_irqsave(&xhci->lock, flags); 727 spin_lock_irqsave(&xhci->lock, flags);
586 728
587 if (hcd->self.root_hub->do_remote_wakeup) { 729 if (hcd->self.root_hub->do_remote_wakeup) {
588 port = HCS_MAX_PORTS(xhci->hcs_params1); 730 port_index = max_ports;
589 while (port--) { 731 while (port_index--) {
590 if (xhci->resume_done[port] != 0) { 732 if (bus_state->resume_done[port_index] != 0) {
591 spin_unlock_irqrestore(&xhci->lock, flags); 733 spin_unlock_irqrestore(&xhci->lock, flags);
592 xhci_dbg(xhci, "suspend failed because " 734 xhci_dbg(xhci, "suspend failed because "
593 "port %d is resuming\n", 735 "port %d is resuming\n",
594 port + 1); 736 port_index + 1);
595 return -EBUSY; 737 return -EBUSY;
596 } 738 }
597 } 739 }
598 } 740 }
599 741
600 port = HCS_MAX_PORTS(xhci->hcs_params1); 742 port_index = max_ports;
601 xhci->bus_suspended = 0; 743 bus_state->bus_suspended = 0;
602 while (port--) { 744 while (port_index--) {
603 /* suspend the port if the port is not suspended */ 745 /* suspend the port if the port is not suspended */
604 u32 __iomem *addr;
605 u32 t1, t2; 746 u32 t1, t2;
606 int slot_id; 747 int slot_id;
607 748
608 addr = &xhci->op_regs->port_status_base + 749 t1 = xhci_readl(xhci, port_array[port_index]);
609 NUM_PORT_REGS * (port & 0xff);
610 t1 = xhci_readl(xhci, addr);
611 t2 = xhci_port_state_to_neutral(t1); 750 t2 = xhci_port_state_to_neutral(t1);
612 751
613 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { 752 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
614 xhci_dbg(xhci, "port %d not suspended\n", port); 753 xhci_dbg(xhci, "port %d not suspended\n", port_index);
615 slot_id = xhci_find_slot_id_by_port(xhci, port + 1); 754 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
755 port_index + 1);
616 if (slot_id) { 756 if (slot_id) {
617 spin_unlock_irqrestore(&xhci->lock, flags); 757 spin_unlock_irqrestore(&xhci->lock, flags);
618 xhci_stop_device(xhci, slot_id, 1); 758 xhci_stop_device(xhci, slot_id, 1);
@@ -620,7 +760,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
620 } 760 }
621 t2 &= ~PORT_PLS_MASK; 761 t2 &= ~PORT_PLS_MASK;
622 t2 |= PORT_LINK_STROBE | XDEV_U3; 762 t2 |= PORT_LINK_STROBE | XDEV_U3;
623 set_bit(port, &xhci->bus_suspended); 763 set_bit(port_index, &bus_state->bus_suspended);
624 } 764 }
625 if (hcd->self.root_hub->do_remote_wakeup) { 765 if (hcd->self.root_hub->do_remote_wakeup) {
626 if (t1 & PORT_CONNECT) { 766 if (t1 & PORT_CONNECT) {
@@ -635,22 +775,24 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
635 775
636 t1 = xhci_port_state_to_neutral(t1); 776 t1 = xhci_port_state_to_neutral(t1);
637 if (t1 != t2) 777 if (t1 != t2)
638 xhci_writel(xhci, t2, addr); 778 xhci_writel(xhci, t2, port_array[port_index]);
639 779
640 if (DEV_HIGHSPEED(t1)) { 780 if (DEV_HIGHSPEED(t1)) {
641 /* enable remote wake up for USB 2.0 */ 781 /* enable remote wake up for USB 2.0 */
642 u32 __iomem *addr; 782 u32 __iomem *addr;
643 u32 tmp; 783 u32 tmp;
644 784
645 addr = &xhci->op_regs->port_power_base + 785 /* Add one to the port status register address to get
646 NUM_PORT_REGS * (port & 0xff); 786 * the port power control register address.
787 */
788 addr = port_array[port_index] + 1;
647 tmp = xhci_readl(xhci, addr); 789 tmp = xhci_readl(xhci, addr);
648 tmp |= PORT_RWE; 790 tmp |= PORT_RWE;
649 xhci_writel(xhci, tmp, addr); 791 xhci_writel(xhci, tmp, addr);
650 } 792 }
651 } 793 }
652 hcd->state = HC_STATE_SUSPENDED; 794 hcd->state = HC_STATE_SUSPENDED;
653 xhci->next_statechange = jiffies + msecs_to_jiffies(10); 795 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
654 spin_unlock_irqrestore(&xhci->lock, flags); 796 spin_unlock_irqrestore(&xhci->lock, flags);
655 return 0; 797 return 0;
656} 798}
@@ -658,13 +800,24 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
658int xhci_bus_resume(struct usb_hcd *hcd) 800int xhci_bus_resume(struct usb_hcd *hcd)
659{ 801{
660 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 802 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
661 int port; 803 int max_ports, port_index;
804 u32 __iomem **port_array;
805 struct xhci_bus_state *bus_state;
662 u32 temp; 806 u32 temp;
663 unsigned long flags; 807 unsigned long flags;
664 808
665 xhci_dbg(xhci, "resume root hub\n"); 809 if (hcd->speed == HCD_USB3) {
810 max_ports = xhci->num_usb3_ports;
811 port_array = xhci->usb3_ports;
812 xhci_dbg(xhci, "resume USB 3.0 root hub\n");
813 } else {
814 max_ports = xhci->num_usb2_ports;
815 port_array = xhci->usb2_ports;
816 xhci_dbg(xhci, "resume USB 2.0 root hub\n");
817 }
818 bus_state = &xhci->bus_state[hcd_index(hcd)];
666 819
667 if (time_before(jiffies, xhci->next_statechange)) 820 if (time_before(jiffies, bus_state->next_statechange))
668 msleep(5); 821 msleep(5);
669 822
670 spin_lock_irqsave(&xhci->lock, flags); 823 spin_lock_irqsave(&xhci->lock, flags);
@@ -678,57 +831,57 @@ int xhci_bus_resume(struct usb_hcd *hcd)
678 temp &= ~CMD_EIE; 831 temp &= ~CMD_EIE;
679 xhci_writel(xhci, temp, &xhci->op_regs->command); 832 xhci_writel(xhci, temp, &xhci->op_regs->command);
680 833
681 port = HCS_MAX_PORTS(xhci->hcs_params1); 834 port_index = max_ports;
682 while (port--) { 835 while (port_index--) {
683 /* Check whether need resume ports. If needed 836 /* Check whether need resume ports. If needed
684 resume port and disable remote wakeup */ 837 resume port and disable remote wakeup */
685 u32 __iomem *addr;
686 u32 temp; 838 u32 temp;
687 int slot_id; 839 int slot_id;
688 840
689 addr = &xhci->op_regs->port_status_base + 841 temp = xhci_readl(xhci, port_array[port_index]);
690 NUM_PORT_REGS * (port & 0xff);
691 temp = xhci_readl(xhci, addr);
692 if (DEV_SUPERSPEED(temp)) 842 if (DEV_SUPERSPEED(temp))
693 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 843 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
694 else 844 else
695 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 845 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
696 if (test_bit(port, &xhci->bus_suspended) && 846 if (test_bit(port_index, &bus_state->bus_suspended) &&
697 (temp & PORT_PLS_MASK)) { 847 (temp & PORT_PLS_MASK)) {
698 if (DEV_SUPERSPEED(temp)) { 848 if (DEV_SUPERSPEED(temp)) {
699 temp = xhci_port_state_to_neutral(temp); 849 temp = xhci_port_state_to_neutral(temp);
700 temp &= ~PORT_PLS_MASK; 850 temp &= ~PORT_PLS_MASK;
701 temp |= PORT_LINK_STROBE | XDEV_U0; 851 temp |= PORT_LINK_STROBE | XDEV_U0;
702 xhci_writel(xhci, temp, addr); 852 xhci_writel(xhci, temp, port_array[port_index]);
703 } else { 853 } else {
704 temp = xhci_port_state_to_neutral(temp); 854 temp = xhci_port_state_to_neutral(temp);
705 temp &= ~PORT_PLS_MASK; 855 temp &= ~PORT_PLS_MASK;
706 temp |= PORT_LINK_STROBE | XDEV_RESUME; 856 temp |= PORT_LINK_STROBE | XDEV_RESUME;
707 xhci_writel(xhci, temp, addr); 857 xhci_writel(xhci, temp, port_array[port_index]);
708 858
709 spin_unlock_irqrestore(&xhci->lock, flags); 859 spin_unlock_irqrestore(&xhci->lock, flags);
710 msleep(20); 860 msleep(20);
711 spin_lock_irqsave(&xhci->lock, flags); 861 spin_lock_irqsave(&xhci->lock, flags);
712 862
713 temp = xhci_readl(xhci, addr); 863 temp = xhci_readl(xhci, port_array[port_index]);
714 temp = xhci_port_state_to_neutral(temp); 864 temp = xhci_port_state_to_neutral(temp);
715 temp &= ~PORT_PLS_MASK; 865 temp &= ~PORT_PLS_MASK;
716 temp |= PORT_LINK_STROBE | XDEV_U0; 866 temp |= PORT_LINK_STROBE | XDEV_U0;
717 xhci_writel(xhci, temp, addr); 867 xhci_writel(xhci, temp, port_array[port_index]);
718 } 868 }
719 slot_id = xhci_find_slot_id_by_port(xhci, port + 1); 869 slot_id = xhci_find_slot_id_by_port(hcd,
870 xhci, port_index + 1);
720 if (slot_id) 871 if (slot_id)
721 xhci_ring_device(xhci, slot_id); 872 xhci_ring_device(xhci, slot_id);
722 } else 873 } else
723 xhci_writel(xhci, temp, addr); 874 xhci_writel(xhci, temp, port_array[port_index]);
724 875
725 if (DEV_HIGHSPEED(temp)) { 876 if (DEV_HIGHSPEED(temp)) {
726 /* disable remote wake up for USB 2.0 */ 877 /* disable remote wake up for USB 2.0 */
727 u32 __iomem *addr; 878 u32 __iomem *addr;
728 u32 tmp; 879 u32 tmp;
729 880
730 addr = &xhci->op_regs->port_power_base + 881 /* Add one to the port status register address to get
731 NUM_PORT_REGS * (port & 0xff); 882 * the port power control register address.
883 */
884 addr = port_array[port_index] + 1;
732 tmp = xhci_readl(xhci, addr); 885 tmp = xhci_readl(xhci, addr);
733 tmp &= ~PORT_RWE; 886 tmp &= ~PORT_RWE;
734 xhci_writel(xhci, tmp, addr); 887 xhci_writel(xhci, tmp, addr);
@@ -737,8 +890,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
737 890
738 (void) xhci_readl(xhci, &xhci->op_regs->command); 891 (void) xhci_readl(xhci, &xhci->op_regs->command);
739 892
740 xhci->next_statechange = jiffies + msecs_to_jiffies(5); 893 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
741 hcd->state = HC_STATE_RUNNING;
742 /* re-enable irqs */ 894 /* re-enable irqs */
743 temp = xhci_readl(xhci, &xhci->op_regs->command); 895 temp = xhci_readl(xhci, &xhci->op_regs->command);
744 temp |= CMD_EIE; 896 temp |= CMD_EIE;
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index a9534396e85b..a003e79aacdc 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -814,14 +814,64 @@ void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
814 ep0_ctx->deq |= ep_ring->cycle_state; 814 ep0_ctx->deq |= ep_ring->cycle_state;
815} 815}
816 816
817/*
818 * The xHCI roothub may have ports of differing speeds in any order in the port
819 * status registers. xhci->port_array provides an array of the port speed for
820 * each offset into the port status registers.
821 *
822 * The xHCI hardware wants to know the roothub port number that the USB device
823 * is attached to (or the roothub port its ancestor hub is attached to). All we
824 * know is the index of that port under either the USB 2.0 or the USB 3.0
825 * roothub, but that doesn't give us the real index into the HW port status
826 * registers. Scan through the xHCI roothub port array, looking for the Nth
827 * entry of the correct port speed. Return the port number of that entry.
828 */
829static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
830 struct usb_device *udev)
831{
832 struct usb_device *top_dev;
833 unsigned int num_similar_speed_ports;
834 unsigned int faked_port_num;
835 int i;
836
837 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
838 top_dev = top_dev->parent)
839 /* Found device below root hub */;
840 faked_port_num = top_dev->portnum;
841 for (i = 0, num_similar_speed_ports = 0;
842 i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
843 u8 port_speed = xhci->port_array[i];
844
845 /*
846 * Skip ports that don't have known speeds, or have duplicate
847 * Extended Capabilities port speed entries.
848 */
849 if (port_speed == 0 || port_speed == -1)
850 continue;
851
852 /*
853 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
854 * 1.1 ports are under the USB 2.0 hub. If the port speed
855 * matches the device speed, it's a similar speed port.
856 */
857 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
858 num_similar_speed_ports++;
859 if (num_similar_speed_ports == faked_port_num)
860 /* Roothub ports are numbered from 1 to N */
861 return i+1;
862 }
863 return 0;
864}
865
817/* Setup an xHCI virtual device for a Set Address command */ 866/* Setup an xHCI virtual device for a Set Address command */
818int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) 867int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
819{ 868{
820 struct xhci_virt_device *dev; 869 struct xhci_virt_device *dev;
821 struct xhci_ep_ctx *ep0_ctx; 870 struct xhci_ep_ctx *ep0_ctx;
822 struct usb_device *top_dev;
823 struct xhci_slot_ctx *slot_ctx; 871 struct xhci_slot_ctx *slot_ctx;
824 struct xhci_input_control_ctx *ctrl_ctx; 872 struct xhci_input_control_ctx *ctrl_ctx;
873 u32 port_num;
874 struct usb_device *top_dev;
825 875
826 dev = xhci->devs[udev->slot_id]; 876 dev = xhci->devs[udev->slot_id];
827 /* Slot ID 0 is reserved */ 877 /* Slot ID 0 is reserved */
@@ -863,16 +913,20 @@ int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *ud
863 BUG(); 913 BUG();
864 } 914 }
865 /* Find the root hub port this device is under */ 915 /* Find the root hub port this device is under */
916 port_num = xhci_find_real_port_number(xhci, udev);
917 if (!port_num)
918 return -EINVAL;
919 slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(port_num);
920 /* Set the port number in the virtual_device to the faked port number */
866 for (top_dev = udev; top_dev->parent && top_dev->parent->parent; 921 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
867 top_dev = top_dev->parent) 922 top_dev = top_dev->parent)
868 /* Found device below root hub */; 923 /* Found device below root hub */;
869 slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
870 dev->port = top_dev->portnum; 924 dev->port = top_dev->portnum;
871 xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum); 925 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
926 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->port);
872 927
873 /* Is this a LS/FS device under a HS hub? */ 928 /* Is this a LS/FS device under an external HS hub? */
874 if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) && 929 if (udev->tt && udev->tt->hub->parent) {
875 udev->tt) {
876 slot_ctx->tt_info = udev->tt->hub->slot_id; 930 slot_ctx->tt_info = udev->tt->hub->slot_id;
877 slot_ctx->tt_info |= udev->ttport << 8; 931 slot_ctx->tt_info |= udev->ttport << 8;
878 if (udev->tt->multi) 932 if (udev->tt->multi)
@@ -1452,7 +1506,8 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
1452 1506
1453 xhci->page_size = 0; 1507 xhci->page_size = 0;
1454 xhci->page_shift = 0; 1508 xhci->page_shift = 0;
1455 xhci->bus_suspended = 0; 1509 xhci->bus_state[0].bus_suspended = 0;
1510 xhci->bus_state[1].bus_suspended = 0;
1456} 1511}
1457 1512
1458static int xhci_test_trb_in_td(struct xhci_hcd *xhci, 1513static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
@@ -1748,6 +1803,20 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
1748 } 1803 }
1749 xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n", 1804 xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
1750 xhci->num_usb2_ports, xhci->num_usb3_ports); 1805 xhci->num_usb2_ports, xhci->num_usb3_ports);
1806
1807 /* Place limits on the number of roothub ports so that the hub
1808 * descriptors aren't longer than the USB core will allocate.
1809 */
1810 if (xhci->num_usb3_ports > 15) {
1811 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
1812 xhci->num_usb3_ports = 15;
1813 }
1814 if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
1815 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
1816 USB_MAXCHILDREN);
1817 xhci->num_usb2_ports = USB_MAXCHILDREN;
1818 }
1819
1751 /* 1820 /*
1752 * Note we could have all USB 3.0 ports, or all USB 2.0 ports. 1821 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
1753 * Not sure how the USB core will handle a hub with no ports... 1822 * Not sure how the USB core will handle a hub with no ports...
@@ -1772,6 +1841,8 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
1772 "addr = %p\n", i, 1841 "addr = %p\n", i,
1773 xhci->usb2_ports[port_index]); 1842 xhci->usb2_ports[port_index]);
1774 port_index++; 1843 port_index++;
1844 if (port_index == xhci->num_usb2_ports)
1845 break;
1775 } 1846 }
1776 } 1847 }
1777 if (xhci->num_usb3_ports) { 1848 if (xhci->num_usb3_ports) {
@@ -1790,6 +1861,8 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
1790 "addr = %p\n", i, 1861 "addr = %p\n", i,
1791 xhci->usb3_ports[port_index]); 1862 xhci->usb3_ports[port_index]);
1792 port_index++; 1863 port_index++;
1864 if (port_index == xhci->num_usb3_ports)
1865 break;
1793 } 1866 }
1794 } 1867 }
1795 return 0; 1868 return 0;
@@ -1971,8 +2044,10 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
1971 init_completion(&xhci->addr_dev); 2044 init_completion(&xhci->addr_dev);
1972 for (i = 0; i < MAX_HC_SLOTS; ++i) 2045 for (i = 0; i < MAX_HC_SLOTS; ++i)
1973 xhci->devs[i] = NULL; 2046 xhci->devs[i] = NULL;
1974 for (i = 0; i < MAX_HC_PORTS; ++i) 2047 for (i = 0; i < USB_MAXCHILDREN; ++i) {
1975 xhci->resume_done[i] = 0; 2048 xhci->bus_state[0].resume_done[i] = 0;
2049 xhci->bus_state[1].resume_done[i] = 0;
2050 }
1976 2051
1977 if (scratchpad_alloc(xhci, flags)) 2052 if (scratchpad_alloc(xhci, flags))
1978 goto fail; 2053 goto fail;
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index bb668a894ab9..ceea9f33491c 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -50,13 +50,45 @@ static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
50/* called during probe() after chip reset completes */ 50/* called during probe() after chip reset completes */
51static int xhci_pci_setup(struct usb_hcd *hcd) 51static int xhci_pci_setup(struct usb_hcd *hcd)
52{ 52{
53 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 53 struct xhci_hcd *xhci;
54 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 54 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
55 int retval; 55 int retval;
56 u32 temp; 56 u32 temp;
57 57
58 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2; 58 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
59 59
60 if (usb_hcd_is_primary_hcd(hcd)) {
61 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
62 if (!xhci)
63 return -ENOMEM;
64 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
65 xhci->main_hcd = hcd;
66 /* Mark the first roothub as being USB 2.0.
67 * The xHCI driver will register the USB 3.0 roothub.
68 */
69 hcd->speed = HCD_USB2;
70 hcd->self.root_hub->speed = USB_SPEED_HIGH;
71 /*
72 * USB 2.0 roothub under xHCI has an integrated TT,
73 * (rate matching hub) as opposed to having an OHCI/UHCI
74 * companion controller.
75 */
76 hcd->has_tt = 1;
77 } else {
78 /* xHCI private pointer was set in xhci_pci_probe for the second
79 * registered roothub.
80 */
81 xhci = hcd_to_xhci(hcd);
82 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
83 if (HCC_64BIT_ADDR(temp)) {
84 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
85 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
86 } else {
87 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
88 }
89 return 0;
90 }
91
60 xhci->cap_regs = hcd->regs; 92 xhci->cap_regs = hcd->regs;
61 xhci->op_regs = hcd->regs + 93 xhci->op_regs = hcd->regs +
62 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase)); 94 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
@@ -85,13 +117,13 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
85 /* Make sure the HC is halted. */ 117 /* Make sure the HC is halted. */
86 retval = xhci_halt(xhci); 118 retval = xhci_halt(xhci);
87 if (retval) 119 if (retval)
88 return retval; 120 goto error;
89 121
90 xhci_dbg(xhci, "Resetting HCD\n"); 122 xhci_dbg(xhci, "Resetting HCD\n");
91 /* Reset the internal HC memory state and registers. */ 123 /* Reset the internal HC memory state and registers. */
92 retval = xhci_reset(xhci); 124 retval = xhci_reset(xhci);
93 if (retval) 125 if (retval)
94 return retval; 126 goto error;
95 xhci_dbg(xhci, "Reset complete\n"); 127 xhci_dbg(xhci, "Reset complete\n");
96 128
97 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); 129 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
@@ -106,14 +138,85 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
106 /* Initialize HCD and host controller data structures. */ 138 /* Initialize HCD and host controller data structures. */
107 retval = xhci_init(hcd); 139 retval = xhci_init(hcd);
108 if (retval) 140 if (retval)
109 return retval; 141 goto error;
110 xhci_dbg(xhci, "Called HCD init\n"); 142 xhci_dbg(xhci, "Called HCD init\n");
111 143
112 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 144 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
113 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 145 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
114 146
115 /* Find any debug ports */ 147 /* Find any debug ports */
116 return xhci_pci_reinit(xhci, pdev); 148 retval = xhci_pci_reinit(xhci, pdev);
149 if (!retval)
150 return retval;
151
152error:
153 kfree(xhci);
154 return retval;
155}
156
157/*
158 * We need to register our own PCI probe function (instead of the USB core's
159 * function) in order to create a second roothub under xHCI.
160 */
161static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
162{
163 int retval;
164 struct xhci_hcd *xhci;
165 struct hc_driver *driver;
166 struct usb_hcd *hcd;
167
168 driver = (struct hc_driver *)id->driver_data;
169 /* Register the USB 2.0 roothub.
170 * FIXME: USB core must know to register the USB 2.0 roothub first.
171 * This is sort of silly, because we could just set the HCD driver flags
172 * to say USB 2.0, but I'm not sure what the implications would be in
173 * the other parts of the HCD code.
174 */
175 retval = usb_hcd_pci_probe(dev, id);
176
177 if (retval)
178 return retval;
179
180 /* USB 2.0 roothub is stored in the PCI device now. */
181 hcd = dev_get_drvdata(&dev->dev);
182 xhci = hcd_to_xhci(hcd);
183 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
184 pci_name(dev), hcd);
185 if (!xhci->shared_hcd) {
186 retval = -ENOMEM;
187 goto dealloc_usb2_hcd;
188 }
189
190 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
191 * is called by usb_add_hcd().
192 */
193 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
194
195 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
196 IRQF_DISABLED | IRQF_SHARED);
197 if (retval)
198 goto put_usb3_hcd;
199 /* Roothub already marked as USB 3.0 speed */
200 return 0;
201
202put_usb3_hcd:
203 usb_put_hcd(xhci->shared_hcd);
204dealloc_usb2_hcd:
205 usb_hcd_pci_remove(dev);
206 return retval;
207}
208
209static void xhci_pci_remove(struct pci_dev *dev)
210{
211 struct xhci_hcd *xhci;
212
213 xhci = hcd_to_xhci(pci_get_drvdata(dev));
214 if (xhci->shared_hcd) {
215 usb_remove_hcd(xhci->shared_hcd);
216 usb_put_hcd(xhci->shared_hcd);
217 }
218 usb_hcd_pci_remove(dev);
219 kfree(xhci);
117} 220}
118 221
119#ifdef CONFIG_PM 222#ifdef CONFIG_PM
@@ -122,7 +225,8 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
122 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 225 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
123 int retval = 0; 226 int retval = 0;
124 227
125 if (hcd->state != HC_STATE_SUSPENDED) 228 if (hcd->state != HC_STATE_SUSPENDED ||
229 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
126 return -EINVAL; 230 return -EINVAL;
127 231
128 retval = xhci_suspend(xhci); 232 retval = xhci_suspend(xhci);
@@ -143,13 +247,13 @@ static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
143static const struct hc_driver xhci_pci_hc_driver = { 247static const struct hc_driver xhci_pci_hc_driver = {
144 .description = hcd_name, 248 .description = hcd_name,
145 .product_desc = "xHCI Host Controller", 249 .product_desc = "xHCI Host Controller",
146 .hcd_priv_size = sizeof(struct xhci_hcd), 250 .hcd_priv_size = sizeof(struct xhci_hcd *),
147 251
148 /* 252 /*
149 * generic hardware linkage 253 * generic hardware linkage
150 */ 254 */
151 .irq = xhci_irq, 255 .irq = xhci_irq,
152 .flags = HCD_MEMORY | HCD_USB3, 256 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
153 257
154 /* 258 /*
155 * basic lifecycle operations 259 * basic lifecycle operations
@@ -210,8 +314,8 @@ static struct pci_driver xhci_pci_driver = {
210 .name = (char *) hcd_name, 314 .name = (char *) hcd_name,
211 .id_table = pci_ids, 315 .id_table = pci_ids,
212 316
213 .probe = usb_hcd_pci_probe, 317 .probe = xhci_pci_probe,
214 .remove = usb_hcd_pci_remove, 318 .remove = xhci_pci_remove,
215 /* suspend and resume implemented later */ 319 /* suspend and resume implemented later */
216 320
217 .shutdown = usb_hcd_pci_shutdown, 321 .shutdown = usb_hcd_pci_shutdown,
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 3289bf4832c9..cfc1ad92473f 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -380,10 +380,8 @@ static struct xhci_segment *find_trb_seg(
380 while (cur_seg->trbs > trb || 380 while (cur_seg->trbs > trb ||
381 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { 381 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
382 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; 382 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
383 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) == 383 if (generic_trb->field[3] & LINK_TOGGLE)
384 TRB_TYPE(TRB_LINK) && 384 *cycle_state ^= 0x1;
385 (generic_trb->field[3] & LINK_TOGGLE))
386 *cycle_state = ~(*cycle_state) & 0x1;
387 cur_seg = cur_seg->next; 385 cur_seg = cur_seg->next;
388 if (cur_seg == start_seg) 386 if (cur_seg == start_seg)
389 /* Looped over the entire list. Oops! */ 387 /* Looped over the entire list. Oops! */
@@ -497,18 +495,29 @@ void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
497 trb = &state->new_deq_ptr->generic; 495 trb = &state->new_deq_ptr->generic;
498 if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) && 496 if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
499 (trb->field[3] & LINK_TOGGLE)) 497 (trb->field[3] & LINK_TOGGLE))
500 state->new_cycle_state = ~(state->new_cycle_state) & 0x1; 498 state->new_cycle_state ^= 0x1;
501 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); 499 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
502 500
501 /*
502 * If there is only one segment in a ring, find_trb_seg()'s while loop
503 * will not run, and it will return before it has a chance to see if it
504 * needs to toggle the cycle bit. It can't tell if the stalled transfer
505 * ended just before the link TRB on a one-segment ring, or if the TD
506 * wrapped around the top of the ring, because it doesn't have the TD in
507 * question. Look for the one-segment case where stalled TRB's address
508 * is greater than the new dequeue pointer address.
509 */
510 if (ep_ring->first_seg == ep_ring->first_seg->next &&
511 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
512 state->new_cycle_state ^= 0x1;
513 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
514
503 /* Don't update the ring cycle state for the producer (us). */ 515 /* Don't update the ring cycle state for the producer (us). */
504 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", 516 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
505 state->new_deq_seg); 517 state->new_deq_seg);
506 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); 518 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
507 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", 519 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
508 (unsigned long long) addr); 520 (unsigned long long) addr);
509 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
510 ep_ring->dequeue = state->new_deq_ptr;
511 ep_ring->deq_seg = state->new_deq_seg;
512} 521}
513 522
514static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 523static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
@@ -599,13 +608,14 @@ static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
599static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, 608static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
600 struct xhci_td *cur_td, int status, char *adjective) 609 struct xhci_td *cur_td, int status, char *adjective)
601{ 610{
602 struct usb_hcd *hcd = xhci_to_hcd(xhci); 611 struct usb_hcd *hcd;
603 struct urb *urb; 612 struct urb *urb;
604 struct urb_priv *urb_priv; 613 struct urb_priv *urb_priv;
605 614
606 urb = cur_td->urb; 615 urb = cur_td->urb;
607 urb_priv = urb->hcpriv; 616 urb_priv = urb->hcpriv;
608 urb_priv->td_cnt++; 617 urb_priv->td_cnt++;
618 hcd = bus_to_hcd(urb->dev->bus);
609 619
610 /* Only giveback urb when this is the last td in urb */ 620 /* Only giveback urb when this is the last td in urb */
611 if (urb_priv->td_cnt == urb_priv->length) { 621 if (urb_priv->td_cnt == urb_priv->length) {
@@ -824,8 +834,7 @@ void xhci_stop_endpoint_command_watchdog(unsigned long arg)
824 if (ret < 0) { 834 if (ret < 0) {
825 /* This is bad; the host is not responding to commands and it's 835 /* This is bad; the host is not responding to commands and it's
826 * not allowing itself to be halted. At least interrupts are 836 * not allowing itself to be halted. At least interrupts are
827 * disabled, so we can set HC_STATE_HALT and notify the 837 * disabled. If we call usb_hc_died(), it will attempt to
828 * USB core. But if we call usb_hc_died(), it will attempt to
829 * disconnect all device drivers under this host. Those 838 * disconnect all device drivers under this host. Those
830 * disconnect() methods will wait for all URBs to be unlinked, 839 * disconnect() methods will wait for all URBs to be unlinked,
831 * so we must complete them. 840 * so we must complete them.
@@ -870,9 +879,8 @@ void xhci_stop_endpoint_command_watchdog(unsigned long arg)
870 } 879 }
871 } 880 }
872 spin_unlock(&xhci->lock); 881 spin_unlock(&xhci->lock);
873 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
874 xhci_dbg(xhci, "Calling usb_hc_died()\n"); 882 xhci_dbg(xhci, "Calling usb_hc_died()\n");
875 usb_hc_died(xhci_to_hcd(xhci)); 883 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
876 xhci_dbg(xhci, "xHCI host controller is dead.\n"); 884 xhci_dbg(xhci, "xHCI host controller is dead.\n");
877} 885}
878 886
@@ -951,9 +959,26 @@ static void handle_set_deq_completion(struct xhci_hcd *xhci,
951 } else { 959 } else {
952 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", 960 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
953 ep_ctx->deq); 961 ep_ctx->deq);
962 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
963 dev->eps[ep_index].queued_deq_ptr) ==
964 (ep_ctx->deq & ~(EP_CTX_CYCLE_MASK))) {
965 /* Update the ring's dequeue segment and dequeue pointer
966 * to reflect the new position.
967 */
968 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
969 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
970 } else {
971 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
972 "Ptr command & xHCI internal state.\n");
973 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
974 dev->eps[ep_index].queued_deq_seg,
975 dev->eps[ep_index].queued_deq_ptr);
976 }
954 } 977 }
955 978
956 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; 979 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
980 dev->eps[ep_index].queued_deq_seg = NULL;
981 dev->eps[ep_index].queued_deq_ptr = NULL;
957 /* Restart any rings with pending URBs */ 982 /* Restart any rings with pending URBs */
958 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 983 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
959} 984}
@@ -1118,7 +1143,6 @@ bandwidth_change:
1118 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); 1143 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1119 break; 1144 break;
1120 case TRB_TYPE(TRB_CMD_NOOP): 1145 case TRB_TYPE(TRB_CMD_NOOP):
1121 ++xhci->noops_handled;
1122 break; 1146 break;
1123 case TRB_TYPE(TRB_RESET_EP): 1147 case TRB_TYPE(TRB_RESET_EP):
1124 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); 1148 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
@@ -1162,15 +1186,55 @@ static void handle_vendor_event(struct xhci_hcd *xhci,
1162 handle_cmd_completion(xhci, &event->event_cmd); 1186 handle_cmd_completion(xhci, &event->event_cmd);
1163} 1187}
1164 1188
1189/* @port_id: the one-based port ID from the hardware (indexed from array of all
1190 * port registers -- USB 3.0 and USB 2.0).
1191 *
1192 * Returns a zero-based port number, which is suitable for indexing into each of
1193 * the split roothubs' port arrays and bus state arrays.
1194 */
1195static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1196 struct xhci_hcd *xhci, u32 port_id)
1197{
1198 unsigned int i;
1199 unsigned int num_similar_speed_ports = 0;
1200
1201 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1202 * and usb2_ports are 0-based indexes. Count the number of similar
1203 * speed ports, up to 1 port before this port.
1204 */
1205 for (i = 0; i < (port_id - 1); i++) {
1206 u8 port_speed = xhci->port_array[i];
1207
1208 /*
1209 * Skip ports that don't have known speeds, or have duplicate
1210 * Extended Capabilities port speed entries.
1211 */
1212 if (port_speed == 0 || port_speed == -1)
1213 continue;
1214
1215 /*
1216 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1217 * 1.1 ports are under the USB 2.0 hub. If the port speed
1218 * matches the device speed, it's a similar speed port.
1219 */
1220 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1221 num_similar_speed_ports++;
1222 }
1223 return num_similar_speed_ports;
1224}
1225
1165static void handle_port_status(struct xhci_hcd *xhci, 1226static void handle_port_status(struct xhci_hcd *xhci,
1166 union xhci_trb *event) 1227 union xhci_trb *event)
1167{ 1228{
1168 struct usb_hcd *hcd = xhci_to_hcd(xhci); 1229 struct usb_hcd *hcd;
1169 u32 port_id; 1230 u32 port_id;
1170 u32 temp, temp1; 1231 u32 temp, temp1;
1171 u32 __iomem *addr; 1232 int max_ports;
1172 int ports;
1173 int slot_id; 1233 int slot_id;
1234 unsigned int faked_port_index;
1235 u8 major_revision;
1236 struct xhci_bus_state *bus_state;
1237 u32 __iomem **port_array;
1174 1238
1175 /* Port status change events always have a successful completion code */ 1239 /* Port status change events always have a successful completion code */
1176 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) { 1240 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
@@ -1180,14 +1244,50 @@ static void handle_port_status(struct xhci_hcd *xhci,
1180 port_id = GET_PORT_ID(event->generic.field[0]); 1244 port_id = GET_PORT_ID(event->generic.field[0]);
1181 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); 1245 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1182 1246
1183 ports = HCS_MAX_PORTS(xhci->hcs_params1); 1247 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1184 if ((port_id <= 0) || (port_id > ports)) { 1248 if ((port_id <= 0) || (port_id > max_ports)) {
1185 xhci_warn(xhci, "Invalid port id %d\n", port_id); 1249 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1186 goto cleanup; 1250 goto cleanup;
1187 } 1251 }
1188 1252
1189 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS * (port_id - 1); 1253 /* Figure out which usb_hcd this port is attached to:
1190 temp = xhci_readl(xhci, addr); 1254 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1255 */
1256 major_revision = xhci->port_array[port_id - 1];
1257 if (major_revision == 0) {
1258 xhci_warn(xhci, "Event for port %u not in "
1259 "Extended Capabilities, ignoring.\n",
1260 port_id);
1261 goto cleanup;
1262 }
1263 if (major_revision == (u8) -1) {
1264 xhci_warn(xhci, "Event for port %u duplicated in"
1265 "Extended Capabilities, ignoring.\n",
1266 port_id);
1267 goto cleanup;
1268 }
1269
1270 /*
1271 * Hardware port IDs reported by a Port Status Change Event include USB
1272 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1273 * resume event, but we first need to translate the hardware port ID
1274 * into the index into the ports on the correct split roothub, and the
1275 * correct bus_state structure.
1276 */
1277 /* Find the right roothub. */
1278 hcd = xhci_to_hcd(xhci);
1279 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1280 hcd = xhci->shared_hcd;
1281 bus_state = &xhci->bus_state[hcd_index(hcd)];
1282 if (hcd->speed == HCD_USB3)
1283 port_array = xhci->usb3_ports;
1284 else
1285 port_array = xhci->usb2_ports;
1286 /* Find the faked port hub number */
1287 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1288 port_id);
1289
1290 temp = xhci_readl(xhci, port_array[faked_port_index]);
1191 if (hcd->state == HC_STATE_SUSPENDED) { 1291 if (hcd->state == HC_STATE_SUSPENDED) {
1192 xhci_dbg(xhci, "resume root hub\n"); 1292 xhci_dbg(xhci, "resume root hub\n");
1193 usb_hcd_resume_root_hub(hcd); 1293 usb_hcd_resume_root_hub(hcd);
@@ -1207,8 +1307,9 @@ static void handle_port_status(struct xhci_hcd *xhci,
1207 temp = xhci_port_state_to_neutral(temp); 1307 temp = xhci_port_state_to_neutral(temp);
1208 temp &= ~PORT_PLS_MASK; 1308 temp &= ~PORT_PLS_MASK;
1209 temp |= PORT_LINK_STROBE | XDEV_U0; 1309 temp |= PORT_LINK_STROBE | XDEV_U0;
1210 xhci_writel(xhci, temp, addr); 1310 xhci_writel(xhci, temp, port_array[faked_port_index]);
1211 slot_id = xhci_find_slot_id_by_port(xhci, port_id); 1311 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1312 faked_port_index);
1212 if (!slot_id) { 1313 if (!slot_id) {
1213 xhci_dbg(xhci, "slot_id is zero\n"); 1314 xhci_dbg(xhci, "slot_id is zero\n");
1214 goto cleanup; 1315 goto cleanup;
@@ -1216,16 +1317,16 @@ static void handle_port_status(struct xhci_hcd *xhci,
1216 xhci_ring_device(xhci, slot_id); 1317 xhci_ring_device(xhci, slot_id);
1217 xhci_dbg(xhci, "resume SS port %d finished\n", port_id); 1318 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1218 /* Clear PORT_PLC */ 1319 /* Clear PORT_PLC */
1219 temp = xhci_readl(xhci, addr); 1320 temp = xhci_readl(xhci, port_array[faked_port_index]);
1220 temp = xhci_port_state_to_neutral(temp); 1321 temp = xhci_port_state_to_neutral(temp);
1221 temp |= PORT_PLC; 1322 temp |= PORT_PLC;
1222 xhci_writel(xhci, temp, addr); 1323 xhci_writel(xhci, temp, port_array[faked_port_index]);
1223 } else { 1324 } else {
1224 xhci_dbg(xhci, "resume HS port %d\n", port_id); 1325 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1225 xhci->resume_done[port_id - 1] = jiffies + 1326 bus_state->resume_done[faked_port_index] = jiffies +
1226 msecs_to_jiffies(20); 1327 msecs_to_jiffies(20);
1227 mod_timer(&hcd->rh_timer, 1328 mod_timer(&hcd->rh_timer,
1228 xhci->resume_done[port_id - 1]); 1329 bus_state->resume_done[faked_port_index]);
1229 /* Do the rest in GetPortStatus */ 1330 /* Do the rest in GetPortStatus */
1230 } 1331 }
1231 } 1332 }
@@ -1236,7 +1337,7 @@ cleanup:
1236 1337
1237 spin_unlock(&xhci->lock); 1338 spin_unlock(&xhci->lock);
1238 /* Pass this up to the core */ 1339 /* Pass this up to the core */
1239 usb_hcd_poll_rh_status(xhci_to_hcd(xhci)); 1340 usb_hcd_poll_rh_status(hcd);
1240 spin_lock(&xhci->lock); 1341 spin_lock(&xhci->lock);
1241} 1342}
1242 1343
@@ -1990,12 +2091,12 @@ cleanup:
1990 trb_comp_code != COMP_BABBLE)) 2091 trb_comp_code != COMP_BABBLE))
1991 xhci_urb_free_priv(xhci, urb_priv); 2092 xhci_urb_free_priv(xhci, urb_priv);
1992 2093
1993 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb); 2094 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
1994 xhci_dbg(xhci, "Giveback URB %p, len = %d, " 2095 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
1995 "status = %d\n", 2096 "status = %d\n",
1996 urb, urb->actual_length, status); 2097 urb, urb->actual_length, status);
1997 spin_unlock(&xhci->lock); 2098 spin_unlock(&xhci->lock);
1998 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status); 2099 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
1999 spin_lock(&xhci->lock); 2100 spin_lock(&xhci->lock);
2000 } 2101 }
2001 2102
@@ -2119,7 +2220,6 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd)
2119 xhci_warn(xhci, "WARNING: Host System Error\n"); 2220 xhci_warn(xhci, "WARNING: Host System Error\n");
2120 xhci_halt(xhci); 2221 xhci_halt(xhci);
2121hw_died: 2222hw_died:
2122 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
2123 spin_unlock(&xhci->lock); 2223 spin_unlock(&xhci->lock);
2124 return -ESHUTDOWN; 2224 return -ESHUTDOWN;
2125 } 2225 }
@@ -2187,8 +2287,12 @@ hw_died:
2187irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) 2287irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2188{ 2288{
2189 irqreturn_t ret; 2289 irqreturn_t ret;
2290 struct xhci_hcd *xhci;
2190 2291
2292 xhci = hcd_to_xhci(hcd);
2191 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 2293 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2294 if (xhci->shared_hcd)
2295 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2192 2296
2193 ret = xhci_irq(hcd); 2297 ret = xhci_irq(hcd);
2194 2298
@@ -2332,7 +2436,7 @@ static int prepare_transfer(struct xhci_hcd *xhci,
2332 INIT_LIST_HEAD(&td->cancelled_td_list); 2436 INIT_LIST_HEAD(&td->cancelled_td_list);
2333 2437
2334 if (td_index == 0) { 2438 if (td_index == 0) {
2335 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb); 2439 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2336 if (unlikely(ret)) { 2440 if (unlikely(ret)) {
2337 xhci_urb_free_priv(xhci, urb_priv); 2441 xhci_urb_free_priv(xhci, urb_priv);
2338 urb->hcpriv = NULL; 2442 urb->hcpriv = NULL;
@@ -3131,24 +3235,6 @@ static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3131 return 0; 3235 return 0;
3132} 3236}
3133 3237
3134/* Queue a no-op command on the command ring */
3135static int queue_cmd_noop(struct xhci_hcd *xhci)
3136{
3137 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
3138}
3139
3140/*
3141 * Place a no-op command on the command ring to test the command and
3142 * event ring.
3143 */
3144void *xhci_setup_one_noop(struct xhci_hcd *xhci)
3145{
3146 if (queue_cmd_noop(xhci) < 0)
3147 return NULL;
3148 xhci->noops_submitted++;
3149 return xhci_ring_cmd_db;
3150}
3151
3152/* Queue a slot enable or disable request on the command ring */ 3238/* Queue a slot enable or disable request on the command ring */
3153int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) 3239int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3154{ 3240{
@@ -3229,6 +3315,7 @@ static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3229 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 3315 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3230 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); 3316 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3231 u32 type = TRB_TYPE(TRB_SET_DEQ); 3317 u32 type = TRB_TYPE(TRB_SET_DEQ);
3318 struct xhci_virt_ep *ep;
3232 3319
3233 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); 3320 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3234 if (addr == 0) { 3321 if (addr == 0) {
@@ -3237,6 +3324,14 @@ static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3237 deq_seg, deq_ptr); 3324 deq_seg, deq_ptr);
3238 return 0; 3325 return 0;
3239 } 3326 }
3327 ep = &xhci->devs[slot_id]->eps[ep_index];
3328 if ((ep->ep_state & SET_DEQ_PENDING)) {
3329 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3330 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3331 return 0;
3332 }
3333 ep->queued_deq_seg = deq_seg;
3334 ep->queued_deq_ptr = deq_ptr;
3240 return queue_command(xhci, lower_32_bits(addr) | cycle_state, 3335 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3241 upper_32_bits(addr), trb_stream_id, 3336 upper_32_bits(addr), trb_stream_id,
3242 trb_slot_id | trb_ep_index | type, false); 3337 trb_slot_id | trb_ep_index | type, false);
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 2083fc2179b2..9a3645fd759b 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -93,17 +93,20 @@ void xhci_quiesce(struct xhci_hcd *xhci)
93 * 93 *
94 * Disable any IRQs and clear the run/stop bit. 94 * Disable any IRQs and clear the run/stop bit.
95 * HC will complete any current and actively pipelined transactions, and 95 * HC will complete any current and actively pipelined transactions, and
96 * should halt within 16 microframes of the run/stop bit being cleared. 96 * should halt within 16 ms of the run/stop bit being cleared.
97 * Read HC Halted bit in the status register to see when the HC is finished. 97 * Read HC Halted bit in the status register to see when the HC is finished.
98 * XXX: shouldn't we set HC_STATE_HALT here somewhere?
99 */ 98 */
100int xhci_halt(struct xhci_hcd *xhci) 99int xhci_halt(struct xhci_hcd *xhci)
101{ 100{
101 int ret;
102 xhci_dbg(xhci, "// Halt the HC\n"); 102 xhci_dbg(xhci, "// Halt the HC\n");
103 xhci_quiesce(xhci); 103 xhci_quiesce(xhci);
104 104
105 return handshake(xhci, &xhci->op_regs->status, 105 ret = handshake(xhci, &xhci->op_regs->status,
106 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); 106 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
107 if (!ret)
108 xhci->xhc_state |= XHCI_STATE_HALTED;
109 return ret;
107} 110}
108 111
109/* 112/*
@@ -130,11 +133,13 @@ static int xhci_start(struct xhci_hcd *xhci)
130 xhci_err(xhci, "Host took too long to start, " 133 xhci_err(xhci, "Host took too long to start, "
131 "waited %u microseconds.\n", 134 "waited %u microseconds.\n",
132 XHCI_MAX_HALT_USEC); 135 XHCI_MAX_HALT_USEC);
136 if (!ret)
137 xhci->xhc_state &= ~XHCI_STATE_HALTED;
133 return ret; 138 return ret;
134} 139}
135 140
136/* 141/*
137 * Reset a halted HC, and set the internal HC state to HC_STATE_HALT. 142 * Reset a halted HC.
138 * 143 *
139 * This resets pipelines, timers, counters, state machines, etc. 144 * This resets pipelines, timers, counters, state machines, etc.
140 * Transactions will be terminated immediately, and operational registers 145 * Transactions will be terminated immediately, and operational registers
@@ -156,8 +161,6 @@ int xhci_reset(struct xhci_hcd *xhci)
156 command = xhci_readl(xhci, &xhci->op_regs->command); 161 command = xhci_readl(xhci, &xhci->op_regs->command);
157 command |= CMD_RESET; 162 command |= CMD_RESET;
158 xhci_writel(xhci, command, &xhci->op_regs->command); 163 xhci_writel(xhci, command, &xhci->op_regs->command);
159 /* XXX: Why does EHCI set this here? Shouldn't other code do this? */
160 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
161 164
162 ret = handshake(xhci, &xhci->op_regs->command, 165 ret = handshake(xhci, &xhci->op_regs->command,
163 CMD_RESET, 0, 250 * 1000); 166 CMD_RESET, 0, 250 * 1000);
@@ -350,7 +353,6 @@ static void xhci_event_ring_work(unsigned long arg)
350 353
351 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); 354 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
352 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp); 355 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
353 xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
354 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask); 356 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
355 xhci->error_bitmask = 0; 357 xhci->error_bitmask = 0;
356 xhci_dbg(xhci, "Event ring:\n"); 358 xhci_dbg(xhci, "Event ring:\n");
@@ -370,10 +372,6 @@ static void xhci_event_ring_work(unsigned long arg)
370 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]); 372 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
371 } 373 }
372 } 374 }
373
374 if (xhci->noops_submitted != NUM_TEST_NOOPS)
375 if (xhci_setup_one_noop(xhci))
376 xhci_ring_cmd_db(xhci);
377 spin_unlock_irqrestore(&xhci->lock, flags); 375 spin_unlock_irqrestore(&xhci->lock, flags);
378 376
379 if (!xhci->zombie) 377 if (!xhci->zombie)
@@ -383,6 +381,21 @@ static void xhci_event_ring_work(unsigned long arg)
383} 381}
384#endif 382#endif
385 383
384static int xhci_run_finished(struct xhci_hcd *xhci)
385{
386 if (xhci_start(xhci)) {
387 xhci_halt(xhci);
388 return -ENODEV;
389 }
390 xhci->shared_hcd->state = HC_STATE_RUNNING;
391
392 if (xhci->quirks & XHCI_NEC_HOST)
393 xhci_ring_cmd_db(xhci);
394
395 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
396 return 0;
397}
398
386/* 399/*
387 * Start the HC after it was halted. 400 * Start the HC after it was halted.
388 * 401 *
@@ -402,9 +415,14 @@ int xhci_run(struct usb_hcd *hcd)
402 u32 ret; 415 u32 ret;
403 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 416 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
404 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 417 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
405 void (*doorbell)(struct xhci_hcd *) = NULL; 418
419 /* Start the xHCI host controller running only after the USB 2.0 roothub
420 * is setup.
421 */
406 422
407 hcd->uses_new_polling = 1; 423 hcd->uses_new_polling = 1;
424 if (!usb_hcd_is_primary_hcd(hcd))
425 return xhci_run_finished(xhci);
408 426
409 xhci_dbg(xhci, "xhci_run\n"); 427 xhci_dbg(xhci, "xhci_run\n");
410 /* unregister the legacy interrupt */ 428 /* unregister the legacy interrupt */
@@ -461,7 +479,6 @@ int xhci_run(struct usb_hcd *hcd)
461 xhci_writel(xhci, temp, &xhci->ir_set->irq_control); 479 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
462 480
463 /* Set the HCD state before we enable the irqs */ 481 /* Set the HCD state before we enable the irqs */
464 hcd->state = HC_STATE_RUNNING;
465 temp = xhci_readl(xhci, &xhci->op_regs->command); 482 temp = xhci_readl(xhci, &xhci->op_regs->command);
466 temp |= (CMD_EIE); 483 temp |= (CMD_EIE);
467 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n", 484 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
@@ -475,24 +492,27 @@ int xhci_run(struct usb_hcd *hcd)
475 &xhci->ir_set->irq_pending); 492 &xhci->ir_set->irq_pending);
476 xhci_print_ir_set(xhci, 0); 493 xhci_print_ir_set(xhci, 0);
477 494
478 if (NUM_TEST_NOOPS > 0)
479 doorbell = xhci_setup_one_noop(xhci);
480 if (xhci->quirks & XHCI_NEC_HOST) 495 if (xhci->quirks & XHCI_NEC_HOST)
481 xhci_queue_vendor_command(xhci, 0, 0, 0, 496 xhci_queue_vendor_command(xhci, 0, 0, 0,
482 TRB_TYPE(TRB_NEC_GET_FW)); 497 TRB_TYPE(TRB_NEC_GET_FW));
483 498
484 if (xhci_start(xhci)) { 499 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
485 xhci_halt(xhci); 500 return 0;
486 return -ENODEV; 501}
487 }
488 502
489 if (doorbell) 503static void xhci_only_stop_hcd(struct usb_hcd *hcd)
490 (*doorbell)(xhci); 504{
491 if (xhci->quirks & XHCI_NEC_HOST) 505 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
492 xhci_ring_cmd_db(xhci);
493 506
494 xhci_dbg(xhci, "Finished xhci_run\n"); 507 spin_lock_irq(&xhci->lock);
495 return 0; 508 xhci_halt(xhci);
509
510 /* The shared_hcd is going to be deallocated shortly (the USB core only
511 * calls this function when allocation fails in usb_add_hcd(), or
512 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
513 */
514 xhci->shared_hcd = NULL;
515 spin_unlock_irq(&xhci->lock);
496} 516}
497 517
498/* 518/*
@@ -509,7 +529,15 @@ void xhci_stop(struct usb_hcd *hcd)
509 u32 temp; 529 u32 temp;
510 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 530 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
511 531
532 if (!usb_hcd_is_primary_hcd(hcd)) {
533 xhci_only_stop_hcd(xhci->shared_hcd);
534 return;
535 }
536
512 spin_lock_irq(&xhci->lock); 537 spin_lock_irq(&xhci->lock);
538 /* Make sure the xHC is halted for a USB3 roothub
539 * (xhci_stop() could be called as part of failed init).
540 */
513 xhci_halt(xhci); 541 xhci_halt(xhci);
514 xhci_reset(xhci); 542 xhci_reset(xhci);
515 spin_unlock_irq(&xhci->lock); 543 spin_unlock_irq(&xhci->lock);
@@ -542,6 +570,8 @@ void xhci_stop(struct usb_hcd *hcd)
542 * This is called when the machine is rebooting or halting. We assume that the 570 * This is called when the machine is rebooting or halting. We assume that the
543 * machine will be powered off, and the HC's internal state will be reset. 571 * machine will be powered off, and the HC's internal state will be reset.
544 * Don't bother to free memory. 572 * Don't bother to free memory.
573 *
574 * This will only ever be called with the main usb_hcd (the USB3 roothub).
545 */ 575 */
546void xhci_shutdown(struct usb_hcd *hcd) 576void xhci_shutdown(struct usb_hcd *hcd)
547{ 577{
@@ -657,6 +687,7 @@ int xhci_suspend(struct xhci_hcd *xhci)
657 687
658 spin_lock_irq(&xhci->lock); 688 spin_lock_irq(&xhci->lock);
659 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 689 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
690 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
660 /* step 1: stop endpoint */ 691 /* step 1: stop endpoint */
661 /* skipped assuming that port suspend has done */ 692 /* skipped assuming that port suspend has done */
662 693
@@ -706,10 +737,15 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
706{ 737{
707 u32 command, temp = 0; 738 u32 command, temp = 0;
708 struct usb_hcd *hcd = xhci_to_hcd(xhci); 739 struct usb_hcd *hcd = xhci_to_hcd(xhci);
709 int old_state, retval; 740 struct usb_hcd *secondary_hcd;
741 int retval;
710 742
711 old_state = hcd->state; 743 /* Wait a bit if either of the roothubs need to settle from the
712 if (time_before(jiffies, xhci->next_statechange)) 744 * transistion into bus suspend.
745 */
746 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
747 time_before(jiffies,
748 xhci->bus_state[1].next_statechange))
713 msleep(100); 749 msleep(100);
714 750
715 spin_lock_irq(&xhci->lock); 751 spin_lock_irq(&xhci->lock);
@@ -762,16 +798,34 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
762 xhci_dbg(xhci, "xhci_stop completed - status = %x\n", 798 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
763 xhci_readl(xhci, &xhci->op_regs->status)); 799 xhci_readl(xhci, &xhci->op_regs->status));
764 800
765 xhci_dbg(xhci, "Initialize the HCD\n"); 801 /* USB core calls the PCI reinit and start functions twice:
766 retval = xhci_init(hcd); 802 * first with the primary HCD, and then with the secondary HCD.
803 * If we don't do the same, the host will never be started.
804 */
805 if (!usb_hcd_is_primary_hcd(hcd))
806 secondary_hcd = hcd;
807 else
808 secondary_hcd = xhci->shared_hcd;
809
810 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
811 retval = xhci_init(hcd->primary_hcd);
767 if (retval) 812 if (retval)
768 return retval; 813 return retval;
814 xhci_dbg(xhci, "Start the primary HCD\n");
815 retval = xhci_run(hcd->primary_hcd);
816 if (retval)
817 goto failed_restart;
769 818
770 xhci_dbg(xhci, "Start the HCD\n"); 819 xhci_dbg(xhci, "Start the secondary HCD\n");
771 retval = xhci_run(hcd); 820 retval = xhci_run(secondary_hcd);
772 if (!retval) 821 if (!retval) {
773 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 822 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
823 set_bit(HCD_FLAG_HW_ACCESSIBLE,
824 &xhci->shared_hcd->flags);
825 }
826failed_restart:
774 hcd->state = HC_STATE_SUSPENDED; 827 hcd->state = HC_STATE_SUSPENDED;
828 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
775 return retval; 829 return retval;
776 } 830 }
777 831
@@ -792,10 +846,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
792 */ 846 */
793 847
794 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 848 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
795 if (!hibernated) 849 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
796 hcd->state = old_state;
797 else
798 hcd->state = HC_STATE_SUSPENDED;
799 850
800 spin_unlock_irq(&xhci->lock); 851 spin_unlock_irq(&xhci->lock);
801 return 0; 852 return 0;
@@ -1167,13 +1218,13 @@ int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1167 if (ret || !urb->hcpriv) 1218 if (ret || !urb->hcpriv)
1168 goto done; 1219 goto done;
1169 temp = xhci_readl(xhci, &xhci->op_regs->status); 1220 temp = xhci_readl(xhci, &xhci->op_regs->status);
1170 if (temp == 0xffffffff) { 1221 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1171 xhci_dbg(xhci, "HW died, freeing TD.\n"); 1222 xhci_dbg(xhci, "HW died, freeing TD.\n");
1172 urb_priv = urb->hcpriv; 1223 urb_priv = urb->hcpriv;
1173 1224
1174 usb_hcd_unlink_urb_from_ep(hcd, urb); 1225 usb_hcd_unlink_urb_from_ep(hcd, urb);
1175 spin_unlock_irqrestore(&xhci->lock, flags); 1226 spin_unlock_irqrestore(&xhci->lock, flags);
1176 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, -ESHUTDOWN); 1227 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1177 xhci_urb_free_priv(xhci, urb_priv); 1228 xhci_urb_free_priv(xhci, urb_priv);
1178 return ret; 1229 return ret;
1179 } 1230 }
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 7f127df6dd55..711de253bc0f 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -644,6 +644,9 @@ struct xhci_ep_ctx {
644#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 644#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
645#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 645#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
646 646
647/* deq bitmasks */
648#define EP_CTX_CYCLE_MASK (1 << 0)
649
647 650
648/** 651/**
649 * struct xhci_input_control_context 652 * struct xhci_input_control_context
@@ -746,6 +749,12 @@ struct xhci_virt_ep {
746 struct timer_list stop_cmd_timer; 749 struct timer_list stop_cmd_timer;
747 int stop_cmds_pending; 750 int stop_cmds_pending;
748 struct xhci_hcd *xhci; 751 struct xhci_hcd *xhci;
752 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
753 * command. We'll need to update the ring's dequeue segment and dequeue
754 * pointer after the command completes.
755 */
756 struct xhci_segment *queued_deq_seg;
757 union xhci_trb *queued_deq_ptr;
749 /* 758 /*
750 * Sometimes the xHC can not process isochronous endpoint ring quickly 759 * Sometimes the xHC can not process isochronous endpoint ring quickly
751 * enough, and it will miss some isoc tds on the ring and generate 760 * enough, and it will miss some isoc tds on the ring and generate
@@ -1161,8 +1170,29 @@ struct s3_save {
1161 u64 erst_dequeue; 1170 u64 erst_dequeue;
1162}; 1171};
1163 1172
1173struct xhci_bus_state {
1174 unsigned long bus_suspended;
1175 unsigned long next_statechange;
1176
1177 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1178 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1179 u32 port_c_suspend;
1180 u32 suspended_ports;
1181 unsigned long resume_done[USB_MAXCHILDREN];
1182};
1183
1184static inline unsigned int hcd_index(struct usb_hcd *hcd)
1185{
1186 if (hcd->speed == HCD_USB3)
1187 return 0;
1188 else
1189 return 1;
1190}
1191
1164/* There is one ehci_hci structure per controller */ 1192/* There is one ehci_hci structure per controller */
1165struct xhci_hcd { 1193struct xhci_hcd {
1194 struct usb_hcd *main_hcd;
1195 struct usb_hcd *shared_hcd;
1166 /* glue to PCI and HCD framework */ 1196 /* glue to PCI and HCD framework */
1167 struct xhci_cap_regs __iomem *cap_regs; 1197 struct xhci_cap_regs __iomem *cap_regs;
1168 struct xhci_op_regs __iomem *op_regs; 1198 struct xhci_op_regs __iomem *op_regs;
@@ -1224,9 +1254,6 @@ struct xhci_hcd {
1224 /* Host controller watchdog timer structures */ 1254 /* Host controller watchdog timer structures */
1225 unsigned int xhc_state; 1255 unsigned int xhc_state;
1226 1256
1227 unsigned long bus_suspended;
1228 unsigned long next_statechange;
1229
1230 u32 command; 1257 u32 command;
1231 struct s3_save s3; 1258 struct s3_save s3;
1232/* Host controller is dying - not responding to commands. "I'm not dead yet!" 1259/* Host controller is dying - not responding to commands. "I'm not dead yet!"
@@ -1242,18 +1269,15 @@ struct xhci_hcd {
1242 * There are no reports of xHCI host controllers that display this issue. 1269 * There are no reports of xHCI host controllers that display this issue.
1243 */ 1270 */
1244#define XHCI_STATE_DYING (1 << 0) 1271#define XHCI_STATE_DYING (1 << 0)
1272#define XHCI_STATE_HALTED (1 << 1)
1245 /* Statistics */ 1273 /* Statistics */
1246 int noops_submitted;
1247 int noops_handled;
1248 int error_bitmask; 1274 int error_bitmask;
1249 unsigned int quirks; 1275 unsigned int quirks;
1250#define XHCI_LINK_TRB_QUIRK (1 << 0) 1276#define XHCI_LINK_TRB_QUIRK (1 << 0)
1251#define XHCI_RESET_EP_QUIRK (1 << 1) 1277#define XHCI_RESET_EP_QUIRK (1 << 1)
1252#define XHCI_NEC_HOST (1 << 2) 1278#define XHCI_NEC_HOST (1 << 2)
1253 u32 port_c_suspend[8]; /* port suspend change*/ 1279 /* There are two roothubs to keep track of bus suspend info for */
1254 u32 suspended_ports[8]; /* which ports are 1280 struct xhci_bus_state bus_state[2];
1255 suspended */
1256 unsigned long resume_done[MAX_HC_PORTS];
1257 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1281 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1258 u8 *port_array; 1282 u8 *port_array;
1259 /* Array of pointers to USB 3.0 PORTSC registers */ 1283 /* Array of pointers to USB 3.0 PORTSC registers */
@@ -1264,18 +1288,15 @@ struct xhci_hcd {
1264 unsigned int num_usb2_ports; 1288 unsigned int num_usb2_ports;
1265}; 1289};
1266 1290
1267/* For testing purposes */
1268#define NUM_TEST_NOOPS 0
1269
1270/* convert between an HCD pointer and the corresponding EHCI_HCD */ 1291/* convert between an HCD pointer and the corresponding EHCI_HCD */
1271static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1292static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1272{ 1293{
1273 return (struct xhci_hcd *) (hcd->hcd_priv); 1294 return *((struct xhci_hcd **) (hcd->hcd_priv));
1274} 1295}
1275 1296
1276static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1297static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1277{ 1298{
1278 return container_of((void *) xhci, struct usb_hcd, hcd_priv); 1299 return xhci->main_hcd;
1279} 1300}
1280 1301
1281#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 1302#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
@@ -1471,7 +1492,6 @@ struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1471 dma_addr_t suspect_dma); 1492 dma_addr_t suspect_dma);
1472int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1493int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1473void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1494void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1474void *xhci_setup_one_noop(struct xhci_hcd *xhci);
1475int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); 1495int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1476int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, 1496int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1477 u32 slot_id); 1497 u32 slot_id);
@@ -1525,7 +1545,8 @@ int xhci_bus_resume(struct usb_hcd *hcd);
1525#endif /* CONFIG_PM */ 1545#endif /* CONFIG_PM */
1526 1546
1527u32 xhci_port_state_to_neutral(u32 state); 1547u32 xhci_port_state_to_neutral(u32 state);
1528int xhci_find_slot_id_by_port(struct xhci_hcd *xhci, u16 port); 1548int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1549 u16 port);
1529void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1550void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1530 1551
1531/* xHCI contexts */ 1552/* xHCI contexts */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 07:20:09 -0500