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-rw-r--r--drivers/usb/host/xhci-mem.c21
-rw-r--r--drivers/usb/host/xhci.h175
2 files changed, 196 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 7cf15ca854be..be5a05b2021c 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -220,6 +220,12 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
220 dma_pool_destroy(xhci->segment_pool); 220 dma_pool_destroy(xhci->segment_pool);
221 xhci->segment_pool = NULL; 221 xhci->segment_pool = NULL;
222 xhci_dbg(xhci, "Freed segment pool\n"); 222 xhci_dbg(xhci, "Freed segment pool\n");
223 xhci_writel(xhci, 0, &xhci->op_regs->dcbaa_ptr[1]);
224 xhci_writel(xhci, 0, &xhci->op_regs->dcbaa_ptr[0]);
225 if (xhci->dcbaa)
226 pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
227 xhci->dcbaa, xhci->dcbaa->dma);
228 xhci->dcbaa = NULL;
223 xhci->page_size = 0; 229 xhci->page_size = 0;
224 xhci->page_shift = 0; 230 xhci->page_shift = 0;
225} 231}
@@ -263,6 +269,21 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
263 xhci_writel(xhci, val, &xhci->op_regs->config_reg); 269 xhci_writel(xhci, val, &xhci->op_regs->config_reg);
264 270
265 /* 271 /*
272 * Section 5.4.8 - doorbell array must be
273 * "physically contiguous and 64-byte (cache line) aligned".
274 */
275 xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
276 sizeof(*xhci->dcbaa), &dma);
277 if (!xhci->dcbaa)
278 goto fail;
279 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
280 xhci->dcbaa->dma = dma;
281 xhci_dbg(xhci, "// Setting device context base array address to 0x%x\n",
282 xhci->dcbaa->dma);
283 xhci_writel(xhci, (u32) 0, &xhci->op_regs->dcbaa_ptr[1]);
284 xhci_writel(xhci, dma, &xhci->op_regs->dcbaa_ptr[0]);
285
286 /*
266 * Initialize the ring segment pool. The ring must be a contiguous 287 * Initialize the ring segment pool. The ring must be a contiguous
267 * structure comprised of TRBs. The TRBs must be 16 byte aligned, 288 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
268 * however, the command ring segment needs 64-byte aligned segments, 289 * however, the command ring segment needs 64-byte aligned segments,
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index ed331310f1a8..f168fcac5999 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -436,6 +436,180 @@ struct xhci_doorbell_array {
436#define DB_MASK (0xff << 8) 436#define DB_MASK (0xff << 8)
437 437
438 438
439/**
440 * struct xhci_slot_ctx
441 * @dev_info: Route string, device speed, hub info, and last valid endpoint
442 * @dev_info2: Max exit latency for device number, root hub port number
443 * @tt_info: tt_info is used to construct split transaction tokens
444 * @dev_state: slot state and device address
445 *
446 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
447 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
448 * reserved at the end of the slot context for HC internal use.
449 */
450struct xhci_slot_ctx {
451 u32 dev_info;
452 u32 dev_info2;
453 u32 tt_info;
454 u32 dev_state;
455 /* offset 0x10 to 0x1f reserved for HC internal use */
456 u32 reserved[4];
457} __attribute__ ((packed));
458
459/* dev_info bitmasks */
460/* Route String - 0:19 */
461#define ROUTE_STRING_MASK (0xfffff)
462/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
463#define DEV_SPEED (0xf << 20)
464/* bit 24 reserved */
465/* Is this LS/FS device connected through a HS hub? - bit 25 */
466#define DEV_MTT (0x1 << 25)
467/* Set if the device is a hub - bit 26 */
468#define DEV_HUB (0x1 << 26)
469/* Index of the last valid endpoint context in this device context - 27:31 */
470#define LAST_EP_MASK (0x1f << 27)
471#define LAST_EP(p) ((p) << 27)
472
473/* dev_info2 bitmasks */
474/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
475#define MAX_EXIT (0xffff)
476/* Root hub port number that is needed to access the USB device */
477#define ROOT_HUB_PORT (0xff << 16)
478
479/* tt_info bitmasks */
480/*
481 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
482 * The Slot ID of the hub that isolates the high speed signaling from
483 * this low or full-speed device. '0' if attached to root hub port.
484 */
485#define TT_SLOT (0xff)
486/*
487 * The number of the downstream facing port of the high-speed hub
488 * '0' if the device is not low or full speed.
489 */
490#define TT_PORT (0xff << 8)
491
492/* dev_state bitmasks */
493/* USB device address - assigned by the HC */
494#define DEV_ADDR (0xff)
495/* bits 8:26 reserved */
496/* Slot state */
497#define SLOT_STATE (0x1f << 27)
498
499
500/**
501 * struct xhci_ep_ctx
502 * @ep_info: endpoint state, streams, mult, and interval information.
503 * @ep_info2: information on endpoint type, max packet size, max burst size,
504 * error count, and whether the HC will force an event for all
505 * transactions.
506 * @ep_ring: 64-bit ring address. If the endpoint only defines one flow,
507 * this points to the endpoint transfer ring. Otherwise, it points
508 * to a flow context array, which has a ring pointer for each flow.
509 * @intr_target:
510 * 64-bit address of the Interrupter Target that will receive
511 * events from this endpoint.
512 *
513 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
514 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
515 * reserved at the end of the endpoint context for HC internal use.
516 */
517struct xhci_ep_ctx {
518 u32 ep_info;
519 u32 ep_info2;
520 /* 64-bit endpoint ring address */
521 u32 ep_ring[2];
522 /* 64-bit address of the interrupter target */
523 u32 intr_target[2];
524 /* offset 0x14 - 0x1f reserved for HC internal use */
525 u32 reserved[2];
526} __attribute__ ((packed));
527
528/* ep_info bitmasks */
529/*
530 * Endpoint State - bits 0:2
531 * 0 - disabled
532 * 1 - running
533 * 2 - halted due to halt condition - ok to manipulate endpoint ring
534 * 3 - stopped
535 * 4 - TRB error
536 * 5-7 - reserved
537 */
538#define EP_STATE (0xf)
539/* Mult - Max number of burtst within an interval, in EP companion desc. */
540#define EP_MULT(p) ((p & 0x3) << 8)
541/* bits 10:14 are Max Primary Streams */
542/* bit 15 is Linear Stream Array */
543/* Interval - period between requests to an endpoint - 125u increments. */
544#define EP_INTERVAL (0xff << 16)
545
546/* ep_info2 bitmasks */
547/*
548 * Force Event - generate transfer events for all TRBs for this endpoint
549 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
550 */
551#define FORCE_EVENT (0x1)
552#define ERROR_COUNT(p) (((p) & 0x3) << 1)
553#define EP_TYPE(p) ((p) << 3)
554#define ISOC_OUT_EP 1
555#define BULK_OUT_EP 2
556#define INT_OUT_EP 3
557#define CTRL_EP 4
558#define ISOC_IN_EP 5
559#define BULK_IN_EP 6
560#define INT_IN_EP 7
561/* bit 6 reserved */
562/* bit 7 is Host Initiate Disable - for disabling stream selection */
563#define MAX_BURST(p) (((p)&0xff) << 8)
564#define MAX_PACKET(p) (((p)&0xffff) << 16)
565
566
567/**
568 * struct xhci_device_control
569 * Input/Output context; see section 6.2.5.
570 *
571 * @drop_context: set the bit of the endpoint context you want to disable
572 * @add_context: set the bit of the endpoint context you want to enable
573 */
574struct xhci_device_control {
575 u32 drop_flags;
576 u32 add_flags;
577 u32 rsvd[6];
578 struct xhci_slot_ctx slot;
579 struct xhci_ep_ctx ep[31];
580} __attribute__ ((packed));
581
582/* drop context bitmasks */
583#define DROP_EP(x) (0x1 << x)
584/* add context bitmasks */
585#define ADD_EP(x) (0x1 << x)
586
587
588/**
589 * struct xhci_device_context_array
590 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
591 */
592struct xhci_device_context_array {
593 /* 64-bit device addresses; we only write 32-bit addresses */
594 u32 dev_context_ptrs[2*MAX_HC_SLOTS];
595 /* private xHCD pointers */
596 dma_addr_t dma;
597} __attribute__ ((packed));
598/* TODO: write function to set the 64-bit device DMA address */
599/*
600 * TODO: change this to be dynamically sized at HC mem init time since the HC
601 * might not be able to handle the maximum number of devices possible.
602 */
603
604
605struct xhci_stream_ctx {
606 /* 64-bit stream ring address, cycle state, and stream type */
607 u32 stream_ring[2];
608 /* offset 0x14 - 0x1f reserved for HC internal use */
609 u32 reserved[2];
610} __attribute__ ((packed));
611
612
439struct xhci_transfer_event { 613struct xhci_transfer_event {
440 /* 64-bit buffer address, or immediate data */ 614 /* 64-bit buffer address, or immediate data */
441 u32 buffer[2]; 615 u32 buffer[2];
@@ -725,6 +899,7 @@ struct xhci_hcd {
725 int msix_count; 899 int msix_count;
726 struct msix_entry *msix_entries; 900 struct msix_entry *msix_entries;
727 /* data structures */ 901 /* data structures */
902 struct xhci_device_context_array *dcbaa;
728 struct xhci_ring *cmd_ring; 903 struct xhci_ring *cmd_ring;
729 struct xhci_ring *event_ring; 904 struct xhci_ring *event_ring;
730 struct xhci_erst erst; 905 struct xhci_erst erst;