diff options
Diffstat (limited to 'drivers/usb/host/xhci.h')
-rw-r--r-- | drivers/usb/host/xhci.h | 41 |
1 files changed, 29 insertions, 12 deletions
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index f8416639bf31..58ed9d088e63 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h | |||
@@ -28,17 +28,6 @@ | |||
28 | #include <linux/kernel.h> | 28 | #include <linux/kernel.h> |
29 | #include <linux/usb/hcd.h> | 29 | #include <linux/usb/hcd.h> |
30 | 30 | ||
31 | /* | ||
32 | * Registers should always be accessed with double word or quad word accesses. | ||
33 | * | ||
34 | * Some xHCI implementations may support 64-bit address pointers. Registers | ||
35 | * with 64-bit address pointers should be written to with dword accesses by | ||
36 | * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. | ||
37 | * xHCI implementations that do not support 64-bit address pointers will ignore | ||
38 | * the high dword, and write order is irrelevant. | ||
39 | */ | ||
40 | #include <asm-generic/io-64-nonatomic-lo-hi.h> | ||
41 | |||
42 | /* Code sharing between pci-quirks and xhci hcd */ | 31 | /* Code sharing between pci-quirks and xhci hcd */ |
43 | #include "xhci-ext-caps.h" | 32 | #include "xhci-ext-caps.h" |
44 | #include "pci-quirks.h" | 33 | #include "pci-quirks.h" |
@@ -1279,7 +1268,7 @@ union xhci_trb { | |||
1279 | * since the command ring is 64-byte aligned. | 1268 | * since the command ring is 64-byte aligned. |
1280 | * It must also be greater than 16. | 1269 | * It must also be greater than 16. |
1281 | */ | 1270 | */ |
1282 | #define TRBS_PER_SEGMENT 256 | 1271 | #define TRBS_PER_SEGMENT 64 |
1283 | /* Allow two commands + a link TRB, along with any reserved command TRBs */ | 1272 | /* Allow two commands + a link TRB, along with any reserved command TRBs */ |
1284 | #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) | 1273 | #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) |
1285 | #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) | 1274 | #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) |
@@ -1614,6 +1603,34 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) | |||
1614 | #define xhci_warn_ratelimited(xhci, fmt, args...) \ | 1603 | #define xhci_warn_ratelimited(xhci, fmt, args...) \ |
1615 | dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | 1604 | dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
1616 | 1605 | ||
1606 | /* | ||
1607 | * Registers should always be accessed with double word or quad word accesses. | ||
1608 | * | ||
1609 | * Some xHCI implementations may support 64-bit address pointers. Registers | ||
1610 | * with 64-bit address pointers should be written to with dword accesses by | ||
1611 | * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. | ||
1612 | * xHCI implementations that do not support 64-bit address pointers will ignore | ||
1613 | * the high dword, and write order is irrelevant. | ||
1614 | */ | ||
1615 | static inline u64 xhci_read_64(const struct xhci_hcd *xhci, | ||
1616 | __le64 __iomem *regs) | ||
1617 | { | ||
1618 | __u32 __iomem *ptr = (__u32 __iomem *) regs; | ||
1619 | u64 val_lo = readl(ptr); | ||
1620 | u64 val_hi = readl(ptr + 1); | ||
1621 | return val_lo + (val_hi << 32); | ||
1622 | } | ||
1623 | static inline void xhci_write_64(struct xhci_hcd *xhci, | ||
1624 | const u64 val, __le64 __iomem *regs) | ||
1625 | { | ||
1626 | __u32 __iomem *ptr = (__u32 __iomem *) regs; | ||
1627 | u32 val_lo = lower_32_bits(val); | ||
1628 | u32 val_hi = upper_32_bits(val); | ||
1629 | |||
1630 | writel(val_lo, ptr); | ||
1631 | writel(val_hi, ptr + 1); | ||
1632 | } | ||
1633 | |||
1617 | static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) | 1634 | static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) |
1618 | { | 1635 | { |
1619 | return xhci->quirks & XHCI_LINK_TRB_QUIRK; | 1636 | return xhci->quirks & XHCI_LINK_TRB_QUIRK; |