diff options
Diffstat (limited to 'drivers/usb/host/xhci.c')
-rw-r--r-- | drivers/usb/host/xhci.c | 203 |
1 files changed, 111 insertions, 92 deletions
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 4265b48856f6..924a6ccdb622 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c | |||
@@ -40,6 +40,10 @@ static int link_quirk; | |||
40 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); | 40 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); |
41 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); | 41 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); |
42 | 42 | ||
43 | static unsigned int quirks; | ||
44 | module_param(quirks, uint, S_IRUGO); | ||
45 | MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); | ||
46 | |||
43 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ | 47 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ |
44 | /* | 48 | /* |
45 | * xhci_handshake - spin reading hc until handshake completes or fails | 49 | * xhci_handshake - spin reading hc until handshake completes or fails |
@@ -60,7 +64,7 @@ int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr, | |||
60 | u32 result; | 64 | u32 result; |
61 | 65 | ||
62 | do { | 66 | do { |
63 | result = xhci_readl(xhci, ptr); | 67 | result = readl(ptr); |
64 | if (result == ~(u32)0) /* card removed */ | 68 | if (result == ~(u32)0) /* card removed */ |
65 | return -ENODEV; | 69 | return -ENODEV; |
66 | result &= mask; | 70 | result &= mask; |
@@ -82,13 +86,13 @@ void xhci_quiesce(struct xhci_hcd *xhci) | |||
82 | u32 mask; | 86 | u32 mask; |
83 | 87 | ||
84 | mask = ~(XHCI_IRQS); | 88 | mask = ~(XHCI_IRQS); |
85 | halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT; | 89 | halted = readl(&xhci->op_regs->status) & STS_HALT; |
86 | if (!halted) | 90 | if (!halted) |
87 | mask &= ~CMD_RUN; | 91 | mask &= ~CMD_RUN; |
88 | 92 | ||
89 | cmd = xhci_readl(xhci, &xhci->op_regs->command); | 93 | cmd = readl(&xhci->op_regs->command); |
90 | cmd &= mask; | 94 | cmd &= mask; |
91 | xhci_writel(xhci, cmd, &xhci->op_regs->command); | 95 | writel(cmd, &xhci->op_regs->command); |
92 | } | 96 | } |
93 | 97 | ||
94 | /* | 98 | /* |
@@ -124,11 +128,11 @@ static int xhci_start(struct xhci_hcd *xhci) | |||
124 | u32 temp; | 128 | u32 temp; |
125 | int ret; | 129 | int ret; |
126 | 130 | ||
127 | temp = xhci_readl(xhci, &xhci->op_regs->command); | 131 | temp = readl(&xhci->op_regs->command); |
128 | temp |= (CMD_RUN); | 132 | temp |= (CMD_RUN); |
129 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", | 133 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
130 | temp); | 134 | temp); |
131 | xhci_writel(xhci, temp, &xhci->op_regs->command); | 135 | writel(temp, &xhci->op_regs->command); |
132 | 136 | ||
133 | /* | 137 | /* |
134 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | 138 | * Wait for the HCHalted Status bit to be 0 to indicate the host is |
@@ -158,16 +162,16 @@ int xhci_reset(struct xhci_hcd *xhci) | |||
158 | u32 state; | 162 | u32 state; |
159 | int ret, i; | 163 | int ret, i; |
160 | 164 | ||
161 | state = xhci_readl(xhci, &xhci->op_regs->status); | 165 | state = readl(&xhci->op_regs->status); |
162 | if ((state & STS_HALT) == 0) { | 166 | if ((state & STS_HALT) == 0) { |
163 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); | 167 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); |
164 | return 0; | 168 | return 0; |
165 | } | 169 | } |
166 | 170 | ||
167 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); | 171 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
168 | command = xhci_readl(xhci, &xhci->op_regs->command); | 172 | command = readl(&xhci->op_regs->command); |
169 | command |= CMD_RESET; | 173 | command |= CMD_RESET; |
170 | xhci_writel(xhci, command, &xhci->op_regs->command); | 174 | writel(command, &xhci->op_regs->command); |
171 | 175 | ||
172 | ret = xhci_handshake(xhci, &xhci->op_regs->command, | 176 | ret = xhci_handshake(xhci, &xhci->op_regs->command, |
173 | CMD_RESET, 0, 10 * 1000 * 1000); | 177 | CMD_RESET, 0, 10 * 1000 * 1000); |
@@ -321,6 +325,9 @@ static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |||
321 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | 325 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
322 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | 326 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
323 | 327 | ||
328 | if (xhci->quirks & XHCI_PLAT) | ||
329 | return; | ||
330 | |||
324 | xhci_free_irq(xhci); | 331 | xhci_free_irq(xhci); |
325 | 332 | ||
326 | if (xhci->msix_entries) { | 333 | if (xhci->msix_entries) { |
@@ -422,7 +429,7 @@ static void compliance_mode_recovery(unsigned long arg) | |||
422 | xhci = (struct xhci_hcd *)arg; | 429 | xhci = (struct xhci_hcd *)arg; |
423 | 430 | ||
424 | for (i = 0; i < xhci->num_usb3_ports; i++) { | 431 | for (i = 0; i < xhci->num_usb3_ports; i++) { |
425 | temp = xhci_readl(xhci, xhci->usb3_ports[i]); | 432 | temp = readl(xhci->usb3_ports[i]); |
426 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { | 433 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { |
427 | /* | 434 | /* |
428 | * Compliance Mode Detected. Letting USB Core | 435 | * Compliance Mode Detected. Letting USB Core |
@@ -611,24 +618,23 @@ int xhci_run(struct usb_hcd *hcd) | |||
611 | 618 | ||
612 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 619 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
613 | "// Set the interrupt modulation register"); | 620 | "// Set the interrupt modulation register"); |
614 | temp = xhci_readl(xhci, &xhci->ir_set->irq_control); | 621 | temp = readl(&xhci->ir_set->irq_control); |
615 | temp &= ~ER_IRQ_INTERVAL_MASK; | 622 | temp &= ~ER_IRQ_INTERVAL_MASK; |
616 | temp |= (u32) 160; | 623 | temp |= (u32) 160; |
617 | xhci_writel(xhci, temp, &xhci->ir_set->irq_control); | 624 | writel(temp, &xhci->ir_set->irq_control); |
618 | 625 | ||
619 | /* Set the HCD state before we enable the irqs */ | 626 | /* Set the HCD state before we enable the irqs */ |
620 | temp = xhci_readl(xhci, &xhci->op_regs->command); | 627 | temp = readl(&xhci->op_regs->command); |
621 | temp |= (CMD_EIE); | 628 | temp |= (CMD_EIE); |
622 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 629 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
623 | "// Enable interrupts, cmd = 0x%x.", temp); | 630 | "// Enable interrupts, cmd = 0x%x.", temp); |
624 | xhci_writel(xhci, temp, &xhci->op_regs->command); | 631 | writel(temp, &xhci->op_regs->command); |
625 | 632 | ||
626 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | 633 | temp = readl(&xhci->ir_set->irq_pending); |
627 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 634 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
628 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | 635 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", |
629 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); | 636 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
630 | xhci_writel(xhci, ER_IRQ_ENABLE(temp), | 637 | writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); |
631 | &xhci->ir_set->irq_pending); | ||
632 | xhci_print_ir_set(xhci, 0); | 638 | xhci_print_ir_set(xhci, 0); |
633 | 639 | ||
634 | if (xhci->quirks & XHCI_NEC_HOST) | 640 | if (xhci->quirks & XHCI_NEC_HOST) |
@@ -698,18 +704,17 @@ void xhci_stop(struct usb_hcd *hcd) | |||
698 | 704 | ||
699 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 705 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
700 | "// Disabling event ring interrupts"); | 706 | "// Disabling event ring interrupts"); |
701 | temp = xhci_readl(xhci, &xhci->op_regs->status); | 707 | temp = readl(&xhci->op_regs->status); |
702 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | 708 | writel(temp & ~STS_EINT, &xhci->op_regs->status); |
703 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | 709 | temp = readl(&xhci->ir_set->irq_pending); |
704 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | 710 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
705 | &xhci->ir_set->irq_pending); | ||
706 | xhci_print_ir_set(xhci, 0); | 711 | xhci_print_ir_set(xhci, 0); |
707 | 712 | ||
708 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); | 713 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
709 | xhci_mem_cleanup(xhci); | 714 | xhci_mem_cleanup(xhci); |
710 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 715 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
711 | "xhci_stop completed - status = %x", | 716 | "xhci_stop completed - status = %x", |
712 | xhci_readl(xhci, &xhci->op_regs->status)); | 717 | readl(&xhci->op_regs->status)); |
713 | } | 718 | } |
714 | 719 | ||
715 | /* | 720 | /* |
@@ -739,7 +744,7 @@ void xhci_shutdown(struct usb_hcd *hcd) | |||
739 | 744 | ||
740 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 745 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
741 | "xhci_shutdown completed - status = %x", | 746 | "xhci_shutdown completed - status = %x", |
742 | xhci_readl(xhci, &xhci->op_regs->status)); | 747 | readl(&xhci->op_regs->status)); |
743 | 748 | ||
744 | /* Yet another workaround for spurious wakeups at shutdown with HSW */ | 749 | /* Yet another workaround for spurious wakeups at shutdown with HSW */ |
745 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | 750 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) |
@@ -749,28 +754,28 @@ void xhci_shutdown(struct usb_hcd *hcd) | |||
749 | #ifdef CONFIG_PM | 754 | #ifdef CONFIG_PM |
750 | static void xhci_save_registers(struct xhci_hcd *xhci) | 755 | static void xhci_save_registers(struct xhci_hcd *xhci) |
751 | { | 756 | { |
752 | xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command); | 757 | xhci->s3.command = readl(&xhci->op_regs->command); |
753 | xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification); | 758 | xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); |
754 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); | 759 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
755 | xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg); | 760 | xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); |
756 | xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size); | 761 | xhci->s3.erst_size = readl(&xhci->ir_set->erst_size); |
757 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); | 762 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
758 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | 763 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
759 | xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); | 764 | xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending); |
760 | xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control); | 765 | xhci->s3.irq_control = readl(&xhci->ir_set->irq_control); |
761 | } | 766 | } |
762 | 767 | ||
763 | static void xhci_restore_registers(struct xhci_hcd *xhci) | 768 | static void xhci_restore_registers(struct xhci_hcd *xhci) |
764 | { | 769 | { |
765 | xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command); | 770 | writel(xhci->s3.command, &xhci->op_regs->command); |
766 | xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | 771 | writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); |
767 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); | 772 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); |
768 | xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg); | 773 | writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); |
769 | xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size); | 774 | writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); |
770 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); | 775 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); |
771 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); | 776 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); |
772 | xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending); | 777 | writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
773 | xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control); | 778 | writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); |
774 | } | 779 | } |
775 | 780 | ||
776 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) | 781 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
@@ -866,9 +871,9 @@ int xhci_suspend(struct xhci_hcd *xhci) | |||
866 | /* skipped assuming that port suspend has done */ | 871 | /* skipped assuming that port suspend has done */ |
867 | 872 | ||
868 | /* step 2: clear Run/Stop bit */ | 873 | /* step 2: clear Run/Stop bit */ |
869 | command = xhci_readl(xhci, &xhci->op_regs->command); | 874 | command = readl(&xhci->op_regs->command); |
870 | command &= ~CMD_RUN; | 875 | command &= ~CMD_RUN; |
871 | xhci_writel(xhci, command, &xhci->op_regs->command); | 876 | writel(command, &xhci->op_regs->command); |
872 | 877 | ||
873 | /* Some chips from Fresco Logic need an extraordinary delay */ | 878 | /* Some chips from Fresco Logic need an extraordinary delay */ |
874 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; | 879 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; |
@@ -885,9 +890,9 @@ int xhci_suspend(struct xhci_hcd *xhci) | |||
885 | xhci_save_registers(xhci); | 890 | xhci_save_registers(xhci); |
886 | 891 | ||
887 | /* step 4: set CSS flag */ | 892 | /* step 4: set CSS flag */ |
888 | command = xhci_readl(xhci, &xhci->op_regs->command); | 893 | command = readl(&xhci->op_regs->command); |
889 | command |= CMD_CSS; | 894 | command |= CMD_CSS; |
890 | xhci_writel(xhci, command, &xhci->op_regs->command); | 895 | writel(command, &xhci->op_regs->command); |
891 | if (xhci_handshake(xhci, &xhci->op_regs->status, | 896 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
892 | STS_SAVE, 0, 10 * 1000)) { | 897 | STS_SAVE, 0, 10 * 1000)) { |
893 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); | 898 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); |
@@ -951,16 +956,16 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
951 | xhci_set_cmd_ring_deq(xhci); | 956 | xhci_set_cmd_ring_deq(xhci); |
952 | /* step 3: restore state and start state*/ | 957 | /* step 3: restore state and start state*/ |
953 | /* step 3: set CRS flag */ | 958 | /* step 3: set CRS flag */ |
954 | command = xhci_readl(xhci, &xhci->op_regs->command); | 959 | command = readl(&xhci->op_regs->command); |
955 | command |= CMD_CRS; | 960 | command |= CMD_CRS; |
956 | xhci_writel(xhci, command, &xhci->op_regs->command); | 961 | writel(command, &xhci->op_regs->command); |
957 | if (xhci_handshake(xhci, &xhci->op_regs->status, | 962 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
958 | STS_RESTORE, 0, 10 * 1000)) { | 963 | STS_RESTORE, 0, 10 * 1000)) { |
959 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); | 964 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); |
960 | spin_unlock_irq(&xhci->lock); | 965 | spin_unlock_irq(&xhci->lock); |
961 | return -ETIMEDOUT; | 966 | return -ETIMEDOUT; |
962 | } | 967 | } |
963 | temp = xhci_readl(xhci, &xhci->op_regs->status); | 968 | temp = readl(&xhci->op_regs->status); |
964 | } | 969 | } |
965 | 970 | ||
966 | /* If restore operation fails, re-initialize the HC during resume */ | 971 | /* If restore operation fails, re-initialize the HC during resume */ |
@@ -984,17 +989,16 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
984 | xhci_cleanup_msix(xhci); | 989 | xhci_cleanup_msix(xhci); |
985 | 990 | ||
986 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); | 991 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
987 | temp = xhci_readl(xhci, &xhci->op_regs->status); | 992 | temp = readl(&xhci->op_regs->status); |
988 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | 993 | writel(temp & ~STS_EINT, &xhci->op_regs->status); |
989 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | 994 | temp = readl(&xhci->ir_set->irq_pending); |
990 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | 995 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
991 | &xhci->ir_set->irq_pending); | ||
992 | xhci_print_ir_set(xhci, 0); | 996 | xhci_print_ir_set(xhci, 0); |
993 | 997 | ||
994 | xhci_dbg(xhci, "cleaning up memory\n"); | 998 | xhci_dbg(xhci, "cleaning up memory\n"); |
995 | xhci_mem_cleanup(xhci); | 999 | xhci_mem_cleanup(xhci); |
996 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", | 1000 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", |
997 | xhci_readl(xhci, &xhci->op_regs->status)); | 1001 | readl(&xhci->op_regs->status)); |
998 | 1002 | ||
999 | /* USB core calls the PCI reinit and start functions twice: | 1003 | /* USB core calls the PCI reinit and start functions twice: |
1000 | * first with the primary HCD, and then with the secondary HCD. | 1004 | * first with the primary HCD, and then with the secondary HCD. |
@@ -1023,9 +1027,9 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
1023 | } | 1027 | } |
1024 | 1028 | ||
1025 | /* step 4: set Run/Stop bit */ | 1029 | /* step 4: set Run/Stop bit */ |
1026 | command = xhci_readl(xhci, &xhci->op_regs->command); | 1030 | command = readl(&xhci->op_regs->command); |
1027 | command |= CMD_RUN; | 1031 | command |= CMD_RUN; |
1028 | xhci_writel(xhci, command, &xhci->op_regs->command); | 1032 | writel(command, &xhci->op_regs->command); |
1029 | xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, | 1033 | xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, |
1030 | 0, 250 * 1000); | 1034 | 0, 250 * 1000); |
1031 | 1035 | ||
@@ -1464,7 +1468,7 @@ int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |||
1464 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | 1468 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); |
1465 | if (ret || !urb->hcpriv) | 1469 | if (ret || !urb->hcpriv) |
1466 | goto done; | 1470 | goto done; |
1467 | temp = xhci_readl(xhci, &xhci->op_regs->status); | 1471 | temp = readl(&xhci->op_regs->status); |
1468 | if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { | 1472 | if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { |
1469 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | 1473 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1470 | "HW died, freeing TD."); | 1474 | "HW died, freeing TD."); |
@@ -1892,8 +1896,8 @@ static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, | |||
1892 | * (bit 1). The default control endpoint is added during the Address | 1896 | * (bit 1). The default control endpoint is added during the Address |
1893 | * Device command and is never removed until the slot is disabled. | 1897 | * Device command and is never removed until the slot is disabled. |
1894 | */ | 1898 | */ |
1895 | valid_add_flags = ctrl_ctx->add_flags >> 2; | 1899 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1896 | valid_drop_flags = ctrl_ctx->drop_flags >> 2; | 1900 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; |
1897 | 1901 | ||
1898 | /* Use hweight32 to count the number of ones in the add flags, or | 1902 | /* Use hweight32 to count the number of ones in the add flags, or |
1899 | * number of endpoints added. Don't count endpoints that are changed | 1903 | * number of endpoints added. Don't count endpoints that are changed |
@@ -1909,8 +1913,8 @@ static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | |||
1909 | u32 valid_add_flags; | 1913 | u32 valid_add_flags; |
1910 | u32 valid_drop_flags; | 1914 | u32 valid_drop_flags; |
1911 | 1915 | ||
1912 | valid_add_flags = ctrl_ctx->add_flags >> 2; | 1916 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1913 | valid_drop_flags = ctrl_ctx->drop_flags >> 2; | 1917 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; |
1914 | 1918 | ||
1915 | return hweight32(valid_drop_flags) - | 1919 | return hweight32(valid_drop_flags) - |
1916 | hweight32(valid_add_flags & valid_drop_flags); | 1920 | hweight32(valid_add_flags & valid_drop_flags); |
@@ -3585,7 +3589,7 @@ void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |||
3585 | 3589 | ||
3586 | spin_lock_irqsave(&xhci->lock, flags); | 3590 | spin_lock_irqsave(&xhci->lock, flags); |
3587 | /* Don't disable the slot if the host controller is dead. */ | 3591 | /* Don't disable the slot if the host controller is dead. */ |
3588 | state = xhci_readl(xhci, &xhci->op_regs->status); | 3592 | state = readl(&xhci->op_regs->status); |
3589 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || | 3593 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || |
3590 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | 3594 | (xhci->xhc_state & XHCI_STATE_HALTED)) { |
3591 | xhci_free_virt_device(xhci, udev->slot_id); | 3595 | xhci_free_virt_device(xhci, udev->slot_id); |
@@ -3712,13 +3716,15 @@ disable_slot: | |||
3712 | } | 3716 | } |
3713 | 3717 | ||
3714 | /* | 3718 | /* |
3715 | * Issue an Address Device command (which will issue a SetAddress request to | 3719 | * Issue an Address Device command and optionally send a corresponding |
3716 | * the device). | 3720 | * SetAddress request to the device. |
3717 | * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so | 3721 | * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so |
3718 | * we should only issue and wait on one address command at the same time. | 3722 | * we should only issue and wait on one address command at the same time. |
3719 | */ | 3723 | */ |
3720 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | 3724 | static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, |
3725 | enum xhci_setup_dev setup) | ||
3721 | { | 3726 | { |
3727 | const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address"; | ||
3722 | unsigned long flags; | 3728 | unsigned long flags; |
3723 | int timeleft; | 3729 | int timeleft; |
3724 | struct xhci_virt_device *virt_dev; | 3730 | struct xhci_virt_device *virt_dev; |
@@ -3771,12 +3777,12 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
3771 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); | 3777 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
3772 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); | 3778 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
3773 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, | 3779 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
3774 | slot_ctx->dev_info >> 27); | 3780 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3775 | 3781 | ||
3776 | spin_lock_irqsave(&xhci->lock, flags); | 3782 | spin_lock_irqsave(&xhci->lock, flags); |
3777 | cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring); | 3783 | cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring); |
3778 | ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma, | 3784 | ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma, |
3779 | udev->slot_id); | 3785 | udev->slot_id, setup); |
3780 | if (ret) { | 3786 | if (ret) { |
3781 | spin_unlock_irqrestore(&xhci->lock, flags); | 3787 | spin_unlock_irqrestore(&xhci->lock, flags); |
3782 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | 3788 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
@@ -3794,8 +3800,8 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
3794 | * command on a timeout. | 3800 | * command on a timeout. |
3795 | */ | 3801 | */ |
3796 | if (timeleft <= 0) { | 3802 | if (timeleft <= 0) { |
3797 | xhci_warn(xhci, "%s while waiting for address device command\n", | 3803 | xhci_warn(xhci, "%s while waiting for setup %s command\n", |
3798 | timeleft == 0 ? "Timeout" : "Signal"); | 3804 | timeleft == 0 ? "Timeout" : "Signal", act); |
3799 | /* cancel the address device command */ | 3805 | /* cancel the address device command */ |
3800 | ret = xhci_cancel_cmd(xhci, NULL, cmd_trb); | 3806 | ret = xhci_cancel_cmd(xhci, NULL, cmd_trb); |
3801 | if (ret < 0) | 3807 | if (ret < 0) |
@@ -3806,26 +3812,27 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
3806 | switch (virt_dev->cmd_status) { | 3812 | switch (virt_dev->cmd_status) { |
3807 | case COMP_CTX_STATE: | 3813 | case COMP_CTX_STATE: |
3808 | case COMP_EBADSLT: | 3814 | case COMP_EBADSLT: |
3809 | xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n", | 3815 | xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n", |
3810 | udev->slot_id); | 3816 | act, udev->slot_id); |
3811 | ret = -EINVAL; | 3817 | ret = -EINVAL; |
3812 | break; | 3818 | break; |
3813 | case COMP_TX_ERR: | 3819 | case COMP_TX_ERR: |
3814 | dev_warn(&udev->dev, "Device not responding to set address.\n"); | 3820 | dev_warn(&udev->dev, "Device not responding to setup %s.\n", act); |
3815 | ret = -EPROTO; | 3821 | ret = -EPROTO; |
3816 | break; | 3822 | break; |
3817 | case COMP_DEV_ERR: | 3823 | case COMP_DEV_ERR: |
3818 | dev_warn(&udev->dev, "ERROR: Incompatible device for address " | 3824 | dev_warn(&udev->dev, |
3819 | "device command.\n"); | 3825 | "ERROR: Incompatible device for setup %s command\n", act); |
3820 | ret = -ENODEV; | 3826 | ret = -ENODEV; |
3821 | break; | 3827 | break; |
3822 | case COMP_SUCCESS: | 3828 | case COMP_SUCCESS: |
3823 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | 3829 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3824 | "Successful Address Device command"); | 3830 | "Successful setup %s command", act); |
3825 | break; | 3831 | break; |
3826 | default: | 3832 | default: |
3827 | xhci_err(xhci, "ERROR: unexpected command completion " | 3833 | xhci_err(xhci, |
3828 | "code 0x%x.\n", virt_dev->cmd_status); | 3834 | "ERROR: unexpected setup %s command completion code 0x%x.\n", |
3835 | act, virt_dev->cmd_status); | ||
3829 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); | 3836 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
3830 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); | 3837 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
3831 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); | 3838 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); |
@@ -3850,7 +3857,7 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
3850 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); | 3857 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
3851 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); | 3858 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
3852 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, | 3859 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
3853 | slot_ctx->dev_info >> 27); | 3860 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3854 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); | 3861 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
3855 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); | 3862 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
3856 | /* | 3863 | /* |
@@ -3859,7 +3866,7 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
3859 | */ | 3866 | */ |
3860 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | 3867 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
3861 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, | 3868 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, |
3862 | slot_ctx->dev_info >> 27); | 3869 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3863 | /* Zero the input context control for later use */ | 3870 | /* Zero the input context control for later use */ |
3864 | ctrl_ctx->add_flags = 0; | 3871 | ctrl_ctx->add_flags = 0; |
3865 | ctrl_ctx->drop_flags = 0; | 3872 | ctrl_ctx->drop_flags = 0; |
@@ -3871,6 +3878,16 @@ int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |||
3871 | return 0; | 3878 | return 0; |
3872 | } | 3879 | } |
3873 | 3880 | ||
3881 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | ||
3882 | { | ||
3883 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS); | ||
3884 | } | ||
3885 | |||
3886 | int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) | ||
3887 | { | ||
3888 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY); | ||
3889 | } | ||
3890 | |||
3874 | /* | 3891 | /* |
3875 | * Transfer the port index into real index in the HW port status | 3892 | * Transfer the port index into real index in the HW port status |
3876 | * registers. Caculate offset between the port's PORTSC register | 3893 | * registers. Caculate offset between the port's PORTSC register |
@@ -4042,7 +4059,7 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, | |||
4042 | port_array = xhci->usb2_ports; | 4059 | port_array = xhci->usb2_ports; |
4043 | port_num = udev->portnum - 1; | 4060 | port_num = udev->portnum - 1; |
4044 | pm_addr = port_array[port_num] + PORTPMSC; | 4061 | pm_addr = port_array[port_num] + PORTPMSC; |
4045 | pm_val = xhci_readl(xhci, pm_addr); | 4062 | pm_val = readl(pm_addr); |
4046 | hlpm_addr = port_array[port_num] + PORTHLPMC; | 4063 | hlpm_addr = port_array[port_num] + PORTHLPMC; |
4047 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | 4064 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); |
4048 | 4065 | ||
@@ -4082,26 +4099,26 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, | |||
4082 | spin_lock_irqsave(&xhci->lock, flags); | 4099 | spin_lock_irqsave(&xhci->lock, flags); |
4083 | 4100 | ||
4084 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | 4101 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); |
4085 | xhci_writel(xhci, hlpm_val, hlpm_addr); | 4102 | writel(hlpm_val, hlpm_addr); |
4086 | /* flush write */ | 4103 | /* flush write */ |
4087 | xhci_readl(xhci, hlpm_addr); | 4104 | readl(hlpm_addr); |
4088 | } else { | 4105 | } else { |
4089 | hird = xhci_calculate_hird_besl(xhci, udev); | 4106 | hird = xhci_calculate_hird_besl(xhci, udev); |
4090 | } | 4107 | } |
4091 | 4108 | ||
4092 | pm_val &= ~PORT_HIRD_MASK; | 4109 | pm_val &= ~PORT_HIRD_MASK; |
4093 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); | 4110 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); |
4094 | xhci_writel(xhci, pm_val, pm_addr); | 4111 | writel(pm_val, pm_addr); |
4095 | pm_val = xhci_readl(xhci, pm_addr); | 4112 | pm_val = readl(pm_addr); |
4096 | pm_val |= PORT_HLE; | 4113 | pm_val |= PORT_HLE; |
4097 | xhci_writel(xhci, pm_val, pm_addr); | 4114 | writel(pm_val, pm_addr); |
4098 | /* flush write */ | 4115 | /* flush write */ |
4099 | xhci_readl(xhci, pm_addr); | 4116 | readl(pm_addr); |
4100 | } else { | 4117 | } else { |
4101 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); | 4118 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); |
4102 | xhci_writel(xhci, pm_val, pm_addr); | 4119 | writel(pm_val, pm_addr); |
4103 | /* flush write */ | 4120 | /* flush write */ |
4104 | xhci_readl(xhci, pm_addr); | 4121 | readl(pm_addr); |
4105 | if (udev->usb2_hw_lpm_besl_capable) { | 4122 | if (udev->usb2_hw_lpm_besl_capable) { |
4106 | spin_unlock_irqrestore(&xhci->lock, flags); | 4123 | spin_unlock_irqrestore(&xhci->lock, flags); |
4107 | mutex_lock(hcd->bandwidth_mutex); | 4124 | mutex_lock(hcd->bandwidth_mutex); |
@@ -4455,7 +4472,7 @@ static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd, | |||
4455 | if (!config) | 4472 | if (!config) |
4456 | return timeout; | 4473 | return timeout; |
4457 | 4474 | ||
4458 | for (i = 0; i < USB_MAXINTERFACES; i++) { | 4475 | for (i = 0; i < config->desc.bNumInterfaces; i++) { |
4459 | struct usb_driver *driver; | 4476 | struct usb_driver *driver; |
4460 | struct usb_interface *intf = config->interface[i]; | 4477 | struct usb_interface *intf = config->interface[i]; |
4461 | 4478 | ||
@@ -4704,7 +4721,7 @@ int xhci_get_frame(struct usb_hcd *hcd) | |||
4704 | { | 4721 | { |
4705 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | 4722 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
4706 | /* EHCI mods by the periodic size. Why? */ | 4723 | /* EHCI mods by the periodic size. Why? */ |
4707 | return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3; | 4724 | return readl(&xhci->run_regs->microframe_index) >> 3; |
4708 | } | 4725 | } |
4709 | 4726 | ||
4710 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) | 4727 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
@@ -4748,18 +4765,20 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) | |||
4748 | 4765 | ||
4749 | xhci->cap_regs = hcd->regs; | 4766 | xhci->cap_regs = hcd->regs; |
4750 | xhci->op_regs = hcd->regs + | 4767 | xhci->op_regs = hcd->regs + |
4751 | HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase)); | 4768 | HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)); |
4752 | xhci->run_regs = hcd->regs + | 4769 | xhci->run_regs = hcd->regs + |
4753 | (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK); | 4770 | (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK); |
4754 | /* Cache read-only capability registers */ | 4771 | /* Cache read-only capability registers */ |
4755 | xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1); | 4772 | xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1); |
4756 | xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2); | 4773 | xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2); |
4757 | xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); | 4774 | xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3); |
4758 | xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); | 4775 | xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase); |
4759 | xhci->hci_version = HC_VERSION(xhci->hcc_params); | 4776 | xhci->hci_version = HC_VERSION(xhci->hcc_params); |
4760 | xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | 4777 | xhci->hcc_params = readl(&xhci->cap_regs->hcc_params); |
4761 | xhci_print_registers(xhci); | 4778 | xhci_print_registers(xhci); |
4762 | 4779 | ||
4780 | xhci->quirks = quirks; | ||
4781 | |||
4763 | get_quirks(dev, xhci); | 4782 | get_quirks(dev, xhci); |
4764 | 4783 | ||
4765 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious | 4784 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious |