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path: root/drivers/usb/host/xhci-mem.c
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Diffstat (limited to 'drivers/usb/host/xhci-mem.c')
-rw-r--r--drivers/usb/host/xhci-mem.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 4b87026f8a5a..bce4391a0e7d 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -1958,7 +1958,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1958 xhci_warn(xhci, "WARN something wrong with SW event ring " 1958 xhci_warn(xhci, "WARN something wrong with SW event ring "
1959 "dequeue ptr.\n"); 1959 "dequeue ptr.\n");
1960 /* Update HC event ring dequeue pointer */ 1960 /* Update HC event ring dequeue pointer */
1961 temp = readq(&xhci->ir_set->erst_dequeue); 1961 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1962 temp &= ERST_PTR_MASK; 1962 temp &= ERST_PTR_MASK;
1963 /* Don't clear the EHB bit (which is RW1C) because 1963 /* Don't clear the EHB bit (which is RW1C) because
1964 * there might be more events to service. 1964 * there might be more events to service.
@@ -2312,7 +2312,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2312 (unsigned long long)xhci->cmd_ring->first_seg->dma); 2312 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2313 2313
2314 /* Set the address in the Command Ring Control register */ 2314 /* Set the address in the Command Ring Control register */
2315 val_64 = readq(&xhci->op_regs->cmd_ring); 2315 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2316 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | 2316 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2317 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | 2317 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2318 xhci->cmd_ring->cycle_state; 2318 xhci->cmd_ring->cycle_state;
@@ -2396,7 +2396,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2396 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2396 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2397 "// Set ERST base address for ir_set 0 = 0x%llx", 2397 "// Set ERST base address for ir_set 0 = 0x%llx",
2398 (unsigned long long)xhci->erst.erst_dma_addr); 2398 (unsigned long long)xhci->erst.erst_dma_addr);
2399 val_64 = readq(&xhci->ir_set->erst_base); 2399 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2400 val_64 &= ERST_PTR_MASK; 2400 val_64 &= ERST_PTR_MASK;
2401 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); 2401 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2402 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); 2402 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);