diff options
Diffstat (limited to 'drivers/usb/host/xhci-dbg.c')
-rw-r--r-- | drivers/usb/host/xhci-dbg.c | 485 |
1 files changed, 485 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c new file mode 100644 index 000000000000..2501c571f855 --- /dev/null +++ b/drivers/usb/host/xhci-dbg.c | |||
@@ -0,0 +1,485 @@ | |||
1 | /* | ||
2 | * xHCI host controller driver | ||
3 | * | ||
4 | * Copyright (C) 2008 Intel Corp. | ||
5 | * | ||
6 | * Author: Sarah Sharp | ||
7 | * Some code borrowed from the Linux EHCI driver. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but | ||
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
16 | * for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software Foundation, | ||
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | |||
23 | #include "xhci.h" | ||
24 | |||
25 | #define XHCI_INIT_VALUE 0x0 | ||
26 | |||
27 | /* Add verbose debugging later, just print everything for now */ | ||
28 | |||
29 | void xhci_dbg_regs(struct xhci_hcd *xhci) | ||
30 | { | ||
31 | u32 temp; | ||
32 | |||
33 | xhci_dbg(xhci, "// xHCI capability registers at %p:\n", | ||
34 | xhci->cap_regs); | ||
35 | temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); | ||
36 | xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n", | ||
37 | &xhci->cap_regs->hc_capbase, temp); | ||
38 | xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n", | ||
39 | (unsigned int) HC_LENGTH(temp)); | ||
40 | #if 0 | ||
41 | xhci_dbg(xhci, "// HCIVERSION: 0x%x\n", | ||
42 | (unsigned int) HC_VERSION(temp)); | ||
43 | #endif | ||
44 | |||
45 | xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs); | ||
46 | |||
47 | temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off); | ||
48 | xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n", | ||
49 | &xhci->cap_regs->run_regs_off, | ||
50 | (unsigned int) temp & RTSOFF_MASK); | ||
51 | xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs); | ||
52 | |||
53 | temp = xhci_readl(xhci, &xhci->cap_regs->db_off); | ||
54 | xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp); | ||
55 | xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba); | ||
56 | } | ||
57 | |||
58 | static void xhci_print_cap_regs(struct xhci_hcd *xhci) | ||
59 | { | ||
60 | u32 temp; | ||
61 | |||
62 | xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs); | ||
63 | |||
64 | temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); | ||
65 | xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n", | ||
66 | (unsigned int) temp); | ||
67 | xhci_dbg(xhci, "CAPLENGTH: 0x%x\n", | ||
68 | (unsigned int) HC_LENGTH(temp)); | ||
69 | xhci_dbg(xhci, "HCIVERSION: 0x%x\n", | ||
70 | (unsigned int) HC_VERSION(temp)); | ||
71 | |||
72 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1); | ||
73 | xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n", | ||
74 | (unsigned int) temp); | ||
75 | xhci_dbg(xhci, " Max device slots: %u\n", | ||
76 | (unsigned int) HCS_MAX_SLOTS(temp)); | ||
77 | xhci_dbg(xhci, " Max interrupters: %u\n", | ||
78 | (unsigned int) HCS_MAX_INTRS(temp)); | ||
79 | xhci_dbg(xhci, " Max ports: %u\n", | ||
80 | (unsigned int) HCS_MAX_PORTS(temp)); | ||
81 | |||
82 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2); | ||
83 | xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n", | ||
84 | (unsigned int) temp); | ||
85 | xhci_dbg(xhci, " Isoc scheduling threshold: %u\n", | ||
86 | (unsigned int) HCS_IST(temp)); | ||
87 | xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n", | ||
88 | (unsigned int) HCS_ERST_MAX(temp)); | ||
89 | |||
90 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); | ||
91 | xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n", | ||
92 | (unsigned int) temp); | ||
93 | xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n", | ||
94 | (unsigned int) HCS_U1_LATENCY(temp)); | ||
95 | xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n", | ||
96 | (unsigned int) HCS_U2_LATENCY(temp)); | ||
97 | |||
98 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | ||
99 | xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp); | ||
100 | xhci_dbg(xhci, " HC generates %s bit addresses\n", | ||
101 | HCC_64BIT_ADDR(temp) ? "64" : "32"); | ||
102 | /* FIXME */ | ||
103 | xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n"); | ||
104 | |||
105 | temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off); | ||
106 | xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK); | ||
107 | } | ||
108 | |||
109 | static void xhci_print_command_reg(struct xhci_hcd *xhci) | ||
110 | { | ||
111 | u32 temp; | ||
112 | |||
113 | temp = xhci_readl(xhci, &xhci->op_regs->command); | ||
114 | xhci_dbg(xhci, "USBCMD 0x%x:\n", temp); | ||
115 | xhci_dbg(xhci, " HC is %s\n", | ||
116 | (temp & CMD_RUN) ? "running" : "being stopped"); | ||
117 | xhci_dbg(xhci, " HC has %sfinished hard reset\n", | ||
118 | (temp & CMD_RESET) ? "not " : ""); | ||
119 | xhci_dbg(xhci, " Event Interrupts %s\n", | ||
120 | (temp & CMD_EIE) ? "enabled " : "disabled"); | ||
121 | xhci_dbg(xhci, " Host System Error Interrupts %s\n", | ||
122 | (temp & CMD_EIE) ? "enabled " : "disabled"); | ||
123 | xhci_dbg(xhci, " HC has %sfinished light reset\n", | ||
124 | (temp & CMD_LRESET) ? "not " : ""); | ||
125 | } | ||
126 | |||
127 | static void xhci_print_status(struct xhci_hcd *xhci) | ||
128 | { | ||
129 | u32 temp; | ||
130 | |||
131 | temp = xhci_readl(xhci, &xhci->op_regs->status); | ||
132 | xhci_dbg(xhci, "USBSTS 0x%x:\n", temp); | ||
133 | xhci_dbg(xhci, " Event ring is %sempty\n", | ||
134 | (temp & STS_EINT) ? "not " : ""); | ||
135 | xhci_dbg(xhci, " %sHost System Error\n", | ||
136 | (temp & STS_FATAL) ? "WARNING: " : "No "); | ||
137 | xhci_dbg(xhci, " HC is %s\n", | ||
138 | (temp & STS_HALT) ? "halted" : "running"); | ||
139 | } | ||
140 | |||
141 | static void xhci_print_op_regs(struct xhci_hcd *xhci) | ||
142 | { | ||
143 | xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs); | ||
144 | xhci_print_command_reg(xhci); | ||
145 | xhci_print_status(xhci); | ||
146 | } | ||
147 | |||
148 | static void xhci_print_ports(struct xhci_hcd *xhci) | ||
149 | { | ||
150 | u32 __iomem *addr; | ||
151 | int i, j; | ||
152 | int ports; | ||
153 | char *names[NUM_PORT_REGS] = { | ||
154 | "status", | ||
155 | "power", | ||
156 | "link", | ||
157 | "reserved", | ||
158 | }; | ||
159 | |||
160 | ports = HCS_MAX_PORTS(xhci->hcs_params1); | ||
161 | addr = &xhci->op_regs->port_status_base; | ||
162 | for (i = 0; i < ports; i++) { | ||
163 | for (j = 0; j < NUM_PORT_REGS; ++j) { | ||
164 | xhci_dbg(xhci, "%p port %s reg = 0x%x\n", | ||
165 | addr, names[j], | ||
166 | (unsigned int) xhci_readl(xhci, addr)); | ||
167 | addr++; | ||
168 | } | ||
169 | } | ||
170 | } | ||
171 | |||
172 | void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num) | ||
173 | { | ||
174 | void *addr; | ||
175 | u32 temp; | ||
176 | |||
177 | addr = &ir_set->irq_pending; | ||
178 | temp = xhci_readl(xhci, addr); | ||
179 | if (temp == XHCI_INIT_VALUE) | ||
180 | return; | ||
181 | |||
182 | xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num); | ||
183 | |||
184 | xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr, | ||
185 | (unsigned int)temp); | ||
186 | |||
187 | addr = &ir_set->irq_control; | ||
188 | temp = xhci_readl(xhci, addr); | ||
189 | xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr, | ||
190 | (unsigned int)temp); | ||
191 | |||
192 | addr = &ir_set->erst_size; | ||
193 | temp = xhci_readl(xhci, addr); | ||
194 | xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr, | ||
195 | (unsigned int)temp); | ||
196 | |||
197 | addr = &ir_set->rsvd; | ||
198 | temp = xhci_readl(xhci, addr); | ||
199 | if (temp != XHCI_INIT_VALUE) | ||
200 | xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n", | ||
201 | addr, (unsigned int)temp); | ||
202 | |||
203 | addr = &ir_set->erst_base[0]; | ||
204 | temp = xhci_readl(xhci, addr); | ||
205 | xhci_dbg(xhci, " %p: ir_set.erst_base[0] = 0x%x\n", | ||
206 | addr, (unsigned int) temp); | ||
207 | |||
208 | addr = &ir_set->erst_base[1]; | ||
209 | temp = xhci_readl(xhci, addr); | ||
210 | xhci_dbg(xhci, " %p: ir_set.erst_base[1] = 0x%x\n", | ||
211 | addr, (unsigned int) temp); | ||
212 | |||
213 | addr = &ir_set->erst_dequeue[0]; | ||
214 | temp = xhci_readl(xhci, addr); | ||
215 | xhci_dbg(xhci, " %p: ir_set.erst_dequeue[0] = 0x%x\n", | ||
216 | addr, (unsigned int) temp); | ||
217 | |||
218 | addr = &ir_set->erst_dequeue[1]; | ||
219 | temp = xhci_readl(xhci, addr); | ||
220 | xhci_dbg(xhci, " %p: ir_set.erst_dequeue[1] = 0x%x\n", | ||
221 | addr, (unsigned int) temp); | ||
222 | } | ||
223 | |||
224 | void xhci_print_run_regs(struct xhci_hcd *xhci) | ||
225 | { | ||
226 | u32 temp; | ||
227 | int i; | ||
228 | |||
229 | xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs); | ||
230 | temp = xhci_readl(xhci, &xhci->run_regs->microframe_index); | ||
231 | xhci_dbg(xhci, " %p: Microframe index = 0x%x\n", | ||
232 | &xhci->run_regs->microframe_index, | ||
233 | (unsigned int) temp); | ||
234 | for (i = 0; i < 7; ++i) { | ||
235 | temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]); | ||
236 | if (temp != XHCI_INIT_VALUE) | ||
237 | xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n", | ||
238 | &xhci->run_regs->rsvd[i], | ||
239 | i, (unsigned int) temp); | ||
240 | } | ||
241 | } | ||
242 | |||
243 | void xhci_print_registers(struct xhci_hcd *xhci) | ||
244 | { | ||
245 | xhci_print_cap_regs(xhci); | ||
246 | xhci_print_op_regs(xhci); | ||
247 | xhci_print_ports(xhci); | ||
248 | } | ||
249 | |||
250 | void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb) | ||
251 | { | ||
252 | int i; | ||
253 | for (i = 0; i < 4; ++i) | ||
254 | xhci_dbg(xhci, "Offset 0x%x = 0x%x\n", | ||
255 | i*4, trb->generic.field[i]); | ||
256 | } | ||
257 | |||
258 | /** | ||
259 | * Debug a transfer request block (TRB). | ||
260 | */ | ||
261 | void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb) | ||
262 | { | ||
263 | u64 address; | ||
264 | u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK; | ||
265 | |||
266 | switch (type) { | ||
267 | case TRB_TYPE(TRB_LINK): | ||
268 | xhci_dbg(xhci, "Link TRB:\n"); | ||
269 | xhci_print_trb_offsets(xhci, trb); | ||
270 | |||
271 | address = trb->link.segment_ptr[0] + | ||
272 | (((u64) trb->link.segment_ptr[1]) << 32); | ||
273 | xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address); | ||
274 | |||
275 | xhci_dbg(xhci, "Interrupter target = 0x%x\n", | ||
276 | GET_INTR_TARGET(trb->link.intr_target)); | ||
277 | xhci_dbg(xhci, "Cycle bit = %u\n", | ||
278 | (unsigned int) (trb->link.control & TRB_CYCLE)); | ||
279 | xhci_dbg(xhci, "Toggle cycle bit = %u\n", | ||
280 | (unsigned int) (trb->link.control & LINK_TOGGLE)); | ||
281 | xhci_dbg(xhci, "No Snoop bit = %u\n", | ||
282 | (unsigned int) (trb->link.control & TRB_NO_SNOOP)); | ||
283 | break; | ||
284 | case TRB_TYPE(TRB_TRANSFER): | ||
285 | address = trb->trans_event.buffer[0] + | ||
286 | (((u64) trb->trans_event.buffer[1]) << 32); | ||
287 | /* | ||
288 | * FIXME: look at flags to figure out if it's an address or if | ||
289 | * the data is directly in the buffer field. | ||
290 | */ | ||
291 | xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address); | ||
292 | break; | ||
293 | case TRB_TYPE(TRB_COMPLETION): | ||
294 | address = trb->event_cmd.cmd_trb[0] + | ||
295 | (((u64) trb->event_cmd.cmd_trb[1]) << 32); | ||
296 | xhci_dbg(xhci, "Command TRB pointer = %llu\n", address); | ||
297 | xhci_dbg(xhci, "Completion status = %u\n", | ||
298 | (unsigned int) GET_COMP_CODE(trb->event_cmd.status)); | ||
299 | xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags); | ||
300 | break; | ||
301 | default: | ||
302 | xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n", | ||
303 | (unsigned int) type>>10); | ||
304 | xhci_print_trb_offsets(xhci, trb); | ||
305 | break; | ||
306 | } | ||
307 | } | ||
308 | |||
309 | /** | ||
310 | * Debug a segment with an xHCI ring. | ||
311 | * | ||
312 | * @return The Link TRB of the segment, or NULL if there is no Link TRB | ||
313 | * (which is a bug, since all segments must have a Link TRB). | ||
314 | * | ||
315 | * Prints out all TRBs in the segment, even those after the Link TRB. | ||
316 | * | ||
317 | * XXX: should we print out TRBs that the HC owns? As long as we don't | ||
318 | * write, that should be fine... We shouldn't expect that the memory pointed to | ||
319 | * by the TRB is valid at all. Do we care about ones the HC owns? Probably, | ||
320 | * for HC debugging. | ||
321 | */ | ||
322 | void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg) | ||
323 | { | ||
324 | int i; | ||
325 | u32 addr = (u32) seg->dma; | ||
326 | union xhci_trb *trb = seg->trbs; | ||
327 | |||
328 | for (i = 0; i < TRBS_PER_SEGMENT; ++i) { | ||
329 | trb = &seg->trbs[i]; | ||
330 | xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr, | ||
331 | (unsigned int) trb->link.segment_ptr[0], | ||
332 | (unsigned int) trb->link.segment_ptr[1], | ||
333 | (unsigned int) trb->link.intr_target, | ||
334 | (unsigned int) trb->link.control); | ||
335 | addr += sizeof(*trb); | ||
336 | } | ||
337 | } | ||
338 | |||
339 | void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring) | ||
340 | { | ||
341 | xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n", | ||
342 | ring->dequeue, | ||
343 | (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg, | ||
344 | ring->dequeue)); | ||
345 | xhci_dbg(xhci, "Ring deq updated %u times\n", | ||
346 | ring->deq_updates); | ||
347 | xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n", | ||
348 | ring->enqueue, | ||
349 | (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg, | ||
350 | ring->enqueue)); | ||
351 | xhci_dbg(xhci, "Ring enq updated %u times\n", | ||
352 | ring->enq_updates); | ||
353 | } | ||
354 | |||
355 | /** | ||
356 | * Debugging for an xHCI ring, which is a queue broken into multiple segments. | ||
357 | * | ||
358 | * Print out each segment in the ring. Check that the DMA address in | ||
359 | * each link segment actually matches the segment's stored DMA address. | ||
360 | * Check that the link end bit is only set at the end of the ring. | ||
361 | * Check that the dequeue and enqueue pointers point to real data in this ring | ||
362 | * (not some other ring). | ||
363 | */ | ||
364 | void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring) | ||
365 | { | ||
366 | /* FIXME: Throw an error if any segment doesn't have a Link TRB */ | ||
367 | struct xhci_segment *seg; | ||
368 | struct xhci_segment *first_seg = ring->first_seg; | ||
369 | xhci_debug_segment(xhci, first_seg); | ||
370 | |||
371 | if (!ring->enq_updates && !ring->deq_updates) { | ||
372 | xhci_dbg(xhci, " Ring has not been updated\n"); | ||
373 | return; | ||
374 | } | ||
375 | for (seg = first_seg->next; seg != first_seg; seg = seg->next) | ||
376 | xhci_debug_segment(xhci, seg); | ||
377 | } | ||
378 | |||
379 | void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) | ||
380 | { | ||
381 | u32 addr = (u32) erst->erst_dma_addr; | ||
382 | int i; | ||
383 | struct xhci_erst_entry *entry; | ||
384 | |||
385 | for (i = 0; i < erst->num_entries; ++i) { | ||
386 | entry = &erst->entries[i]; | ||
387 | xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", | ||
388 | (unsigned int) addr, | ||
389 | (unsigned int) entry->seg_addr[0], | ||
390 | (unsigned int) entry->seg_addr[1], | ||
391 | (unsigned int) entry->seg_size, | ||
392 | (unsigned int) entry->rsvd); | ||
393 | addr += sizeof(*entry); | ||
394 | } | ||
395 | } | ||
396 | |||
397 | void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci) | ||
398 | { | ||
399 | u32 val; | ||
400 | |||
401 | val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]); | ||
402 | xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = 0x%x\n", val); | ||
403 | val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[1]); | ||
404 | xhci_dbg(xhci, "// xHC command ring deq ptr high bits = 0x%x\n", val); | ||
405 | } | ||
406 | |||
407 | void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_device_control *ctx, dma_addr_t dma, unsigned int last_ep) | ||
408 | { | ||
409 | int i, j; | ||
410 | int last_ep_ctx = 31; | ||
411 | /* Fields are 32 bits wide, DMA addresses are in bytes */ | ||
412 | int field_size = 32 / 8; | ||
413 | |||
414 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n", | ||
415 | &ctx->drop_flags, (unsigned long long)dma, | ||
416 | ctx->drop_flags); | ||
417 | dma += field_size; | ||
418 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n", | ||
419 | &ctx->add_flags, (unsigned long long)dma, | ||
420 | ctx->add_flags); | ||
421 | dma += field_size; | ||
422 | for (i = 0; i > 6; ++i) { | ||
423 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", | ||
424 | &ctx->rsvd[i], (unsigned long long)dma, | ||
425 | ctx->rsvd[i], i); | ||
426 | dma += field_size; | ||
427 | } | ||
428 | |||
429 | xhci_dbg(xhci, "Slot Context:\n"); | ||
430 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n", | ||
431 | &ctx->slot.dev_info, | ||
432 | (unsigned long long)dma, ctx->slot.dev_info); | ||
433 | dma += field_size; | ||
434 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n", | ||
435 | &ctx->slot.dev_info2, | ||
436 | (unsigned long long)dma, ctx->slot.dev_info2); | ||
437 | dma += field_size; | ||
438 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n", | ||
439 | &ctx->slot.tt_info, | ||
440 | (unsigned long long)dma, ctx->slot.tt_info); | ||
441 | dma += field_size; | ||
442 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n", | ||
443 | &ctx->slot.dev_state, | ||
444 | (unsigned long long)dma, ctx->slot.dev_state); | ||
445 | dma += field_size; | ||
446 | for (i = 0; i > 4; ++i) { | ||
447 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", | ||
448 | &ctx->slot.reserved[i], (unsigned long long)dma, | ||
449 | ctx->slot.reserved[i], i); | ||
450 | dma += field_size; | ||
451 | } | ||
452 | |||
453 | if (last_ep < 31) | ||
454 | last_ep_ctx = last_ep + 1; | ||
455 | for (i = 0; i < last_ep_ctx; ++i) { | ||
456 | xhci_dbg(xhci, "Endpoint %02d Context:\n", i); | ||
457 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n", | ||
458 | &ctx->ep[i].ep_info, | ||
459 | (unsigned long long)dma, ctx->ep[i].ep_info); | ||
460 | dma += field_size; | ||
461 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n", | ||
462 | &ctx->ep[i].ep_info2, | ||
463 | (unsigned long long)dma, ctx->ep[i].ep_info2); | ||
464 | dma += field_size; | ||
465 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - deq[0]\n", | ||
466 | &ctx->ep[i].deq[0], | ||
467 | (unsigned long long)dma, ctx->ep[i].deq[0]); | ||
468 | dma += field_size; | ||
469 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - deq[1]\n", | ||
470 | &ctx->ep[i].deq[1], | ||
471 | (unsigned long long)dma, ctx->ep[i].deq[1]); | ||
472 | dma += field_size; | ||
473 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n", | ||
474 | &ctx->ep[i].tx_info, | ||
475 | (unsigned long long)dma, ctx->ep[i].tx_info); | ||
476 | dma += field_size; | ||
477 | for (j = 0; j < 3; ++j) { | ||
478 | xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", | ||
479 | &ctx->ep[i].reserved[j], | ||
480 | (unsigned long long)dma, | ||
481 | ctx->ep[i].reserved[j], j); | ||
482 | dma += field_size; | ||
483 | } | ||
484 | } | ||
485 | } | ||