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path: root/drivers/usb/host/r8a66597.h
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-rw-r--r--drivers/usb/host/r8a66597.h440
1 files changed, 34 insertions, 406 deletions
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index d72680b433f9..228e3fb23854 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -26,390 +26,16 @@
26#ifndef __R8A66597_H__ 26#ifndef __R8A66597_H__
27#define __R8A66597_H__ 27#define __R8A66597_H__
28 28
29#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK) 29#ifdef CONFIG_HAVE_CLK
30#include <linux/clk.h> 30#include <linux/clk.h>
31#endif 31#endif
32 32
33#include <linux/usb/r8a66597.h> 33#include <linux/usb/r8a66597.h>
34 34
35#define SYSCFG0 0x00
36#define SYSCFG1 0x02
37#define SYSSTS0 0x04
38#define SYSSTS1 0x06
39#define DVSTCTR0 0x08
40#define DVSTCTR1 0x0A
41#define TESTMODE 0x0C
42#define PINCFG 0x0E
43#define DMA0CFG 0x10
44#define DMA1CFG 0x12
45#define CFIFO 0x14
46#define D0FIFO 0x18
47#define D1FIFO 0x1C
48#define CFIFOSEL 0x20
49#define CFIFOCTR 0x22
50#define CFIFOSIE 0x24
51#define D0FIFOSEL 0x28
52#define D0FIFOCTR 0x2A
53#define D1FIFOSEL 0x2C
54#define D1FIFOCTR 0x2E
55#define INTENB0 0x30
56#define INTENB1 0x32
57#define INTENB2 0x34
58#define BRDYENB 0x36
59#define NRDYENB 0x38
60#define BEMPENB 0x3A
61#define SOFCFG 0x3C
62#define INTSTS0 0x40
63#define INTSTS1 0x42
64#define INTSTS2 0x44
65#define BRDYSTS 0x46
66#define NRDYSTS 0x48
67#define BEMPSTS 0x4A
68#define FRMNUM 0x4C
69#define UFRMNUM 0x4E
70#define USBADDR 0x50
71#define USBREQ 0x54
72#define USBVAL 0x56
73#define USBINDX 0x58
74#define USBLENG 0x5A
75#define DCPCFG 0x5C
76#define DCPMAXP 0x5E
77#define DCPCTR 0x60
78#define PIPESEL 0x64
79#define PIPECFG 0x68
80#define PIPEBUF 0x6A
81#define PIPEMAXP 0x6C
82#define PIPEPERI 0x6E
83#define PIPE1CTR 0x70
84#define PIPE2CTR 0x72
85#define PIPE3CTR 0x74
86#define PIPE4CTR 0x76
87#define PIPE5CTR 0x78
88#define PIPE6CTR 0x7A
89#define PIPE7CTR 0x7C
90#define PIPE8CTR 0x7E
91#define PIPE9CTR 0x80
92#define PIPE1TRE 0x90
93#define PIPE1TRN 0x92
94#define PIPE2TRE 0x94
95#define PIPE2TRN 0x96
96#define PIPE3TRE 0x98
97#define PIPE3TRN 0x9A
98#define PIPE4TRE 0x9C
99#define PIPE4TRN 0x9E
100#define PIPE5TRE 0xA0
101#define PIPE5TRN 0xA2
102#define DEVADD0 0xD0
103#define DEVADD1 0xD2
104#define DEVADD2 0xD4
105#define DEVADD3 0xD6
106#define DEVADD4 0xD8
107#define DEVADD5 0xDA
108#define DEVADD6 0xDC
109#define DEVADD7 0xDE
110#define DEVADD8 0xE0
111#define DEVADD9 0xE2
112#define DEVADDA 0xE4
113
114/* System Configuration Control Register */
115#define XTAL 0xC000 /* b15-14: Crystal selection */
116#define XTAL48 0x8000 /* 48MHz */
117#define XTAL24 0x4000 /* 24MHz */
118#define XTAL12 0x0000 /* 12MHz */
119#define XCKE 0x2000 /* b13: External clock enable */
120#define PLLC 0x0800 /* b11: PLL control */
121#define SCKE 0x0400 /* b10: USB clock enable */
122#define PCSDIS 0x0200 /* b9: not CS wakeup */
123#define LPSME 0x0100 /* b8: Low power sleep mode */
124#define HSE 0x0080 /* b7: Hi-speed enable */
125#define DCFM 0x0040 /* b6: Controller function select */
126#define DRPD 0x0020 /* b5: D+/- pull down control */
127#define DPRPU 0x0010 /* b4: D+ pull up control */
128#define USBE 0x0001 /* b0: USB module operation enable */
129
130/* System Configuration Status Register */
131#define OVCBIT 0x8000 /* b15-14: Over-current bit */
132#define OVCMON 0xC000 /* b15-14: Over-current monitor */
133#define SOFEA 0x0020 /* b5: SOF monitor */
134#define IDMON 0x0004 /* b3: ID-pin monitor */
135#define LNST 0x0003 /* b1-0: D+, D- line status */
136#define SE1 0x0003 /* SE1 */
137#define FS_KSTS 0x0002 /* Full-Speed K State */
138#define FS_JSTS 0x0001 /* Full-Speed J State */
139#define LS_JSTS 0x0002 /* Low-Speed J State */
140#define LS_KSTS 0x0001 /* Low-Speed K State */
141#define SE0 0x0000 /* SE0 */
142
143/* Device State Control Register */
144#define EXTLP0 0x0400 /* b10: External port */
145#define VBOUT 0x0200 /* b9: VBUS output */
146#define WKUP 0x0100 /* b8: Remote wakeup */
147#define RWUPE 0x0080 /* b7: Remote wakeup sense */
148#define USBRST 0x0040 /* b6: USB reset enable */
149#define RESUME 0x0020 /* b5: Resume enable */
150#define UACT 0x0010 /* b4: USB bus enable */
151#define RHST 0x0007 /* b1-0: Reset handshake status */
152#define HSPROC 0x0004 /* HS handshake is processing */
153#define HSMODE 0x0003 /* Hi-Speed mode */
154#define FSMODE 0x0002 /* Full-Speed mode */
155#define LSMODE 0x0001 /* Low-Speed mode */
156#define UNDECID 0x0000 /* Undecided */
157
158/* Test Mode Register */
159#define UTST 0x000F /* b3-0: Test select */
160#define H_TST_PACKET 0x000C /* HOST TEST Packet */
161#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
162#define H_TST_K 0x000A /* HOST TEST K */
163#define H_TST_J 0x0009 /* HOST TEST J */
164#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
165#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
166#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
167#define P_TST_K 0x0002 /* PERI TEST K */
168#define P_TST_J 0x0001 /* PERI TEST J */
169#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
170
171/* Data Pin Configuration Register */
172#define LDRV 0x8000 /* b15: Drive Current Adjust */
173#define VIF1 0x0000 /* VIF = 1.8V */
174#define VIF3 0x8000 /* VIF = 3.3V */
175#define INTA 0x0001 /* b1: USB INT-pin active */
176
177/* DMAx Pin Configuration Register */
178#define DREQA 0x4000 /* b14: Dreq active select */
179#define BURST 0x2000 /* b13: Burst mode */
180#define DACKA 0x0400 /* b10: Dack active select */
181#define DFORM 0x0380 /* b9-7: DMA mode select */
182#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
183#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
184#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
185#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
186#define DENDA 0x0040 /* b6: Dend active select */
187#define PKTM 0x0020 /* b5: Packet mode */
188#define DENDE 0x0010 /* b4: Dend enable */
189#define OBUS 0x0004 /* b2: OUTbus mode */
190
191/* CFIFO/DxFIFO Port Select Register */
192#define RCNT 0x8000 /* b15: Read count mode */
193#define REW 0x4000 /* b14: Buffer rewind */
194#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
195#define DREQE 0x1000 /* b12: DREQ output enable */
196#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
197#define MBW 0x0800
198#else
199#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
200#endif
201#define MBW_8 0x0000 /* 8bit */
202#define MBW_16 0x0400 /* 16bit */
203#define BIGEND 0x0100 /* b8: Big endian mode */
204#define BYTE_LITTLE 0x0000 /* little dendian */
205#define BYTE_BIG 0x0100 /* big endifan */
206#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
207#define CURPIPE 0x000F /* b2-0: PIPE select */
208
209/* CFIFO/DxFIFO Port Control Register */
210#define BVAL 0x8000 /* b15: Buffer valid flag */
211#define BCLR 0x4000 /* b14: Buffer clear */
212#define FRDY 0x2000 /* b13: FIFO ready */
213#define DTLN 0x0FFF /* b11-0: FIFO received data length */
214
215/* Interrupt Enable Register 0 */
216#define VBSE 0x8000 /* b15: VBUS interrupt */
217#define RSME 0x4000 /* b14: Resume interrupt */
218#define SOFE 0x2000 /* b13: Frame update interrupt */
219#define DVSE 0x1000 /* b12: Device state transition interrupt */
220#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
221#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
222#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
223#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
224
225/* Interrupt Enable Register 1 */
226#define OVRCRE 0x8000 /* b15: Over-current interrupt */
227#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
228#define DTCHE 0x1000 /* b12: Detach sense interrupt */
229#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
230#define EOFERRE 0x0040 /* b6: EOF error interrupt */
231#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
232#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
233
234/* BRDY Interrupt Enable/Status Register */
235#define BRDY9 0x0200 /* b9: PIPE9 */
236#define BRDY8 0x0100 /* b8: PIPE8 */
237#define BRDY7 0x0080 /* b7: PIPE7 */
238#define BRDY6 0x0040 /* b6: PIPE6 */
239#define BRDY5 0x0020 /* b5: PIPE5 */
240#define BRDY4 0x0010 /* b4: PIPE4 */
241#define BRDY3 0x0008 /* b3: PIPE3 */
242#define BRDY2 0x0004 /* b2: PIPE2 */
243#define BRDY1 0x0002 /* b1: PIPE1 */
244#define BRDY0 0x0001 /* b1: PIPE0 */
245
246/* NRDY Interrupt Enable/Status Register */
247#define NRDY9 0x0200 /* b9: PIPE9 */
248#define NRDY8 0x0100 /* b8: PIPE8 */
249#define NRDY7 0x0080 /* b7: PIPE7 */
250#define NRDY6 0x0040 /* b6: PIPE6 */
251#define NRDY5 0x0020 /* b5: PIPE5 */
252#define NRDY4 0x0010 /* b4: PIPE4 */
253#define NRDY3 0x0008 /* b3: PIPE3 */
254#define NRDY2 0x0004 /* b2: PIPE2 */
255#define NRDY1 0x0002 /* b1: PIPE1 */
256#define NRDY0 0x0001 /* b1: PIPE0 */
257
258/* BEMP Interrupt Enable/Status Register */
259#define BEMP9 0x0200 /* b9: PIPE9 */
260#define BEMP8 0x0100 /* b8: PIPE8 */
261#define BEMP7 0x0080 /* b7: PIPE7 */
262#define BEMP6 0x0040 /* b6: PIPE6 */
263#define BEMP5 0x0020 /* b5: PIPE5 */
264#define BEMP4 0x0010 /* b4: PIPE4 */
265#define BEMP3 0x0008 /* b3: PIPE3 */
266#define BEMP2 0x0004 /* b2: PIPE2 */
267#define BEMP1 0x0002 /* b1: PIPE1 */
268#define BEMP0 0x0001 /* b0: PIPE0 */
269
270/* SOF Pin Configuration Register */
271#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
272#define BRDYM 0x0040 /* b6: BRDY clear timing */
273#define INTL 0x0020 /* b5: Interrupt sense select */
274#define EDGESTS 0x0010 /* b4: */
275#define SOFMODE 0x000C /* b3-2: SOF pin select */
276#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
277#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
278#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
279
280/* Interrupt Status Register 0 */
281#define VBINT 0x8000 /* b15: VBUS interrupt */
282#define RESM 0x4000 /* b14: Resume interrupt */
283#define SOFR 0x2000 /* b13: SOF frame update interrupt */
284#define DVST 0x1000 /* b12: Device state transition interrupt */
285#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
286#define BEMP 0x0400 /* b10: Buffer empty interrupt */
287#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
288#define BRDY 0x0100 /* b8: Buffer ready interrupt */
289#define VBSTS 0x0080 /* b7: VBUS input port */
290#define DVSQ 0x0070 /* b6-4: Device state */
291#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
292#define DS_SPD_ADDR 0x0060 /* Suspend Address */
293#define DS_SPD_DFLT 0x0050 /* Suspend Default */
294#define DS_SPD_POWR 0x0040 /* Suspend Powered */
295#define DS_SUSP 0x0040 /* Suspend */
296#define DS_CNFG 0x0030 /* Configured */
297#define DS_ADDS 0x0020 /* Address */
298#define DS_DFLT 0x0010 /* Default */
299#define DS_POWR 0x0000 /* Powered */
300#define DVSQS 0x0030 /* b5-4: Device state */
301#define VALID 0x0008 /* b3: Setup packet detected flag */
302#define CTSQ 0x0007 /* b2-0: Control transfer stage */
303#define CS_SQER 0x0006 /* Sequence error */
304#define CS_WRND 0x0005 /* Control write nodata status stage */
305#define CS_WRSS 0x0004 /* Control write status stage */
306#define CS_WRDS 0x0003 /* Control write data stage */
307#define CS_RDSS 0x0002 /* Control read status stage */
308#define CS_RDDS 0x0001 /* Control read data stage */
309#define CS_IDST 0x0000 /* Idle or setup stage */
310
311/* Interrupt Status Register 1 */
312#define OVRCR 0x8000 /* b15: Over-current interrupt */
313#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
314#define DTCH 0x1000 /* b12: Detach sense interrupt */
315#define ATTCH 0x0800 /* b11: Attach sense interrupt */
316#define EOFERR 0x0040 /* b6: EOF-error interrupt */
317#define SIGN 0x0020 /* b5: Setup ignore interrupt */
318#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
319
320/* Frame Number Register */
321#define OVRN 0x8000 /* b15: Overrun error */
322#define CRCE 0x4000 /* b14: Received data error */
323#define FRNM 0x07FF /* b10-0: Frame number */
324
325/* Micro Frame Number Register */
326#define UFRNM 0x0007 /* b2-0: Micro frame number */
327
328/* Default Control Pipe Maxpacket Size Register */
329/* Pipe Maxpacket Size Register */
330#define DEVSEL 0xF000 /* b15-14: Device address select */
331#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
332
333/* Default Control Pipe Control Register */
334#define BSTS 0x8000 /* b15: Buffer status */
335#define SUREQ 0x4000 /* b14: Send USB request */
336#define CSCLR 0x2000 /* b13: complete-split status clear */
337#define CSSTS 0x1000 /* b12: complete-split status */
338#define SUREQCLR 0x0800 /* b11: stop setup request */
339#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
340#define SQSET 0x0080 /* b7: Sequence toggle bit set */
341#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
342#define PBUSY 0x0020 /* b5: pipe busy */
343#define PINGE 0x0010 /* b4: ping enable */
344#define CCPL 0x0004 /* b2: Enable control transfer complete */
345#define PID 0x0003 /* b1-0: Response PID */
346#define PID_STALL11 0x0003 /* STALL */
347#define PID_STALL 0x0002 /* STALL */
348#define PID_BUF 0x0001 /* BUF */
349#define PID_NAK 0x0000 /* NAK */
350
351/* Pipe Window Select Register */
352#define PIPENM 0x0007 /* b2-0: Pipe select */
353
354/* Pipe Configuration Register */
355#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
356#define R8A66597_ISO 0xC000 /* Isochronous */
357#define R8A66597_INT 0x8000 /* Interrupt */
358#define R8A66597_BULK 0x4000 /* Bulk */
359#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
360#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
361#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
362#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
363#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
364#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
365
366/* Pipe Buffer Configuration Register */
367#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
368#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
369#define PIPE0BUF 256
370#define PIPExBUF 64
371
372/* Pipe Maxpacket Size Register */
373#define MXPS 0x07FF /* b10-0: Maxpacket size */
374
375/* Pipe Cycle Configuration Register */
376#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
377#define IITV 0x0007 /* b2-0: Isochronous interval */
378
379/* Pipex Control Register */
380#define BSTS 0x8000 /* b15: Buffer status */
381#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
382#define CSCLR 0x2000 /* b13: complete-split status clear */
383#define CSSTS 0x1000 /* b12: complete-split status */
384#define ATREPM 0x0400 /* b10: Auto repeat mode */
385#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
386#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
387#define SQSET 0x0080 /* b7: Sequence toggle bit set */
388#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
389#define PBUSY 0x0020 /* b5: pipe busy */
390#define PID 0x0003 /* b1-0: Response PID */
391
392/* PIPExTRE */
393#define TRENB 0x0200 /* b9: Transaction counter enable */
394#define TRCLR 0x0100 /* b8: Transaction counter clear */
395
396/* PIPExTRN */
397#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
398
399/* DEVADDx */
400#define UPPHUB 0x7800
401#define HUBPORT 0x0700
402#define USBSPD 0x00C0
403#define RTPORT 0x0001
404
405#define R8A66597_MAX_NUM_PIPE 10 35#define R8A66597_MAX_NUM_PIPE 10
406#define R8A66597_BUF_BSIZE 8 36#define R8A66597_BUF_BSIZE 8
407#define R8A66597_MAX_DEVICE 10 37#define R8A66597_MAX_DEVICE 10
408#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
409#define R8A66597_MAX_ROOT_HUB 1
410#else
411#define R8A66597_MAX_ROOT_HUB 2 38#define R8A66597_MAX_ROOT_HUB 2
412#endif
413#define R8A66597_MAX_SAMPLING 5 39#define R8A66597_MAX_SAMPLING 5
414#define R8A66597_RH_POLL_TIME 10 40#define R8A66597_RH_POLL_TIME 10
415#define R8A66597_MAX_DMA_CHANNEL 2 41#define R8A66597_MAX_DMA_CHANNEL 2
@@ -487,7 +113,7 @@ struct r8a66597_root_hub {
487struct r8a66597 { 113struct r8a66597 {
488 spinlock_t lock; 114 spinlock_t lock;
489 unsigned long reg; 115 unsigned long reg;
490#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK) 116#ifdef CONFIG_HAVE_CLK
491 struct clk *clk; 117 struct clk *clk;
492#endif 118#endif
493 struct r8a66597_platdata *pdata; 119 struct r8a66597_platdata *pdata;
@@ -504,6 +130,7 @@ struct r8a66597 {
504 unsigned short interval_map; 130 unsigned short interval_map;
505 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; 131 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
506 unsigned char dma_map; 132 unsigned char dma_map;
133 unsigned int max_root_hub;
507 134
508 struct list_head child_device; 135 struct list_head child_device;
509 unsigned long child_connect_map[4]; 136 unsigned long child_connect_map[4];
@@ -550,21 +177,22 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
550 unsigned long offset, u16 *buf, 177 unsigned long offset, u16 *buf,
551 int len) 178 int len)
552{ 179{
553#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
554 unsigned long fifoaddr = r8a66597->reg + offset; 180 unsigned long fifoaddr = r8a66597->reg + offset;
555 unsigned long count; 181 unsigned long count;
556 182
557 count = len / 4; 183 if (r8a66597->pdata->on_chip) {
558 insl(fifoaddr, buf, count); 184 count = len / 4;
185 insl(fifoaddr, buf, count);
559 186
560 if (len & 0x00000003) { 187 if (len & 0x00000003) {
561 unsigned long tmp = inl(fifoaddr); 188 unsigned long tmp = inl(fifoaddr);
562 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); 189 memcpy((unsigned char *)buf + count * 4, &tmp,
190 len & 0x03);
191 }
192 } else {
193 len = (len + 1) / 2;
194 insw(fifoaddr, buf, len);
563 } 195 }
564#else
565 len = (len + 1) / 2;
566 insw(r8a66597->reg + offset, buf, len);
567#endif
568} 196}
569 197
570static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 198static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
@@ -578,33 +206,33 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
578 int len) 206 int len)
579{ 207{
580 unsigned long fifoaddr = r8a66597->reg + offset; 208 unsigned long fifoaddr = r8a66597->reg + offset;
581#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
582 unsigned long count; 209 unsigned long count;
583 unsigned char *pb; 210 unsigned char *pb;
584 int i; 211 int i;
585 212
586 count = len / 4; 213 if (r8a66597->pdata->on_chip) {
587 outsl(fifoaddr, buf, count); 214 count = len / 4;
215 outsl(fifoaddr, buf, count);
216
217 if (len & 0x00000003) {
218 pb = (unsigned char *)buf + count * 4;
219 for (i = 0; i < (len & 0x00000003); i++) {
220 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
221 outb(pb[i], fifoaddr + i);
222 else
223 outb(pb[i], fifoaddr + 3 - i);
224 }
225 }
226 } else {
227 int odd = len & 0x0001;
588 228
589 if (len & 0x00000003) { 229 len = len / 2;
590 pb = (unsigned char *)buf + count * 4; 230 outsw(fifoaddr, buf, len);
591 for (i = 0; i < (len & 0x00000003); i++) { 231 if (unlikely(odd)) {
592 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) 232 buf = &buf[len];
593 outb(pb[i], fifoaddr + i); 233 outb((unsigned char)*buf, fifoaddr);
594 else
595 outb(pb[i], fifoaddr + 3 - i);
596 } 234 }
597 } 235 }
598#else
599 int odd = len & 0x0001;
600
601 len = len / 2;
602 outsw(fifoaddr, buf, len);
603 if (unlikely(odd)) {
604 buf = &buf[len];
605 outb((unsigned char)*buf, fifoaddr);
606 }
607#endif
608} 236}
609 237
610static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 238static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 21:54:41 -0500