diff options
Diffstat (limited to 'drivers/usb/host/isp1760-hcd.h')
-rw-r--r-- | drivers/usb/host/isp1760-hcd.h | 206 |
1 files changed, 206 insertions, 0 deletions
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h new file mode 100644 index 000000000000..3d86d0f6b147 --- /dev/null +++ b/drivers/usb/host/isp1760-hcd.h | |||
@@ -0,0 +1,206 @@ | |||
1 | #ifndef _ISP1760_HCD_H_ | ||
2 | #define _ISP1760_HCD_H_ | ||
3 | |||
4 | /* exports for if */ | ||
5 | struct usb_hcd *isp1760_register(u64 res_start, u64 res_len, int irq, | ||
6 | u64 irqflags, struct device *dev, const char *busname); | ||
7 | int init_kmem_once(void); | ||
8 | void deinit_kmem_cache(void); | ||
9 | |||
10 | /* EHCI capability registers */ | ||
11 | #define HC_CAPLENGTH 0x00 | ||
12 | #define HC_HCSPARAMS 0x04 | ||
13 | #define HC_HCCPARAMS 0x08 | ||
14 | |||
15 | /* EHCI operational registers */ | ||
16 | #define HC_USBCMD 0x20 | ||
17 | #define HC_USBSTS 0x24 | ||
18 | #define HC_FRINDEX 0x2c | ||
19 | #define HC_CONFIGFLAG 0x60 | ||
20 | #define HC_PORTSC1 0x64 | ||
21 | #define HC_ISO_PTD_DONEMAP_REG 0x130 | ||
22 | #define HC_ISO_PTD_SKIPMAP_REG 0x134 | ||
23 | #define HC_ISO_PTD_LASTPTD_REG 0x138 | ||
24 | #define HC_INT_PTD_DONEMAP_REG 0x140 | ||
25 | #define HC_INT_PTD_SKIPMAP_REG 0x144 | ||
26 | #define HC_INT_PTD_LASTPTD_REG 0x148 | ||
27 | #define HC_ATL_PTD_DONEMAP_REG 0x150 | ||
28 | #define HC_ATL_PTD_SKIPMAP_REG 0x154 | ||
29 | #define HC_ATL_PTD_LASTPTD_REG 0x158 | ||
30 | |||
31 | /* Configuration Register */ | ||
32 | #define HC_HW_MODE_CTRL 0x300 | ||
33 | #define ALL_ATX_RESET (1 << 31) | ||
34 | #define HW_DATA_BUS_32BIT (1 << 8) | ||
35 | #define HW_DACK_POL_HIGH (1 << 6) | ||
36 | #define HW_DREQ_POL_HIGH (1 << 5) | ||
37 | #define HW_INTR_HIGH_ACT (1 << 2) | ||
38 | #define HW_INTR_EDGE_TRIG (1 << 1) | ||
39 | #define HW_GLOBAL_INTR_EN (1 << 0) | ||
40 | |||
41 | #define HC_CHIP_ID_REG 0x304 | ||
42 | #define HC_SCRATCH_REG 0x308 | ||
43 | |||
44 | #define HC_RESET_REG 0x30c | ||
45 | #define SW_RESET_RESET_HC (1 << 1) | ||
46 | #define SW_RESET_RESET_ALL (1 << 0) | ||
47 | |||
48 | #define HC_BUFFER_STATUS_REG 0x334 | ||
49 | #define ATL_BUFFER 0x1 | ||
50 | #define INT_BUFFER 0x2 | ||
51 | #define ISO_BUFFER 0x4 | ||
52 | #define BUFFER_MAP 0x7 | ||
53 | |||
54 | #define HC_MEMORY_REG 0x33c | ||
55 | #define HC_PORT1_CTRL 0x374 | ||
56 | #define PORT1_POWER (3 << 3) | ||
57 | #define PORT1_INIT1 (1 << 7) | ||
58 | #define PORT1_INIT2 (1 << 23) | ||
59 | |||
60 | /* Interrupt Register */ | ||
61 | #define HC_INTERRUPT_REG 0x310 | ||
62 | |||
63 | #define HC_INTERRUPT_ENABLE 0x314 | ||
64 | #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT) | ||
65 | #define FINAL_HW_CONFIG (HW_GLOBAL_INTR_EN | HW_DATA_BUS_32BIT) | ||
66 | |||
67 | #define HC_ISO_INT (1 << 9) | ||
68 | #define HC_ATL_INT (1 << 8) | ||
69 | #define HC_INTL_INT (1 << 7) | ||
70 | #define HC_EOT_INT (1 << 3) | ||
71 | #define HC_SOT_INT (1 << 1) | ||
72 | |||
73 | #define HC_ISO_IRQ_MASK_OR_REG 0x318 | ||
74 | #define HC_INT_IRQ_MASK_OR_REG 0x31C | ||
75 | #define HC_ATL_IRQ_MASK_OR_REG 0x320 | ||
76 | #define HC_ISO_IRQ_MASK_AND_REG 0x324 | ||
77 | #define HC_INT_IRQ_MASK_AND_REG 0x328 | ||
78 | #define HC_ATL_IRQ_MASK_AND_REG 0x32C | ||
79 | |||
80 | /* Register sets */ | ||
81 | #define HC_BEGIN_OF_ATL 0x0c00 | ||
82 | #define HC_BEGIN_OF_INT 0x0800 | ||
83 | #define HC_BEGIN_OF_ISO 0x0400 | ||
84 | #define HC_BEGIN_OF_PAYLOAD 0x1000 | ||
85 | |||
86 | /* urb state*/ | ||
87 | #define DELETE_URB (0x0008) | ||
88 | #define NO_TRANSFER_ACTIVE (0xffffffff) | ||
89 | |||
90 | #define ATL_REGS_OFFSET (0xc00) | ||
91 | #define INT_REGS_OFFSET (0x800) | ||
92 | |||
93 | /* Philips Transfer Descriptor (PTD) */ | ||
94 | struct ptd { | ||
95 | __le32 dw0; | ||
96 | __le32 dw1; | ||
97 | __le32 dw2; | ||
98 | __le32 dw3; | ||
99 | __le32 dw4; | ||
100 | __le32 dw5; | ||
101 | __le32 dw6; | ||
102 | __le32 dw7; | ||
103 | }; | ||
104 | |||
105 | struct inter_packet_info { | ||
106 | void *data_buffer; | ||
107 | u32 payload; | ||
108 | #define PTD_FIRE_NEXT (1 << 0) | ||
109 | #define PTD_URB_FINISHED (1 << 1) | ||
110 | struct urb *urb; | ||
111 | struct isp1760_qh *qh; | ||
112 | struct isp1760_qtd *qtd; | ||
113 | }; | ||
114 | |||
115 | |||
116 | typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, | ||
117 | struct isp1760_qtd *qtd); | ||
118 | |||
119 | #define isp1760_info(priv, fmt, args...) \ | ||
120 | dev_info(priv_to_hcd(priv)->self.controller, fmt, ##args) | ||
121 | |||
122 | #define isp1760_err(priv, fmt, args...) \ | ||
123 | dev_err(priv_to_hcd(priv)->self.controller, fmt, ##args) | ||
124 | |||
125 | /* chip memory management */ | ||
126 | struct memory_chunk { | ||
127 | unsigned int start; | ||
128 | unsigned int size; | ||
129 | unsigned int free; | ||
130 | }; | ||
131 | |||
132 | /* | ||
133 | * 60kb divided in: | ||
134 | * - 32 blocks @ 256 bytes | ||
135 | * - 20 blocks @ 1024 bytes | ||
136 | * - 4 blocks @ 8192 bytes | ||
137 | */ | ||
138 | |||
139 | #define BLOCK_1_NUM 32 | ||
140 | #define BLOCK_2_NUM 20 | ||
141 | #define BLOCK_3_NUM 4 | ||
142 | |||
143 | #define BLOCK_1_SIZE 256 | ||
144 | #define BLOCK_2_SIZE 1024 | ||
145 | #define BLOCK_3_SIZE 8192 | ||
146 | #define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) | ||
147 | #define PAYLOAD_SIZE 0xf000 | ||
148 | |||
149 | /* I saw if some reloads if the pointer was negative */ | ||
150 | #define ISP1760_NULL_POINTER (0x400) | ||
151 | |||
152 | /* ATL */ | ||
153 | /* DW0 */ | ||
154 | #define PTD_VALID 1 | ||
155 | #define PTD_LENGTH(x) (((u32) x) << 3) | ||
156 | #define PTD_MAXPACKET(x) (((u32) x) << 18) | ||
157 | #define PTD_MULTI(x) (((u32) x) << 29) | ||
158 | #define PTD_ENDPOINT(x) (((u32) x) << 31) | ||
159 | /* DW1 */ | ||
160 | #define PTD_DEVICE_ADDR(x) (((u32) x) << 3) | ||
161 | #define PTD_PID_TOKEN(x) (((u32) x) << 10) | ||
162 | #define PTD_TRANS_BULK ((u32) 2 << 12) | ||
163 | #define PTD_TRANS_INT ((u32) 3 << 12) | ||
164 | #define PTD_TRANS_SPLIT ((u32) 1 << 14) | ||
165 | #define PTD_SE_USB_LOSPEED ((u32) 2 << 16) | ||
166 | #define PTD_PORT_NUM(x) (((u32) x) << 18) | ||
167 | #define PTD_HUB_NUM(x) (((u32) x) << 25) | ||
168 | #define PTD_PING(x) (((u32) x) << 26) | ||
169 | /* DW2 */ | ||
170 | #define PTD_RL_CNT(x) (((u32) x) << 25) | ||
171 | #define PTD_DATA_START_ADDR(x) (((u32) x) << 8) | ||
172 | #define BASE_ADDR 0x1000 | ||
173 | /* DW3 */ | ||
174 | #define PTD_CERR(x) (((u32) x) << 23) | ||
175 | #define PTD_NAC_CNT(x) (((u32) x) << 19) | ||
176 | #define PTD_ACTIVE ((u32) 1 << 31) | ||
177 | #define PTD_DATA_TOGGLE(x) (((u32) x) << 25) | ||
178 | |||
179 | #define DW3_HALT_BIT (1 << 30) | ||
180 | #define DW3_ERROR_BIT (1 << 28) | ||
181 | #define DW3_QTD_ACTIVE (1 << 31) | ||
182 | |||
183 | #define INT_UNDERRUN (1 << 2) | ||
184 | #define INT_BABBLE (1 << 1) | ||
185 | #define INT_EXACT (1 << 0) | ||
186 | |||
187 | #define DW1_GET_PID(x) (((x) >> 10) & 0x3) | ||
188 | #define PTD_XFERRED_LENGTH(x) ((x) & 0x7fff) | ||
189 | #define PTD_XFERRED_LENGTH_LO(x) ((x) & 0x7ff) | ||
190 | |||
191 | #define SETUP_PID (2) | ||
192 | #define IN_PID (1) | ||
193 | #define OUT_PID (0) | ||
194 | #define GET_QTD_TOKEN_TYPE(x) ((x) & 0x3) | ||
195 | |||
196 | #define DATA_TOGGLE (1 << 31) | ||
197 | #define GET_DATA_TOGGLE(x) ((x) >> 31) | ||
198 | |||
199 | /* Errata 1 */ | ||
200 | #define RL_COUNTER (0) | ||
201 | #define NAK_COUNTER (0) | ||
202 | #define ERR_COUNTER (2) | ||
203 | |||
204 | #define HC_ATL_PL_SIZE (8192) | ||
205 | |||
206 | #endif | ||