diff options
Diffstat (limited to 'drivers/usb/host/ehci-sched.c')
-rw-r--r-- | drivers/usb/host/ehci-sched.c | 127 |
1 files changed, 0 insertions, 127 deletions
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c index d4a8ace49676..e682f2342ef8 100644 --- a/drivers/usb/host/ehci-sched.c +++ b/drivers/usb/host/ehci-sched.c | |||
@@ -479,109 +479,6 @@ static int disable_periodic (struct ehci_hcd *ehci) | |||
479 | } | 479 | } |
480 | 480 | ||
481 | /*-------------------------------------------------------------------------*/ | 481 | /*-------------------------------------------------------------------------*/ |
482 | #ifdef CONFIG_CPU_FREQ | ||
483 | |||
484 | static int safe_to_modify_i (struct ehci_hcd *ehci, struct ehci_qh *qh) | ||
485 | { | ||
486 | int now; /* current (frame * 8) + uframe */ | ||
487 | int prev_start, next_start; /* uframes from/to split start */ | ||
488 | int start_uframe = ffs(le32_to_cpup (&qh->hw_info2) & QH_SMASK); | ||
489 | int end_uframe = fls((le32_to_cpup (&qh->hw_info2) & QH_CMASK) >> 8); | ||
490 | int split_duration = end_uframe - start_uframe; | ||
491 | |||
492 | now = readl(&ehci->regs->frame_index) % (ehci->periodic_size << 3); | ||
493 | |||
494 | next_start = ((1024 << 3) + (qh->start << 3) + start_uframe - now) | ||
495 | % (qh->period << 3); | ||
496 | prev_start = (qh->period << 3) - next_start; | ||
497 | |||
498 | /* | ||
499 | * Make sure there will be at least one uframe when qh is safe. | ||
500 | */ | ||
501 | if ((qh->period << 3) <= (ehci->i_thresh + 2 + split_duration)) | ||
502 | /* never safe */ | ||
503 | return -EINVAL; | ||
504 | |||
505 | /* | ||
506 | * Wait 1 uframe after transaction should have started, to make | ||
507 | * sure controller has time to write back overlay, so we can | ||
508 | * check QTD_STS_STS to see if transaction is in progress. | ||
509 | */ | ||
510 | if ((next_start > ehci->i_thresh) && (prev_start > 1)) | ||
511 | /* safe to set "i" bit if split isn't in progress */ | ||
512 | return (qh->hw_token & STATUS_BIT(ehci)) ? 0 : 1; | ||
513 | else | ||
514 | return 0; | ||
515 | } | ||
516 | |||
517 | /* Set inactivate bit for all the split interrupt QHs. */ | ||
518 | static void qh_inactivate_split_intr_qhs (struct ehci_hcd *ehci) | ||
519 | { | ||
520 | struct ehci_qh *qh; | ||
521 | int not_done, safe; | ||
522 | u32 inactivate = INACTIVATE_BIT(ehci); | ||
523 | u32 active = ACTIVE_BIT(ehci); | ||
524 | |||
525 | do { | ||
526 | not_done = 0; | ||
527 | list_for_each_entry(qh, &ehci->split_intr_qhs, | ||
528 | split_intr_qhs) { | ||
529 | if (qh->hw_info1 & inactivate) | ||
530 | /* already off */ | ||
531 | continue; | ||
532 | /* | ||
533 | * To avoid setting "I" after the start split happens, | ||
534 | * don't set it if the QH might be cached in the | ||
535 | * controller. Some HCs (Broadcom/ServerWorks HT1000) | ||
536 | * will stop in the middle of a split transaction when | ||
537 | * the "I" bit is set. | ||
538 | */ | ||
539 | safe = safe_to_modify_i(ehci, qh); | ||
540 | if (safe == 0) { | ||
541 | not_done = 1; | ||
542 | } else if (safe > 0) { | ||
543 | qh->was_active = qh->hw_token & active; | ||
544 | qh->hw_info1 |= inactivate; | ||
545 | } | ||
546 | } | ||
547 | } while (not_done); | ||
548 | wmb(); | ||
549 | } | ||
550 | |||
551 | static void qh_reactivate_split_intr_qhs (struct ehci_hcd *ehci) | ||
552 | { | ||
553 | struct ehci_qh *qh; | ||
554 | u32 token; | ||
555 | int not_done, safe; | ||
556 | u32 inactivate = INACTIVATE_BIT(ehci); | ||
557 | u32 active = ACTIVE_BIT(ehci); | ||
558 | u32 halt = HALT_BIT(ehci); | ||
559 | |||
560 | do { | ||
561 | not_done = 0; | ||
562 | list_for_each_entry(qh, &ehci->split_intr_qhs, split_intr_qhs) { | ||
563 | if (!(qh->hw_info1 & inactivate)) /* already on */ | ||
564 | continue; | ||
565 | /* | ||
566 | * Don't reactivate if cached, or controller might | ||
567 | * overwrite overlay after we modify it! | ||
568 | */ | ||
569 | safe = safe_to_modify_i(ehci, qh); | ||
570 | if (safe == 0) { | ||
571 | not_done = 1; | ||
572 | } else if (safe > 0) { | ||
573 | /* See EHCI 1.0 section 4.15.2.4. */ | ||
574 | token = qh->hw_token; | ||
575 | qh->hw_token = (token | halt) & ~active; | ||
576 | wmb(); | ||
577 | qh->hw_info1 &= ~inactivate; | ||
578 | wmb(); | ||
579 | qh->hw_token = (token & ~halt) | qh->was_active; | ||
580 | } | ||
581 | } | ||
582 | } while (not_done); | ||
583 | } | ||
584 | #endif | ||
585 | 482 | ||
586 | /* periodic schedule slots have iso tds (normal or split) first, then a | 483 | /* periodic schedule slots have iso tds (normal or split) first, then a |
587 | * sparse tree for active interrupt transfers. | 484 | * sparse tree for active interrupt transfers. |
@@ -599,17 +496,6 @@ static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh) | |||
599 | period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK), | 496 | period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK), |
600 | qh, qh->start, qh->usecs, qh->c_usecs); | 497 | qh, qh->start, qh->usecs, qh->c_usecs); |
601 | 498 | ||
602 | #ifdef CONFIG_CPU_FREQ | ||
603 | /* | ||
604 | * If low/full speed interrupt QHs are inactive (because of | ||
605 | * cpufreq changing processor speeds), start QH with I flag set-- | ||
606 | * it will automatically be cleared when cpufreq is done. | ||
607 | */ | ||
608 | if (ehci->cpufreq_changing) | ||
609 | if (!(qh->hw_info1 & (cpu_to_le32(1 << 13)))) | ||
610 | qh->hw_info1 |= INACTIVATE_BIT(ehci); | ||
611 | #endif | ||
612 | |||
613 | /* high bandwidth, or otherwise every microframe */ | 499 | /* high bandwidth, or otherwise every microframe */ |
614 | if (period == 0) | 500 | if (period == 0) |
615 | period = 1; | 501 | period = 1; |
@@ -658,12 +544,6 @@ static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh) | |||
658 | ? ((qh->usecs + qh->c_usecs) / qh->period) | 544 | ? ((qh->usecs + qh->c_usecs) / qh->period) |
659 | : (qh->usecs * 8); | 545 | : (qh->usecs * 8); |
660 | 546 | ||
661 | #ifdef CONFIG_CPU_FREQ | ||
662 | /* add qh to list of low/full speed interrupt QHs, if applicable */ | ||
663 | if (!(qh->hw_info1 & (cpu_to_le32(1 << 13)))) { | ||
664 | list_add(&qh->split_intr_qhs, &ehci->split_intr_qhs); | ||
665 | } | ||
666 | #endif | ||
667 | /* maybe enable periodic schedule processing */ | 547 | /* maybe enable periodic schedule processing */ |
668 | if (!ehci->periodic_sched++) | 548 | if (!ehci->periodic_sched++) |
669 | return enable_periodic (ehci); | 549 | return enable_periodic (ehci); |
@@ -683,13 +563,6 @@ static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh) | |||
683 | // THEN | 563 | // THEN |
684 | // qh->hw_info1 |= __constant_cpu_to_hc32(1 << 7 /* "ignore" */); | 564 | // qh->hw_info1 |= __constant_cpu_to_hc32(1 << 7 /* "ignore" */); |
685 | 565 | ||
686 | #ifdef CONFIG_CPU_FREQ | ||
687 | /* remove qh from list of low/full speed interrupt QHs */ | ||
688 | if (!(qh->hw_info1 & (cpu_to_le32(1 << 13)))) { | ||
689 | list_del_init(&qh->split_intr_qhs); | ||
690 | } | ||
691 | #endif | ||
692 | |||
693 | /* high bandwidth, or otherwise part of every microframe */ | 566 | /* high bandwidth, or otherwise part of every microframe */ |
694 | if ((period = qh->period) == 0) | 567 | if ((period = qh->period) == 0) |
695 | period = 1; | 568 | period = 1; |